Display panel

Abstract

The invention discloses a display panel, a gate drive circuit comprises a shift register, and the shift register comprises an input module, a pull-up module, a pull-down module, a feedback module, a pull-down control module and a node control module. The newly added node control module can pull down the potential of the pull-up node to the potential of the low potential line according to the potential of the first node so as to reduce or prevent the pull-up module from being opened abnormally, so that the pulse number of the output gate driving signal in one frame is consistent with the expectation; therefore, the risk that the pulse number of the gate drive signal is abnormal in one frame is improved or avoided, and the stability of the gate drive circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Display panels, as display components of electronic devices, have been widely used, and gate driving circuits are an important component of display panels.

[0003] Therefore, the stability of the gate drive circuit is an important parameter to measure reliability. However, if the node potential inside the gate drive circuit is abnormal, the stability will be reduced, resulting in poor display. Summary of the invention

[0004] The present application provides a display panel to alleviate the technical problem of low stability caused by an abnormal number of pulses of a gate driving signal in one frame.

[0005] The present application provides a display panel, the display panel includes a gate drive circuit, the gate drive circuit includes a shift register, the shift register includes: an input module, the input module is used to receive a forward scan control signal and a first control signal, and control the forward scan control signal to be input to a pull-up node according to the first control signal; a pull-up module, the pull-up module is used to receive the potential of the pull-up node and a first clock signal, and control the first clock signal to output a gate drive signal to a gate drive line according to the potential of the pull-up node; a pull-down module, the pull-down module is used to receive the potential of the pull-down node and a low potential signal, and control the low potential signal to be output to the gate drive line according to the potential of the pull-down node; a feedback module, the feedback module is used to receive the potential of the pull-down node and the low potential signal, and control the low potential signal to be output to the pull-up node according to the potential of the pull-down node; a pull-down control module A module, the pull-down control module includes a first transistor, a second transistor and a third transistor, the first transistor is used to receive a second clock signal and the forward scan control signal, and control the second clock signal to be output to the first node according to the forward scan control signal, the second transistor is used to receive a third clock signal and a reverse scan control signal, and control the third clock signal to be output to the first node according to the reverse scan control signal, the third transistor is used to receive the potential of the first node and a high potential signal, and control the high potential signal to be output to the pull-down node according to the potential of the first node; and a node control module, the node control module is used to receive the potential of the pull-up node, the potential of the first node and the low potential signal, and control the low potential signal to be output to the pull-up node according to the potential of the first node, so as to pull down the potential of the pull-up node to the potential of the low potential signal.

[0006] In some embodiments, the node control module includes a fourth transistor, a first electrode of the fourth transistor is connected to the pull-up node, a second electrode of the fourth transistor is connected to the low potential line, a gate of the fourth transistor is connected to the first node, and the fourth transistor is an N-channel transistor.

[0007] In some embodiments, the node control module includes a fourth transistor and a seventh transistor, the first electrode of the fourth transistor is connected to the pull-up node, the second electrode of the fourth transistor is connected to the first electrode of the seventh transistor, the second electrode of the seventh transistor is connected to the low potential line, the first node is connected to the gate of the fourth transistor and the gate of the seventh transistor, and the fourth transistor and the seventh transistor are both N-channel transistors.

[0008] In some embodiments, the pull-up module includes a second pull-up transistor, a gate of the second pull-up transistor is connected to the pull-up node, a first electrode of the second pull-up transistor is connected to the first clock line, and a second electrode of the second pull-up transistor is connected to the gate drive line.

[0009] In some embodiments, the shift register also includes: a fifth transistor, which is used to receive the reverse scan control signal and the second control signal, and control the reverse scan control signal to be output to the pull-up node according to the second control signal; and a sixth transistor, which is used to receive the potential of the pull-up node and the low potential signal, and control the low potential signal to be output to the pull-down node according to the potential of the pull-up node.

[0010] In some embodiments, the gate drive line is used to transmit the Nth level gate drive signal; the gate of the fifth transistor is connected to the second control line; the gate drive circuit includes a plurality of cascaded shift registers, and in the tail-stage shift register of the gate drive circuit, the second control line is a start line, and the start line is used to transmit the start signal of the next frame; in the non-tail-stage shift register of the gate drive circuit, the second control line is the N+2th level gate drive line, and the N+2th level gate drive line is used to transmit the N+2th level gate drive signal.

[0011] In some implementation manners, the tail-stage shift register is provided with the node control module, and the non-tail-stage shift register is not provided with the node control module.

[0012] In some embodiments, the input module includes an input transistor, a first electrode of the input transistor is connected to the forward scan control line, a second electrode of the input transistor is connected to the pull-up node, and a gate of the input transistor is connected to the first control line.

[0013] In some embodiments, in the first-stage shift register of the gate drive circuit, the first control line is the start line, which is used to transmit the start signal of this frame; in the non-first-stage shift register of the gate drive circuit, the first control line is the N-2th gate drive line, and the N-2th gate drive line is used to transmit the N-2th gate drive signal.

[0014] In some implementation methods, the tail-stage shift register and the first-stage shift register are both provided with the node control module, and the shift register between the tail-stage shift register and the first-stage shift register is not provided with the node control module.

[0015] In some embodiments, the shift register also includes: a first global transistor, the first global transistor is used to receive a first global control signal and control the potential of the gate drive line according to the first global control signal; a second global transistor, the second global transistor is used to receive the first global control signal and control the low potential signal to be output to the pull-down node according to the first global control signal; and a third global transistor, the third global transistor is used to receive a second global control signal and control the low potential signal to be output to the gate drive line according to the second global control signal.

[0016] In some of the embodiments, the gate driving circuit includes a plurality of the shift registers connected in cascade, and each of the shift registers in the gate driving circuit is provided with the node control module.

[0017] The display panel provided in the present application can, through a newly added node control module, pull down the potential of the pull-up node to the potential of the low potential line according to the potential of the first node, so as to reduce or prevent the abnormal opening of the pull-up module, so that the number of pulses of the gate drive signal outputted by it in one frame is consistent with expectations, thereby improving or avoiding the risk of abnormal number of pulses of the gate drive signal in one frame and improving the stability of the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit principle block diagram of a shift register in the related technology.

[0019] Figure 2 for Figure 1 The circuit schematic of the shift register shown.

[0020] Figure 3 It is a timing diagram of a gate drive circuit in the related art.

[0021] Figure 4 It is a schematic diagram of the cascade relationship between the shift registers of the gate drive circuit in the related art.

[0022] Figure 5 It is a circuit schematic diagram of a tail-stage shift register in the related art.

[0023] Figure 6 Another timing diagram of a gate drive circuit in the related art.

[0024] Figure 7 A circuit principle block diagram of a shift register provided in an embodiment of the present application.

[0025] Figure 8 for Figure 7 A circuit schematic of a shift register shown.

[0026] Fig. 9 for Figure 7 Another circuit schematic of the shift register shown.

[0027] Fig.10 A schematic diagram of a cascade relationship between shift registers in a gate drive circuit provided in an embodiment of the present application.

[0028] Fig.11 A schematic diagram of another cascade relationship between shift registers in a gate drive circuit provided in an embodiment of the present application.

[0029] Fig.12 A circuit schematic diagram of a tail-stage shift register provided in an embodiment of the present application.

[0030] Fig.13 A schematic diagram of the relationship between the start signal of the current frame and the start signal of the next frame provided in an embodiment of the present application.

[0031] Fig.14 for Figure 8 or Fig. 9 The timing simulation diagram of the shift register shown. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0034] Figure 1 It is a circuit principle block diagram of a shift register in the related technology. Figure 2 for Figure 1 The shift register includes an input module 10, a pull-up module 20, a pull-down module 40, a feedback module 50 and a pull-down control module 30, wherein the input module 10 is connected to the pull-up module 20 via a pull-up node Q1, the pull-down module 40 is connected to the pull-down module 40 via a pull-down node P, the feedback module 50 is connected to the pull-up node Q1 and the pull-down node P, and the gate drive line is connected to the pull-up module 20 and the pull-down module 40.

[0035] The gate driving line is used to transmit the Nth stage gate driving signal ST(N).

[0036] Exemplarily, the pull-down control module 30 includes a first transistor NT3, a second transistor NT4, and a third transistor NT8, wherein the first electrode of the first transistor NT3 is connected to the second clock line, the second electrode of the first transistor NT3 is connected to the first node A, and the gate of the first transistor NT3 is connected to the forward scanning control line. The first electrode of the second transistor NT4 is connected to the third clock line, the second electrode of the second transistor NT4 is connected to the first node A, and the gate of the second transistor NT4 is connected to the reverse scanning control line. The gate of the third transistor NT8 is connected to the first node A, the first electrode of the third transistor NT8 is connected to the high potential line, and the second electrode of the third transistor NT8 is connected to the pull-down node P.

[0037] Among them, the forward scan control line is used to transmit the forward scan control signal U2D. The reverse scan control line is used to transmit the reverse scan control signal D2U. The second clock line is used to transmit the N+2 clock signal CKN+2. The third clock line is used to transmit the N-2 clock signal CKN-2. The high potential line is used to transmit the high potential signal VGH, which can turn on the N-channel transistor or turn off the P-channel transistor when connected to the gate of the transistor.

[0038] The first electrode is one of the source and the drain, and the second electrode is the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.

[0039] Exemplarily, the pull-down module 40 includes a pull-down transistor NT10, a gate of the pull-down transistor NT10 is connected to the pull-down node P, a first electrode of the pull-down transistor NT10 is connected to the low potential line, and a second electrode of the pull-down transistor NT10 is connected to the gate drive line.

[0040] The low potential line is used to transmit a low potential signal VGL, which can turn on a P-channel transistor or turn off an N-channel transistor when connected to the gate of the transistor.

[0041] Exemplarily, the input module 10 includes an input transistor NT1, a first electrode of the input transistor NT1 is connected to the forward scanning control line, a second electrode of the input transistor NT1 is connected to the pull-up node Q1, and a gate of the input transistor NT1 is connected to the first control line.

[0042] The first control line is used to transmit the N-2th stage gate driving signal ST(N-2) or the start signal STV_frame_n of the current frame.

[0043] Exemplarily, the pull-up module 20 includes a first pull-up transistor NT7 and a second pull-up transistor NT9, the first electrode of the first pull-up transistor NT7 is connected to the pull-up node Q1, the gate of the first pull-up transistor NT7 is connected to the high potential line, the second electrode of the first pull-up transistor NT7 is connected to the second pull-up node Q2 and the gate of the second pull-up transistor NT9, the first electrode of the second pull-up transistor NT9 is connected to the first clock line, and the second electrode of the second pull-up transistor NT9 is connected to the gate drive line.

[0044] The first clock line is used to transmit the Nth clock signal CKN.

[0045] Exemplarily, the feedback module 50 includes a feedback transistor NT5, a first electrode of the feedback transistor NT5 is connected to the pull-up node Q1, a second electrode of the feedback transistor NT5 is connected to the low potential line, and a gate of the feedback transistor NT5 is connected to the pull-down node P.

[0046] Exemplarily, the shift register further includes a fifth transistor NT2 and a sixth transistor NT6, wherein a first electrode of the fifth transistor NT2 is connected to a reverse scan control line, a gate electrode of the fifth transistor NT2 is connected to a second control line, and a second electrode of the fifth transistor NT2 is connected to a pull-up node Q1. A gate electrode of the sixth transistor NT6 is connected to a second electrode of the fifth transistor NT2 and to the pull-up node Q1, a first electrode of the sixth transistor NT6 is connected to a low potential line, and a second electrode of the sixth transistor NT6 is connected to a pull-down node P.

[0047] The second control line is used to transmit the N+2th stage gate driving signal ST(N+2) or the start signal STV_frame_n+1 of the next frame.

[0048] Exemplarily, the shift register also includes a first global transistor NT11, a second global transistor NT12 and a third global transistor NT13, the first electrode of the first global transistor NT11 is connected to the gate drive line, the second electrode of the first global transistor NT11 is connected to the gate of the first global transistor NT11 and the first global control line; the gate of the second global transistor NT12 is connected to the first global control line, the first electrode of the second global transistor NT12 is connected to the pull-down node P, and the second electrode of the second global transistor NT12 is connected to the low potential line; the first electrode of the third global transistor NT13 is connected to the gate drive line, the second electrode of the third global transistor NT13 is connected to the low potential line, and the gate of the third global transistor NT13 is connected to the second global control line.

[0049] The first global control line is used to transmit a first global control signal GAS1, and the second global control line is used to transmit a second global control signal GAS2.

[0050] Exemplarily, the shift register further includes a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected to the low potential line, and the other end of the first capacitor C1 is connected to the pull-up node Q1. One end of the second capacitor C2 is connected to the low potential line, and the other end of the second capacitor C2 is connected to the pull-down node P.

[0051] Figure 3 The timing diagram of the gate driving circuit in the related art is shown in FIG. The working phases in a frame include a display phase, a touch phase and a blank phase. The display phase and the touch phase can alternate in a frame, and the blank phase is at the end of a frame.

[0052] It can be seen that in the display stage, under the action of the high potential signal VGH, the forward scan control signal U2D, the low potential signal VGL, the reverse scan control signal D2U, the start signal STV, the clock signal (for example, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4), the first global control signal GAS1 and the second global control signal GAS2, the first level gate drive signal ST(1), the second level gate drive signal ST(2), the third level gate drive signal ST(3), the fourth level gate drive signal ST(4) and the like can be generated to achieve progressive scanning.

[0053] During the touch stage, under the action of the above-mentioned corresponding signals, the first-level gate drive signal ST(1), the second-level gate drive signal ST(2), the third-level gate drive signal ST(3), the fourth-level gate drive signal ST(4), etc. stop outputting corresponding pulses, and correspondingly, the line-by-line scanning process will also be terminated; when entering the display stage again, the original line-by-line scanning or display will continue.

[0054] Figure 4 The schematic diagram is a cascade relationship diagram between the shift registers of the gate drive circuit of the related art. In the gate drive circuit, K shift registers are cascaded, for example, a first-stage shift register generating a first-stage gate drive signal ST(1), a second-stage shift register generating a second-stage gate drive signal ST(2) ... a K-1-stage shift register generating a K-1-stage gate drive signal ST(K-1), and a tail-stage shift register (K-stage shift register) generating a K-stage gate drive signal ST(K).

[0055] Each shift register is connected to a high potential line, a low potential line and a corresponding clock line. For example, the first-stage shift register is connected to the 1st clock line, the 2nd clock line and the 4th clock line, the second-stage shift register is connected to the 1st clock line, the 2nd clock line and the 3rd clock line, and so on. The K-1th stage shift register is connected to the 2nd clock line, the 3rd clock line and the 4th clock line, and the Kth stage shift register is connected to the 1st clock line, the 3rd clock line and the 4th clock line. The 1st clock line, the 2nd clock line, the 3rd clock line and the 4th clock line are respectively used to transmit the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4.

[0056] The start line is connected to the first-stage shift register and the last-stage shift register to transmit the start signal STV_frame_n of the current frame and the start signal STV_frame_n+1 of the next frame to the first-stage shift register and the last-stage shift register respectively. Figure 5 As shown, Figure 2 By comparison, it can be seen that the gate of the fifth transistor NT2 is connected to the start signal STV_frame_n+1 of the next frame.

[0057] Since the tail-stage shift register adopts the K-1th gate drive signal ST(K-1) output by the K-1th shift register as the trigger signal, and adopts the start signal STV_frame_n+1 of the next frame as the pull-down signal, and the start signal STV_frame_n+1 of the next frame is also used as the trigger signal of the first-stage shift register in the next frame, the pull-down signal at this time will be delayed by a certain time compared with the logical pull-down time. At this time, the potential of the pull-up node Q1 is not pulled down in time. The potential of the pull-up node Q1 is not pulled down in time, resulting in the Nth-stage gate drive signal ST(N) outputting multiple pulses in one frame, which is manifested macroscopically as the presence of image difference in the tail stage.

[0058] Specifically, Figure 6 As shown, in the continuous Nth frame (Frame_N) and the N+1th frame (Frame_N+1), they both include a display phase and a blank phase. Under the control of the start signal STV, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, each shift register generates a corresponding first-level gate drive signal ST(1), a second-level gate drive signal ST(2), a third-level gate drive signal ST(3), a fourth-level gate drive signal ST(4) ... an Nth-level gate drive signal ST(N).

[0059] Among them, the Nth stage gate drive signal ST(N) is generated by the tail stage shift register. In each frame, since the potential of the pull-up node Q1 is not pulled down in time, the Nth stage gate drive signal ST(N) outputs multiple pulses in one frame, which is manifested macroscopically as the presence of image difference in the tail stage.

[0060] Based on this, see Figures 7 to 14 , this embodiment provides a gate driving circuit, the gate driving circuit includes a shift register, such as Figure 7 , Figure 8As shown, the shift register includes an input module 10, a pull-up module 20, a pull-down module 40, a feedback module 50, a pull-down control module 30 and a node control module 60. The input module 10 is connected to the forward scanning control line, the first control line and the pull-up node Q1; the pull-up module 20 is connected to the pull-up node Q1, the first clock line and the gate drive line; the pull-down module 40 is connected to the pull-down node P, the gate drive line and the low potential line; the feedback module 50 is connected to the pull-down node P, the low potential line and the pull-up node Q1; the pull-down control module 30 includes a first crystal The body transistor NT3, the second transistor NT4 and the third transistor NT8, the first transistor NT3 is connected to the second clock line, the forward scan control line and the first node A, the second transistor NT4 is connected to the third clock line, the reverse scan control line and the first node A, the third transistor NT8 is connected to the first node A, the high potential line and the pull-down node P; the node control module 60 is connected to the pull-up node Q1, the first node A and the low potential line, and the node control module 60 pulls down the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A.

[0061] It can be understood that the gate drive circuit provided in this embodiment can lower the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A through the newly added node control module 60, so as to reduce or prevent the pull-up module 20 from opening abnormally, so that the number of pulses of the gate drive signal outputted therefrom in one frame is consistent with expectations, thereby improving or avoiding the risk of abnormal number of pulses of the gate drive signal in one frame and improving the stability of the gate drive circuit.

[0062] In one embodiment, if Figure 8 As shown, the node control module 60 includes a fourth transistor NT14, a first electrode of the fourth transistor NT14 is connected to the pull-up node Q1, a second electrode of the fourth transistor NT14 is connected to the low potential line, a gate of the fourth transistor NT14 is connected to the first node A, and the fourth transistor NT14 is an N-channel transistor.

[0063] It should be noted that when the first node A is at a high potential, the fourth transistor NT14 is turned on, and the potential of the pull-up node Q1 is pulled down to the potential of the low potential signal VGL, which can control the second pull-up transistor NT9 to be closed, thereby avoiding the abnormal picture caused by the gate drive signal outputting multiple pulses in one frame.

[0064] In one embodiment, if Fig. 9As shown, the node control module 60 includes a fourth transistor NT14 and a seventh transistor NT15, the first electrode of the fourth transistor NT14 is connected to the pull-up node Q1, the second electrode of the fourth transistor NT14 is connected to the first electrode of the seventh transistor NT15, the second electrode of the seventh transistor NT15 is connected to the low potential line, and the first node A is connected to the gate of the fourth transistor NT14 and the gate of the seventh transistor NT15. ​​The fourth transistor NT14 and the seventh transistor NT15 are both N-channel transistors.

[0065] It should be noted that when the first node A is at a high potential, the fourth transistor NT14 and the seventh transistor NT15 are turned on, which can not only pull the potential of the pull-up node Q1 down to the potential of the low potential signal VGL, thereby controlling the second pull-up transistor NT9 to be turned off, avoiding the abnormal picture caused by the gate drive signal outputting multiple pulses in one frame; and the fourth transistor NT14 and the seventh transistor NT15 connected in series, when turned off, can further reduce the leakage path of the pull-up node Q1, especially in the touch stage which requires a longer pause time.

[0066] In one embodiment, if Fig. 9 As shown, the pull-up module 20 includes a second pull-up transistor NT9, a gate of the second pull-up transistor NT9 is connected to the pull-up node Q1, a first electrode of the second pull-up transistor NT9 is connected to the first clock line, and a second electrode of the second pull-up transistor NT9 is connected to the gate drive line.

[0067] In one embodiment, the shift register further includes a fifth transistor NT2 and a sixth transistor NT6, the fifth transistor NT2 is connected to the reverse scan control line, the second control line and the pull-up node Q1; the sixth transistor NT6 is connected to the fifth transistor NT2, the pull-up node Q1, the low potential line and the pull-down node P.

[0068] Other structures in the shift register can be found in Figure 2 Wherein, each transistor may be an N-channel thin film transistor.

[0069] exist Fig.10 , Fig.11 In the embodiment, the gate drive circuit includes a plurality of cascaded shift registers, such as a first-stage shift register for generating a first-stage gate drive signal ST(1), a second-stage shift register for generating a second-stage gate drive signal ST(2) ... a K-1th-stage shift register for generating a K-1th-stage gate drive signal ST(K-1), and a tail-stage shift register (Kth-stage shift register) for generating a Kth-stage gate drive signal ST(K).

[0070] In the tail stage shift register of the gate drive circuit, the second control line is the start line, such as Fig.12 As shown, the start line is used to transmit the start signal STV_frame_n+1 of the next frame. In the non-tail stage shift register of the gate drive circuit, the second control line is the N+2 stage gate drive line, such as Figure 8 , Fig. 9 As shown, the N+2-th gate driving line is used to transmit the N+2-th gate driving signal ST(N+2).

[0071] In one embodiment, if Fig.10 As shown, the tail-stage shift register is provided with a node control module 60 , while the non-tail-stage shift register is not provided with a node control module 60 .

[0072] It should be noted that a node control module 60 is set in the tail-stage shift register, which can lower the potential of the pull-up node Q1 to the potential of the low-potential line according to the potential of the first node A, so as to reduce or prevent the pull-up module 20 from opening abnormally, so that the number of pulses of the last-stage gate drive signal outputted by it in one frame is consistent with expectations, thereby improving or avoiding the picture abnormality caused by the last-stage gate drive signal having multiple pulses in one frame, and improving the stability of the gate drive circuit.

[0073] Furthermore, since the node control module 60 is not provided in any non-tail stage shift register, the space occupied by the frame of the non-tail stage shift register can be reduced, thereby facilitating a narrower frame.

[0074] Furthermore, this embodiment can be suitable for a driving scheme that performs only forward scanning.

[0075] In one embodiment, in the first-stage shift register of the gate drive circuit, the first control line is the start line, which is used to transmit the start signal STV_frame_n of the current frame; in the non-first-stage shift register of the gate drive circuit, the first control line is the N-2th gate drive line, which is used to transmit the N-2th gate drive signal ST(N-2).

[0076] In one embodiment, if Fig.11 As shown, both the tail-stage shift register and the first-stage shift register are provided with a node control module 60 , and the shift register between the tail-stage shift register and the first-stage shift register is not provided with a node control module 60 .

[0077] It should be noted that a node control module 60 is set in both the first-stage shift register and the last-stage shift register, which can lower the potential of the pull-up node Q1 to the potential of the low-potential line according to the potential of the first node A, so as to reduce or prevent the abnormal opening of the pull-up module 20, so that the number of pulses of the first-stage and last-stage gate drive signals outputted therefrom in one frame is consistent with expectations, thereby improving or avoiding the picture abnormality caused by the first-stage and last-stage gate drive signals having multiple pulses in one frame, and improving the stability of the gate drive circuit.

[0078] Furthermore, since the node control module 60 is not provided in the shift registers between the last-stage shift register and the first-stage shift register, the space occupied by the frame of the non-last-stage shift register can be reduced, thereby facilitating a narrower frame.

[0079] Furthermore, this embodiment can be suitable for driving schemes of forward scanning and reverse scanning.

[0080] In one embodiment, each shift register in the gate driving circuit is provided with a node control module 60 .

[0081] It should be noted that a node control module 60 is provided in each shift register, which can lower the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A, so as to reduce or prevent the pull-up module 20 from opening abnormally, so that the number of pulses of the gate drive signal of each level outputted therefrom in one frame is consistent with expectations, thereby improving or avoiding the picture abnormality caused by the gate drive signal of each level having multiple pulses in one frame, and improving the stability of the gate drive circuit.

[0082] Especially in display drivers with a touch function or a touch stage, since the touch function may be enabled or the touch stage may be entered at any time, the gate drive circuit needs to terminate the line-by-line scanning at any time, and the last line scanned before the termination is usually prone to screen abnormalities. By setting a node control module 60 in each shift register, the screen abnormalities can be improved or avoided, thereby improving the stability of the gate drive circuit.

[0083] Similarly, this embodiment can be suitable for a driving scheme that performs at least one of forward scanning and reverse scanning.

[0084] Fig.13 A schematic diagram of the relationship between the start signal STV_frame_n of the current frame and the start signal STV_frame_n+1 of the next frame provided in the embodiment of the present application. Fig.13As shown, the waveforms of the start signal STV_frame_n of the current frame and the start signal STV_frame_n+1 of the next frame are the same, but they appear one after the other, that is, the start signal STV_frame_n of the current frame appears before the start signal STV_frame_n+1 of the next frame.

[0085] Fig.14 for Figure 8 or Fig. 9 Schematic diagram of timing simulation of the shift register shown. It can be seen that when the N-2-stage gate drive signal ST(N-2) is at a high potential, the input transistor NT1 is turned on, the potential of the pull-up node Q1 is raised to a high potential (the potential of the second pull-up node Q2 is also raised to a high potential), the second pull-up transistor NT9 is turned on, and the pulse of the N-th clock signal CKN is output as the pulse of the N-stage gate drive signal ST(N). At this time, the potential of the pull-down node P is at a low potential.

[0086] After the pulse output of the Nth level gate drive signal ST(N) is completed, the potential of the pull-down node P is switched to a high potential, and the N+2th level gate drive signal ST(N+2) also has a pulse. The potential of the first node A will alternate between a high potential and a low potential. When the potential is high, the node control module 60 will pull down the potential of the pull-up node Q1 to avoid abnormal opening of the second pull-up transistor NT9, thereby improving or avoiding the abnormal picture and improving the stability of the gate drive circuit.

[0087] In one embodiment, the present embodiment provides a display panel, and the display panel includes the above-mentioned gate driving circuit.

[0088] It can be understood that since the display panel provided in this embodiment includes the above-mentioned gate drive circuit, the newly added node control module 60 can also lower the potential of the pull-up node Q1 to the potential of the low potential line according to the potential of the first node A, so as to reduce or prevent the pull-up module 20 from opening abnormally, so that the number of pulses of the gate drive signal outputted therefrom in one frame is consistent with expectations, thereby improving or avoiding the risk of abnormal number of pulses of the gate drive signal in one frame and improving the stability of the gate drive circuit.

[0089] It should be noted that the display panel may be a liquid crystal display panel or a self-luminous display panel. In the case of a liquid crystal display panel, the gate drive circuit may scan the sub-pixels row by row to control the data signal to be written into the corresponding sub-pixels. Alternatively, in the case of a light-emitting display panel, the gate drive circuit may be used to drive the corresponding transistor in the pixel circuit.

[0090] The self-luminous display panel may be, for example, an organic light emitting diode display panel, a mini light emitting diode display panel, a micro light emitting diode display panel or a quantum dot light emitting diode display panel.

[0091] In one embodiment, the display panel may also be a touch display panel, such as an IN Cell Touch display panel or an ON Cell Touch display panel.

[0092] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] The gate drive circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a gate driving circuit, the gate driving circuit includes a shift register, and the shift register includes: An input module, the input module is used to receive a forward scan control signal and a first control signal, and control the forward scan control signal to be input to an upward pull node according to the first control signal; A pull-up module, the pull-up module is used to receive the potential of the pull-up node and a first clock signal, and control the first clock signal to output a gate drive signal to the gate drive line according to the potential of the pull-up node; A pull-down module, the pull-down module is used to receive the potential of the pull-down node and the low potential signal, and control the low potential signal to be output to the gate drive line according to the potential of the pull-down node; A feedback module, the feedback module is used to receive the potential of the pull-down node and the low potential signal, and control the low potential signal to be output to the pull-up node according to the potential of the pull-down node; a pull-down control module, the pull-down control module comprising a first transistor, a second transistor and a third transistor, the first transistor being used to receive a second clock signal and the forward scan control signal, and controlling the second clock signal to be output to the first node according to the forward scan control signal, the second transistor being used to receive a third clock signal and a reverse scan control signal, and controlling the third clock signal to be output to the first node according to the reverse scan control signal, the third transistor being used to receive a potential of the first node and a high potential signal, and controlling the high potential signal to be output to the pull-down node according to the potential of the first node; and A node control module, the node control module is used to receive the potential of the pull-up node, the potential of the first node and the low potential signal, and control the low potential signal to be output to the pull-up node according to the potential of the first node, so as to pull down the potential of the pull-up node to the potential of the low potential signal.

2. The display panel according to claim 1, characterized in that: The node control module includes a fourth transistor, a first electrode of the fourth transistor is connected to the pull-up node, a second electrode of the fourth transistor is connected to the low potential line, a gate of the fourth transistor is connected to the first node, and the fourth transistor is an N-channel transistor.

3. The display panel according to claim 1, characterized in that: The node control module includes a fourth transistor and a seventh transistor, the first electrode of the fourth transistor is connected to the pull-up node, the second electrode of the fourth transistor is connected to the first electrode of the seventh transistor, the second electrode of the seventh transistor is connected to the low potential line, the first node is connected to the gate of the fourth transistor and the gate of the seventh transistor, and the fourth transistor and the seventh transistor are both N-channel transistors.

4. The display panel according to claim 1, characterized in that: The pull-up module includes a second pull-up transistor, a gate of the second pull-up transistor is connected to the pull-up node, a first electrode of the second pull-up transistor is connected to the first clock line, and a second electrode of the second pull-up transistor is connected to the gate drive line.

5. The display panel according to claim 1, characterized in that: The shift register further includes: a fifth transistor, the fifth transistor being configured to receive the reverse scan control signal and a second control signal, and to control the reverse scan control signal to be output to the pull-up node according to the second control signal; and A sixth transistor, the sixth transistor is used to receive the potential of the pull-up node and the low potential signal, and control the low potential signal to be output to the pull-down node according to the potential of the pull-up node.

6. The display panel according to claim 5, characterized in that: The gate drive line is used to transmit the Nth level gate drive signal; The gate of the fifth transistor is connected to the second control line; The gate driving circuit comprises a plurality of the shift registers connected in cascade, and in the tail-stage shift register of the gate driving circuit, the second control line is a start line, and the start line is used to transmit a start signal of a next frame; In the non-tail-stage shift register of the gate driving circuit, the second control line is an N+2-th stage gate driving line, and the N+2-th stage gate driving line is used to transmit an N+2-th stage gate driving signal.

7. The display panel according to claim 6, characterized in that: The tail-stage shift register is provided with the node control module, while the non-tail-stage shift register is not provided with the node control module.

8. The display panel according to claim 6, characterized in that: The input module comprises an input transistor, a first electrode of the input transistor is connected to the forward scanning control line, a second electrode of the input transistor is connected to the pull-up node, and a gate of the input transistor is connected to the first control line.

9. The display panel according to claim 8, characterized in that: In the first-stage shift register of the gate driving circuit, the first control line is the start line, and the start line is used to transmit the start signal of the current frame; In the non-first-stage shift register of the gate driving circuit, the first control line is an N-2-stage gate driving line, and the N-2-stage gate driving line is used to transmit an N-2-stage gate driving signal.

10. The display panel according to claim 9, characterized in that: The tail-stage shift register and the first-stage shift register are both provided with the node control module, and the shift register between the tail-stage shift register and the first-stage shift register is not provided with the node control module.

11. The display panel according to claim 5, characterized in that: The shift register further includes: a first global transistor, the first global transistor being used to receive a first global control signal and control a potential of the gate drive line according to the first global control signal; a second global transistor, the second global transistor being configured to receive the first global control signal and control the low potential signal to be output to the pull-down node according to the first global control signal; and A third global transistor is used for receiving a second global control signal and controlling the low potential signal to be output to the gate drive line according to the second global control signal.

12. The display panel according to claim 11, characterized in that: The gate driving circuit includes a plurality of cascaded shift registers, and each shift register in the gate driving circuit is provided with the node control module.

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