Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises a first drive circuit which comprises a plurality of stages of shift registers; the shift register comprises a first shift control module which is electrically connected with an input end, a first clock end, a first power supply end, a first node, a second node and a third node; the second shift control module is electrically connected with the input end, the first clock end, the first node, a second power supply end and a fourth node; the shift output module is electrically connected with the fourth node, the second node, the first power supply end, the second power supply end and a shift output end; and the potential control module is electrically connected with the third node, a second clock end and the second node. According to the shift register, the potential control module is additionally arranged in the shift register, so that the output effectiveness, accuracy and stability of the shift register can be ensured, and the display quality of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] A display panel is usually provided with a plurality of pixels, and a driving circuit is used to scan each pixel row by row, so that data signals can be written into each pixel row by row, so that each pixel can display and emit light according to the data signal it receives, thereby presenting a corresponding display screen.

[0003] Usually, a cascaded multi-stage shift register is provided in the driving circuit. By controlling the signals of the corresponding nodes in each stage of the shift register, the gate driving signal output by the shift register can be controlled.

[0004] However, at present, some nodes in the shift register may leak electricity, thereby affecting the accuracy of the gate driving signal output by the shift register, and further affecting the display quality of the display panel. Summary of the invention

[0005] The present invention provides a display panel and a display device to improve the output stability of a shift register.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising: a first driving circuit, the first driving circuit comprising a multi-stage shift register;

[0007] The shift register comprises:

[0008] A first shift control module, electrically connected to the input terminal, the first clock terminal, the first power terminal, the first node, the second node and the third node, and used to control a signal of the first node, a signal of the second node and a signal of the third node;

[0009] a second shift control module, electrically connected to the input terminal, the first clock terminal, the first node, the second power terminal and the fourth node, and used to control a signal of the fourth node;

[0010] a shift output module, electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal and the shift output terminal, and used for controlling the shift output terminal to output a shift signal;

[0011] A potential control module is electrically connected to the third node, the second clock terminal and the second node, and is used to control the signal of the second node.

[0012] According to another aspect of the present invention, a display device is provided, comprising: the display panel as described above.

[0013] In the present invention, a potential control module is added to the shift register, the potential control module receives the second clock signal provided by the second clock end, the second clock signal has periodic high-low level jumps, the potential control module controls the signal of the second node according to the second clock signal provided by the second clock end and the signal of the third node, and the potential control module can enhance the voltage holding capacity of the second node. In particular, when the shift register works in a low-frequency mode, the second node may work at a low level or a high level for a long time, then the second clock signal with periodic high-low level jumps can be periodically coupled to the second node, thereby enhancing the voltage holding capacity of the second node so that the second node is kept at the corresponding required level for a long time, reducing the leakage current of the second node, which is conducive to ensuring the output effectiveness, accuracy and stability of the shift register, and further conducive to improving the display quality of the display panel.

[0014] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a shift register provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of a shift register provided for comparison;

[0022] Figure 7 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0023] Figure 8 yes Figure 7 The working timing diagram of the shift register shown;

[0024] Fig. 9 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0025] Fig.10 yes Fig. 9 The working timing diagram of the shift register shown;

[0026] Fig.11 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0027] Fig.12 yes Fig.11 The low frequency operation timing diagram of the shift register in the first display partition is shown;

[0028] Fig.13 yes Fig.11 The high frequency operation timing diagram of the shift register in the second display partition is shown;

[0029] Fig.14 is a schematic diagram of a refresh output portion in another shift register provided by an embodiment of the present invention;

[0030] Fig.15 yes Fig.14 The low frequency operation timing diagram of the shift register in the first display partition is shown;

[0031] Fig.16 yes Fig.14 The high frequency operation timing diagram of the shift register in the second display partition is shown;

[0032] Fig.17 is a schematic diagram of a refresh output portion in another shift register provided by an embodiment of the present invention;

[0033] Fig.18 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention, Figure 3 is a schematic diagram of a shift register provided by an embodiment of the present invention, Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention, Figure 5 is a schematic diagram of another shift register provided by an embodiment of the present invention, with reference to Figures 1 to 5 As shown, the display panel 10 includes: a first driving circuit 11, the first driving circuit 11 includes a multi-stage shift register 12; the shift register 12 includes: a first shift control module 110, electrically connected to the input terminal IN, the first clock terminal CK, the first power supply terminal VG1, the first node N1, the second node N2 and the third node N3, for controlling the signal of the first node N1, the signal of the second node N2 and the signal of the third node N3; a second shift control module 120, electrically connected to the input terminal IN, the first clock terminal CK, the first node N1, the second power supply terminal VG2 and the fourth node N4, for controlling the signal of the fourth node N4; a shift output module 130, electrically connected to the fourth node N4, the second node N2, the first power supply terminal VG1, the second power supply terminal VG2 and the shift output terminal NEXT, for controlling the shift output terminal NEXT to output a shift signal; a potential control module 140, electrically connected to the third node N3, the second clock terminal XCK and the second node N2, for controlling the signal of the second node N2.

[0037] In this embodiment, the shift register 12 includes a first shift control module 110. The first shift control module 110 is electrically connected to the input terminal IN to receive an input signal provided by the input terminal IN; the first shift control module 110 is electrically connected to the first clock terminal CK to receive a first clock signal provided by the first clock terminal CK; the first shift control module 110 is electrically connected to the first power supply terminal VG1 to receive a first power supply signal provided by the first power supply terminal VG1. The first shift control module 110 is also electrically connected to the first node N1, the second node N2, and the third node N3. The first shift control module 110 controls the signal of the first node N1, the signal of the second node N2, and the signal of the third node N3 according to the input signal provided by the input terminal IN, the first clock signal provided by the first clock terminal CK, and the first power supply signal provided by the first power supply terminal VG1, so that the signals of the first node N1, the second node N2, and the third node N3 are changed from high to low level.

[0038] The shift register 12 includes a second shift control module 120. The second power supply terminal VG2 provides a second power supply signal, which is different from the first power supply signal provided by the first power supply terminal VG1, and one of the second power supply signal and the first power supply signal is at a low level and the other is at a high level. The second shift control module 120 controls the signal of the fourth node N4 according to the input signal provided by the input terminal IN, the first clock signal, the signal of the first node N1, and the second power supply signal, so that the signal of the fourth node N4 jumps between high and low levels.

[0039] The shift register 12 includes a potential control module 140. The second clock terminal XCK provides a second clock signal, and the second clock signal provided by the second clock terminal XCK is different from the first clock signal provided by the first clock terminal CK. The second clock signal provided by the second clock terminal XCK undergoes periodic high-low level jumps, and the first clock signal provided by the first clock terminal CK undergoes periodic high-low level jumps. The second clock signal and the first clock signal can optionally have the same frequency, but different phases. The potential control module 140 controls the signal of the second node N2 according to the signal of the third node N3 and the second clock signal provided by the second clock terminal XCK, so that the signal of the second node N2 undergoes high-low level jumps.

[0040] The shift register 12 includes a shift output module 130. The shift output module 130 controls the shift output terminal NEXT to output a shift signal according to the signal of the fourth node N4, the signal of the second node N2, the first power signal of the first power terminal VG1, and the second power signal of the second power terminal VG2, wherein the shift signal includes a valid level and an invalid level, wherein one of the valid level and the invalid level of the shift signal is a high level and the other is a low level.

[0041] Optional, reference Figure 1 to Figure 2As shown, the display panel 10 may further include a plurality of signal lines 20 for providing signals to the first driving circuit 11. Exemplarily, the plurality of signal lines 20 of the display panel 10 at least include an input signal line STV, a first clock signal line CKL1, a second clock signal line CKL2, a first power signal line VL1, and a second power signal line VL2; the input signal line STV provides an input signal to the input terminal IN of at least one stage of the shift register 12; the first clock signal line CKL1 and the second clock signal line CKL2 respectively provide a first clock signal to the first clock terminal CK of the shift register 12 and provide a second clock signal to the second clock terminal XCK of the shift register 12; the first power signal line VL1 provides a first power signal to the first power terminal VG1 of the shift register 12; the second power signal line VL2 provides a second power signal to the second power terminal VG2 of the shift register 12. The display panel 10 may further include a plurality of signal lines 20 of other types, which will not be described in detail herein.

[0042] refer to Figure 2 As shown, the shift output terminal NEXT of the i-th shift register 12 / Gi can be electrically connected to the input terminal IN of the (i+m)-th shift register 12, where m=1, and the shift output terminal NEXT of the i-th shift register 12 / Gi is electrically connected to the input terminal IN of the (i+1)-th shift register 12 / G(i+1). In other embodiments, the shift output terminal of the i-th shift register can also be electrically connected to the input terminal IN of the (i+m)-th shift register, where m can be an integer greater than 1, such as m=2, or m=3, or m=4, or m is equal to other positive integers, not limited to Figure 2 As shown, m=1.

[0043] refer to Figure 4 and Figure 5As shown, the optional shift output module 130 includes: a first output submodule 131 and a second output submodule 132; the first output submodule 131 is electrically connected to the fourth node N4, the second power supply terminal VG2 and the shift output terminal NEXT, and is used to control the shift output terminal NEXT to output a shift signal; the second output submodule 132 is electrically connected to the second node N2, the first power supply terminal VG1 and the shift output terminal NEXT, and is used to control the shift output terminal NEXT to output a shift signal. The optional first output submodule 131 includes: an eleventh transistor M11 and a third capacitor Ca3; the gate of the eleventh transistor M11 is electrically connected to the fourth node N4, the first end of the eleventh transistor M11 is electrically connected to the second power supply terminal VG2, and the second end of the eleventh transistor M11 is electrically connected to the shift output terminal NEXT; the first plate of the third capacitor Ca3 is electrically connected to the fourth node N4, and the second plate of the third capacitor Ca3 is electrically connected to the second power supply terminal VG2. The optional second output submodule 132 includes: a twelfth transistor M12; a gate of the twelfth transistor M12 is electrically connected to the second node N2, a first end of the twelfth transistor M12 is electrically connected to the first power supply terminal VG1, and a second end of the twelfth transistor M12 is electrically connected to the shift output terminal NEXT. Figure 5 As shown, the optional second output submodule 132 includes: a fourth capacitor Ca4; a first plate of the fourth capacitor Ca4 is electrically connected to the second node N2, and a second plate of the fourth capacitor Ca4 is electrically connected to the shift output terminal NEXT.

[0044] In this embodiment, the shift output module 130 includes a first output submodule 131, and the optional first output submodule 131 includes an eleventh transistor M11 and a third capacitor Ca3, and the gate of the eleventh transistor M11 is electrically connected to the fourth node N4; when the signal of the fourth node N4 controls the eleventh transistor M11 to turn on, the second power signal provided by the second power terminal VG2 is written into the shift output terminal NEXT through the turned-on eleventh transistor M11. The shift output module 130 includes a second output submodule 132, and the optional second output submodule 132 includes a twelfth transistor M12, and the gate of the twelfth transistor M12 is electrically connected to the second node N2; when the signal of the second node N2 controls the twelfth transistor M12 to turn on, the first power signal provided by the first power terminal VG1 is written into the shift output terminal NEXT through the turned-on twelfth transistor M12.

[0045] The first output submodule 131 and the second output submodule 132 in the shift output module 130 are turned on in a time-sharing manner.

[0046] The eleventh transistor M11 and the twelfth transistor M12 are both PMOS, the second power supply signal is a high level vgh and the first power supply signal is a low level vgl. Based on this, the signal of the second node N2 is a high level, and after the signal of the fourth node N4 jumps from a high level to a low level, the eleventh transistor M11 is turned on and the twelfth transistor M12 is turned off, and the high level vgh provided by the second power supply terminal VG2 is transmitted through the turned-on eleventh transistor M11 and written to the shift output terminal NEXT. Alternatively, the signal of the fourth node N4 is a high level, and after the signal of the second node N2 jumps from a high level to a low level, the eleventh transistor M11 is turned off and the twelfth transistor M12 is turned on, and the low level vgl provided by the first power supply terminal VG1 is transmitted through the turned-on twelfth transistor M12 and written to the shift output terminal NEXT.

[0047] In other embodiments, at least one of the eleventh transistor and the twelfth transistor can be an NMOS, and the high and low levels of the power signals provided by the first power supply terminal and the second power supply terminal in the corresponding shift output module can be adaptively adjusted, not limited to Figure 4 or Figure 5 shown.

[0048] Figure 6 is a schematic diagram of a shift register provided for comparison, and Figure 5 compared to, Figure 6 The shift register 12a is not provided with the bit control module 140, and accordingly, the shift register 12a is not provided with the third node. Figure 6 In the embodiment, the effective level of the optional shift output terminal NEXT is a high level vgh and the invalid level is a low level. When the shift register 12a outputs an invalid level vgl, the low level of the shift output terminal NEXT is coupled by the fourth capacitor Ca4, so that the potential of the second node N2 is low enough, thereby ensuring that the shift register 12a can normally output the low level vgl.

[0049] Figure 6 In the embodiment, when the shift register 12a works in the low frequency mode, specifically in the data holding stage, the second node N2 of the shift register 12a is at a low level to ensure that the shift output terminal NEXT is kept at a low level vgl for a long time, but in practice the low level of the second node N2 will gradually increase due to leakage, which may cause the low level of the shift output terminal NEXT to rise, thereby causing the output of the shift register 12a to be abnormal. Even if the fourth capacitor Ca4 is increased to enhance the voltage holding capability of the second node N2, the leakage current of the second node N2 increases during the long data holding stage, thereby causing the low level of the second node N2 to still rise, thereby causing the output of the shift register 12a to be abnormal.

[0050] In this embodiment, a potential control module 140 is added between the third node N3 and the second node N2. The potential control module 140 controls the signal of the second node N2 according to the signal of the third node N3 and the second clock signal provided by the second clock terminal XCK, so as to avoid the problem of output abnormality caused by leakage of the second node N2.

[0051] refer to Figure 4 As shown, when the shift register 12 operates in the data holding stage, the second node N2 is at a low level, and the shift output terminal NEXT of the shift register 12 outputs the first power signal vgl.

[0052] After the second clock signal provided by the second clock terminal XCK jumps from a low level to a high level, the potential control module 140 is controlled to be turned off. At this time, the turned-off potential control module 140 blocks the second clock terminal XCK and the second node N2. Then, the high level of the second clock signal will not affect the signal of the second node N2, and the second node N2 remains at a low level.

[0053] After the second clock signal provided by the second clock terminal XCK jumps from a high level to a low level, the potential control module 140 is controlled to be turned on. At this time, the turned-on potential control module 140 connects the second clock terminal XCK and the second node N2. Then, the low level of the second clock signal pulls down the signal of the second node N2 through coupling, so that the second node N2 remains at a low level.

[0054] Therefore, in the present embodiment, a potential control module 140 is provided so that the periodic high and low level jumps of the second clock signal can periodically couple the second node N2. Then, in the data holding stage, the second node N2 can be kept at a low level to avoid the problem that the low level of the second node N2 gradually increases due to leakage. In this way, the output of the shift output terminal NEXT can be guaranteed to be normal. In particular, when the shift register 12 operates in the low-frequency mode, the potential control module 140 can be provided to ensure the output of the shift output terminal NEXT is normal.

[0055] Furthermore, Figure 5 The fourth capacitor Ca4 is added to further enhance the voltage holding capability of the second node N2. It can be understood that in the embodiment of the present invention, the fourth capacitor Ca4 may be provided in the shift register 12, or may not be provided.

[0056] Similarly, in other embodiments, assuming that the twelfth transistor is NMOS, the potential control module is set so that the periodic high and low level jumps of the second clock signal can periodically couple the second node. Then, the second node can be kept at a high level during the data retention stage to avoid the problem of the high level of the second node gradually decreasing due to leakage, thereby ensuring that the output of the shift output end is normal.

[0057] In the present invention, a potential control module is added to the shift register, the potential control module receives the second clock signal provided by the second clock end, the second clock signal has periodic high-low level jumps, the potential control module controls the signal of the second node according to the second clock signal provided by the second clock end and the signal of the third node, and the potential control module can enhance the voltage holding capacity of the second node. In particular, when the shift register works in a low-frequency mode, the second node may work at a low level or a high level for a long time, then the second clock signal with periodic high-low level jumps can be periodically coupled to the second node, thereby enhancing the voltage holding capacity of the second node so that the second node is kept at the corresponding required level for a long time, reducing the leakage current of the second node, which is conducive to ensuring the output effectiveness, accuracy and stability of the shift register, and further conducive to improving the display quality of the display panel.

[0058] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0059] refer to Figures 3 to 5 As shown, in the display panel 10, the shift register 12 includes a first shift control module 110, a second shift control module 120 and a shift output module 130, and the first shift control module 110, the second shift control module 120 and the shift output module 130 constitute a shift output part of the shift register 12, and the shift output part includes an input terminal IN and a shift output terminal NEXT, which is used to control the shift output terminal NEXT to output a shift signal, and the shift signal includes a valid level and an invalid level. In the display panel 10, in the shift register 12, the structural settings of the first shift control module 110, the second shift control module 120 and the shift output module 130 are diverse. Exemplarily, the structure of the first shift control module 110, the second shift control module 120 and the shift output module 130 can be "p*T+k*C", where "T" represents a transistor, "C" represents a storage capacitor, and p and k are constants. Exemplarily, p is 9, k is 2, and the structure of the first shift control module 110, the second shift control module 120, and the shift output module 130 includes 9 transistors and 2 capacitors, but p and k are not limited thereto; for example, p is 7, k is 2, and so on. In the following multiple embodiments, the structure composed of the first shift control module 110, the second shift control module 120, and the shift output module 130 is not specifically limited, and relevant practitioners can adaptively adjust the shift output unit according to needs, which is not limited to the following figure.

[0060] Figure 71 is a schematic diagram of another shift register provided by an embodiment of the present invention, wherein the optional first shift control module 110 includes: a first shift control submodule 111 and a second shift control submodule 112; the first shift control submodule 111 is electrically connected to the input terminal IN, the first clock terminal CK, the first power supply terminal VG1, the first node N1 and the second node N2, and is used to control the signal of the first node N1 and the signal of the second node N2; the second shift control submodule 112 is electrically connected to the input terminal IN, the first clock terminal CK, the first power supply terminal VG1 and the third node N3, and is used to control the signal of the third node N3. The optional first shift control submodule 111 includes: a fourth transistor M4 and a fifth transistor M5; the gate of the fourth transistor M4 is electrically connected to the first clock terminal CK, the first end of the fourth transistor M4 is electrically connected to the input terminal IN, and the second end of the fourth transistor M4 is electrically connected to the first node N1; the gate of the fifth transistor M5 is electrically connected to the first power supply terminal VG1, the first end of the fifth transistor M5 is electrically connected to the first node N1, and the second end of the fifth transistor M5 is electrically connected to the second node N2. The second shift control submodule 112 includes: a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is electrically connected to the first clock terminal CK, the first end of the sixth transistor M6 is electrically connected to the input terminal IN, and the second end of the sixth transistor M6 is electrically connected to the first end of the seventh transistor M7; the gate of the seventh transistor M7 is electrically connected to the first power supply terminal VG1, and the second end of the seventh transistor M7 is electrically connected to the third node N3.

[0061] In this embodiment, the first clock signal provided by the first clock terminal CK controls the fourth transistor M4 and the sixth transistor M6 to be turned on or turned off simultaneously. When the first clock signal provided by the first clock terminal CK controls the fourth transistor M4 and the sixth transistor M6 to be turned on simultaneously, the input signal provided by the input terminal IN is written into the first node N1 through the turned-on fourth transistor M4, and the input signal provided by the input terminal IN is transmitted to the seventh transistor M7 through the turned-on sixth transistor M6.

[0062] The first power signal provided by the first power terminal VG1 controls the fifth transistor M5 and the seventh transistor M7 to remain turned on, so that the signal of the first node N1 is written into the second node N2 through the turned-on fifth transistor M5, and the signal at the output end of the sixth transistor M6 is transmitted to the third node N3 through the seventh transistor M7.

[0063] The optional second shift control module 120 includes: a third shift control submodule 121 and a fourth shift control submodule 122; the third shift control submodule 121 is electrically connected to the input terminal IN, the second power supply terminal VG2 and the sixth node N6, and is used to control the signal of the sixth node N6; the fourth shift control submodule 122 is electrically connected to the sixth node N6, the first clock terminal CK, the second power supply terminal VG2, the first node N1 and the fourth node N4, and is used to control the signal of the fourth node N4. The optional third shift control submodule 121 includes: an eighth transistor M8; the gate of the eighth transistor M8 is electrically connected to the input terminal IN, the first end of the eighth transistor M8 is electrically connected to the second power supply terminal VG2, and the second end of the eighth transistor M8 is electrically connected to the sixth node N6. The optional fourth shift control submodule 122 includes: a ninth transistor M9 and a tenth transistor M10; the gate of the ninth transistor M9 is electrically connected to the sixth node N6, the first end of the ninth transistor M9 is electrically connected to the first clock terminal CK, and the second end of the ninth transistor M9 is electrically connected to the fourth node N4; the gate of the tenth transistor M10 is electrically connected to the first node N1, the first end of the tenth transistor M10 is electrically connected to the second power supply terminal VG2, and the second end of the tenth transistor M10 is electrically connected to the fourth node N4. The fourth shift control submodule 122 includes: a second capacitor Ca2; the first plate of the second capacitor Ca2 is electrically connected to the sixth node N6, and the second plate of the second capacitor Ca2 is electrically connected to the first clock terminal CK.

[0064] In this embodiment, the input signal provided by the input terminal IN controls the eighth transistor M8 to turn on or off. When the input signal provided by the input terminal IN controls the eighth transistor M8 to turn on, the second power signal provided by the second power terminal VG2 is transmitted to the sixth node N6 through the turned-on eighth transistor M8.

[0065] The signal of the sixth node N6 controls the ninth transistor M9 to turn on or off. When the signal of the sixth node N6 controls the ninth transistor M9 to turn on, the first clock signal provided by the first clock terminal CK is written into the fourth node N4. The signal of the first node N1 controls the tenth transistor M10 to turn on or off. When the signal of the first node N1 controls the tenth transistor M10 to turn on, the second power supply signal provided by the second power supply terminal VG2 is transmitted to the fourth node N4 through the turned-on tenth transistor M10.

[0066] The optional potential control module 140 includes: a first electronic control submodule 141 and a second electronic control submodule 142; the first electronic control submodule 141 is electrically connected to the second clock terminal XCK and the third node N3, and is used to control the signal of the third node N3; the second electronic control submodule 142 is electrically connected to the third node N3 and the second node N2, and is used to control the signal of the second node N2.

[0067] The optional first electric control submodule 141 includes: a first electric control unit 141a and a first coupling unit 141b; the first electric control unit 141a is electrically connected to the second clock terminal XCK, the third node N3 and the fifth node N5, and is used to control the signal of the fifth node N5; the first end of the first coupling unit 141b is electrically connected to the fifth node N5, and the second end of the first coupling unit 141b is electrically connected to the third node N3. The optional first electric control unit 141a includes: a first transistor M1; the gate of the first transistor M1 is electrically connected to the third node N3, the first end of the first transistor M1 is electrically connected to the second clock terminal XCK, and the second end of the first transistor M1 is electrically connected to the fifth node N5. The first coupling unit 141b includes: a first capacitor Ca1; the first plate of the first capacitor Ca1 is electrically connected to the fifth node N5, and the second plate of the first capacitor Ca1 is electrically connected to the third node N3.

[0068] The optional second electric control submodule 142 includes: a third transistor M3; a gate and a first end of the third transistor M3 are electrically connected to a third node N3, and a second end of the third transistor M3 is electrically connected to a second node N2.

[0069] In this embodiment, the signal of the third node N3 controls the first transistor M1 to turn on or off. When the signal of the third node N3 controls the first transistor M1 to turn on, the second clock signal provided by the second clock terminal XCK is transmitted to the fifth node N5 through the turned-on first transistor M1, and the signal of the third node N3 can be coupled through the first capacitor Ca1.

[0070] The signal of the third node N3 also controls the third transistor M3 to turn on or off. When the signal of the third node N3 controls the third transistor M3 to turn on, the signal of the third node N3 is written into the second node N2 through the turned-on third transistor M3.

[0071] The first transistor M1 and the third transistor M3 are optionally PMOS. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are optionally PMOS. The eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are optionally PMOS. The eleventh transistor M11 and the twelfth transistor M12 are optionally PMOS. Correspondingly, the first power supply signal provided by the first power supply terminal VG1 is a low level vgl, and the second power supply signal provided by the second power supply terminal VG2 is a high level vgh. However, it is not limited to this, and relevant practitioners can reasonably design the transistors in the circuit and the signals at the signal end according to the product requirements.

[0072] In this embodiment, the phase of the first clock signal provided by the optional first clock terminal VG1 is different from the phase of the second clock signal provided by the second clock terminal XCK. The period of the optional first clock signal is the same as the period of the second clock signal. The phase difference between the optional first clock signal and the second clock signal is 2 / H, where H is the period of the first clock signal.

[0073] The working process of the optional shift register includes: a first stage and a second stage; in the first stage, the transmission path between the first power supply terminal and the shift output terminal in the shift output module is controlled to be conductive, so that the first power supply signal provided by the first power supply terminal is transmitted to the shift output terminal; in the second stage, the transmission path between the second power supply terminal and the shift output terminal in the shift output module is controlled to be conductive, so that the second power supply signal provided by the second power supply terminal is transmitted to the shift output terminal.

[0074] The second clock signal optionally provided by the second clock terminal jumps between a first level signal and a second level signal; in the first stage, when the second clock signal jumps to the first level signal, the potential control module is controlled to be turned on, and when the second clock signal jumps to the second level signal, the potential control module is controlled to be turned off, the first level signal has the same polarity as the signal of the second node, and the second level signal has an opposite polarity to the signal of the second node; in the second stage, the potential control module is turned off.

[0075] In this embodiment, when the first power signal vgl provided by the optional first power terminal VG1 is transmitted to the shift output terminal NEXT, the shift output terminal NEXT outputs an invalid level shift signal; conversely, when the second power signal vgh provided by the second power terminal VG2 is transmitted to the shift output terminal NEXT, the shift output terminal NEXT outputs a valid level shift signal. Then the first stage of the shift register 12 can also be understood as the invalid level output stage of the shift signal, and similarly, the second stage of the shift register 12 can also be understood as the valid level output stage of the shift signal.

[0076] Taking the twelfth transistor M12 as a PMOS as an example, it can be known that in the first stage, the second node N2 is at a low level, and when the second clock signal jumps to a low level with the same signal polarity as the second node N2, the potential control module 140 is turned on, and when the second clock signal jumps to a high level with the opposite signal polarity to the second node N2, the potential control module 140 is turned off; in the second stage, the second node N2 should be at a high level, and the potential control module 140 is turned off.

[0077] In other embodiments, if the twelfth transistor is NMOS, then in the first stage, the second node should be at a high level, and when the second clock signal jumps to a high level with the same signal polarity as the second node, the potential control module is turned on, and when the second clock signal jumps to a low level with an opposite signal polarity to the second node, the potential control module is turned off; in the second stage, the second node is at a low level and the potential control module is turned off.

[0078] Figure 8 yes Figure 7 The shift register working timing diagram is shown in Figure 1. Figure 7 and Figure 8 As shown, the working process of the shift register 12 includes at least the following stages:

[0079] In the t11 stage, the first clock signal provided by the first clock terminal CK is at a high level, the sixth transistor M6 and the fourth transistor M4 are both turned off, the fifth transistor M5 and the seventh transistor M7 remain turned on, the first node N1, the second node N2 and the third node N3 are all maintained at the low level of the previous stage; the eighth transistor M8 is turned off, the sixth node N6 remains at the high level of the previous stage, and the ninth transistor M9 is turned off; the tenth transistor M10 is turned on, the fourth node N4 is at a high level, and the eleventh transistor M11 is turned off; the twelfth transistor M12 is turned on, and the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT. In this stage, the first transistor M1 is turned on, and when the second clock signal provided by the second clock terminal XCK jumps from a high level to a low level, the low level of the node N3b can be pulled down to a lower level through the coupling of the first capacitor Ca1, then the low level of the node N3b controls the third transistor M3 to turn on and the low level of the node N3b is written into the second node N2, ensuring that the twelfth transistor M12 is turned on, that is, when the second clock signal jumps to a low level with the same signal polarity as the second node N2, the potential control module 140 is turned on; sequentially, when the second clock signal provided by the second clock terminal XCK jumps from a low level to a high level, the level of the node N3b (the same as the third node N3) can be pulled up through the coupling of the first capacitor Ca1, then the level of the node N3b is higher than the second node N2, the third transistor M3 is controlled to be turned off, the level of the node N3b does not affect the second node N2, the second node N2 remains at a low level and controls the twelfth transistor M12 to turn on, that is, when the second clock signal jumps to a high level with a signal polarity opposite to that of the second node N2, the potential control module 140 is turned off.

[0080] In the t12 stage, the first clock signal provided by the first clock terminal CK is at a low level, then the sixth transistor M6 and the fourth transistor M4 are turned on at the same time, the fifth transistor M5 and the seventh transistor M7 remain turned on, and the high-level signal provided by the input terminal IN is written into the first node N1, the second node N2 and the third node N3 respectively; the first transistor M1, the third transistor M3, the eighth transistor M8, the tenth transistor M10 and the twelfth transistor M12 are all turned off; the first clock terminal CK pulls down the potential of the sixth node N6 through the second capacitor Ca2 coupling, and the ninth transistor M9 is turned on; the low level of the first clock signal is written into the fourth node N4, and the eleventh transistor M11 is turned on; the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT. That is, in the second stage, the potential control module 140 is turned off.

[0081] In the stage t13, the first clock signal provided by the first clock terminal CK is at a high level, the sixth transistor M6 and the fourth transistor M4 are turned off at the same time, the fifth transistor M5 and the seventh transistor M7 remain turned on, and the first node N1, the second node N2 and the third node N3 all maintain a high level; the first transistor M1, the third transistor M3, the eighth transistor M8, the tenth transistor M10 and the twelfth transistor M12 are all turned off; the first clock terminal CK pulls up the potential of the sixth node N6 through the second capacitor Ca2 coupling, and the ninth transistor M9 is turned off; the fourth node N4 remains at a low level, and the eleventh transistor M11 is turned on; the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT. That is, in the second stage, the potential control module 140 is turned off.

[0082] In the t14 stage, the first clock signal provided by the first clock terminal CK undergoes a high-low level jump, the fifth transistor M5 and the seventh transistor M7 remain turned on, then when the sixth transistor M6 and the fourth transistor M4 are turned on, the low level signal provided by the input terminal IN is written into the first node N1, the second node N2 and the third node N3 respectively; the eighth transistor M8, the tenth transistor M10 and the twelfth transistor M12 are all turned on; the sixth node N6 and the fourth node N4 are both high levels, the ninth transistor M9 and the eleventh transistor M11 are both turned off; the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT. In this stage, the first transistor M1 is turned on, and when the second clock signal provided by the second clock terminal XCK jumps from a high level to a low level, the low level of the node N3b (the same as the third node N3) can be pulled down to a lower level through the coupling of the first capacitor Ca1, then the low level of the node N3b controls the third transistor M3 to turn on and the low level of the node N3b is written into the second node N2, ensuring that the twelfth transistor M12 is turned on, that is, when the second clock signal jumps to a low level with the same signal polarity as the second node N2, the potential control module 140 is turned on; sequentially, when the second clock signal provided by the second clock terminal XCK jumps from a low level to a high level, the level of the node N3b can be pulled up through the coupling of the first capacitor Ca1, then the level of the node N3b is higher than the second node N2, the third transistor M3 is controlled to be turned off, the level of the node N3b does not affect the second node N2, the second node N2 remains at a low level and controls the twelfth transistor M12 to turn on, that is, when the second clock signal jumps to a high level with a signal polarity opposite to that of the second node N2, the potential control module 140 is turned off.

[0083] Optional Figure 7 A fourth capacitor (see Figure 5 As shown, a fourth capacitor Ca4 is provided, and the fourth capacitor can enhance the voltage holding capability of the second node N2.

[0084] As described above, the stage from t12 to t13 is the output stage of the effective level of the shift signal of the shift register 12, i.e., the second stage, and the stage from t14 to t11 of the next frame is the output stage of the invalid level of the shift signal of the shift register 12, i.e., the first stage. Obviously, from the stage t14 of the current frame to the stage t11 of the next frame (the first stage), the second node N2 maintains a relatively low level, and the potential control module 140 is turned on when the second clock signal jumps to a low level, and the potential control module 140 is turned off when the second clock signal jumps to a high level, so that the potential of the second node N2 can be pulled down, and then the twelfth transistor M12 is continuously controlled to be turned on, which is beneficial for the first power supply signal vgl provided by the first power supply terminal VG1 to be transmitted to the shift output terminal NEXT. In particular, when the shift register 12 operates in a low-frequency mode, by adding a potential control module 140 and using a second clock signal with periodic high and low level jumps to periodically couple the second node N2, the low voltage holding capability of the second node N2 can be enhanced and the leakage current of the second node N2 can be reduced, which is beneficial to ensuring the output validity, accuracy and stability of the shift register 12, and further beneficial to improving the display quality of the display panel.

[0085] Fig. 9 is a schematic diagram of another shift register provided by an embodiment of the present invention, and Figure 7 different, Fig. 9 The optional first electric control submodule 141 includes: a second electric control unit 141c; the second electric control unit 141c is electrically connected to the fourth node N4, the third power supply terminal VG3 and the fifth node N5, and is used to control the signal of the fifth node N5. The optional second electric control unit 141c includes: a second transistor M2; the gate of the second transistor M2 is electrically connected to the fourth node N4, the first end of the second transistor M2 is electrically connected to the third power supply terminal VG3, and the second end of the second transistor M2 is electrically connected to the fifth node N5. The third power supply signal provided by the optional third power supply terminal VG3 is a fixed voltage signal. The second power supply signal provided by the optional second power supply terminal VG2 is the same as the third power supply signal.

[0086] In this embodiment, the first electric control submodule 141 includes a first transistor M1, a second transistor M2 and a first capacitor Ca1, wherein the gate of the second transistor M2 is electrically connected to a fourth node N4, the first end of the second transistor M2 is electrically connected to a third power supply terminal VG3, and the second end of the second transistor M2 is electrically connected to a fifth node N5. The signal of the fourth node N4 controls the second transistor M2 to turn on or off. When the signal of the fourth node N4 controls the second transistor M2 to turn on, the third power supply signal provided by the third power supply terminal VG3 is written to the fifth node N5.

[0087] The third power signal provided by the optional third power terminal VG3 is a fixed voltage signal. The second power signal provided by the optional second power terminal VG2 is the same as the third power signal. In this embodiment, the second power signal is a high level vgh, and the third power signal provided by the optional third power terminal VG3 is a high level vgh.

[0088] The working process of the shift register 12 includes a first stage and a second stage.

[0089] Fig.10 yes Fig. 9 The shift register working timing diagram is shown in Figure 1. Fig. 9 and Fig.10 As shown, the working process of the shift register 12 includes at least the following stages:

[0090] In the stage t21, the signals of multiple nodes and the on-off states of transistors are similar to those in the stage t11 and will not be repeated; wherein, the fourth node N4 is at a high level, controlling the second transistor M2 to be turned off.

[0091] In the stage from t22 to t23, the signals of multiple nodes and the on-off states of transistors are similar to those in the stage from t12 to t13, and will not be repeated; wherein, the fourth node N4 is at a low level, controlling the second transistor M2 to turn on, and the third power supply signal vgh provided by the third power supply terminal VG3 is transmitted to the fifth node N5, and the third power supply signal vgh is coupled to the potential of the pull-up node N3b through the first capacitor Ca1 to ensure that the node N3b is at a high level. That is, in the second stage, the potential control module 140 is turned off.

[0092] In the stage t24, the signals of multiple nodes and the on-off states of transistors are similar to those in the stage t14 and will not be repeated; wherein, the fourth node N4 is at a high level, controlling the second transistor M2 to be turned off.

[0093] Optional Fig. 9 A fourth capacitor (see Figure 5 As shown, a fourth capacitor Ca4 is provided, and the fourth capacitor can enhance the voltage holding capability of the second node N2.

[0094] As described above, the stage from t22 to t23 is the output stage of the effective level of the shift signal of the shift register 12. During this stage, the second transistor M2 is turned on, and the third power supply signal vgh provided by the third power supply terminal VG3 can be coupled to the potential of the pull-up node N3b through the first capacitor Ca1, thereby ensuring that the third transistor M3 is turned off, preventing the high and low level jumps of the second clock signal from affecting the potential of the node N3b, further enhancing the voltage holding ability of the second node N2, and reducing the leakage current of the second node N2, which is beneficial to ensuring the output validity, accuracy and stability of the shift register 12, and further beneficial to improving the display quality of the display panel.

[0095] Fig.11 is a schematic diagram of another shift register provided by an embodiment of the present invention, Figure 7 The shift register 12 shown is based on Fig.11 The optional shift register 12 shown also includes a refresh output unit 150, which includes a scan output terminal OUT. The refresh output unit 150 is also electrically connected to a first refresh signal line. The refresh output unit 150 controls the scan output terminal OUT to output a gate drive signal Gout in response to a first refresh control signal Ctrl1 provided by the first refresh signal line. The gate drive signal Gout includes a valid level and an invalid level.

[0096] In this embodiment, the optional refresh output unit 150 is a "5T3C" structure. Exemplarily, the refresh output unit 150 includes a first transistor Mb1, a second transistor Mb2, a third transistor Mb3, a fourth transistor Mb4, and a fifth transistor Mb5, and the refresh output unit 150 also includes a first capacitor Cb1, a second capacitor Cb2, and a third capacitor Cb3. The transistors in the optional refresh output unit 150 are all PMOS.

[0097] A gate of the transistor Mb1 is electrically connected to the node Nb1 , a first terminal of the transistor Mb1 is electrically connected to the fourth node N4 , and a second terminal of the transistor Mb1 is electrically connected to the node Nb2 .

[0098] The gate of transistor Mb2 is electrically connected to the second control terminal B, which can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3 and the node N3b. The first end of transistor Mb2 is electrically connected to the first refresh signal line to receive the first refresh control signal Ctrl1 and the second end is electrically connected to the node Nb1.

[0099] The gate of transistor Mb3 is electrically connected to the first control terminal A, which can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3 and the node N3b. The first end of transistor Mb3 receives the high level signal vgh and the second end is electrically connected to the node Nb2.

[0100] The gate of the transistor Mb4 is electrically connected to the node Nb2, a first terminal of the transistor Mb4 receives the high level signal vgh and a second terminal of the transistor Mb4 is electrically connected to the scan output terminal OUT.

[0101] The gate of the transistor Mb5 is electrically connected to the second node N2, the first end of the transistor Mb5 receives the low level signal vgl and the second end is electrically connected to the scan output terminal OUT.

[0102] One plate of the capacitor Cb1 receives the high level signal vgh and the other plate is electrically connected to the node Nb2.

[0103] One plate of the capacitor Cb2 receives the high level signal vgh or the low level signal vgl, and the other plate of the capacitor Cb2 is electrically connected to the node Nb1.

[0104] One plate of the capacitor Cb3 is electrically connected to the second node N2 and the other plate of the capacitor Cb3 is electrically connected to the scan output terminal OUT.

[0105] based on Fig.11 The shift register 12 shown in the figure can realize partition refresh of the display panel. Specifically, the display panel has a multi-frequency refresh mode; in the multi-frequency refresh mode, the display area of ​​the display panel includes at least a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

[0106] Optionally, in the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the first display partition is greater than the frequency of the gate drive signal; in the multi-frequency refresh mode, the frequency of the gate drive signal of the shift register in the first display partition is less than the frequency of the gate drive signal of the shift register in the second display partition. Therefore, the first display partition works at a low frequency, and the second display partition works at a high frequency. Optionally, in the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the second display partition can be equal to the frequency of the gate drive signal, but is not limited thereto.

[0107] Exemplarily, in the multi-frequency refresh mode, the first refresh frequency of the first display partition is 30 Hz, and the second refresh frequency of the second display partition is 120 Hz. For example, the refresh frequency of the display panel is 120 Hz. Then in the multi-frequency refresh mode, in the first display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 30 Hz; in the second display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 120 Hz.

[0108] Exemplarily, in the multi-frequency refresh mode, the first refresh frequency of the first display partition is 30 Hz, and the second refresh frequency of the second display partition is 60 Hz. For example, the refresh frequency of the display panel is 120 Hz. Then in the multi-frequency refresh mode, in the first display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 30 Hz; in the second display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 60 Hz.

[0109] The working process of the optional shift register 12 includes a data writing stage and a data holding stage; in the data writing stage, the first refresh control signal Ctrl1 provided by the first refresh signal line to the shift register 12 is a valid level, so that the shift signal of the shift register 12 is a valid level and the gate drive signal Gout is a valid level; in the data holding stage, the first refresh control signal Ctrl1 provided by the first refresh signal line to the shift register 12 is an invalid level, so that the shift signal of the shift register 12 is a valid level and the gate drive signal Gout is an invalid level.

[0110] In this embodiment, the effective level of the first refresh control signal Ctrl1 is a low level vgl and the ineffective level of the first refresh control signal Ctrl1 is a high level vgh as an example to illustrate the working principle of the shift register 12. The gate of the optional transistor Mb2 is electrically connected to the shift output terminal NEXT, and the gate of the transistor Mb3 is electrically connected to the second node N2. The high level of the shift signal is an effective level and the low level is an ineffective level, and the high level of the gate drive signal Gout is an effective level and the low level is an ineffective level.

[0111] Fig.11 The second control terminal B can be selected as the shift output terminal NEXT, and the first control terminal A can be selected as the second node N2.

[0112] Fig.12 yes Fig.11 The low frequency operation timing diagram of the shift register in the first display partition is shown. Fig.11 and Fig.12 As shown, in the first display partition, the shift signal frequency of the shift register 12 is greater than the gate drive signal frequency. When the shift signal of the shift register 12 is at a valid level, there is a situation where the gate drive signal of the shift register 12 is at an invalid level, thereby achieving low-frequency operation. Fig.11 The working condition of the shift register 12 in the first display partition is shown. In the stage from t32 to t33, the first refresh control signal Ctrl1 is at a high level vgh, i.e., an invalid level, so that the shift register 12 satisfies the situation that the shift signal is at a valid level and the gate drive signal is at an invalid level.

[0113] refer to Fig.11 and Fig.12 As shown, the low-frequency operation process of the shift register 12 includes:

[0114] In stage t31, the second node N2 is at a low level, and the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on and transistor Mb3 is turned on; node Nb1 is at a high level, transistor Mb1 is turned off; node Nb2 is at a high level, transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0115] From t32 to t33, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; the transistor Mb2 is turned off and the transistor Mb3 is turned off; the node Nb1 remains at a high level, and the transistor Mb1 is turned off; the node Nb2 remains at a high level, and the transistor Mb4 is turned off; the transistor Mb5 is turned off, and the gate drive signal Gout output by the scan output terminal OUT remains at a low level. It can be seen that in this stage, the shift signal is at a valid level and the gate drive signal Gout is at an invalid level.

[0116] During and after stage t34, the second node N2 is at a low level, and the first power signal vgl provided by the first power terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb3 is turned on; node Nb1 is at a high level, and transistor Mb1 is turned off; node Nb2 is at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0117] As described above, when the shift register 12 operates in the low frequency mode, the high level signal provided by the first refresh signal line can keep the node Nb1 at the high level vgh, and keep the gate drive signal Gout of the scan output terminal OUT at the low level vgl. This effectively enhances the circuit stability and effectiveness of the shift register 12 operating in the low frequency mode.

[0118] Fig.13 yes Fig.11 The high-frequency operation timing diagram of the shift register in the second display partition is shown. Fig.11 and Fig.13 As shown, in the optional second display partition, the shift signal frequency of the shift register 12 is equal to the gate drive signal frequency. Then, when the shift signal of the shift register 12 is at an effective level, the gate drive signal of the shift register 12 is at an effective level, thereby achieving high-frequency operation. Fig.11The working condition of the shift register 12 in the second display partition is shown. In the stage from t42 to t43, the first refresh control signal Ctrl1 is at a low level vgl, i.e., a valid level, so that the shift register 12 satisfies the conditions that the shift signal is at a valid level and the gate drive signal is at a valid level.

[0119] refer to Fig.11 and Fig.13 As shown, the high-frequency operation process of the shift register 12 includes:

[0120] In stage t41, the second node N2 is at a low level, and the first power signal vgl provided by the first power terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on and transistor Mb3 is turned on; node Nb1 is at a low level, transistor Mb1 is turned on; node Nb2 is at a high level, transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0121] From t42 to t43, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; the transistor Mb2 is turned off and the transistor Mb3 is turned off; the node Nb1 remains at a low level, and the transistor Mb1 is turned on; the node Nb2 is at a low level, and the transistor Mb4 is turned on; the transistor Mb5 is turned off, and the gate drive signal Gout outputted by the scan output terminal OUT is at a high level. It can be seen that in this stage, the shift signal is at a valid level and the gate drive signal Gout is at a valid level.

[0122] During and after stage t44, the second node N2 is at a low level, and the first power signal vgl provided by the first power terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb3 is turned on; node Nb1 is at a low level, and transistor Mb1 is turned on; node Nb2 is at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0123] As described above, when the shift register 12 operates in the high frequency mode, the circuit stability and effectiveness of the shift register 12 operating in the high frequency mode are improved.

[0124] Fig.14 is a schematic diagram of a refresh output unit in another shift register provided by an embodiment of the present invention, and Fig.11 The difference is that, Fig.14 The optional refresh output section 150 is shown as a "6T4C" structure and includes two refresh signal lines. Fig.14 Only the refresh output unit 150 in the shift register 12 is shown, and other structures of the shift register 12 can be referred to Fig.11 As shown, it will not be repeated here.

[0125] Specifically, the refresh output unit 150 includes a transistor Mb1, a transistor Mb2, a transistor Mb4, a transistor Mb5, a capacitor Cb1, a capacitor Cb2 and a capacitor Cb3. The connection method of the four transistors and the three capacitors is similar to Fig.11 same.

[0126] and Fig.11 The difference is that the refresh output unit 150 also includes a transistor Mb31, a transistor Mb6 and a fourth capacitor Cb4. Among them, the gate of the transistor Mb6 is electrically connected to the second control terminal B, and the second control terminal B can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3 and the node N3b. The first end of the transistor Mb6 is electrically connected to the second refresh signal line to receive the second refresh control signal Ctrl2, and the second end of the transistor Mb6 is electrically connected to the gate of the transistor Mb31. The first plate of the capacitor Cb4 is electrically connected to the gate of the transistor Mb31, and the second plate of the capacitor Cb4 can receive a high level signal vgh and a low level signal vgl. The first end of the transistor Mb31 receives the high level signal vgh and the second end is electrically connected to the node Nb2.

[0127] The control signal Ctrl2 provided by the optional second refresh signal line is different from the control signal Ctrl1 provided by the first refresh signal line. The control signal Ctrl2 provided by the optional second refresh signal line and the control signal Ctrl1 provided by the first refresh signal line are both high-low level transition signals, and the two are in opposite phases.

[0128] Fig.14 The second control terminal B can be selected as the shift output terminal NEXT.

[0129] based on Fig.14 With the shift register 12 shown, the display panel can achieve partition refresh.

[0130] Fig.15 yes Fig.14 The low frequency operation timing diagram of the shift register in the first display partition is shown. Fig.14 and Fig.15 As shown, in the first display partition, the shift signal frequency of the shift register 12 is greater than the gate drive signal frequency. When the shift signal of the shift register 12 is at a valid level, there is a situation where the gate drive signal of the shift register 12 is at an invalid level, thereby achieving low-frequency operation. Fig.14The working condition of the shift register 12 in the first display partition is shown. In the stage from t52 to t53, the first refresh control signal Ctrl1 is a high level vgh, that is, an invalid level, and the second refresh control signal Ctrl2 is a low level vgl, that is, a valid level, so that the shift register 12 satisfies the situation that the shift signal is a valid level and the gate drive signal is an invalid level.

[0131] refer to Fig.14 and Fig.15 As shown, the low-frequency operation process of the shift register 12 includes:

[0132] In the t51 stage, the second node N2 is at a low level, and the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; the transistor Mb2 is turned on, and the high level vgh of the first refresh control signal Ctrl1 is written into the node Nb1, and the transistor Mb1 is turned off; the transistor Mb6 is turned on, and the low level vgl of the second refresh control signal Ctrl2 is written into the node Nb21, and the transistor Mb31 is turned on; the node Nb2 is at a high level, and the transistor Mb4 is turned off; the transistor Mb5 is turned on, and the gate drive signal Gout outputted by the scan output terminal OUT is at a low level vgl.

[0133] From t52 to t53, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; the transistor Mb2 is turned off and the transistor Mb6 is turned off; the node Nb1 remains at a high level, and the transistor Mb1 is turned off; the node Nb21 remains at a low level, and the transistor Mb31 is turned on; the node Nb2 remains at a high level, and the transistor Mb4 is turned off; the transistor Mb5 is turned off, and the gate drive signal Gout output by the scan output terminal OUT remains at a low level. It can be seen that in this stage, the shift signal is at a valid level and the gate drive signal Gout is at an invalid level.

[0134] During and after stage t54, the second node N2 is at a low level, and the first power signal vgl provided by the first power terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb6 is turned on; node Nb1 is at a high level, and transistor Mb1 is turned off; node Nb21 is at a low level, transistor Mb31 is turned on, node Nb2 is at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0135] As described above, when the shift register 12 operates in the low-frequency mode, the high-level signal provided by the first refresh signal line can keep the node Nb1 at a high level vgh, and the low-level signal provided by the second refresh signal line can keep the node Nb21 at a low level vgl, and the corresponding transistor Mb31 is turned on to keep the node Nb2 at a high level, and the transistor Mb4 is kept off, so that the gate drive signal Gout of the scan output terminal OUT is kept at a low level vgl. This effectively enhances the circuit stability and effectiveness of the shift register 12 operating in the low-frequency mode.

[0136] Fig.16 yes Fig.14 The high-frequency operation timing diagram of the shift register in the second display partition is shown. Fig.14 and Fig.16 As shown, in the optional second display partition, the shift signal frequency of the shift register 12 is equal to the gate drive signal frequency. Then, when the shift signal of the shift register 12 is at an effective level, the gate drive signal of the shift register 12 is at an effective level, thereby achieving high-frequency operation. Fig.14 The working condition of the shift register 12 in the second display partition is shown. In the stage from t62 to t63, the first refresh control signal Ctrl1 is a low level vgl, i.e., a valid level, and the second refresh control signal Ctrl2 is a high level vgh, i.e., an invalid level, so that the shift register 12 satisfies the situation that the shift signal is a valid level and the gate drive signal is a valid level.

[0137] refer to Fig.14 and Fig.16 As shown, the high-frequency operation process of the shift register 12 includes:

[0138] In the t61 stage, the second node N2 is at a low level, and the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; the transistor Mb2 is turned on, and the low level vgl of the first refresh control signal Ctrl1 is written into the node Nb1, the transistor Mb1 is turned on, and the high level of the fourth node N4 is written into the node Nb2; the transistor Mb6 is turned on, and the high level vgh of the second refresh control signal Ctrl2 is written into the node Nb21, and the transistor Mb31 is turned off; the node Nb2 is at a high level, and the transistor Mb4 is turned off; the transistor Mb5 is turned on, and the gate drive signal Gout outputted by the scan output terminal OUT is at a low level vgl.

[0139] From t62 to t63, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; the transistor Mb2 is turned off and the transistor Mb6 is turned off; the node Nb1 remains at a low level, and the transistor Mb1 is turned on; the node Nb21 remains at a high level, and the transistor Mb31 is turned off; the low level of the fourth node N4 is written to the node Nb2, and the transistor Mb4 is turned on; the transistor Mb5 is turned off, and the gate drive signal Gout output by the scan output terminal OUT is at a high level. It can be seen that in this stage, the shift signal is at a valid level and the gate drive signal Gout is at a valid level.

[0140] During and after stage t64, the second node N2 is at a low level, and the first power signal vgl provided by the first power terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb6 is turned on; node Nb1 is at a low level, and transistor Mb1 is turned on; node Nb21 is at a high level, and transistor Mb31 is turned off; the high level of the fourth node N4 is written into node Nb2, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0141] As described above, when the shift register 12 operates in the high frequency mode, the circuit stability and effectiveness of the shift register 12 operating in the high frequency mode are improved.

[0142] Fig.17 is a schematic diagram of a refresh output unit in another shift register provided by an embodiment of the present invention, and Fig.14 The difference is that, Fig.17 The optional refresh output section 150 is shown as a "7T4C" structure. Fig.17 Only the refresh output unit 150 in the shift register 12 is shown, and other structures of the shift register 12 can be referred to Fig.11 As shown, it will not be repeated here.

[0143] Specifically, the refresh output unit 150 includes a transistor Mb1, a transistor Mb2, a transistor Mb31, a transistor Mb4, a transistor Mb5, a transistor Mb6, a capacitor Cb1, a capacitor Cb2, a capacitor Cb3 and a capacitor Cb4. The connection method of the six transistors and the four capacitors is the same as Fig.14 same.

[0144] and Fig.14 The difference is that a transistor Mb32 is newly added in the refresh output unit 150, and the gate of the transistor Mb32 is electrically connected to the first control terminal A, which can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3 and the node N3b. The first end of the transistor Mb32 receives a high-level signal vgh and the second end is electrically connected to the node Nb2.

[0145] Fig.17 The low-frequency operation timing of the shift register can be referred to Fig.15 As shown, Fig.17 The high-frequency working timing of the shift register can be referred to Fig.16 shown.

[0146] The inventor has found through research that the refresh output unit of the shift register of the present invention is not limited to the above structure, and any refresh output unit falls within the scope of the present invention under the premise of ensuring the normal operation of the shift register and stable and effective output.

[0147] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention. Therefore, the display device has the technical features of the display panel and the driving process provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by the embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0148] For example, Fig.18 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.18 As shown, the display device 1 includes a display panel 10 provided in an embodiment of the present invention. The display device 1 provided in an embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0149] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0150] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: a first driving circuit, wherein the first driving circuit comprises a multi-stage shift register; The shift register comprises: A first shift control module, electrically connected to the input terminal, the first clock terminal, the first power terminal, the first node, the second node and the third node, and used to control a signal of the first node, a signal of the second node and a signal of the third node; a second shift control module, electrically connected to the input terminal, the first clock terminal, the first node, the second power terminal and the fourth node, and used to control a signal of the fourth node; a shift output module, electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal and the shift output terminal, and used for controlling the shift output terminal to output a shift signal; A potential control module is electrically connected to the third node, the second clock terminal and the second node, and is used to control the signal of the second node.

2. The display panel according to claim 1, characterized in that: The potential control module includes: a first electric control submodule and a second electric control submodule; The first electronic control submodule is electrically connected to the second clock terminal and the third node, and is used to control the signal of the third node; The second electronic control submodule is electrically connected to the third node and the second node, and is used to control a signal of the second node.

3. The display panel according to claim 2, characterized in that: The first electronic control submodule includes: a first electronic control unit and a first coupling unit; The first electronic control unit is electrically connected to the second clock terminal, the third node and the fifth node, and is used to control the signal of the fifth node; A first end of the first coupling unit is electrically connected to the fifth node, and a second end of the first coupling unit is electrically connected to the third node.

4. The display panel according to claim 3, characterized in that: The first electronic control unit includes: a first transistor; A gate of the first transistor is electrically connected to the third node, a first terminal of the first transistor is electrically connected to the second clock terminal, and a second terminal of the first transistor is electrically connected to the fifth node.

5. The display panel according to claim 3, characterized in that: The first coupling unit includes: a first capacitor; The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the third node.

6. The display panel according to claim 1, characterized in that: A phase of a first clock signal provided by the first clock terminal is different from a phase of a second clock signal provided by the second clock terminal.

7. The display panel according to claim 6, characterized in that: A period of the first clock signal is the same as a period of the second clock signal.

8. The display panel according to claim 7, characterized in that: The phase difference between the first clock signal and the second clock signal is 2 / H, where H is the period of the first clock signal.

9. The display panel according to claim 3, characterized in that: The first electronic control submodule includes: a second electronic control unit; The second electronic control unit is electrically connected to the fourth node, the third power supply terminal and the fifth node, and is used to control the signal of the fifth node.

10. The display panel according to claim 9, characterized in that: The second electronic control unit includes: a second transistor; A gate of the second transistor is electrically connected to the fourth node, a first terminal of the second transistor is electrically connected to the third power supply terminal, and a second terminal of the second transistor is electrically connected to the fifth node.

11. The display panel according to claim 9, characterized in that: The third power signal provided by the third power terminal is a fixed voltage signal.

12. The display panel according to claim 11, characterized in that: The second power signal provided by the second power terminal is the same as the third power signal.

13. The display panel according to claim 2, characterized in that: The second electronic control submodule includes: a third transistor; The gate and the first terminal of the third transistor are both electrically connected to the third node, and the second terminal of the third transistor is electrically connected to the second node.

14. The display panel according to claim 1, characterized in that: The first shift control module includes: a first shift control submodule and a second shift control submodule; The first shift control submodule is electrically connected to the input terminal, the first clock terminal, the first power terminal, the first node and the second node, and is used to control a signal of the first node and a signal of the second node; The second shift control submodule is electrically connected to the input terminal, the first clock terminal, the first power terminal and the third node, and is used to control a signal of the third node.

15. The display panel according to claim 14, characterized in that: The first shift control submodule includes: a fourth transistor and a fifth transistor; The gate of the fourth transistor is electrically connected to the first clock terminal, the first terminal of the fourth transistor is electrically connected to the input terminal, and the second terminal of the fourth transistor is electrically connected to the first node; A gate of the fifth transistor is electrically connected to the first power supply terminal, a first terminal of the fifth transistor is electrically connected to the first node, and a second terminal of the fifth transistor is electrically connected to the second node.

16. The display panel according to claim 14, characterized in that: The second shift control submodule includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is electrically connected to the first clock terminal, the first terminal of the sixth transistor is electrically connected to the input terminal, and the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor; A gate of the seventh transistor is electrically connected to the first power supply terminal, and a second terminal of the seventh transistor is electrically connected to the third node.

17. The display panel according to claim 1, characterized in that: The second shift control module includes: a third shift control submodule and a fourth shift control submodule; The third shift control submodule is electrically connected to the input terminal, the second power terminal and the sixth node, and is used to control the signal of the sixth node; The fourth shift control submodule is electrically connected to the sixth node, the first clock terminal, the second power terminal, the first node and the fourth node, and is used to control the signal of the fourth node.

18. The display panel according to claim 17, characterized in that: The third shift control submodule comprises: an eighth transistor; A gate of the eighth transistor is electrically connected to the input terminal, a first terminal of the eighth transistor is electrically connected to the second power terminal, and a second terminal of the eighth transistor is electrically connected to the sixth node.

19. The display panel according to claim 17, characterized in that: The fourth shift control submodule includes: a ninth transistor and a tenth transistor; The gate of the ninth transistor is electrically connected to the sixth node, the first terminal of the ninth transistor is electrically connected to the first clock terminal, and the second terminal of the ninth transistor is electrically connected to the fourth node; A gate of the tenth transistor is electrically connected to the first node, a first terminal of the tenth transistor is electrically connected to the second power supply terminal, and a second terminal of the tenth transistor is electrically connected to the fourth node.

20. The display panel according to claim 17, characterized in that: The fourth shift control submodule includes: a second capacitor; The first plate of the second capacitor is electrically connected to the sixth node, and the second plate of the second capacitor is electrically connected to the first clock end.

21. The display panel according to claim 1, characterized in that: The shift output module comprises: a first output submodule and a second output submodule; The first output submodule is electrically connected to the fourth node, the second power supply terminal and the shift output terminal, and is used to control the shift output terminal to output the shift signal; The second output submodule is electrically connected to the second node, the first power supply terminal and the shift output terminal, and is used to control the shift output terminal to output the shift signal.

22. The display panel according to claim 21, characterized in that: The first output submodule includes: an eleventh transistor and a third capacitor; The gate of the eleventh transistor is electrically connected to the fourth node, the first terminal of the eleventh transistor is electrically connected to the second power supply terminal, and the second terminal of the eleventh transistor is electrically connected to the shift output terminal; The first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the second power supply terminal.

23. The display panel according to claim 21, characterized in that: The second output submodule includes: a twelfth transistor; A gate of the twelfth transistor is electrically connected to the second node, a first terminal of the twelfth transistor is electrically connected to the first power supply terminal, and a second terminal of the twelfth transistor is electrically connected to the shift output terminal.

24. The display panel according to claim 23, characterized in that: The second output submodule includes: a fourth capacitor; The first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is electrically connected to the shift output terminal.

25. The display panel according to claim 1, characterized in that: The working process of the shift register includes: a first stage and a second stage; In the first stage, controlling the transmission path between the first power supply terminal and the shift output terminal in the shift output module to be turned on, so that the first power supply signal provided by the first power supply terminal is transmitted to the shift output terminal; In the second stage, the transmission path between the second power supply terminal and the shift output terminal in the shift output module is controlled to be conductive, so that the second power supply signal provided by the second power supply terminal is transmitted to the shift output terminal.

26. The display panel according to claim 25, characterized in that: The second clock signal provided by the second clock terminal jumps between a first level signal and a second level signal; In the first stage, when the second clock signal jumps to the first level signal, the potential control module is controlled to be turned on, and when the second clock signal jumps to the second level signal, the potential control module is controlled to be turned off, the first level signal has the same polarity as the signal of the second node, and the second level signal has an opposite polarity to the signal of the second node; In the second stage, the potential control module is turned off.

27. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 26.

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