Shifting register and driving method thereof, gate driving circuit and display device

Abstract

The invention provides a shift register and a driving method thereof, a gate driving circuit and a display device, and relates to the technical field of display, the shift register comprises an input sub-circuit which is electrically connected with a first control end, a signal input end, a first node and a second node; the control sub-circuit is electrically connected with the second control end, the first node, the second node, the third node and the fourth node; the output sub-circuit is electrically connected with the first power supply end, the second power supply end, the third node, the fourth node and the signal output end respectively; and the reset sub-circuit is electrically connected with a third control end, a third power supply end and a third node, and is configured to respond to a third control signal input by the third control end, and conduct the third power supply end and the third node, so that the signal of the third node disconnects the connection between the first power supply end and the signal output end. The stability of output signals can be improved, and poor display phenomena such as cross grains and cross bands of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] The thin film transistor (TFT) in the driving circuit may have characteristic fluctuations. If the fluctuation amplitude is large, it is easy to cause the waveform of the output signal of the driving circuit to fluctuate. For example, in the gate driving circuit, due to the unstable characteristics of TFT, the waveform of the circuit output signal is prone to step voltage.

[0003] The output signal of the gate drive circuit is provided to the pixel drive circuit of the display panel to control the corresponding TFT in the pixel drive circuit to turn on or off. If there is a step voltage in the signal waveform, it is easy to cause brightness differences in different pixel rows of the display panel, resulting in display defects such as horizontal stripes and horizontal bands. Summary of the invention

[0004] The present application provides a shift register and a driving method thereof, a gate driving circuit, and a display device, which can solve the problem of fluctuation in the output signal waveform of the existing gate driving circuit.

[0005] In a first aspect, the present application provides a shift register, the shift register comprising:

[0006] An input subcircuit, electrically connected to the first control terminal, the signal input terminal, the first node and the second node, respectively, and configured to control the potential of the first node and the second node respectively in response to a first control signal inputted from the first control terminal;

[0007] a control subcircuit, electrically connected to the second control terminal, the first node, the second node, the third node and the fourth node, respectively, and configured to control the potentials of the third node and the fourth node respectively in response to a signal of the first node, a signal of the second node and a second control signal inputted from the second control terminal;

[0008] an output subcircuit, electrically connected to the first power supply terminal, the second power supply terminal, the third node, the fourth node and the signal output terminal, respectively, and configured to control the connection and disconnection between the first power supply terminal and the signal output terminal in response to a signal of the third node, and to control the connection and disconnection between the second power supply terminal and the signal output terminal in response to a signal of the fourth node;

[0009] A reset subcircuit is electrically connected to the third control terminal, the third power supply terminal and the third node, respectively, and is configured to connect the third power supply terminal and the third node in response to a third control signal input from the third control terminal, so that the signal at the third node disconnects the connection between the first power supply terminal and the signal output terminal.

[0010] Optionally, the control subcircuit includes:

[0011] a first control module, electrically connected to the first node, the second node and the third node respectively, and configured to control the potential of the third node in response to a signal of the second node; wherein the reset subcircuit is electrically connected to the third node via the first node;

[0012] The second control module is electrically connected to the second control terminal, the first node, the second node and the fourth node, respectively, and is configured to control the potential of the fourth node in response to the signal of the first node, the signal of the second node and the second control signal input from the second control terminal.

[0013] Optionally, the reset subcircuit comprises a first transistor;

[0014] The control electrode of the first transistor is electrically connected to the third control terminal, the first electrode of the first transistor is electrically connected to the third power supply terminal, and the second electrode of the first transistor is electrically connected to the third node through the first node.

[0015] Optionally, the reset subcircuit includes a second transistor;

[0016] The control electrode of the second transistor is electrically connected to the third control terminal, the first electrode of the second transistor is electrically connected to the third power supply terminal, and the second electrode of the second transistor is electrically connected to the third node.

[0017] Optionally, the third control end multiplexes the signal output end.

[0018] Optionally, the effective level state corresponding to the second transistor is opposite to the level state corresponding to the power supply voltage of the first power supply terminal.

[0019] In a second aspect, the present application provides a gate driving circuit, comprising: N shift registers as described in the first aspect; N shift registers are cascaded;

[0020] The signal input terminal of the shift register of the first stage is used to receive a scan start signal;

[0021] The signal output terminal of the shift register at the n-1th stage is electrically connected to the signal input terminal of the shift register at the nth stage; wherein, 2≤n≤N, and N and n are positive integers respectively.

[0022] In a third aspect, the present application provides a display device, the display device comprising: a pixel, and a shift register as described in the first aspect;

[0023] The pixel comprises a pixel circuit and a light emitting element coupled to the pixel circuit. The pixel circuit comprises a drive control transistor. The signal output terminal of the shift register is electrically connected to the control electrode of the drive control transistor.

[0024] In a third aspect, the present application provides a shift register driving method for controlling the shift register as described in the first aspect, the method comprising:

[0025] In the target frame, a third control signal with a first level is sent to the third control terminal so that the third control signal with the first level turns on the third power terminal and the third node, and disconnects the connection between the first power terminal and the signal output terminal based on the signal of the third node.

[0026] Optionally, in the target frame, sending a third control signal having a first level to the third control terminal includes:

[0027] In at least one frame before the shift register is powered off, the third control signal having the first level is sent to the third control terminal.

[0028] Optionally, sending the third control signal having the first level to the third control terminal in at least one frame before the shift register is powered off includes:

[0029] In the last frame before the shift register is powered off, the third control signal with the first level is sent to the third control terminal; wherein the duration of the last frame is greater than or equal to 3 times the unit scan duration and less than or equal to 10 times the unit scan duration.

[0030] Optionally, in the target frame, sending a third control signal having a first level to the third control terminal includes:

[0031] The third control signal having the first level is sent to the third control terminal in at least one frame before the shift register refresh frame.

[0032] Optionally, in the target frame, sending a third control signal having a first level to the third control terminal includes:

[0033] During a blanking phase of a refresh frame, the third control signal having the first level is sent to the third control terminal.

[0034] Optionally, sending the third control signal having the first level to the third control terminal during the blanking phase of the refresh frame includes:

[0035] In the blanking phase, after continuously sending the third control signal with the second level to the third control terminal for a first time period, switching to sending the third control signal with the first level to the third control terminal;

[0036] Before the second time period to the next display stage, the third control signal with the second level is switched to be sent to the third control terminal.

[0037] Optionally, in the target frame, sending a third control signal having a first level to the third control terminal includes:

[0038] In a refresh frame, the output signal of the signal output terminal is sent to the third control terminal as the third control signal; wherein the output signal includes a level state corresponding to the first level.

[0039] A shift register and a driving method thereof, a gate driving circuit, and a display device provided by the present application have at least the following advantages: the shift register comprises: an input subcircuit, electrically connected to a first control terminal, a signal input terminal, a first node, and a second node, respectively, and configured to control the potential of the first node and the second node respectively in response to a first control signal input from the first control terminal; a control subcircuit, electrically connected to a second control terminal, a first node, a second node, a third node, and a fourth node, respectively, and configured to control the potential of the third node and the fourth node respectively in response to a signal of the first node, a signal of the second node, and a second control signal input from the second control terminal; The output subcircuit is electrically connected to the first power supply terminal, the second power supply terminal, the third node, the fourth node and the signal output terminal, respectively, and is configured to control the on-off of the first power supply terminal and the signal output terminal in response to the signal of the third node, and to control the on-off of the second power supply terminal and the signal output terminal in response to the signal of the fourth node; the reset subcircuit is electrically connected to the third control terminal, the third power supply terminal and the third node, respectively, and is configured to conduct the third power supply terminal and the third node in response to the third control signal input by the third control terminal, so that the signal of the third node disconnects the connection between the first power supply terminal and the signal output terminal. In this way, the third node can be reset by the reset subcircuit, so that the signal of the third node disconnects the connection between the first power supply terminal and the signal output terminal, avoiding the output signal of the signal output terminal from having a step voltage, thereby improving the stability of the output signal, reducing the brightness difference between different rows of the display panel, and improving the display defects such as horizontal stripes and horizontal bands of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 is a structural schematic diagram of a shift register provided in an embodiment of the present application;

[0042] Figure 2 It is a structural schematic diagram of an 8T pixel driving circuit in the related art;

[0043] Figure 3 is a driving timing diagram corresponding to an 8T pixel driving circuit in the related art;

[0044] Figure 4 is a waveform diagram of GateN, ResetP and node N1 in the related art;

[0045] Figure 5 It is one of the transistor-level schematic diagrams of a shift register provided in an embodiment of the present application;

[0046] Figure 6 yes Figure 5 The driving timing diagram corresponding to the shift register shown;

[0047] Figure 7 This is the second transistor-level schematic diagram of a shift register provided in an embodiment of the present application;

[0048] Figure 8 This is the third transistor-level schematic diagram of a shift register provided in an embodiment of the present application;

[0049] Fig. 9 It is a schematic diagram of the steps of a shift register driving method provided in an embodiment of the present application;

[0050] Fig.10 This is one of the timing diagrams of a driving method provided in an embodiment of the present application;

[0051] Fig.11 This is the second timing diagram of a driving method provided in an embodiment of the present application;

[0052] Fig.12 This is the third timing diagram of a driving method provided in an embodiment of the present application;

[0053] Fig.13 This is the fourth timing diagram of a driving method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in some embodiments to clearly and completely describe the technical solutions in some embodiments. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] In some embodiments, a plurality of signals have a first level and a second level. The first level and the second level only represent that the level of the signal has two states, and do not represent that the first level or the second level has a specific value.

[0056] In some embodiments, the transistors used in the shift register 10 may be thin film transistors TFT or metal oxide semiconductor (MOS) field effect transistors, for example, N-channel TFT or P-channel TFT, which is not limited in the embodiments of the present application.

[0057] Figure 1 is a structural diagram of a shift register 10 provided in an embodiment of the present application, such as Figure 1 As shown, the shift register 10 comprises:

[0058] The input sub-circuit 101 is electrically connected to the first control terminal CK, the signal input terminal Input, the first node N1 and the second node N2, respectively, and is configured to control the potential of the first node N1 and the second node N2 in response to the first control signal inputted from the first control terminal CK;

[0059] The control subcircuit 102 is electrically connected to the second control terminal CB, the first node N1, the second node N2, the third node N7 and the fourth node N4, respectively, and is configured to control the potentials of the third node N7 and the fourth node N4 respectively in response to the signal of the first node N1, the signal of the second node N2 and the second control signal input from the second control terminal CB;

[0060] The output sub-circuit 103 is electrically connected to the first power supply terminal, the second power supply terminal, the third node N7, the fourth node N4 and the signal output terminal Out, respectively, and is configured to control the connection and disconnection of the first power supply terminal and the signal output terminal Out in response to the signal of the third node N7, and to control the connection and disconnection of the second power supply terminal and the signal output terminal Out in response to the signal of the fourth node N4;

[0061] The reset sub-circuit 104 is electrically connected to the third control terminal NCX, the third power supply terminal and the third node N7, respectively, and is configured to respond to a third control signal input to the third control terminal NCX, turn on the third power supply terminal and the third node N7, so that the signal of the third node N7 disconnects the connection between the first power supply terminal and the signal output terminal Out.

[0062] In some embodiments, the input subcircuit 101 includes a first input module and a second input module. The first input module is electrically connected to the first control terminal CK, the signal input terminal Input and the first node N1, respectively, and is configured to control the connection and disconnection between the signal input terminal Input and the first node N1 in response to a first control signal, thereby controlling the potential of the first node N1. The second input module is electrically connected to the first control terminal CK, the power supply terminal and the second node N2, respectively, and is configured to control the connection and disconnection between the power supply terminal and the second node N2 in response to the first control signal, thereby controlling the potential of the second node N2. Among them, the power supply terminal can be a VGH power supply terminal or a VGL power supply terminal, which is not limited in the embodiments of the present application.

[0063] Optionally, the control subcircuit 102 includes:

[0064] The first control module is electrically connected to the first node N1, the second node N2 and the third node N7 respectively, and is configured to control the potential of the third node N7 in response to the signal of the second node N2; wherein the reset subcircuit 104 is electrically connected to the third node N7 through the first node N1;

[0065] The second control module is electrically connected to the second control terminal CB, the first node N1, the second node N2 and the fourth node N4, respectively, and is configured to control the potential of the fourth node N4 in response to the signal of the first node N1, the signal of the second node N2 and the second control signal input from the second control terminal CB.

[0066] In some embodiments, the control subcircuit 102 includes a first control module and a second control module. The first control module is electrically connected to the first node N1, the second node N2 and the third node N7 respectively, and is configured to control the potential of the third node N7 in response to a signal at the second node N2.

[0067] Wherein, the first control module may further include a pull-down control unit and a pull-down unit. The pull-down control unit is electrically connected to the second node N2 and the fifth node N9, respectively, and is configured to control the potential of the fifth node N9 in response to the signal of the second node N2. The pull-down unit is electrically connected to the first node N1, the third node N7 and the fifth node N9, respectively, and is configured to control the connection and disconnection of the node N8 and the third node N7 in response to the signal of the fifth node N9, thereby controlling the potential of the third node N7. In addition, the first input module in the input subcircuit 101 is also electrically connected to the node N8, and is configured to control the connection and disconnection of the signal input terminal Input and the node N8 in response to the first control signal, thereby controlling the potential of the node N8.

[0068] In some embodiments, the pull-down unit further includes an isolation transistor, which is disposed between the first node N1 and the third node N7, and is a normally open transistor. In this embodiment, the reset subcircuit 104 is electrically connected to the first node N1, so that the reset subcircuit 104 controls the potential of the third node N7 through the first node N1.

[0069] In some embodiments, the second control module is electrically connected to the second control terminal CB, the first node N1, the second node N2 and the fourth node N4, respectively, and is configured to control the potential of the fourth node N4 in response to the signal of the first node N1, the signal of the second node N2 and the second control signal input into the second control terminal CB.

[0070] The second control module includes a first control unit and a second control unit. The first control unit is electrically connected to the first node N1, the power supply terminal and the fourth node N4, respectively, and is configured to control the on-off of the power supply terminal and the fourth node N4 in response to the signal of the first node N1. The power supply terminal can be a VGH power supply terminal or a VGL power supply terminal. The second control unit is electrically connected to the second control terminal CB, the second node N2 and the fourth node N4, respectively, and is configured to control the potential of the fourth node N4 in response to the signal of the second node N2 and the second control signal input by the second control terminal CB.

[0071] In some embodiments, the output subcircuit 103 includes a first output module and a second output module. The first output module is electrically connected to the first power supply terminal, the third node N7 and the signal output terminal Out, respectively, and is configured to control the on-off of the first power supply terminal and the signal output terminal Out in response to the signal of the third node N7. The second output module is electrically connected to the second power supply terminal, the fourth node N4 and the signal output terminal Out, respectively, and is configured to control the on-off of the second power supply terminal and the signal output terminal Out in response to the signal of the fourth node N4. If the first power supply terminal is a VGL power supply terminal, the second power supply terminal is a VGH power supply terminal, and vice versa, if the first power supply terminal is a VGH power supply terminal, the second power supply terminal is a VGL power supply terminal.

[0072] In some display devices in the related art, such as organic light-emitting diode (OLED) display products, the TFT characteristics in the driving circuit are prone to fluctuations. For example, during the reliability test of active-matrix organic light-emitting diode (AMOLED) AMOLED products, the TFT characteristics in the gate driver on array (GOA) circuit on the array substrate fluctuate. If the amplitude is large, it is easy to cause the GOA waveform to fluctuate. Different GOA fluctuations have different degrees of influence on pixels, causing the display panel to have undesirable phenomena such as horizontal stripes and horizontal bands.

[0073] Among them, reliability tests include 8585 test and aging test. In the 8585 test, "8585" is the abbreviation of temperature 85°C and humidity 85% RH (relative humidity). This is a high temperature and high humidity environment test used to simulate extreme hot and humid conditions to verify the durability and stability of AMOLED screens in such environments. Aging test refers to a long-term power-on aging test, which simulates the aging process of display products in actual use by continuously lighting the screen or applying specific signals.

[0074] Figure 2 It is a structural schematic diagram of an 8T pixel driving circuit in the related art, wherein the transistor T2 is an oxide TFT (Oxide TFT), and the transistor T2 is driven by a separate NGOA circuit. Figure 3 is a driving timing diagram corresponding to an 8T pixel driving circuit in the related art, Figure 3 The signal waveforms corresponding to the points N1 and N2 of the EM, GateN, ResetP, GateP, ResetH, and 8T pixel driving circuit are shown. Figure 4 This is a waveform diagram of GateN, ResetP and N1 points in the related technology, such as Figure 4 As shown, there is a step when the GateN signal is closed, which will cause the voltage fluctuation of the N1 point. The voltage fluctuation of N1 can easily cause brightness differences in different rows of the display panel, resulting in poor display phenomena such as horizontal stripes and horizontal bands.

[0075] In some embodiments, the potential of the third node N7 may affect the bias state of the output transistor controlled by the third node N7. In order to improve the stability of the output signal of the signal output terminal Out, it is necessary to improve the stability of the output transistor, that is, to prevent the output transistor from being in a single bias state for a long time. In this embodiment, the third node N7 is reset by the reset subcircuit 104, so that the signal of the third node N7 disconnects the connection between the first power supply terminal and the signal output terminal Out, specifically, the output transistor controlled by the third node N7 is turned off, thereby changing the current bias state of the output transistor.

[0076] Optionally, the reset sub-circuit 104 includes a first transistor T13;

[0077] The control electrode of the first transistor T13 is electrically connected to the third control terminal NCX, the first electrode of the first transistor T13 is electrically connected to the third power supply terminal, and the second electrode of the first transistor T13 is electrically connected to the third node N7 through the first node N1.

[0078] In some embodiments, the reset subcircuit 104 is electrically connected to the first node N1, and the potential of the third node N7 is controlled through the first node N1. Specifically, the reset subcircuit 104 includes a first transistor T13, and the first transistor T13 is electrically connected to the third control terminal NCX, the third power supply terminal and the third node N7 respectively. Among them, the third control terminal NCX can be electrically connected to an external control circuit such as a timing control circuit, and the timing control circuit is such as a timing controller (Timing Controller, TCON), and the third control terminal NCX can receive a third control signal sent by the timing control circuit. The level state corresponding to the power supply voltage of the third power supply terminal is opposite to the effective level state corresponding to the output transistor, and the output transistor is an output transistor controlled by the third node N7.

[0079] Figure 5 FIG. 1 is one of the transistor-level schematic diagrams of a shift register 10 provided in an embodiment of the present application. Figure 5 As shown, the shift register 10 includes an input subcircuit 101, a control subcircuit 102, an output subcircuit 103 and a reset subcircuit 104. The first input module includes a transistor T1 and a transistor T14, the gates of which are electrically connected to a first control terminal CK. The first control terminal CK can receive an externally input first clock signal as a first control signal. The first electrodes of the transistors T1 and T14 are electrically connected to a signal input terminal Input, as shown in FIG. Figure 5 The shift register 10 shown is a cascaded shift register 10 in a gate driving circuit, and can receive a scan start signal (STV). The second electrode of the transistor T1 is electrically connected to the first node N1, and the second electrode of the transistor T14 is electrically connected to the first node N1. Figure 5 Node N8 in.

[0080] like Figure 5 As shown, the second input module includes a transistor T2 and a transistor T3, the gate of the transistor T1 is electrically connected to the first control terminal CK, the first electrode of the transistor T1 is electrically connected to the VGL power supply terminal, and the second electrode of the transistor T1 is electrically connected to the second node N2. The gate of the transistor T2 is electrically connected to the first node N1, the first electrode of the transistor T2 is electrically connected to the first control terminal CK, and the second electrode of the transistor T2 is electrically connected to the second node N2.

[0081] like Figure 5 As shown, the pull-down control unit includes a transistor T4, a transistor T5 and a capacitor C3, and the middle node between the transistor T4 and the transistor T5 is a node N5. One end of the capacitor C3 is electrically connected to the node N5, and the other end is electrically connected to the gate of the transistor T4, and the gate of the transistor T4 is also electrically connected to the fifth node N9. The first electrode of the transistor T4 is electrically connected to the second control terminal CB. The gate of the transistor T5 is electrically connected to the second node N2, and the first electrode of the transistor T5 is electrically connected to the VGH power supply terminal.

[0082] like Figure 5 As shown, the pull-down unit includes a transistor T12, a transistor T15, and a transistor T16, wherein the transistor T12 and the transistor T15 are normally open transistors as isolation transistors, that is, the gates of the transistor T12 and the transistor T15 are electrically connected to the VGL power supply terminal. The first electrode of the transistor T12 is electrically connected to the first node N1, and the second electrode of the transistor T12 is electrically connected to the third node N7. The first electrode of the transistor T15 is electrically connected to the node N8, and the second electrode of the transistor T15 is electrically connected to the fifth node N9. The gate and the first electrode of the transistor T16 are electrically connected to the fifth node N9, respectively, and the second electrode of the transistor T16 is electrically connected to the third node N7.

[0083] like Figure 5As shown, the first control unit includes a transistor T8, the gate of the transistor T8 is electrically connected to the first node N1, the first electrode of the transistor T8 is electrically connected to the VGH power supply terminal, and the second electrode of the transistor T8 is electrically connected to the fourth node N4. The second control unit includes a transistor T6, a transistor T7, a transistor T11 and a capacitor C1. Among them, the transistor T11 is an isolation transistor, the gate of the transistor T11 is electrically connected to the VGL power supply terminal, the first electrode of the transistor T11 is electrically connected to the second node N2, the second electrode of the transistor T11 is electrically connected to the node N6, and the transistor T11 is a normally open transistor. The gate of the transistor T6 is electrically connected to the node N6, the first electrode of the transistor T6 is electrically connected to the second control terminal CB, and the second electrode of the transistor T6 is electrically connected to the node N3. Among them, the two ends of the capacitor C3 are electrically connected to the node N6 and the node N3 respectively. The gate of the transistor T7 is electrically connected to the second control terminal CB, the first electrode of the transistor T7 is electrically connected to the node N3, and the second electrode of the transistor T7 is electrically connected to the fourth node N4.

[0084] like Figure 5 As shown, the first output module includes a transistor T10, the gate of the transistor T10 is electrically connected to the third node N7, the first electrode of the transistor T10 is electrically connected to the VGL power supply terminal, and the second electrode of the transistor T10 is electrically connected to the signal output terminal Out. The second output module includes a transistor T9 and a capacitor C2, the gate of the transistor T9 is electrically connected to the fourth node N4N4, the first electrode of the transistor T9 is electrically connected to the VGH power supply terminal, and the second electrode of the transistor T9 is electrically connected to the signal output terminal Out.

[0085] In some embodiments, the reset sub-circuit 104 includes a first transistor T13, such as Figure 5 As shown, the transistor T13 is a P-type transistor, the control electrode of the first transistor T13 is the gate of the transistor T13, the gate of the transistor T13 is electrically connected to the third control terminal NCX, the first electrode and the second electrode of the first transistor T13 are the source and the drain of the transistor T13 respectively, and the source and the drain of the transistor T13 are electrically connected to the third power supply terminal and the first node N1 respectively. Figure 5 The third power supply terminal is the VGH power supply terminal.

[0086] like Figure 5 As shown, when the third control signal input to the third control terminal NCX is a low level signal, the transistor T13 is turned on, thereby conducting the connection between the VGH power supply terminal and the first node N1. The transistor 12 is a normally open transistor, so when the transistor T13 is turned on, the connection between the VGH power supply terminal and the third node N7 can be conducted. Figure 5In the embodiment, the output transistor controlled by the third node N7 is the transistor T10. When the VGH power supply terminal and the third node N7 are connected, the potential of the third node N7 is pulled high, thereby turning off the transistor T10, thereby switching the transistor T10 from a negative bias state to a positive bias state.

[0087] In some embodiments, if the third control signal inputted by the third control terminal NCX is always at a high level, Figure 5 The driving timing corresponding to the shift register 10 shown is as follows Figure 6 As shown, since the third node N7 of the circuit itself has a secondary pull-down, the waveform of the output signal of the signal output terminal Out also has a secondary pull-down, that is, a step voltage, as shown in FIG. Figure 6 The output signals Nout1 and Nout2 have step voltages. Figure 6 The STV in the figure represents a scan start signal, CK and CB are clock signals respectively, and CB is an inverted signal of CK.

[0088] Simultaneously, the influence of the characteristic fluctuation of transistor T10 is simulated, and it is found that transistor T10 is continuously in the negative bias (NBTS) state. To improve the stability of transistor T10, it is necessary to improve the NBTS state of transistor T10, that is, to shorten the time when transistor T10 is in the NBTS state. Therefore, it is necessary to improve the characteristic stability of transistor T10, so as to make Figure 2 The voltage at point N1 remains stable.

[0089] Optionally, the reset sub-circuit 104 includes a second transistor T17;

[0090] The control electrode of the second transistor T17 is electrically connected to the third control terminal NCX, the first electrode of the second transistor T17 is electrically connected to the third power supply terminal, and the second electrode of the second transistor T17 is electrically connected to the third node N7.

[0091] In some embodiments, the second transistor T17 may be directly electrically connected to the third node N7, and the second transistor T17 is specifically used to control the potential of the third node N7. In addition, since the control electrode of the second transistor T17 is electrically connected to the third control terminal NCX, a special third control signal may be added to control the on and off of the second transistor T17. When the second transistor T17 is turned on, the connection between the third power supply terminal and the third node N7 is turned on, so that the power supply voltage provided by the third power supply terminal is transmitted to the third node N7, thereby changing the potential of the third node N7.

[0092] Figure 7 is a second transistor-level schematic diagram of a shift register 10 provided in an embodiment of the present application, and Figure 5 The difference of the shift register 10 shown is that Figure 7The reset subcircuit 104 of the shift register 10 includes a second transistor T17, a gate of the second transistor T17 is electrically connected to the third control terminal NCX, a first electrode of the second transistor T17 is electrically connected to the third power supply terminal, and a second electrode of the second transistor T17 is electrically connected to the third node N7. The third power supply terminal is a VGH power supply terminal, and the second transistor T17 is a P-type transistor.

[0093] In some embodiments, the level state corresponding to the power supply voltage of the third power supply terminal should be opposite to the effective level state corresponding to the output transistor controlled by the third node N7, so that after the power supply voltage of the third power supply terminal changes the potential of the third node N7, the output transistor controlled by the third node N7 can be turned off, thereby changing the working state of the output transistor. For example, if the output transistor is a P-type transistor, the third power supply terminal can be a VGH power supply terminal. This is only an example, and the embodiments of the present application are not limited to this.

[0094] Optionally, the third control terminal NCX is multiplexed with the signal output terminal Out.

[0095] In some embodiments, the control electrode of the second transistor T17 may be electrically connected to the signal output terminal Out, and the output signal of the signal output terminal Out is used as the third control signal, that is, the third control terminal NCX multiplexes the signal output terminal Out. Figure 8 is a third transistor-level schematic diagram of a shift register 10 provided in an embodiment of the present application, and Figure 5 The difference of the shift register 10 shown is that Figure 8 The reset sub-circuit 104 of the shift register 10 includes a second transistor T17, and the third control terminal NCX is multiplexed with the signal output terminal Out. Figure 8 In the embodiment, the second transistor T17 is an N-type transistor.

[0096] Specifically, the reset subcircuit 104 includes a second transistor T17, a gate of the second transistor T17 is electrically connected to the signal output terminal Out, a first electrode of the second transistor T17 is electrically connected to the third power supply terminal, and a second electrode of the second transistor T17 is electrically connected to the third node N7. The third power supply terminal is a VGH power supply terminal, and the output transistor controlled by the third node N7 is a transistor T10. When the VGH power supply terminal and the third node N7 are connected, the potential of the third node N7 is pulled up, thereby turning off the transistor T10, so that the transistor T10 is switched from a negative bias state to a positive bias state.

[0097] Optionally, the effective level state corresponding to the second transistor T17 is opposite to the level state corresponding to the power supply voltage of the first power supply terminal.

[0098] In some embodiments, such as Figure 6As shown, the output signal of the signal output terminal Out is often at a low level, that is, the transistor T10 is often in a negative bias state. To shorten the time when the transistor T10 is in a negative bias state, it is necessary to adjust the potential of the third node N7 and then turn off the transistor T10. Figure 8 The third control terminal NCX in the shift register 10 shown in FIG. 1 is multiplexed with the signal output terminal Out, and the third control signal is multiplexed as follows: Figure 6 The output signal is shown.

[0099] Specifically, when the output signal is at a high level, the second transistor T17 is controlled to be turned on, so that the potential of the third node N7 turns off the transistor T10, and when the output signal is at a low level, the second transistor T17 is controlled to be turned off, so that the potential of the third node N7 is pulled down to turn on the transistor T10. Figure 8 Taking the circuit shown as an example, the second transistor T17 is an N-type transistor, and the effective level corresponding to the N-type transistor is a high level, which is opposite to the low level corresponding to the VGL voltage of the first power supply terminal, ie, the VGL power supply terminal.

[0100] In the embodiment of the present application, the shift register 10 includes: an input subcircuit 101, which is electrically connected to the first control terminal CK, the signal input terminal Input, the first node N1 and the second node N2, respectively, and is configured to control the potentials of the first node N1 and the second node N2 in response to a first control signal input from the first control terminal CK; a control subcircuit 102, which is electrically connected to the second control terminal CB, the first node N1, the second node N2, the third node N7 and the fourth node N4, respectively, and is configured to control the potentials of the third node N7 and the fourth node N4 in response to a signal of the first node N1, a signal of the second node N2 and a second control signal input from the second control terminal CB; an output The subcircuit 103 is electrically connected to the first power supply terminal, the second power supply terminal, the third node N7, the fourth node N4 and the signal output terminal Out, respectively, and is configured to control the on-off of the first power supply terminal and the signal output terminal Out in response to the signal of the third node N7, and to control the on-off of the second power supply terminal and the signal output terminal Out in response to the signal of the fourth node N4; the reset subcircuit 104 is electrically connected to the third control terminal NCX, the third power supply terminal and the third node N7, respectively, and is configured to conduct the third power supply terminal and the third node N7 in response to the third control signal input by the third control terminal NCX, so that the signal of the third node N7 disconnects the connection between the first power supply terminal and the signal output terminal Out. In this way, the third node N7 can be reset by the reset subcircuit 104, so that the signal of the third node N7 disconnects the connection between the first power supply terminal and the signal output terminal Out, avoiding the output signal of the signal output terminal Out from having a step voltage, thereby improving the stability of the output signal, reducing the brightness difference between different rows of the display panel, and improving the display defects such as horizontal stripes and horizontal bands of the display panel.

[0101] The embodiment of the present application further provides a gate driving circuit, the gate driving circuit comprising: N shift registers 10 as in the above embodiment; N shift registers 10 are cascaded;

[0102] The signal input terminal Input of the first stage shift register 10 is used to receive a scan start signal;

[0103] The signal output terminal Out of the shift register 10 of the n-1th stage is electrically connected to the signal input terminal Input of the shift register 10 of the nth stage; wherein, 2≤n≤N, and N and n are positive integers respectively.

[0104] In some embodiments, the gate drive circuit can be electrically connected to a plurality of pixels, specifically, the signal output terminal Out of a shift register 10 is electrically connected to the gate of the driving control transistor in the pixel circuit of a pixel. Among the cascaded N shift registers 10, the signal input terminal Input of the first-stage shift register 10 can be electrically connected to the scan start terminal (STV) of the gate drive circuit to receive the scan start signal. For the shift registers 10 other than the first-stage shift register 10, the signal output terminal Out of the previous-stage shift register 10 is electrically connected to the signal input terminal Input of the next-stage shift register 10, that is, the signal output terminal Out of the shift register 10 of the n-1th stage is electrically connected to the signal input terminal Input of the shift register 10 of the nth stage.

[0105] A gate driving circuit provided in an embodiment of the present application can obtain the same or similar technical effects as the shift register 10 of the aforementioned embodiment, which will not be described again here to avoid repetition.

[0106] The embodiment of the present application further provides a display device, the display device comprising: a pixel, and a shift register 10 as in the above embodiment;

[0107] The pixel includes a pixel circuit and a light emitting element coupled to the pixel circuit. The pixel circuit includes a drive control transistor. The signal output terminal Out of the shift register 10 is electrically connected to the control electrode of the drive control transistor.

[0108] In some embodiments, the pixel circuit in the pixel may be as follows: Figure 2 As shown, the driving control transistor is T2, and the signal output terminal Out of the shift register 10 provided in this embodiment can be electrically connected to the gate of the transistor T2, that is, the shift register 10 serves as an NGOA circuit corresponding to the transistor T2 to provide a gate driving signal GateN for the transistor T2.

[0109] A display device provided in an embodiment of the present application can obtain the same or similar technical effects as the shift register 10 of the aforementioned embodiment, which will not be described again here to avoid repetition.

[0110] Fig. 9 1 is a schematic diagram of the steps of a driving method of a shift register 10 provided in an embodiment of the present application. The driving method is used to control the shift register 10 of the aforementioned embodiment, and includes:

[0111] Step S1, in the target frame, sends a third control signal with a first level to the third control terminal NCX, so that the third control signal with the first level turns on the third power terminal and the third node N7, and disconnects the connection between the first power terminal and the signal output terminal Out based on the signal of the third node N7.

[0112] In some embodiments, the target frame may be one frame or multiple frames, the target frame may be a refresh frame or a non-refresh frame, and the target frame may be a complete frame or a partial stage of a frame, which is not limited in the embodiments of the present application. In this embodiment, in the target frame, a third control signal having a first level is sent to the third control terminal NCX of the shift register 10 in the aforementioned embodiment. Under the control of the third control signal having the first level, the reset subcircuit 104 in the shift register 10 turns on the connection between the third power supply terminal and the third node N7, so that the power supply voltage provided by the third power supply terminal can change the potential of the third node N7, thereby causing the signal of the third node N7 to disconnect the connection between the first power supply terminal and the signal output terminal Out.

[0113] In a specific embodiment, Figure 5 Taking the shift register 10 shown as an example, a low level signal is sent to the third control terminal NCX in the target frame as the third control signal with the first level. Under the control of the low level signal, the first transistor T13 conducts the VGH power supply terminal and the first node N1. Since the transistor T12 is a normally open transistor, the connection between the VGH power supply terminal and the third node N7 is conducted, thereby raising the potential of the third node N7, and then turning off the transistor T10, that is, the signal of the third node N7 disconnects the connection between the VGL power supply terminal and the signal output terminal Out. In this way, the transistor T10 is switched from the negative bias state to the positive bias state, which can shorten the time when the transistor T10 is in the negative bias state, improve the stability of the transistor T10, and thus improve the stability of the output signal of the signal output terminal Out of the shift register 10.

[0114] In another specific embodiment, Figure 8Taking the shift register 10 shown as an example, in the target frame, the output signal of the multiplexed signal output terminal Out is the third control signal, and the first level is a high level. Under the control of the high-level signal, the second transistor T17 conducts the connection between the VGH power supply terminal and the third node N7, thereby raising the potential of the third node N7, and then turning off the transistor T10, that is, the signal of the third node N7 disconnects the connection between the VGL power supply terminal and the signal output terminal Out. In this way, the transistor T10 can also be switched from a negative bias state to a positive bias state, which can shorten the time when the transistor T10 is in a negative bias state, improve the stability of the transistor T10, and thus improve the stability of the output signal of the signal output terminal Out of the shift register 10.

[0115] In the embodiment of the present application, in the target frame, a third control signal with a first level is sent to the third control terminal NCX, so that the third control signal with a first level conducts the third power supply terminal and the third node N7, and the signal of the third node N7 disconnects the connection between the first power supply terminal and the signal output terminal Out. In this way, the output signal of the signal output terminal Out can be prevented from having a step voltage, thereby improving the stability of the output signal, reducing the brightness difference of different rows of the display panel, and improving the display defects such as horizontal stripes and horizontal bands of the display panel.

[0116] Optionally, step S1 may include:

[0117] Sub-step A1: sending a third control signal with a first level to the third control terminal NCX at least one frame before the shift register 10 is powered off.

[0118] In some embodiments, the target frame may be a frame or a plurality of frames before the shift register 10 is powered off. Fig.10 1 is one of the timing diagrams of a driving method provided in an embodiment of the present application. Figure 5 Taking the shift register 10 shown in FIG. 1 as an example, the shift register 10 is powered off in the last frame. Fig.10 As shown, in the third frame before the power-off frame (including the last frame), the third control signal, namely the NCX signal, is pulled low, that is, the NCX signal with a low level is sent to the third control terminal NCX. Fig.10 The shift register 10 of this embodiment also shows the NSTV signal, NCK / NCB signal, and VGH / VGL power supply voltage signal corresponding to the NGOA circuit, wherein the NSTV signal is a scan start signal, and the NCK / NCB signal can be the first control signal and the second control signal, respectively.

[0119] Optionally, after step S1, the driving method further includes:

[0120] Step S2, at least in the last frame before the shift register 10 is powered off, sending a third control signal with a second level to the third control terminal NCX, so that the third control signal with the second level disconnects the third power terminal from the third node N7.

[0121] In some embodiments, such as Fig.10 As shown, in the last frame before power-off (excluding the power-off frame), the NCX signal is pulled high, so that the high-level NCX signal disconnects the connection between the VGH power supply terminal and the third node N7. Fig.10 The toggle in the code indicates a high-low level switch. The frame marked with toggle is a refresh frame. Fig.10 A refresh frame is shown, while the target frame in this embodiment is a non-refresh frame.

[0122] Optionally, sub-step A1 may include:

[0123] In the last frame before the shift register 10 is powered off, a third control signal with a first level is sent to the third control terminal NCX; wherein the duration of the last frame is greater than or equal to 3 times the unit scanning duration and less than or equal to 10 times the unit scanning duration.

[0124] In some embodiments, the target frame may be a lengthened frame before the shift register 10 is powered off. Fig.11 FIG. 2 is a timing diagram of a driving method provided in an embodiment of the present application. Figure 5 Taking the shift register 10 shown in FIG. 1 as an example, the shift register 10 is powered off in the last frame. Fig.11 As shown, in the extended frame before power-off (excluding the power-off frame), the third control signal, ie, the NCX signal, is pulled low, that is, the NCX signal with a low level is sent to the third control terminal NCX.

[0125] Among them, the duration of the last frame is greater than or equal to 3 times the unit scanning time and less than or equal to 10 times the unit scanning time, that is, the duration of the extended frame is in the range of 3H to 10H, and H represents the unit scanning time required to scan a row of pixels.

[0126] In an embodiment of the present application, a third control signal with a first level is sent to the third control terminal NCX in a target frame during the power-off process, so that the third control signal with the first level turns on the third power supply terminal and the third node N7, thereby controlling the signal of the third node N7 to disconnect the connection between the first power supply terminal and the signal output terminal Out, thereby avoiding the presence of a step voltage in the output signal of the signal output terminal Out, thereby improving the stability of the output signal, reducing the brightness difference of different rows of the display panel, and improving the display defects such as horizontal stripes and horizontal bands of the display panel.

[0127] Optionally, step S1 may include:

[0128] Sub-step A2: sending a third control signal with a first level to the third control terminal NCX at least one frame before the refresh frame of the shift register 10.

[0129] In some embodiments, the target frame may be at least one frame in the power-on process of the shift register 10 . Specifically, the target frame may be one or more frames from the start of power-on of the shift register 10 to before the refresh frame. Fig.12 FIG. 3 is a timing diagram of a driving method provided in an embodiment of the present application. Figure 5 Taking the shift register 10 shown in FIG. 1 as an example, the shift register 10 starts to be powered on. Fig.12 As shown, before refreshing the frame, the third control signal, namely, the NCX signal, is pulled low, that is, the NCX signal with a low level is sent to the third control terminal NCX.

[0130] In some embodiments, the duration of the first level state of the third control signal is greater than or equal to 3 hours and less than or equal to 3 frames. For example, when the NCX signal is powered on at a low level, the low level state of the NCX signal can last for 3 hours to 3 frames, or it can last for 4 frames or 5 frames, depending on how long the driver IC supports the low level state. This is just an example, and the embodiments of the present application are not limited to this.

[0131] In an embodiment of the present application, a third control signal with a first level is sent to the third control terminal NCX in a target frame during the power-on process, so that the third control signal with the first level turns on the third power supply terminal and the third node N7, thereby controlling the signal of the third node N7 to disconnect the connection between the first power supply terminal and the signal output terminal Out, thereby avoiding the presence of a step voltage in the output signal of the signal output terminal Out, thereby improving the stability of the output signal, reducing the brightness difference between different rows of the display panel, and improving the display defects such as horizontal stripes and horizontal bands of the display panel.

[0132] Optionally, the driving method further includes:

[0133] Step S3, in the refresh frame, sends a first control signal to the first control terminal CK, sends a second control signal to the second control terminal CB, and sends an input signal to the signal input terminal Input; wherein the first control signal, the second control signal and the input signal are all signals of a single level state in the target frame.

[0134] In some embodiments, in a refresh frame, a first control signal is sent to the first control terminal CK, a second control signal is sent to the second control terminal CB, and an input signal is sent to the signal input terminal Input, thereby controlling the corresponding transistor to be turned on or off. Fig.10As shown, the frame marked with toggle is a refresh frame, the first control signal is an NCK signal, the second control signal is an NCB signal, and the input signal is an NSTV signal.

[0135] In this embodiment, the target frame is a non-refresh frame, and the first control signal, the second control signal and the input signal in the target frame are all signals in a single level state. Fig.10 The NSTV signal, NCK signal and NCB signal are all high level signals.

[0136] Optionally, step S1 may include:

[0137] Sub-step A3: sending a third control signal with a first level to the third control terminal NCX during the blanking phase of the refresh frame.

[0138] In some embodiments, the target frame may be a refresh frame. Specifically, in a blanking phase of the refresh frame, a third control signal having a first level is sent to the third control terminal NCX. Fig.13 FIG. 4 is a timing diagram of a driving method provided in an embodiment of the present application. Figure 5 Taking the shift register 10 shown in FIG. 1 as an example, the target frame is a refresh frame, such as Fig.10 As shown in FIG. 1 , during the display phase of the refresh frame, the NCK signal and the NCB signal are in a toggle state, and the input signal is a NSTV signal with a high level. During the blanking phase of the refresh frame, the NCK signal, the NCB signal, and the NSTV signal are all in a single level state. Fig.10 As shown, in this embodiment, in the blanking phase of the refresh frame, the third control signal, ie, the NCX signal, is pulled low, that is, the NCX signal with a low level is sent to the third control terminal NCX.

[0139] Optionally, sub-step A3 may include:

[0140] In the blanking phase, after continuously sending the third control signal with the second level to the third control terminal NCX for the first time period, switching to sending the third control signal with the first level to the third control terminal NCX;

[0141] Before the second time period to the next display phase, the third control signal with the second level is sent to the third control terminal NCX.

[0142] In some embodiments, a third control signal with a first level may be sent to the third control terminal NCX during the entire blanking phase, or a third control signal with a first level may be sent to the third control terminal NCX only during part of the blanking phase, and the embodiments of the present application are not limited to this.

[0143] Specifically, in the blanking phase, the third control signal with the second level is first sent to the third control terminal NCX, and after the first duration, the third control signal with the first level is switched to be sent to the third control terminal NCX. Then, after a period of time, before the second duration of the next display phase, the third control signal with the second level is switched to be sent to the third control terminal NCX.

[0144] For example, Fig.13 As shown, after entering the Blank stage, the NCX signal first maintains a high level and then is pulled low, and returns to a high level state before entering the next display stage. Among them, the first duration can be 2H, and the second duration can be 2H to 5H. This is only an example, and the embodiment of the present application does not limit this.

[0145] Optionally, step S1 may include:

[0146] Sub-step A4: in a refresh frame, sending the output signal of the signal output terminal Out as a third control signal to the third control terminal NCX; wherein the output signal includes a level state corresponding to the first level.

[0147] In some embodiments, the target frame may be a refresh frame. Specifically, in the display phase of the refresh frame, the output signal of the multiplexed signal output terminal Out includes a level state corresponding to the first level, and the output signal may be sent to the third control terminal NCX as a third control signal having the first level. Figure 8 Taking the shift register 10 shown as an example, Figure 8 The third control terminal NCX in the multiplexed signal output terminal Out, then in the display phase of the refresh frame, the output signal of the signal output terminal Out can be used as the third control signal to control the opening or closing of the second transistor T17.

[0148] In an embodiment of the present application, in a refresh frame, a third control signal having a first level is sent to the third control terminal NCX so that the third control signal having the first level turns on the third power supply terminal and the third node N7, thereby controlling the signal of the third node N7 to disconnect the connection between the first power supply terminal and the signal output terminal Out. This can avoid the presence of a step voltage in the output signal of the signal output terminal Out, thereby improving the stability of the output signal, reducing the brightness difference between different rows of the display panel, and improving poor display phenomena such as horizontal stripes and horizontal bands on the display panel.

[0149] In the shift register 10 provided in the embodiment of the present application, the threshold voltage drift (ΔVth) of the output transistor TFT in the BTS test is reduced by 0.2V, indicating that the stability of the transistor is improved, that is, the stability of the transistor T10 in the present embodiment is improved, which can improve the stability of the output signal of the shift register 10, reduce the brightness difference between different rows of the display panel, and improve the display defects such as horizontal stripes and horizontal bands of the display panel.

[0150] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0151] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0152] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0153] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0154] The above is a detailed introduction to a shift register and its driving method, a gate driving circuit, and a display device provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A shift register, characterized in that: The shift register comprises: An input subcircuit, electrically connected to the first control terminal, the signal input terminal, the first node and the second node, respectively, and configured to control the potential of the first node and the second node respectively in response to a first control signal inputted from the first control terminal; a control subcircuit, electrically connected to the second control terminal, the first node, the second node, the third node and the fourth node, respectively, and configured to control the potentials of the third node and the fourth node respectively in response to a signal of the first node, a signal of the second node and a second control signal inputted from the second control terminal; an output subcircuit, electrically connected to the first power supply terminal, the second power supply terminal, the third node, the fourth node and the signal output terminal, respectively, and configured to control the connection and disconnection between the first power supply terminal and the signal output terminal in response to a signal of the third node, and to control the connection and disconnection between the second power supply terminal and the signal output terminal in response to a signal of the fourth node; A reset subcircuit is electrically connected to the third control terminal, the third power supply terminal and the third node, respectively, and is configured to connect the third power supply terminal and the third node in response to a third control signal input from the third control terminal, so that the signal at the third node disconnects the connection between the first power supply terminal and the signal output terminal.

2. The shift register according to claim 1, characterized in that: The control subcircuit comprises: a first control module, electrically connected to the first node, the second node and the third node respectively, and configured to control the potential of the third node in response to a signal of the second node; wherein the reset subcircuit is electrically connected to the third node via the first node; The second control module is electrically connected to the second control terminal, the first node, the second node and the fourth node, respectively, and is configured to control the potential of the fourth node in response to the signal of the first node, the signal of the second node and the second control signal input from the second control terminal.

3. The shift register according to claim 2, characterized in that: The reset subcircuit comprises a first transistor; The control electrode of the first transistor is electrically connected to the third control terminal, the first electrode of the first transistor is electrically connected to the third power supply terminal, and the second electrode of the first transistor is electrically connected to the third node through the first node.

4. The shift register according to claim 1, wherein: The reset subcircuit includes a second transistor; The control electrode of the second transistor is electrically connected to the third control terminal, the first electrode of the second transistor is electrically connected to the third power supply terminal, and the second electrode of the second transistor is electrically connected to the third node.

5. The shift register according to claim 4, characterized in that: The third control terminal multiplexes the signal output terminal.

6. The shift register according to claim 5, characterized in that: The effective level state corresponding to the second transistor is opposite to the level state corresponding to the power supply voltage of the first power supply terminal.

7. A gate drive circuit, characterized in that: include: N shift registers as claimed in any one of claims 1 to 6; N shift registers are cascaded; The signal input terminal of the shift register of the first stage is used to receive a scan start signal; The signal output terminal of the shift register at the n-1th stage is electrically connected to the signal input terminal of the shift register at the nth stage; wherein, 2≤n≤N, and N and n are positive integers respectively.

8. A display device, characterized in that: The display device comprises: a pixel, and a shift register as claimed in any one of claims 1 to 6; The pixel comprises a pixel circuit and a light emitting element coupled to the pixel circuit. The pixel circuit comprises a drive control transistor. The signal output terminal of the shift register is electrically connected to the control electrode of the drive control transistor.

9. A shift register driving method, characterized in that: Used to control the shift register as claimed in any one of claims 1 to 6, the method comprising: In the target frame, a third control signal with a first level is sent to the third control terminal so that the third control signal with the first level turns on the third power terminal and the third node, and disconnects the connection between the first power terminal and the signal output terminal based on the signal of the third node.

10. The driving method according to claim 9, characterized in that: The step of sending a third control signal having a first level to a third control terminal in a target frame includes: In at least one frame before the shift register is powered off, the third control signal having the first level is sent to the third control terminal.

11. The driving method according to claim 10, characterized in that: The sending the third control signal having the first level to the third control terminal in at least one frame before the shift register is powered off comprises: In the last frame before the shift register is powered off, the third control signal with the first level is sent to the third control terminal; wherein the duration of the last frame is greater than or equal to 3 times the unit scan duration and less than or equal to 10 times the unit scan duration.

12. The driving method according to claim 9, characterized in that: The step of sending a third control signal having a first level to a third control terminal in a target frame includes: The third control signal having the first level is sent to the third control terminal in at least one frame before the shift register refresh frame.

13. The driving method according to claim 9, characterized in that: The step of sending a third control signal having a first level to a third control terminal in a target frame includes: During a blanking phase of a refresh frame, the third control signal having the first level is sent to the third control terminal.

14. The driving method according to claim 13, characterized in that: The step of sending the third control signal having the first level to the third control terminal during the blanking phase of the refresh frame comprises: In the blanking phase, after continuously sending the third control signal with the second level to the third control terminal for a first time period, switching to sending the third control signal with the first level to the third control terminal; Before the second time period to the next display stage, the third control signal with the second level is switched to be sent to the third control terminal.

15. The driving method according to claim 9, characterized in that: The step of sending a third control signal having a first level to a third control terminal in a target frame includes: In a refresh frame, the output signal of the signal output terminal is sent to the third control terminal as the third control signal; wherein the output signal includes a level state corresponding to the first level.

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