Display device

Abstract

A display device includes a display panel including a plurality of sub-pixels. At least one of the sub-pixels may include: a light emitting diode configured to emit light; a light emitting circuit configured to drive the light emitting diode; and a sensing circuit including a light sensing transistor configured to sense light emitted from the light emitting diode. Therefore, the light intensity of the sub-pixels can be sensed in real time by the sensing circuit to compensate for brightness deviation among the plurality of sub-pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0155471 filed in the Korean Intellectual Property Office on November 10, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device using a light emitting diode (LED). Background Art

[0004] As display devices used for monitors of computers, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] The application range of the display device is diversified to personal mobile devices as well as monitors and televisions of computers, and display devices having a large display area and reduced volume and weight are being studied.

[0006] In addition, recently, a display device including a light emitting diode (LED) has attracted attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it has excellent reliability, making its life longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a fast light emission speed, excellent light emission efficiency, and strong impact resistance, making it excellent in stability and able to display images with high brightness. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device that directly senses and compensates for light emitted from a light emitting diode.

[0008] Another object to be achieved by the present disclosure is to provide a display device having a sensing circuit embedded in a sub-pixel to sense light.

[0009] Another object to be achieved by the present disclosure is to provide a display device that compensates for brightness deviations between sub-pixels in real time.

[0010] Still another object to be achieved by the present disclosure is to provide a display device that easily compensates for brightness deviation while simplifying the structure of sub-pixels.

[0011] Still another object to be achieved by the present disclosure is to provide a display device that compensates for brightness deviation due to threshold voltage deviation of a driving transistor and degradation of a light emitting diode.

[0012] The objects of the present disclosure are not limited to the objects mentioned above, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0013] According to one aspect of the present disclosure, a display device may include: a display panel including a plurality of sub-pixels, wherein at least one of the sub-pixels may include: a light emitting diode configured to emit light; a light emitting circuit configured to drive the light emitting diode; and a sensing circuit including a light sensing transistor configured to sense light emitted from the light emitting diode. Therefore, the light intensity of the sub-pixel may be sensed in real time by the sensing circuit to compensate for the brightness deviation between the plurality of sub-pixels.

[0014] According to another aspect of the present disclosure, a display device may include: a substrate; a light sensing transistor disposed on the substrate; a reflective layer disposed on the light sensing transistor; and a light emitting diode disposed on the reflective layer, the reflective layer including an opening overlapping the light sensing transistor. Thus, the light sensing transistor may sense light emitted from the light emitting diode through the opening in the reflective layer.

[0015] Additional details of example embodiments are included in the detailed description and the accompanying drawings.

[0016] According to the present disclosure, light emitted from a light emitting diode is directly sensed for compensation.

[0017] According to the present disclosure, a sensing circuit that senses light is embedded in a sub-pixel to directly sense light emitted from a light emitting diode.

[0018] According to the present disclosure, the brightness deviation between sub-pixels can be compensated.

[0019] According to the present disclosure, it is possible to compensate for luminance deviation due to threshold voltage deviation of a driving transistor and degradation of a light emitting diode without a complicated internal compensation circuit.

[0020] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 3 is a graph of a drain current Id according to a gate-source voltage Vgs of a fifth transistor;

[0025] Figure 4 is a timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 5A is a circuit diagram of a sub-pixel of a display device in an initialization and data writing period according to an exemplary embodiment of the present disclosure;

[0027] Figure 5B is a circuit diagram of a sub-pixel of a display device in a light emitting period according to an exemplary embodiment of the present disclosure;

[0028] Figure 5C is a circuit diagram of a sub-pixel of a display device in a sensing period according to an exemplary embodiment of the present disclosure; and

[0029] Figure 6 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0031] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0032] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0033] When terms such as “on,” “over,” “below,” and “adjacent” are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the term “immediately” or “directly.”

[0034] When an element or layer is disposed “on” another element or layer, the other layer or element may be directly on the other element or interposed therebetween.

[0035] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0036] Like reference numbers generally refer to like elements throughout the specification.

[0037] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0038] The features of the various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of each other or in association with each other.

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 In the present invention, for the convenience of description, among various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown.

[0041] Reference Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD supplying various signals to the display panel PN; and a timing controller TC controlling the gate driver GD and the data driver DD.

[0042] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 2 and 3. It is shown that one gate driver GD is disposed to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0043] The data driver DD supplies data voltages to the plurality of data lines DL according to the plurality of data control signals and image data supplied from the timing controller TC. The data driver DD may convert the image data into data voltages using reference gamma voltages and may supply the converted data voltages to the plurality of data lines DL.

[0044] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal input from the outside. The timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0045] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP may be formed at the intersections of the scan lines SL and the data lines DL.

[0046] In the display panel PN, an active area AA and a non-active area NA may be defined.

[0047] The active area AA is an area in the display device 100 where an image is displayed. In the active area AA, a plurality of sub-pixels SP configuring a plurality of pixels and a pixel circuit for driving the plurality of sub-pixels SP may be provided. The sub-pixel SP is the minimum unit configuring the active area AA, and n sub-pixels SP may form one pixel, where n is a natural number. In each of the plurality of sub-pixels SP, a pixel circuit for driving a plurality of light emitting diodes 120 (see Figure 2 ) thin film transistor. The plurality of light emitting diodes 120 may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light emitting display panel PN, the light emitting diode 120 may be a light emitting diode (LED) or a micro light emitting diode (micro LED).

[0048] In the active area AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines include: a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP; and a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power line and a high potential power line may also be provided, but are not limited thereto.

[0049] The non-active area NA is an area where no image is displayed, so that the non-active area NA can be defined as an area extending from the active area AA. In the non-active area NA, a link line that transmits a signal to the sub-pixel SP of the active area AA, a pad electrode, a driver IC such as a gate driver IC or a data driver IC, etc. can be disposed.

[0050] Meanwhile, the non-active area NA may be located on the rear surface of the display panel PN, that is, on a surface on which the sub-pixels SP are not disposed or may be omitted, and is not limited to that shown in the drawings.

[0051] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-active area NA in a gate-in-panel (GIP) manner, or installed between a plurality of sub-pixels SP in the active area AA in a gate-in-active-area (GIA) manner.

[0052] For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards. The display panel PN may be electrically connected to the data driver DD and the timing controller TC by bonding the flexible films and the printed circuit board to pad electrodes formed in the non-active area NA of the display panel PN.

[0053] As another example, when the gate driver GD is mounted in the active area AA in a GIA manner, and a side line SRL connecting a signal line on the front surface of the display panel PN to a pad electrode on the rear surface of the display panel PN is formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. Therefore, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero frame having substantially no frame can be achieved.

[0054] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 3 is a graph of the drain current Id according to the gate-source voltage Vgs of the fifth transistor. Specifically, Figure 3 is a graph for explaining an off current of the fifth transistor T5 according to external light.

[0055] First, the subpixel SP of the display device 100 according to the exemplary embodiment of the present disclosure includes a fifth transistor T5 serving as a light sensing transistor for sensing the intensity of light emitted from the light emitting diode 120. Brightness deviations between the plurality of subpixels SP may be compensated based on the light sensing result.

[0056] Reference Figure 2 , each of the plurality of sub-pixels SP includes a light emitting diode 120, a light emitting unit (or circuit) SPa, and a sensing unit (or circuit) SPb. The light emitting unit SPa is a configuration for supplying a driving current to the light emitting diode 120 so that the light emitting diode 120 can emit light, and the sensing unit SPb is a configuration for sensing light emitted from the light emitting diode 120 in real time to detect brightness. The light emitting unit SPa and the sensing unit SPb include a plurality of transistors and a capacitor Cst to drive the light emitting diode 120 and sense the brightness of light.

[0057] A plurality of transistors may be formed by transistors of different types. For example, one of the plurality of transistors may be a transistor having an oxide semiconductor as an active layer. The oxide semiconductor material has a low off current, so that the oxide semiconductor material is suitable for a switching transistor having a short on-time and a long off-time. As another example, another transistor of the plurality of transistors may be a transistor having a low temperature polycrystalline silicon (LTPS) as an active layer. The polycrystalline silicon material has a high mobility, so that it has low power consumption and excellent reliability, so that the polycrystalline silicon material is suitable for driving the transistor DT. In addition, as another example, another transistor of the plurality of transistors may be a transistor having an amorphous silicon (a-Si) as an active layer. Amorphous silicon has the characteristic of generating an off current by external light for use in a light sensing transistor.

[0058] The plurality of transistors may be N-type transistors or P-type transistors. In an N-type transistor, the carriers are electrons, so that the electrons can flow from the source electrode to the drain electrode, and the current can flow from the drain electrode to the source electrode. In a P-type transistor, the carriers are holes, so that the holes can flow from the source electrode to the drain electrode, and the current can flow from the source electrode to the drain electrode. For example, one transistor in the plurality of transistors may be an N-type transistor, and the other transistors in the plurality of transistors may be P-type transistors.

[0059] Hereinafter, description will be made by assuming that the fifth transistor T5 among the plurality of transistors is an N-type transistor including amorphous silicon and the remaining transistors except the fifth transistor T5 are P-type transistors including polycrystalline silicon. However, each of the remaining transistors except the plurality of transistors may be any one of an N-type transistor including polycrystalline silicon or an N-type transistor including an oxide semiconductor, but is not limited thereto.

[0060] Reference Figure 2 , the light emitting unit (or circuit) SPa includes a first transistor T1, a second transistor T2, a driving transistor DT and an emission control transistor ET.

[0061] The driving transistor DT is a transistor that controls a driving current based on the data voltage Data transmitted from the first transistor T1. The driving transistor DT has a gate electrode connected to the first node N1, a source electrode connected to the high potential power line VDD, and a drain electrode connected to the emission control transistor ET.

[0062] The first transistor T1 is a transistor turned on by the first scan signal Scan1(n) to transmit the data voltage Data to the driving transistor DT. The gate electrode of the first transistor T1 is connected to the first scan line, the source electrode is connected to the data line DL, and the drain electrode is connected to the gate electrode of the driving transistor DT as the first node N1. The first transistor T1 is turned on by the first scan signal Scan1(n) from the first scan line to transmit the data voltage Data of the data line DL to the gate electrode of the driving transistor DT.

[0063] The second transistor T2 is a transistor for initializing the anode voltage of the light emitting diode 120. The gate electrode of the second transistor T2 is connected to the first scan line, the source electrode is connected to the initialization line as the fourth node N4, and the drain electrode is connected to the anode of the light emitting diode 120 as the third node N3. The second transistor T2 is turned on by the first scan signal Scan1(n) from the first scan line to supply the initialization voltage VINI to the anode of the light emitting diode 120.

[0064] The emission control transistor ET is a transistor for controlling the light emission period of the light emitting diode 120. The gate electrode of the emission control transistor ET is connected to the emission control line, the source electrode is connected to the drain electrode of the driving transistor DT, and the drain electrode is connected to the anode of the light emitting diode 120 as the third node N3. The emission control transistor ET is turned on by the emission control signal EM(n) of the emission control line to transmit the driving current from the driving transistor DT to the light emitting diode 120.

[0065] When the light emitting diode 120 emits light, the capacitor Cst maintains a potential difference between the gate electrode and the source electrode of the driving transistor DT to allow a constant driving current to flow. The capacitor Cst includes a plurality of capacitor Cst electrodes, and some capacitor Cst electrodes are connected to the first node N1, and the remaining capacitor Cst electrodes are connected to the second node N2.

[0066] Next, the sensing unit (or circuit) SPb includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0067] The third transistor T3 is a transistor for initializing the voltage of the fifth node N5. The gate electrode of the third transistor T3 is connected to the first scan line, the source electrode is connected to the initialization line as the fourth node N4, and the drain electrode is connected to the fifth node N5. The third transistor T3 is turned on by the first scan signal Scan1 (n) to transmit the initialization voltage VINI of the initialization line to the fifth node N5. The gate electrode of the third transistor T3 and the gate electrode of the second transistor T2 are connected to the same first scan line to be turned on or off at the same time and transmit the initialization voltage VINI to the light emitting unit SPa and the sensing unit SPb, respectively.

[0068] The fourth transistor T4 is a transistor for sensing the voltage of the fifth node N5. The fifth node N5 is the drain electrode of the fifth transistor T5, which is a light sensing transistor and senses the voltage of the fifth node N5 to detect the off current flowing through the fifth transistor T5. The gate electrode of the fourth transistor T4 is connected to the second scan line, the source electrode is connected to the fifth node N5, and the drain electrode is connected to the sensing line SSL. The fourth transistor T4 is turned on by the second scan signal Scan2 (n) of the second scan line to connect the fifth node N5 to the sensing line SSL. Although not shown in the figure, the data driver DD including the analog-to-digital converter is connected to the sensing line SSL, and the analog-to-digital converter of the data driver DD can detect the voltage of the fifth node N5 through the sensing line SSL.

[0069] The fifth transistor T5 is a light sensing transistor that senses light emitted from the light emitting diode 120. A gate electrode of the fifth transistor T5 is connected to the first voltage line VL, a drain electrode is connected to the fifth node N5, and a source electrode is connected to the low potential power line VSS.

[0070] At this time, the first voltage line VL is a wiring line to which the off-level voltage is continuously applied to turn off the fifth transistor T5. Therefore, the fifth transistor T5 having a gate electrode connected to the first voltage line VL to which the off-level voltage (e.g., low-level voltage) is applied can always be in an off state.

[0071] The fifth transistor T5 is a transistor having amorphous silicon as an active layer, and is affected by external light so that the intensity of the off current may vary. That is, in the off state, no current should flow through the fifth transistor T5, but in fact, the active layer of the fifth transistor T5 reacts to the external light so that the leakage current can flow. At this time, the off current may vary according to the brightness, intensity or wavelength of the external light.

[0072] Reference Figure 3, when the gate-source voltage Vgs, which is the voltage difference between the gate electrode and the source electrode of the fifth transistor T5, is equal to or higher than the threshold voltage, the fifth transistor T5 is turned on so that the drain current Id can start to flow. For example, it is confirmed that in a section of about 0V or higher, the drain current Id increases linearly. When the gate-source voltage Vgs is equal to or lower than the threshold voltage, the fifth transistor T5 is turned off so that the drain current Id may not flow. For example, in a section of about 0V or lower, the fifth transistor T5 is turned off so that the drain current Id does not flow substantially.

[0073] However, due to external light, the off current may flow through the fifth transistor T5 in the off state. In addition, the off current of the fifth transistor T5 may vary according to the intensity of the external light. For example, in the non-light-emitting period when the light-emitting diode 120 does not emit light, the drain current Id of the fifth transistor T5 that is turned off is about 1E-12A. In the light-emitting period when the light-emitting diode 120 emits light, the drain current Id of the fifth transistor T5 that is turned off is about 1E-9A. Therefore, when external light is incident on the fifth transistor T5 that is turned off, the off current of the fifth transistor T5 may increase, and the brightness of the light of the light-emitting diode 120 can be sensed based on the change in the off current.

[0074] At the same time, the off current can vary according to the brightness, intensity or wavelength of the external light. Therefore, the off current of the fifth transistor T5 can vary according to whether the light emitting diode 120 disposed in the same sub-pixel SP emits light. For example, when the light emitting diode 120 does not emit light, the off current of the fifth transistor T5 will be relatively low, and when the light emitting diode 120 emits light, the off current of the fifth transistor T5 will be relatively high. Therefore, the higher the brightness of the light emitted from the light emitting diode 120, the higher the off current of the fifth transistor T5, and the lower the brightness of the light, the lower the off current of the fifth transistor T5.

[0075] Therefore, when the light emitting diode 120 emits light, the off current flows from the drain electrode of the fifth transistor T5 to the source electrode, thereby changing the voltage of the fifth node N5. Therefore, when the light emitting diode 120 emits light, the voltage change of the fifth node N5 caused by the off current of the fifth transistor T5 is measured to sense the brightness of the light emitted from the light emitting diode 120.

[0076] In the following, reference will be made to Figures 4 to 5C A driving process of the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure is described in more detail.

[0077] Figure 4 is a timing diagram of sub-pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 5Ais a circuit diagram of a sub-pixel of a display device in an initialization and data writing period according to an exemplary embodiment of the present disclosure. Figure 5B is a circuit diagram of a sub-pixel of a display device in a light emitting period according to an exemplary embodiment of the present disclosure. Figure 5C is a circuit diagram of a sub-pixel of a display device in a sensing period according to an exemplary embodiment of the present disclosure.

[0078] Reference Figure 4 , the sub-pixel SP of the display device 100 according to the exemplary embodiment of the present disclosure may be driven in the order of an initialization and data writing period, a light emitting period, and a sensing period. The period from time A to time B is the initialization and data writing period, the period after time C is the light emitting period, and the period after time D is the sensing period. A portion of the light emitting period may overlap with the sensing period. That is, the sensing period may be performed simultaneously with the light emitting period.

[0079] Reference Figure 4 and Figure 5A , in the initialization and data writing period between time A and time B, the low-level first scan signal Scan1(n) is output to the first scan line. Therefore, the first transistor T1, the second transistor T2, and the third transistor T3 may be turned on.

[0080] The turned-on first transistor T1 may transmit the data voltage Data of the data line DL to the first node N1. The data voltage Data may be transmitted to the gate electrode of the driving transistor DT, and the voltage reflected by the data voltage Data may be charged in the capacitor Cst. Therefore, the data voltage Data may be written in the light emitting unit SPa of the sub-pixel SP. Thereafter, the voltage stored in the capacitor Cst constantly maintains the voltage of the gate electrode of the driving transistor DT during the light emitting period to supply a constant driving current to the light emitting diode 120.

[0081] The initialization voltage VINI may be transmitted to the third node N3 through the turned-on second transistor T2, and the initialization voltage VINI may be transmitted to the fifth node N5 through the turned-on third transistor T3. Therefore, the voltage of the anode of the light emitting diode 120 of the light emitting unit SPa may be initialized to the initialization voltage VINI, and the voltage of the fifth node N5 of the sensing unit SPb may be initialized to the initialization voltage VINI.

[0082] Next, refer to Figure 4 and Figure 5B , in the light emitting period after time C, a low level signal of the emission control signal EM(n) may be output to the emission control line. Therefore, the emission control transistor ET may be turned on.

[0083] The driving current from the driving transistor DT may be supplied to the light emitting diode 120 through the turned-on emission control transistor ET. Therefore, the light emitting diode 120 is supplied with the driving current to emit light during a period in which the emission control transistor ET is turned on.

[0084] At the same time, from the time C when the light emitting diode 120 starts to emit light, the off current of the fifth transistor T5 can be increased by the light emitted by the light emitting diode 120. The off current flows from the drain electrode of the fifth transistor T5 to the source electrode, and the voltage of the drain electrode of the fifth transistor T5 changes. For example, in the initialization period between time A and time B, the voltage of the fifth node N5, i.e., the drain of the fifth transistor T5, is initialized to the initialization voltage VINI. However, after the time C when the light emitting diode 120 emits light, the off current flows through the fifth transistor T5, so that the voltage of the fifth node N5 may decrease. The voltage of the fifth node N5 may continue to decrease, and then it may converge to a specific voltage after a predetermined period of time. For example, the voltage of the fifth node N5 may converge to a value VINI-a obtained by subtracting the voltage variation a from the initialization voltage VINI. The voltage variation a of the fifth node N5 may be proportional to the intensity of the light emitted from the light emitting diode 120. The larger the voltage variation a, the stronger the intensity of the emitted light, and the smaller the voltage variation a, the weaker the intensity of the emitted light.

[0085] Next, let’s refer to Figure 4 and Figure 5C , the second scan signal Scan2(n) of a low level is output to the second scan line from time D, which is a sensing period in the middle of a period when the light emitting diode 120 emits light. Therefore, the fourth transistor T4 of the sensing unit SPb may be turned on.

[0086] The turned-on fourth transistor T4 may connect the fifth node N5 to the sensing line SSL. Therefore, the data driver DD may detect a voltage change of the fifth node N5 through the turned-on fourth transistor T4 and the sensing line SSL, and detect the brightness of the light emitting diode 120 based on the voltage change. Therefore, the data driver DD may detect a brightness deviation of each of the plurality of sub-pixels SP, and compensate the data voltage Data applied to the sub-pixel SP in a subsequent frame to compensate for the brightness deviation. As an example, the brightness deviation of each sub-pixel may be compensated, and the brightness deviation between the plurality of sub-pixels may also be compensated.

[0087] Meanwhile, when a micro LED is used as the light emitting diode 120, a reflective layer RE may be formed below the light emitting diode 120 to output light emitted from the light emitting diode 120 to the outside of the display device 100. However, when the reflective layer RE is formed between the light emitting diode 120 and the fifth transistor T5, light emitted from the light emitting diode 120 cannot be incident on the fifth transistor T5, making it difficult to sense the light. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, an opening REO corresponding to the fifth transistor T5 is formed in the reflective layer RE disposed below the light emitting diode 120 to sense brightness.

[0088] In the following, reference will be made to Figure 6 The placement structure of the light emitting diode 120 and the fifth transistor T5 for sensing light emitted from the light emitting diode 120 is described.

[0089] Figure 6 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 6 In the configuration of the plurality of sub-pixels SP, only the driving transistor DT, the fifth transistor T5, the capacitor Cst, and the light emitting diode 120 are shown for convenience of description.

[0090] Reference Figure 6 According to an exemplary embodiment of the present disclosure, the display panel PN of the display device 100 includes a substrate 110, a buffer layer 111, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a second gate insulating layer 112b, a third interlayer insulating layer 113c, a first planarizing layer 114a, an adhesive layer 115, a second planarizing layer 114b, a third planarizing layer 114c, a light shielding layer BSM, an auxiliary electrode BCE, a driving transistor DT, a fifth transistor T5, a capacitor Cst, a high potential power line VDD, a reflective layer RE, a first connection electrode CE1, and a second connection electrode CE2.

[0091] The substrate 110 is a component for supporting various components included in the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include a polymer or plastic, or may be formed of a material having flexibility.

[0092] A light shielding layer BSM is provided in each of a plurality of sub-pixels SP on the substrate 110. The light shielding layer BSM is provided to overlap the driving transistor DT and the fifth transistor T5. The light shielding layer BSM may block light incident from the lower portion of the substrate 110 to the driving active layer DACT of the driving transistor DT and the fifth active layer ACT5 of the fifth transistor T5. The light incident to the driving active layer DACT of the driving transistor DT is blocked by the light shielding layer BSM to minimize leakage current. In addition, external light incident to the fifth transistor T5 is blocked by the light shielding layer BSM to minimize a change in the off current caused by external light other than the light emitted from the light emitting diode 120. Therefore, the light shielding layer BSM is provided to block light incident from the lower portion of the substrate 110 to the fifth transistor T5 to improve the brightness sensing accuracy of the light emitting diode 120.

[0093] The light-shielding layer BSM may be formed of an opaque metal material, and for example, may be formed of a single-layer or double-layer structure formed of any one or alloy of opaque metals such as aluminum (Al), chromium (Cr), tungsten (W), titanium (Ti), nickel (Ni), neodymium (Nd), molybdenum (Mo) and copper (Cu).

[0094] A buffer layer 111 is disposed on the substrate 110 and the light shielding layer BSM. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0095] A driving transistor DT is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The driving transistor DT includes a driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.

[0096] First, a driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be formed of any one of semiconductor materials such as oxide semiconductor, amorphous silicon, or polycrystalline silicon. For example, the driving active layer DACT of the driving transistor DT may be formed of low temperature polycrystalline silicon (LTPS) having high mobility to have low power consumption and excellent reliability, but is not limited thereto.

[0097] The first gate insulating layer 112a is disposed on the driving active layer DACT. The first gate insulating layer 112a is an insulating layer that insulates the driving active layer DACT from the driving gate electrode DGE and may be configured by a single layer or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0098] The driving gate electrode DGE is disposed on the first gate insulating layer 112a and may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0099] A first interlayer insulating layer 113 a , a second interlayer insulating layer 113 b , a second gate insulating layer 112 b , and a third interlayer insulating layer 113 c are sequentially disposed on the driving gate electrode DGE.

[0100] First, a first interlayer insulating layer 113a is disposed on the driving gate electrode DGE, a second interlayer insulating layer 113b is disposed on the first interlayer insulating layer 113a, and a third interlayer insulating layer 113c is disposed on the second interlayer insulating layer 113b. The first interlayer insulating layer 113a, the second interlayer insulating layer 113b, and the third interlayer insulating layer 113c are insulating layers for protecting components thereunder and insulating some components of the display device 100, and may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0101] A second gate insulating layer 112b is disposed between the second interlayer insulating layer 113b and the third interlayer insulating layer 113c. The second gate insulating layer 112b is an insulating layer that insulates the fifth active layer ACT5 of the fifth transistor T5 from the fifth gate electrode GE5. The second gate insulating layer 112b may be configured of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0102] A driving source electrode DSE and a driving drain electrode DDE of the driving transistor DT are disposed on the third interlayer insulating layer 113c. The driving source electrode DSE and the driving drain electrode DDE may be electrically connected to the driving active layer DACT through contact holes formed in the third interlayer insulating layer 113c, the second gate insulating layer 112b, the second interlayer insulating layer 113b, and the first interlayer insulating layer 113a. The driving source electrode DSE may be electrically connected to the high potential power line VDD, and the driving drain electrode DDE may be electrically connected to the light emitting diode 120 through the reflective layer RE. The driving source electrode DSE and the driving drain electrode DDE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0103] Next, a fifth transistor T5 is disposed on the second interlayer insulating layer 113b. The fifth transistor T5 includes a fifth active layer ACT5, a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5. The fifth transistor T5 including the fifth active layer ACT5 may be disposed to overlap the opening REO of the reflective layer RE and the light emitting diode 120.

[0104] A fifth active layer ACT5 is disposed on the second interlayer insulating layer 113b. In order to sense light emitted from the light emitting diode 120, the fifth active layer ACT5 may be formed of amorphous silicon.

[0105] A second gate insulating layer 112b is disposed on the fifth active layer ACT5, and a fifth gate electrode GE5 is disposed on the second gate insulating layer 112b. The fifth gate electrode GE5 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0106] A third interlayer insulating layer 113c is disposed on the fifth gate electrode GE5, and a fifth source electrode SE5 and a fifth drain electrode DE5 are disposed on the third interlayer insulating layer 113c. The fifth source electrode SE5 and the fifth drain electrode DE5 may be electrically connected to the fifth active layer ACT5 through a contact hole formed on the third interlayer insulating layer 113c. The fifth source electrode SE5 and the fifth drain electrode DE5 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0107] Next, a capacitor Cst is disposed on the first gate insulating layer 112a. The capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2.

[0108] First, a first capacitor electrode C1 is disposed on the first gate insulating layer 112a. The first capacitor electrode C1 may be connected to a driving gate electrode DGE disposed on the same layer. The first capacitor electrode C1 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0109] A second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 is disposed to overlap with the first capacitor electrode C1, wherein the first interlayer insulating layer 113a is located therebetween. The second capacitor electrode C2 may be electrically connected to the high potential power line VDD. The second capacitor electrode C2 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0110] Next, a high potential power line VDD is disposed on the third interlayer insulating layer 113c. The high potential power line VDD may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0111] An auxiliary electrode BCE is provided between the high potential power line VDD and the light shielding layer BSM. The auxiliary electrode BCE is provided between the light shielding layer BSM and the high potential power line VDD on the first gate insulating layer 112a. The auxiliary electrode BCE may electrically connect the high potential power line VDD to the light shielding layer BSM. If the light shielding layer BSM floats, the threshold voltage of the driving transistor DT fluctuates, thereby affecting the driving of the display device 100. Therefore, by electrically connecting the light shielding layer BSM to the high potential power line VDD to which a constant voltage is applied through the auxiliary electrode BCE, the light shielding layer BSM may be inhibited from operating as a floating gate. In addition, the fluctuation of the threshold voltage of the driving transistor DT generated by the floating light shielding layer BSM may be minimized. The auxiliary electrode BCE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0112] Next, a first planarization layer 114a is disposed on the driving transistor DT, the fifth transistor T5, the capacitor Cst, and the high potential power line VDD. The first planarization layer 114a may planarize the upper portion of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 114a may be configured by a single layer or a double layer, and may be configured by, for example, benzocyclobutene, photoresist, or acrylic organic material, but is not limited thereto.

[0113] A plurality of reflective layers RE are disposed on the first planarization layer 114a. The reflective layer RE is a configuration that reflects light emitted from the light emitting diode 120 to the upper portion of the substrate 110, and may be disposed to overlap the light emitting diode 120. The reflective layer RE may also be disposed to overlap a circuit configuration of the sub-pixel SP, such as the fifth transistor T5.

[0114] The reflective layer RE reflects light emitted from the light emitting diode 120 and also serves as an electrode electrically connecting the light emitting diode 120 to the pixel configuration of the sub-pixel SP. For example, the reflective layer RE may serve as an electrode electrically connecting the driving transistor DT to the light emitting diode 120. Therefore, considering light reflection efficiency and resistance, the reflective layer RE may include various conductive layers. For example, the reflective layer RE may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, and a transparent conductive layer such as indium tin oxide ITO, but the material of the reflective layer RE is not limited thereto.

[0115] The reflective layer RE includes an opening REO. The opening REO of the reflective layer RE may be arranged to overlap with the fifth transistor T5. The opening REO of the reflective layer RE may be arranged to overlap with at least a portion of the light emitting diode 120. Some of the light emitted from the light emitting diode 120 may be incident on the fifth transistor T5 through the opening REO of the reflective layer RE. Therefore, when the light of the light emitting diode 120 is incident on the fifth transistor T5 through the opening REO of the reflective layer RE, an off current may flow through the fifth transistor T5, and the intensity of the light of the light emitting diode 120 may be sensed.

[0116] An adhesive layer 115 is disposed on the reflective layer RE. The adhesive layer 115 is formed on the entire surface of the substrate 110 to fix the light emitting diode 120 disposed on the adhesive layer 115. The adhesive layer 115 may be formed of a light-curable adhesive material that is cured by light. For example, the adhesive layer 115 may be formed of an acrylic material including a photoresist, but is not limited thereto.

[0117] A light emitting diode 120 is disposed on the adhesive layer 115 in each of the plurality of sub-pixels SP. The light emitting diode 120 is an element that emits light by current, and may include a red light emitting diode 120 that emits red light, a green light emitting diode 120 that emits green light, and a blue light emitting diode 120 that emits blue light, and light having various colors including white light may be realized by a combination thereof.

[0118] The light emitting diode 120 includes a first semiconductor layer 121 , an emission layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 , and an encapsulation layer 126 .

[0119] A first semiconductor layer 121 is disposed on the adhesive layer 115, and a second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers in which n-type impurities and p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0120] An emission layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The emission layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The emission layer 122 may be formed of a single layer or a multiple quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0121] A first electrode 124 is provided on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT to the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with p-type impurities and the first electrode 124 may be an anode. The first electrode 124 may be provided on the top surface of the first semiconductor layer 121 exposed from the emission layer 122 and the second semiconductor layer 123. The first electrode 124 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0122] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode that electrically connects the low potential power line VSS to the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with n-type impurities and the second electrode 125 may be a cathode. The second electrode 125 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0123] However, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities and the first electrode 124 may be a cathode, and the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities and the second electrode 125 may be an anode, but is not limited thereto.

[0124] Next, an encapsulation layer 126 is provided to surround the first semiconductor layer 121, the emission layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 is formed of an insulating material to protect the first semiconductor layer 121, the emission layer 122, and the second semiconductor layer 123. Contact holes exposing the first electrode 124 and the second electrode 125 are formed in the encapsulation layer 126 to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the first electrode 124 and the second electrode 125.

[0125] At the same time, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation layer 126. The light emitting diode 120 manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light emitting diode 120 from the wafer, a portion of the encapsulation layer 126 may be torn. For example, during the process of separating the light emitting diode 120 from the wafer, a portion of the encapsulation layer 126 adjacent to the lower edge of the first semiconductor layer 121 of the light emitting diode 120 is torn. Therefore, a portion of the lower side surface of the first semiconductor layer 121 may be exposed to the outside through the encapsulation layer 126. Although the lower portion of the light emitting diode 120 is exposed from the encapsulation layer 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after the second planarization layer 114b and the third planarization layer 114c covering the side surface of the first semiconductor layer 121. Therefore, short circuit defects can be reduced or prevented.

[0126] Meanwhile, in the present disclosure, it is described that the driving transistor DT is electrically connected to the first semiconductor layer 121 and the first electrode 124 of the light emitting diode 120, and the low potential power line VSS is electrically connected to the second semiconductor layer 123 and the second electrode 125 of the light emitting diode 120, but it is not limited thereto. For example, the high potential power line VDD or the low potential power line VSS may be connected to the first semiconductor layer 121 and the first electrode 124 of the light emitting diode 120, and the driving transistor DT may be electrically connected to the second semiconductor layer 123 and the second electrode 125 of the light emitting diode 120, but it is not limited thereto.

[0127] A second planarization layer 114b is disposed on the adhesive layer 115 and the light emitting diodes 120. The second planarization layer 114b overlaps a portion of the side surface of the plurality of light emitting diodes 120 to fix and protect the plurality of light emitting diodes 120. The torn portion of the encapsulation layer 126 protecting the side surface of the first semiconductor layer 121 of the light emitting diodes 120 may be covered by the second planarization layer 114b. By doing so, contact of the connection electrode with the first semiconductor layer 121 and a short circuit defect may be suppressed thereafter.

[0128] A first connection electrode CE1 is disposed on the second planarization layer 114b. The first connection electrode CE1 is an electrode that electrically connects the first electrode 124 of the light emitting diode 120 to the driving transistor DT. The first connection electrode CE1 may be connected to the reflective layer RE through a contact hole formed in the second planarization layer 114b and the adhesive layer 115. At this time, the reflective layer RE is also connected to the driving drain electrode DDE of the driving transistor DT, so that the driving drain electrode DDE of the driving transistor DT and the first electrode 124 of the light emitting diode 120 may be electrically connected to each other. The first connection electrode CE1 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0129] Next, a third planarization layer 114c is disposed on the first connection electrode CE1 and the light emitting element 120. The third planarization layer 114c is formed to cover the upper portion of the light emitting diode 120. A contact hole may be formed in the third planarization layer 114c to expose the second electrode 125 of the light emitting diode 120. The third planarization layer 114c is disposed in the first electrode 124 and in the region between the first connection electrode CE1 and the second electrode 125 to reduce a short circuit defect in a vertical direction. The third planarization layer 114c may be configured of a single layer or a double layer, and is configured of, for example, benzocyclobutene, a photoresist, or an acrylic organic material, but is not limited thereto.

[0130] A second connection electrode CE2 is disposed on the third planarization layer 114c. The second connection electrode CE2 is an electrode that electrically connects the second electrode 125 of the light emitting diode 120 to the low potential power line VSS. The second connection electrode CE2 may be electrically connected to the second electrode 125 of the light emitting diode 120 through a contact hole formed in the third planarization layer 114c. The second connection electrode CE2 may be formed of a transparent conductive material so that light emitted from the light emitting diode 120 can travel to the outside of the display device 100, and for example, the second connection electrode CE2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0131] Meanwhile, although not shown in the figure, a bank may be provided on the third planarization layer 114c in a region between the plurality of sub-pixels SP and the second connection electrode CE2. The bank is provided to be spaced apart from the light emitting diode 120 at a predetermined interval and may at least partially overlap the reflective layer RE. The bank may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of, for example, a black resin, but is not limited thereto.

[0132] In addition, a protective layer may be provided on the bank, the third planarization layer 114c, and the second connection electrode CE2. The protective layer is a layer for protecting the configuration below the protective layer. The protective layer may be configured by a single layer or a double layer, and may be configured by, for example, benzocyclobutene, light-transmitting epoxy resin, photoresist, or acrylic organic material, but is not limited thereto.

[0133] In the display device 100 according to the exemplary embodiment of the present disclosure, the fifth transistor T5 is disposed under the light emitting diode 120, and the opening REO is formed in the reflective layer RE disposed between the light emitting diode 120 and the fifth transistor T5. Therefore, the fifth transistor T5 can sense the light of the light emitting diode 120. In order to increase the luminous efficiency of the light emitted from the light emitting diode 120, the reflective layer RE can be formed under the light emitting diode 120. At this time, the opening REO is formed on the reflective layer RE so that some of the light emitted from the light emitting diode 120 can be incident on the fifth transistor T5. The off current of the fifth transistor T5 varies according to the amount of light incident on the fifth transistor T5 to change the voltage of the fifth node N5, and the voltage change is detected to sense the brightness of the sub-pixel SP. Therefore, the brightness of the sub-pixel SP can be simply sensed using the fifth transistor T5, and the brightness deviation of each sub-pixel SP or the brightness deviation between multiple sub-pixels SP can be compensated according to the brightness sensing result.

[0134] In the display device 100 according to the exemplary embodiment of the present disclosure, the sensing unit (or circuit) SPb that directly senses the light of the light emitting diode 120 is embedded in the sub-pixel, so that the structure and driving process of the sub-pixel SP can be simplified. The brightness of each of the plurality of sub-pixels SP is affected by various factors, such as the degradation or efficiency difference of the light emitting diode 120 and the threshold voltage deviation of the driving transistor DT. In the display device 100 according to the exemplary embodiment of the present disclosure, the degradation level of the light emitting diode 120 or the threshold voltage deviation of the driving transistor DT is not sensed or compensated separately. However, the sub-pixel SP directly senses the light emitted from the light emitting diode 120 to compensate for the brightness deviation. That is, the sensing unit SPb can be used to compensate for the final emitted light, so that it can have the effect of compensating for both the threshold voltage deviation of the driving transistor DT and the degradation of the light emitting diode 120. In addition, a separate period for internal compensation of the sub-pixel SP is not required, so that the driving process can be simplified. Therefore, in order to compensate for the brightness deviation between the plurality of sub-pixels SP, it is not necessary to use a complex internal compensation circuit, etc., and the circuit configuration of the light emitting unit SPa of the sub-pixel SP and the driving process of the sub-pixel SP can be simplified.

[0135] In addition, as in the display device 100 according to the exemplary embodiment of the present disclosure, when the sensing unit SPb including the fifth transistor T5 directly senses light to compensate for the brightness, it can have the same effect as the camera compensation. Specifically, before the display device 100 is shipped, the brightness deviation can be compensated by directly sensing light using the camera, but after the display device 100 is shipped, such camera compensation is impossible. However, the sensing unit SPb that directly senses light is included in the sub-pixel SP, so that after the display device 100 is shipped, the brightness deviation can be compensated and the brightness can be compensated as efficiently as the camera compensation. In addition, while driving the display device 100, the brightness deviation between the sub-pixels SP can be sensed and compensated in real time, so that the display quality of the image can be improved.

[0136] Exemplary embodiments of the present disclosure may also be described as follows:

[0137] According to one aspect of the present disclosure, a display device may include: a display panel, which includes a plurality of sub-pixels, wherein at least one of the sub-pixels includes: a light-emitting diode, which is configured to emit light; a light-emitting circuit, which is configured to drive the light-emitting diode; and a sensing circuit, which includes a light-sensing transistor, which is configured to sense light emitted from the light-emitting diode.

[0138] The display device may further include a first voltage line connected to a gate electrode of the light sensing transistor, and the first voltage line may be configured to apply an off-level voltage to the gate electrode of the light sensing transistor for turning off the light sensing transistor.

[0139] The first voltage line may be configured to continuously apply an off-level voltage to a gate electrode of the light-sensing transistor.

[0140] The light emitting circuit may include: a driving transistor including a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode; an emission control transistor connected between the drain electrode of the driving transistor and a third node; a first transistor having a drain electrode connected to the first node; and a second transistor connected between a third node and a fourth node, and a light emitting diode may be connected between the third node and a low potential power line.

[0141] The sensing circuit may include: a third transistor connected between the fourth node and the fifth node; a fourth transistor connected between the sensing line and the fifth node, and the light sensing transistor connected between the fifth node and the low potential power line.

[0142] The light sensing transistor may include an active layer formed of amorphous silicon.

[0143] At least one transistor among the driving transistor, the emission control transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor may include one of an active layer formed of polysilicon or an active layer formed of an oxide semiconductor.

[0144] The light sensing transistor may be configured to allow an off current to flow in an off state, and to allow a higher off current to flow as the intensity of light incident on the light sensing transistor is higher.

[0145] At least one of the subpixels can be configured to be driven in the order of an initialization period and a light emitting period including a sensing period, and the second transistor and the third transistor can be configured to be turned on during the initialization period to apply an initialization voltage from the initialization line to the third node and the fifth node.

[0146] During the light emission period, the light sensing transistor may be configured to flow an off current and a voltage at the fifth node may be configured to decrease, and during the sensing period, the fourth transistor may be configured to be turned on to electrically connect the fifth node with the sensing line.

[0147] The sensing period and the light emitting period may overlap.

[0148] The display device may further include a reflective layer disposed between the light sensing transistor and the light emitting diode.

[0149] The reflective layer may include an opaque conductive layer having an opening overlapping the light sensing transistor and the light emitting diode.

[0150] The light emitting circuit may include a driving transistor configured to drive the light emitting diode, and the reflective layer may be electrically connected between the driving transistor and the light emitting diode.

[0151] According to another aspect of the present disclosure, a display device includes: a substrate; a light sensing transistor disposed on the substrate; a reflective layer disposed on the light sensing transistor; and a light emitting diode disposed on the reflective layer, the reflective layer may include an opening overlapping the light sensing transistor.

[0152] The light sensing transistor may be configured to sense light emitted from the light emitting diode and incident on the light sensing transistor through the opening.

[0153] The opening may overlap at least a portion of the light emitting diode.

[0154] The display device may further include a light shielding layer disposed between the substrate and the light sensing transistor, and the light shielding layer may overlap the light sensing transistor.

[0155] The light sensing transistor may include an active layer formed of amorphous silicon.

[0156] The display device may further include a driving transistor on the substrate and electrically connected to the light emitting diode, and the reflective layer may be electrically connected between the driving transistor and the light emitting diode.

[0157] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel comprising a plurality of sub-pixels, at least one of the sub-pixels comprising: a light emitting diode configured to emit light; a light emitting circuit configured to drive the light emitting diode; and A sensing circuit includes a light sensing transistor configured to sense light emitted from the light emitting diode.

2. The display device according to claim 1, further comprising: a first voltage line connected to the gate electrode of the light sensing transistor, The first voltage line is configured to apply an off-level voltage to a gate electrode of the light sensing transistor to turn off the light sensing transistor.

3. The display device according to claim 2, wherein: The first voltage line is configured to continuously apply the off-level voltage to the gate electrode of the light-sensing transistor.

4. The display device according to claim 1, wherein: The lighting circuit comprises: a driving transistor including a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode; an emission control transistor connected between the drain electrode of the drive transistor and the third node; a first transistor having a drain electrode connected to the first node; and a second transistor connected between the third node and the fourth node, and Wherein, the light emitting diode is connected between the third node and the low potential power line.

5. The display device according to claim 4, wherein: The sensing circuit further comprises: a third transistor connected between the fourth node and the fifth node; and a fourth transistor connected between the sensing line and the fifth node, The light sensing transistor is connected between the fifth node and the low potential power line.

6. The display device according to claim 5, wherein: The light-sensing transistor includes an active layer formed of amorphous silicon.

7. The display device according to claim 6, wherein: At least one transistor among the driving transistor, the emission control transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor includes one of an active layer formed of polysilicon or an active layer formed of an oxide semiconductor.

8. The display device according to claim 5, wherein: The light sensing transistor is configured to allow an off current to flow in an off state, and is configured to cause a higher off current to flow as the intensity of light incident on the light sensing transistor is higher.

9. The display device according to claim 8, wherein: The at least one sub-pixel among the sub-pixels is configured to be driven in the order of an initialization period and a light emitting period including a sensing period, and The second transistor and the third transistor are configured to be turned on during the initialization period to apply an initialization voltage from an initialization line to the third node and the fifth node.

10. The display device according to claim 9, wherein: During the light emitting period, the light sensing transistor is configured to cause the off current to flow, and the voltage at the fifth node is configured to decrease; as well as During the sensing period, the fourth transistor is configured to be turned on to electrically connect the fifth node with the sensing line.

11. The display device according to claim 10, wherein: The sensing period overlaps with the light emitting period. 12 . The display device according to claim 1 , further comprising a reflective layer disposed between the light sensing transistor and the light emitting diode.

13. The display device according to claim 12, wherein: The reflective layer includes an opaque conductive layer having an opening, and the opening overlaps the light sensing transistor and the light emitting diode.

14. The display device according to claim 13, wherein: The light emitting circuit includes a driving transistor configured to drive the light emitting diode, and The reflective layer is electrically connected between the driving transistor and the light emitting diode.

15. A display device, comprising: substrate; a light sensing transistor disposed on the substrate; a reflective layer disposed on the light sensing transistor; as well as A light emitting diode is arranged on the reflective layer, The reflective layer includes an opening overlapping with the light sensing transistor.

16. The display device according to claim 15, wherein: The light sensing transistor is configured to sense light emitted from the light emitting diode and incident on the light sensing transistor through the opening.

17. The display device according to claim 15, wherein: The opening overlaps at least a portion of the light emitting diode.

18. The display device according to claim 15, further comprising: A light shielding layer is disposed between the substrate and the light sensing transistor, Wherein, the light shielding layer overlaps with the light sensing transistor.

19. The display device according to claim 15, wherein: The light-sensing transistor includes an active layer formed of amorphous silicon.

20. The display device according to claim 15, further comprising: a driving transistor on the substrate and electrically connected to the light emitting diode, Wherein, the reflective layer is electrically connected between the driving transistor and the light emitting diode.

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