Display panel and display device

Abstract

The invention relates to the technical field of display, in particular to a display panel and a display device. The display panel comprises a pixel circuit and a light-emitting element, the pixel circuit comprises a driving module, a light-emitting control module and a first control module, the control end of the light-emitting control module is connected with a first control line, and the control end of the first control module is connected with a second control line; the output end of the first shift register is electrically connected with the first control line, and the output end of the second shift register is electrically connected with the second control line; the first power supply signal line is electrically connected with the first shift register, the second power supply signal line is electrically connected with the second shift register, and the first power supply signal line and the second power supply signal line are separated from each other; the first power supply signal line and the second power supply signal line are connected to a high level signal or a low level signal. The display panel and the display device effectively solve the problem that in the prior art, when a display panel performs low-gray-scale display, regular bright and dark cross grains are prone to occurring.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is a current-type organic light-emitting device, which refers to a device that emits light through carrier injection and recombination of organic semiconductor materials and luminescent materials under the drive of an electric field. OLED has become one of the research hotspots in the display field because of its excellent color saturation, contrast and response speed, and because its material is thinner, transparent, flexible, and can realize a variety of designs.

[0003] However, the existing organic light emitting display panels are prone to regular bright and dark horizontal stripes when displaying low grayscale, which greatly affects the display quality. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a display panel and a display device, which effectively solves the problem that the display panel in the prior art is prone to regular light and dark horizontal stripes when displaying low grayscale, resulting in the display quality not being effectively improved.

[0005] The present disclosure provides a display panel, comprising: an electrically connected pixel circuit and a light-emitting element, the pixel circuit comprising a driving module, a light-emitting control module and a first control module, the control end of the light-emitting control module being connected to a first control line, and the control end of the first control module being connected to a second control line; the display panel comprising a first shift register and a second shift register, the output end of the first shift register being electrically connected to the first control line, and the output end of the second shift register being electrically connected to the second control line; the display panel further comprising a first power signal line and a second power signal line, the first power signal line being electrically connected to the first shift register, the second power signal line being electrically connected to the second shift register, and the first power signal line and the second power signal line being isolated from each other; the first power signal line and the second power signal line are both connected to a high-level signal or are both connected to a low-level signal.

[0006] The present disclosure also provides a display device, comprising the above-mentioned display panel.

[0007] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0008] In the display panel provided by the present disclosure, the first power signal line and the second power signal line are isolated from each other, that is, the first power signal line and the second power signal line are disconnected, that is, the power signal transmitted on the first power signal line will not affect the power signal transmitted on the second power signal line, so that when the power signal used to drive the first control signal has a potential fluctuation with the first control signal period as a unit, the power signal used to drive the second control signal will not be coupled, so that the second control signal will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, and is conducive to improving the display quality.

[0009] Correspondingly, the display device provided by the present disclosure also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0012] Figure 1 It is a planar schematic diagram of a display panel in the prior art;

[0013] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element in a display panel is provided;

[0014] Figure 3 yes Figure 2 Corresponding signal timing diagram;

[0015] Figure 4 yes Figure 2 A timing diagram of the corresponding EM signal;

[0016] Figure 5 yes Figure 2 Another timing diagram of the corresponding EM signal;

[0017] Figure 6 yes Figure 1 A circuit diagram of a shift register unit in a display panel is provided;

[0018] Figure 7 yes Figure 1 A schematic diagram of the display panel showing a horizontal stripe phenomenon;

[0019] Figure 8 is a plan view schematic diagram of a display panel provided by the present disclosure;

[0020] Fig. 9 is a plan view schematic diagram of another display panel provided by the present disclosure;

[0021] Fig.10 is a plan view of another display panel provided by the present disclosure;

[0022] Fig.11 is a plan view of another display panel provided by the present disclosure;

[0023] Fig.12 is a plan view of another display panel provided by the present disclosure;

[0024] Fig.13 is a plan view of another display panel provided by the present disclosure;

[0025] Fig.14 is a plan view of another display panel provided by the present disclosure;

[0026] Fig.15 is a plan view of another display panel provided by the present disclosure;

[0027] Fig.16 is a plan view of another display panel provided by the present disclosure;

[0028] Fig.17 is a plan view of another display panel provided by the present disclosure;

[0029] Fig.18 It is a plan view of a display device provided by the present disclosure. DETAILED DESCRIPTION

[0030] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0032] Figure 1 is a planar schematic diagram of a display panel in the prior art. Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between a pixel circuit and a light-emitting element in a display panel is provided. Figure 3 yes Figure 2 The corresponding signal timing diagram is: Figure 4 yes Figure 2 A timing diagram of the corresponding EM signal, Figure 5 yes Figure 2 Another timing diagram of the corresponding EM signal, Figure 6 yes Figure 1 A circuit diagram of a shift register unit in a display panel is provided, Figure 7 yes Figure 1 The schematic diagram of the display panel showing the horizontal stripe phenomenon is shown in FIG. Figure 1-Figure 7 In the prior art, the display panel generally includes an electrically connected pixel circuit 1 and a light emitting element 2. The pixel circuit 1 may be an 8T1C pixel circuit, that is, the pixel circuit 1 includes 8 transistors (transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8) and 1 capacitor (capacitor Cst), wherein the transistor T4 and the transistor T5 electrically connected to the gate of the transistor T3 are both N-type transistors, and the remaining transistors are P-type transistors. That is, the transistor T4 and the transistor T5 are turned on when the gate potential is high, and the remaining transistors are turned on when the gate potential is low. Figure 2 The potential of the N4 node in the provided pixel circuit is the anode potential of the OLED light-emitting element, and the potential difference between the anode potential and the cathode potential of the OLED light-emitting element determines the magnitude of the current flowing through the OLED light-emitting element. Figure 2 The transistor T7 in the pixel circuit is used to reset the potential of the N4 node. It should be noted that the present disclosure does not elaborate on the connection structure and working principle of the above pixel circuit, and the details can be understood by referring to the explanation of the pixel circuit in the related art.

[0033] In the display panel, the gate control signal of transistor T1 and transistor T6 is EM signal, the gate control signal of transistor T2 is SP signal, the gate control signal of transistor T4 is S2N signal, the gate control signal of transistor T5 is S1N signal, the gate control signal of transistor T7 and transistor T8 is SPX signal, the switching level of EM signal, SP signal, S1N signal, S2N signal and SPX signal is high level / low level, wherein the high level is the effective signal for controlling the conduction of transistors T4 and transistor T5, and the low level is the effective signal for controlling the conduction of other transistors except transistor T4 and transistor T5. SPX signal, EM signal, SP signal, S1N signal, S2N signal and SPX signal are usually generated and provided by a gate driving circuit (GOA, Gate on Array), and the gate driving circuit includes a plurality of shift registers 3, and SPX signal, EM signal, SP signal, S1N signal, S2N signal and SPX signal are usually generated and provided by different shift registers 3. The shift register 3 generally includes cascaded shift register units, and the output signal of each shift register unit is used as both a control signal of the corresponding transistor in each row of pixel circuits 1 and an input signal of the next shift register unit. The first-level signal input is generated by the driver chip configuration. Accordingly, in order to drive the shift register units of each level to output the drive signal, the driver chip needs to input a power signal to the shift register 3, and the power signal includes a high-level signal and a low-level signal. For example, refer to Figure 6 , the driving chip provides the shift register unit with power signals (VGL signal, VGH signal), clock signals (CK signal, XCK signal) and start signals (STV signal), so that the output end of the shift register unit outputs corresponding control signals to the transistors in the pixel circuit connected thereto, thereby realizing the control of the state of the transistors in the pixel circuit. In the prior art, the power signal line connected to the shift register 3 for outputting the EM signal and the power signal line connected to the shift register 3 for outputting the SPX signal are usually connected and arranged.

[0034] It should be noted that Figure 6 The circuit of the shift register unit for outputting the EM signal and the shift register unit for outputting the SPX signal can be adopted as an example. Figure 6The circuit structure of the shift register unit, the present disclosure does not elaborate on the connection structure and working principle of the above-mentioned shift register unit, and the specific explanation of the shift register unit in the related art can be referred to for understanding. The circuits of the two may also be different, but both need to use power signals, clock signals and start signals to generate and transmit signals. Of course, the display panel also includes a shift register 3 for outputting an SP signal, a shift register 3 for outputting an S1N signal, and a shift register 3 for outputting an S2N signal. Similarly, the driving chip provides a power signal (VGL signal, VGH signal), a clock signal (CK signal and / or XCK signal) and a start signal (STV signal) to the shift register unit in this part of the shift register 3, so that the output end of the shift register unit outputs a corresponding control signal to the transistor in the pixel circuit connected thereto, thereby realizing the control of the state of the transistor in the pixel circuit. The present disclosure does not elaborate on the specific circuit structure and working principle of the shift register unit in this part of the shift register 3, and the specific explanation of the shift register unit in the related art can be referred to for understanding.

[0035] The display panel generally includes a display area (active area) and a porch area (this area is used to prepare for some voltage conversions, and can also be understood as a display blanking area. In display technology, it refers to the area on the display screen used for synchronization signal transmission, rather than the area used to display images. Generally, the active area is followed by the porch area. The porch area is a specific time period when the display device displays an image. During this period, no valid image information is displayed, but it is used for the transmission and processing of synchronization signals to ensure the correct synchronization and stable operation of the display device). The porch area is fixed, and the EM signal is a driving signal with multiple pulses. Therefore, during the display period, different areas of the display panel will have corresponding EM signals falling in the porch area, which will cause light and dark horizontal stripes. Specifically, if Figure 4 As shown, the EM signal has a falling edge in the porch area. At this time, there is no actual jump load, so the jump load of the low-level signal used to drive the falling edge of the EM signal is reduced, and the voltage value of the low-level signal used to drive the EM signal is relatively lower than the set value, so that the difference between the low-level signal and the high-level signal used to drive the EM signal becomes relatively larger; because the power signal line connected to the shift register 3 for outputting the EM signal and the power signal line connected to the shift register 3 for outputting the SPX signal are usually connected and set, that is, the low-level signal used to drive the EM signal and the low-level signal used to drive the SPX signal are common signals, when the difference between the low-level signal and the high-level signal used to drive the EM signal becomes relatively larger, the SPX signal jumps high coupling more, the N4 node potential is higher, and the brightness is brighter. Figure 5As shown, the falling edge of the EM signal is not in the porch area. At this time, for the display area (active area) of the display panel, the low-level signal used to drive the falling edge of the EM signal has an additional jump-down load, and the voltage value of the low-level signal used to drive the EM signal is relatively higher than the set value, so that the difference between the low-level signal and the high-level signal used to drive the EM signal is relatively smaller; because the power signal line connected to the shift register 3 for outputting the EM signal and the power signal line connected to the shift register 3 for outputting the SPX signal are usually connected and set, that is, the low-level signal used to drive the EM signal and the low-level signal used to drive the SPX signal are common signals, when the difference between the low-level signal and the high-level signal used to drive the EM signal becomes relatively smaller, the SPX signal jump-up coupling amount becomes less, the N4 node potential is low, and the brightness is dim. The final display screen presents Figure 7 The display panel 100 ′ in the prior art shown is prone to regular bright and dark horizontal stripes.

[0036] From the above, it can be seen that in the prior art, when the display panel displays at a low grayscale, the states of the falling edge of the EM signal entering and exiting the porch area are different at different times, and the low-level signal used to drive the falling edge of the EM signal has a potential fluctuation in units of the EM signal period. Since the low-level signal used to drive the EM signal and the low-level signal used to drive the SPX signal are common signals, the coupling amount of the SPX signal also fluctuates periodically, resulting in the appearance of light and dark horizontal stripes in the low grayscale picture.

[0037] Similarly, in the prior art, when the display panel displays at a low grayscale, the states of the rising and falling edges of the EM signal entering and exiting the porch area are different at different times, and the high-level signal used to drive the rising and falling edges of the EM signal has a potential fluctuation in units of the EM signal period. Since the high-level signal used to drive the EM signal and the high-level signal used to drive the SPX signal are common signals, the coupling amount of the SPX signal also fluctuates periodically, resulting in the appearance of light and dark horizontal stripes in the low grayscale picture.

[0038] Based on the above problems, the present application proposes a display panel and a display device, which can improve the display problem of horizontal stripes and enhance the display quality. Specific embodiments of the display panel and the display device proposed in the present application are described in detail as follows.

[0039] Figure 8 is a plan view of a display panel provided by the present disclosure, wherein the structure of the pixel circuit in the display panel provided by the embodiment of the present disclosure can refer to Figure 2 ,refer to Figure 2 and Figure 8The embodiment of the present disclosure provides a display panel, the display panel comprising: a pixel circuit 10 and a light emitting element 20 electrically connected, the pixel circuit 10 comprising a driving module 11, a light emitting control module 12 and a first control module 13, the control end of the light emitting control module 12 is connected to a first control line S1, and the control end of the first control module 13 is connected to a second control line S2;

[0040] The display panel includes a first shift register 31 and a second shift register 32, wherein an output end of the first shift register 31 is electrically connected to a first control line S1, and an output end of the second shift register 32 is electrically connected to a second control line S2;

[0041] The display panel further includes a first power signal line L1 and a second power signal line L2, the first power signal line L1 is electrically connected to the first shift register 31, the second power signal line L2 is electrically connected to the second shift register 32, and the first power signal line L1 and the second power signal line L2 are isolated from each other;

[0042] The first power signal line L1 and the second power signal line L2 are both connected to high level signals or are both connected to low level signals.

[0043] Specifically, the display panel provided in this embodiment is an OLED display panel, which includes a pixel circuit 10 and a light-emitting element 20 that are electrically connected. The pixel circuit 10 is used to provide current to the light-emitting element 20 to enable the light-emitting element 20 to emit light.

[0044] The pixel circuit 10 includes a driving module 11, a light-emitting control module 12 and a first control module 13. The control end of the light-emitting control module 12 is connected to the first control line S1. The display panel includes a first shift register 31. The output end of the first shift register 31 is electrically connected to the first control line S1. The display panel also includes a first power signal line L1. The first power signal line L1 is electrically connected to the first shift register 31. The first power signal line L1 can be connected to the power signal, so that the power signal is transmitted to the first shift register 31 via the first power signal line L1. The first shift register 31 generates a first control signal (EM signal) based on the signal including the power signal, and transmits the first control signal (EM signal) to the control end of the light-emitting control module 12 via the first control line S1, thereby realizing the control of the state of the light-emitting control module 12.

[0045] The control end of the first control module 13 is connected to the second control line S2, the display panel includes a second shift register 32, the output end of the second shift register 32 is electrically connected to the second control line S2, the display panel also includes a second power signal line L2, the second power signal line L2 is electrically connected to the second shift register 32, the second power signal line L2 can also be connected to the power signal, so that the power signal is transmitted to the second shift register 32 via the second power signal line L2, the second shift register 32 generates a second control signal (SPX signal) based on the signal including the power signal, and transmits the second control signal (SPX signal) to the control end of the first control module 13 via the second control line S2, so that the state of the first control module 13 can be controlled.

[0046] Because when the display panel displays in low grayscale, the falling edge and / or rising edge of the first control signal (EM signal) enters and exits the porch area in different states at different times, the power supply signal used to drive the first control signal (EM signal) will have a potential fluctuation in units of the first control signal (EM signal) period.

[0047] In this embodiment, the first power signal line L1 and the second power signal line L2 are isolated from each other, that is, the first power signal line L1 and the second power signal line L2 are disconnected, that is, the power signal transmitted on the first power signal line L1 will not affect the power signal transmitted on the second power signal line L2, so that when the power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is beneficial to improving the display quality.

[0048] Both the first power signal line L1 and the second power signal line L2 can be connected to a high-level signal, that is, the first power signal line L1 can be used to connect to a high-level power signal, and at the same time, the second power signal line L2 can be used to connect to a high-level power signal. At this time, the first power signal line L1 and the second power signal line L2 are disconnected, that is, the high-level power signal transmitted on the first power signal line L1 will not affect the high-level power signal transmitted on the second power signal line L2, so that when the high-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the high-level power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is beneficial to improving the display quality.

[0049] Similarly, both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals, that is, the first power signal line L1 can be used to connect to low-level power signals, and at the same time, the second power signal line L2 can be used to connect to low-level power signals. At this time, the first power signal line L1 and the second power signal line L2 are disconnected, that is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2, so that when the low-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is beneficial to improving the display quality.

[0050] Continue to refer Figure 2 and Figure 8 Optionally, the first control module 13 includes a first reset module 131, the control end of the first reset module 131 is connected to the second control line S2, the first end of the first reset module 131 is connected to the REF2 signal, and the second end of the first reset module 131 is connected to the N4 node. The potential of the N4 node in the pixel circuit 10 is the anode potential of the light-emitting element 20. The first reset module 131 in the pixel circuit 10 is used to reset the potential of the N4 node. The first power signal line L1 and the second power signal line L2 are disconnected, that is, the power signal transmitted on the first power signal line L1 will not affect the power signal transmitted on the second power signal line L2, so that when the power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, and will not affect the potential of the N4 node, effectively improving the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is conducive to improving display quality.

[0051] Continue to refer Figure 2 and Figure 8 In some optional embodiments, the first control module 13 includes a bias adjustment module 132 , which is electrically connected to the driving module 11 , and is used to implement bias adjustment on the driving module 11 .

[0052] Specifically, the first control module 13 includes a bias adjustment module 132, a control end of the bias adjustment module 132 is connected to the second control line S2, a first end of the bias adjustment module 132 is connected to the DVH signal, and a second end of the bias adjustment module 132 is electrically connected to the driving module 11. The bias adjustment module 132 can be used to implement bias adjustment of the driving module 11.

[0053] The control end of the first reset module 131 can reuse the second control signal (SPX signal) transmitted to the control end of the bias adjustment module 132, that is, the control end of the bias adjustment module 132 and the control end of the first reset module 131 can both be connected to the second control line S2, which is beneficial to reduce circuit complexity and reduce wiring difficulty.

[0054] The timing sequence of the pixel circuit provided in the embodiment of the present disclosure can refer to Figure 3 ,refer to Figure 2 , Figure 3 and Figure 8 In some optional embodiments, in the low-frequency operation mode of the display panel, a holding period t2 is inserted between two writing periods t1, and the control signal (SPX signal) transmitted by the second control line S2 includes at least one pulse in the holding period t2.

[0055] Specifically, the first control module 13 includes a bias adjustment module 132, a control end of the bias adjustment module 132 is connected to the second control line S2, a first end of the bias adjustment module 132 is connected to the DVH signal, a second end of the bias adjustment module 132 is electrically connected to the driving module 11, and the bias adjustment module 132 can be used to implement bias adjustment of the driving module 11. In the low-frequency working mode of the display panel, a holding period t2 is inserted between two writing periods t1, and the control signal (SPX signal) transmitted by the second control line S2 includes at least one pulse in the holding period t2, so that in the holding period t2, the bias adjustment module 132 can perform bias adjustment on the driving module 11, which can effectively reduce the afterimage effect caused by a long-term static image in the low-frequency working mode of the display panel.

[0056] Continue to refer Figure 2 and Figure 8 In some optional embodiments, both the first power signal line L1 and the second power signal line L2 are connected to low level signals.

[0057] Specifically, when the second control signal (SPX signal) is a low-level signal, the first control module 13 is turned on. In this case, the fluctuation of the low-level power supply signal used to drive the second control signal (SPX signal) has a greater impact on the display problem of light and dark horizontal stripes on the display panel under low grayscale display.

[0058] Both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals, that is, the first power signal line L1 is a signal line for connecting to low-level power signals, and at the same time, the second power signal line L2 is also a signal line for connecting to low-level power signals. At this time, the first power signal line L1 and the second power signal line L2 are disconnected, that is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2, so that when the low-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is beneficial to improving the display quality.

[0059] Fig. 9 is a plan view of another display panel provided by the present disclosure, referring to Figure 2 and Fig. 9 In some optional embodiments, the first power signal line L1 and the second power signal line L2 are both connected to low-level signals, and the first shift register 31 is electrically connected to the first high-level signal line H1, and the second shift register 32 is electrically connected to the second high-level signal line H2, and the first high-level signal line H1 and the second high-level signal line H2 are connected to the same high-level potential.

[0060] Specifically, when the first power signal line L1 and the second power signal line L2 in the display panel are both connected to a low-level signal, the display panel also includes a first high-level signal line H1, and the first high-level signal line H1 is electrically connected to the first shift register 31. The first high-level signal line H1 can be connected to a power signal with a high-level potential, so that the power signal is transmitted to the first shift register 31 via the first high-level signal line H1. The first shift register 31 generates a first control signal (EM signal) based on the signal including the power signal, and transmits the first control signal (EM signal) to the control end of the light-emitting control module 12 via the first control line S1, thereby realizing the control of the state of the light-emitting control module 12.

[0061] The display panel also includes a second high-level signal line H2, which is electrically connected to the second shift register 32. The second high-level signal line H2 can be connected to a power signal with a high level potential, so that the power signal is transmitted to the second shift register 32 via the second high-level signal line H2. The second shift register 32 generates a second control signal (SPX signal) based on the signal including the power signal, and transmits the second control signal (SPX signal) to the control end of the first control module 13 via the second control line S2, thereby realizing the control of the state of the first control module 13.

[0062] The first high-level signal line H1 and the second high-level signal line H2 are connected to the same high-level potential, that is, the first high-level signal line H1 and the second high-level signal line H2 can share the same set of voltage settings, that is, the high-level potential provided to the first high-level signal line H1 and the second high-level signal line H2 by the same set of voltage adjustment modules in the driver chip is conducive to reducing the design difficulty of the driver chip and reducing the production cost of the driver chip.

[0063] Continue to refer Figure 2 and Fig. 9 In some optional embodiments, the absolute values ​​of the low-level signals connected to the first power signal line L1 and the second power signal line L2 are the same.

[0064] Specifically, both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals, that is, the first power signal line L1 is a signal line for connecting to low-level power signals, and at the same time, the second power signal line L2 is also a signal line for connecting to low-level power signals, and the first power signal line L1 and the second power signal line L2 are disconnected, but the absolute values ​​of the low-level signals connected to the first power signal line L1 and the second power signal line L2 are the same, that is, the first power signal line L1 and the second power signal line L2 can be connected to the same low-level signal, that is, the first power signal line L1 and the second power signal line L2 can share the same set of voltage settings, that is, the low-level potential provided to the first power signal line L1 and the second power signal line L2 by the same set of voltage regulation modules in the driver chip is conducive to reducing the design difficulty of the driver chip and reducing the production cost of the driver chip.

[0065] Continue to refer Fig. 9 The first high level signal line H1 and the second high level signal line H2 can be connected and set, so that the first high level signal line H1 and the second high level signal line H2 can be connected through the same pad 40, which is beneficial to reduce the number of pads 40, and is beneficial to reduce the occupied area of ​​the pad 40, thereby improving the space utilization of the display panel.

[0066] Optionally, the first high-level signal line H1 and the second high-level signal line H2 can be connected via a first connecting line 61, and the first connecting line 61 can be disposed on a side of the display panel away from the pad 40 along the second direction Y, thereby avoiding the setting of the first connecting line 61 from affecting the arrangement of signal lines connected to each pad 40.

[0067] Fig.10 is a plan view of another display panel provided by the present disclosure, referring to Fig.10In some optional embodiments, the first power signal line L1 and the second power signal line L2 are both connected to low-level signals, the first power signal line L1 and the second power signal line L2 are disconnected, and the first shift register 31 is electrically connected to the first high-level signal line H1, the second shift register 32 is electrically connected to the second high-level signal line H2, and the first high-level signal line H1 is disconnected from the second high-level signal line H2.

[0068] Specifically, when the first power signal line L1 and the second power signal line L2 in the display panel are both connected to the low-level signal, the first high-level signal line H1 and the second high-level signal line H2 can both be connected to the high-level signal, that is, the first high-level signal line H1 is a signal line for connecting to the high-level power signal, and at the same time, the second high-level signal line H2 is also a signal line for connecting to the high-level power signal. At this time, the first high-level signal line H1 and the second high-level signal line H2 are disconnected, that is, the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signal transmitted on the second high-level signal line H2, so that the high-level power signal used to drive the first control signal (EM signal) appears in the potential with the first control signal (EM signal) period as a unit. When the voltage of the first power signal line L1 fluctuates, the high-level power signal used to drive the second control signal (SPX signal) will not be coupled. At the same time, the first power signal line L1 and the second power signal line L2 are disconnected, that is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2. Therefore, when the low-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled either. Therefore, the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, and is conducive to improving the display quality.

[0069] Fig.11 is a plan view of another display panel provided by the present disclosure, referring to Figure 2 and Fig.11 In some optional embodiments, the pixel circuit 10 further includes a second control module 14, and a control end of the second control module 14 is connected to a third control line S3;

[0070] The display panel further includes a third shift register 33, an output end of the third shift register 33 is electrically connected to a third control line S3;

[0071] The display panel further includes a third power signal line L3, and the third power signal line L3 is electrically connected to the third shift register 33;

[0072] The second power signal line L2 and the third power signal line L3 are electrically connected, and the second power signal line L2 and the third power signal line L3 are both connected to high level signals or low level signals.

[0073] Specifically, in the display panel, the first power signal line L1 and the second power signal line L2 are both connected to a high-level signal or are both connected to a low-level signal. At this time, the first power signal line L1 and the second power signal line L2 are isolated from each other, that is, the power signal transmitted on the first power signal line L1 will not affect the power signal transmitted on the second power signal line L2. Therefore, when the power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, and is conducive to improving the display quality.

[0074] The pixel circuit 10 also includes a second control module 14, the control end of the second control module 14 is connected to the third control line S3, the display panel also includes a third shift register 33, the output end of the third shift register 33 is electrically connected to the third control line S3, the display panel also includes a third power signal line L3, the third power signal line L3 is electrically connected to the third shift register 33, the third power signal line L3 can also be connected to the power signal, so that the power signal is transmitted to the third shift register 33 via the third power signal line L3, the third shift register 33 generates a third control signal (SP signal) based on the signal including the power signal, and transmits the third control signal (SP signal) to the control end of the second control module 14 via the third control line S3, thereby realizing the control of the state of the second control module 14.

[0075] The first power signal line L1, the second power signal line L2 and the third power signal line L3 are all connected to high-level signals or are all connected to low-level signals, that is, the second power signal line L2 and the third power signal line L3 are connected to the same signal, the first power signal line L1, the second power signal line L2 and the third power signal line L3 are all connected to high-level signals, or the first power signal line L1, the second power signal line L2 and the third power signal line L3 are all connected to low-level signals.

[0076] When the first power signal line L1, the second power signal line L2 and the third power signal line L3 are all connected to a high-level signal, that is, the first power signal line L1 is a signal line for connecting a high-level power signal, the second power signal line L2 is a signal line for connecting a high-level power signal, and the third power signal line L3 is also a signal line for connecting a high-level power signal, at this time, the second power signal line L2 and the third power signal line L3 can be electrically connected, that is, the third power signal line L3 is disconnected from the first power signal line L1, so that when the power signal for driving the first control signal (EM signal) appears as the first control signal When the potential fluctuation of the (EM signal) period is a unit, the power signal used to drive the third control signal (SP signal) will not be coupled, so that the third control signal (SP signal) will not have periodic coupling fluctuations. At the same time, when the high-level signals required to be connected to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected, so that the second power signal line L2 and the third power signal line L3 can be connected through the same welding pad 40, which is beneficial to reduce the number of welding pads 40, reduce the occupied area of ​​the welding pads 40, and improve the space utilization of the display panel.

[0077] Similarly, when the first power signal line L1, the second power signal line L2 and the third power signal line L3 are all connected to low-level signals, that is, the first power signal line L1 is a signal line for connecting to a low-level power signal, the second power signal line L2 is a signal line for connecting to a low-level power signal, and the third power signal line L3 is also a signal line for connecting to a low-level power signal, at this time, the second power signal line L2 and the third power signal line L3 can be electrically connected, that is, the third power signal line L3 is disconnected from the first power signal line L1, so that when the power signal for driving the first control signal (EM signal) appears to be the first control signal, When the potential of the signal (EM signal) fluctuates in units of a period, the power signal used to drive the third control signal (SP signal) will not be coupled, so that the third control signal (SP signal) will not have periodic coupling fluctuations. At the same time, when the low-level signals required to be connected to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected, so that the second power signal line L2 and the third power signal line L3 can be connected through the same pad 40, which is beneficial to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0078] Optionally, when the types of transistors electrically connected to the second control line S2 and the transistors electrically connected to the third control line S3 are the same, the requirements for the high level in the driving signal required for the transistor electrically connected to the second control line S2 and the high level in the driving signal required for the transistor electrically connected to the third control line S3 are the same, and the requirements for the low level in the driving signal required for the transistor electrically connected to the second control line S2 and the low level in the driving signal required for the transistor electrically connected to the third control line S3 are the same, so that the second power signal line L2 and the third power signal line L3 can be electrically connected.

[0079] Continue to refer Figure 2 and Fig.11 In some optional embodiments, the pixel circuit 10 further includes a data writing module 141, and the data writing module 141 is used to write a data signal (DATA signal) into the driving module 11;

[0080] The second control module 14 includes a data writing module 141 .

[0081] Specifically, the pixel circuit 10 further includes a data writing module 141, the second control module 14 includes the data writing module 141, the control end of the data writing module 141 is connected to the third control line S3, the first end of the data writing module 141 is connected to the DATA signal, the second end of the data writing module 141 is connected to the driving module 11, and the data writing module 141 is used to write the data signal (DATA signal) into the driving module 11. The transistor T2 in the data writing module 141 is of the same type as the transistor T7 in the first reset module 131, so that the voltage setting of the driving signal can be the same for both, the second shift register 32 electrically connected to the second power signal line L2 is used to input the second control signal (SPX signal) to the first reset module 131, the third shift register 33 electrically connected to the third power signal line L3 is used to input the third control signal (SP signal) to the data writing module 141, and the second power signal line L2 and the third power signal line L3 are electrically connected. At this time, the normal operation and reliability of the transistor T2 in the data writing module 141 and the transistor T7 in the first reset module 131 will not be affected.

[0082] Continue to refer Figure 2 and Fig.11 In some optional embodiments, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32, and along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are respectively located on both sides of the display panel;

[0083] The first sub-shift register 331 is electrically connected to the first sub-power signal line L31, and the second sub-shift register 332 is electrically connected to the second sub-power signal line L32;

[0084] The first sub power signal line L31 and the second sub power signal line L32 are connected at least one side of the display panel along the second direction Y, wherein the first direction X intersects the second direction Y. Optionally, the first direction X and the second direction Y are perpendicular to each other.

[0085] Specifically, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, and the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32. Along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are respectively located on both sides of the display panel, and the first sub-shift register 331 and the second sub-shift register 332 are both connected to the third control line S3. The third control line S3 connected to the pixel circuits 10 arranged in the same row along the first direction X is electrically connected to the first sub-shift register 331 and the second sub-shift register 332 at the same time, that is, the third control signal (SP signal) is input to the data writing module 141 in the pixel circuit 10 through the dual driving structure, so that more pixel circuits 10 can be driven at the same time, reducing signal transmission delay and improving response speed.

[0086] The first sub-shift register 331 is electrically connected to the first sub-power signal line L31, and the second sub-shift register 332 is electrically connected to the second sub-power signal line L32. The first sub-shift register 331 and the second sub-shift register 332 are used to simultaneously input a third control signal (SP signal) to the data writing module 141 in the pixel circuit 10, so that the first sub-power signal line L31 electrically connected to the first sub-shift register 331 and the second sub-power signal line L32 electrically connected to the second sub-shift register 332 can be electrically connected. Along the second direction Y, the first sub-power signal line L31 and the second sub-power signal line L32 are connected on at least one side of the display panel.

[0087] Continue to refer Figure 2 and Fig.11 In some optional embodiments, the display panel includes a display area AA and a non-display area NA surrounding the display area AA, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA, and the second power signal line L2 and the third power signal line L3 are electrically connected in the first non-display area NA1 and / or the second non-display area NA2.

[0088] Specifically, the display panel includes a display area AA and a non-display area NA surrounding the display area AA, the display area AA is used for display, the non-display area NA is not used for display, and the non-display area NA is used to set structures such as a driving circuit. The non-display area NA includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA, and the second power signal line L2 and the third power signal line L3 can be electrically connected in the first non-display area NA1 and / or the second non-display area NA2 through the first connecting line 61, so that the second power signal line L2 and the third power signal line L3 can be electrically connected, and the setting of the display area AA will not be affected.

[0089] It should be noted that Fig.11 exemplarily shows that the second power signal line L2 and the third power signal line L3 are electrically connected in the first non-display area NA1. In other embodiments of the present disclosure, refer to Fig.12 , Fig.12 It is a plan schematic diagram of another display panel provided by the present disclosure, in which the second power signal line L2 and the third power signal line L3 are electrically connected in the first non-display area NA1 and the second non-display area NA2. Of course, the second power signal line L2 and the third power signal line L3 may also be electrically connected in the second non-display area NA2, thereby improving the stability and uniformity of the potential at each point in the second power signal line L2 and the third power signal line L3, which will not be elaborated in the present disclosure.

[0090] Continue to refer Fig.12 In some optional embodiments, the first sub-power signal line L31, the second sub-power signal line L32 and the second power signal line L2 are electrically connected to the same first power bus 50. Thus, the first sub-power signal line L31 and the second sub-power signal line L32 are electrically connected to the second power signal line L2, and the first sub-power signal line L31 and the second sub-power signal line L32 are electrically connected to the second power signal line L2 through the first power bus 50, which can simplify complex wiring design, save wiring space, and improve space utilization.

[0091] Continue to refer Fig.11 In some optional embodiments, the display panel includes a plurality of pads 40, the pads 40 include a first pad 41 and a second pad 42, and the second power signal line L2 and the third power signal line L3 are both electrically connected to the first pad 41 and the second pad 42;

[0092] Along the first direction X, the first pad 41 and the second pad 42 are respectively located at two ends of the display panel.

[0093] Specifically, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, and the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32. Along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are respectively located on both sides of the display panel, the first sub-shift register 331 is electrically connected to the first sub-power signal line L31, and the second sub-shift register 332 is electrically connected to the second sub-power signal line L32. Accordingly, along the first direction X, a first pad 41 and a second pad 42 are respectively provided at both ends of the display panel, and the second power signal line L2 and the third power signal line L3 are both electrically connected to the first pad 41 and the second pad 42, so that signals can be transmitted from the first pad 41 and the second pad 42 to the second power signal line L2 and the third power signal line L3 at the same time, which can effectively reduce the voltage drop and improve the uniformity of the signals transmitted to the second power signal line L2 and the third power signal line L3.

[0094] Optionally, at least one of the first sub-power signal line L31 and the second sub-power signal line L32 and the second power signal line L2 are electrically connected to the same first power bus 50. Fig.11 , when the second power signal line L2 and the third power signal line L3 are electrically connected in the first non-display area NA1 through the first connection line 61, the first sub-power signal line L31 is electrically connected to the first pad 41, and the second sub-power signal line L32 and the second power signal line L2 are electrically connected to the second pad 42 through the same first power bus 50. Of course, in other embodiments of the present disclosure, it can also be set that the first sub-power signal line L31 and the second power signal line L2 are electrically connected to the same first power bus 50, or the first sub-power signal line L31, the second sub-power signal line L32 and the second power signal line L2 are electrically connected to the same first power bus 50, and the present disclosure will not repeat them one by one here.

[0095] Continue to refer Fig.11 In some optional embodiments, the second power signal line L2 and the third power signal line L3 are both connected to a low level potential.

[0096] Specifically, both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals, that is, the first power signal line L1 is a signal line for connecting to low-level power signals, and at the same time, the second power signal line L2 is also a signal line for connecting to low-level power signals. At this time, the first power signal line L1 and the second power signal line L2 are disconnected, that is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2, so that when the low-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is beneficial to improving the display quality.

[0097] At the same time, the third power signal line L3 is also connected to a low-level potential, that is, the third power signal line L3 is also a signal line for connecting a low-level power signal. When the low-level signals required to be connected to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected, so that the second power signal line L2 and the third power signal line L3 can be connected through the same solder pad 40, which is beneficial to reducing the number of solder pads 40, reducing the occupied area of ​​the solder pads 40, and improving the space utilization of the display panel.

[0098] Fig.13 is a plan view of another display panel provided by the present disclosure, referring to Figure 2 and Fig.13 In some optional embodiments, the first shift register 31 is electrically connected to the first high level signal line H1, the second shift register 32 is electrically connected to the second high level signal line H2, the third shift register 33 is electrically connected to the third high level signal H3, and the first high level signal line H1 is disconnected from the second high level signal line H2 and the third high level signal line H3.

[0099] Specifically, both the first high-level signal line H1 and the second high-level signal line H2 can be connected to a high-level signal, that is, the first high-level signal line H1 is a signal line for connecting to a high-level power signal, and at the same time, the second high-level signal line H2 is also a signal line for connecting to a high-level power signal. At this time, the first high-level signal line H1 and the second high-level signal line H2 are disconnected, that is, the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signal transmitted on the second high-level signal line H2, so that when the high-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the high-level power signal used to drive the second control signal (SPX signal) will not be coupled, so that the second control signal (SPX signal) will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is beneficial to improving the display quality.

[0100] The third high-level signal line H3 can be connected to a high-level signal, that is, the third high-level signal line H3 is also a signal line for connecting a high-level power signal. The first high-level signal line H1 is disconnected from the third high-level signal line H3, that is, the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signal transmitted on the third high-level signal line H3, so that when the high-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, it will not affect the signal on the third high-level signal line H3.

[0101] Continue to refer Figure 2 and Fig.13 In some optional embodiments, the second power signal line L2 is electrically connected to the third power signal line L3, and the second high level signal line H2 is electrically connected to the third high level signal line H3.

[0102] Specifically, the second power signal line L2 and the third power signal line L3 are both connected to low-level signals, that is, the second power signal line L2 is a signal line for connecting to a low-level power signal, and the third power signal line L3 is also a signal line for connecting to a low-level power signal. When the low-level signals to be connected to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected, so that the second power signal line L2 and the third power signal line L3 can be connected through the same solder pad 40, which is beneficial to reducing the number of solder pads 40, reducing the occupied area of ​​the solder pads 40, and improving the space utilization of the display panel.

[0103] Similarly, the second high-level signal line H2 and the third high-level signal line H3 are both connected to the high-level signal, that is, the second high-level signal line H2 is a signal line for connecting to a high-level power signal, and the third high-level signal line H3 is also a signal line for connecting to a high-level power signal. When the high-level signals to be connected to the second high-level signal line H2 and the third high-level signal line H3 are the same, the second high-level signal line H2 and the third high-level signal line H3 can be electrically connected, so that the second high-level signal line H2 and the third high-level signal line H3 can be connected through the same welding pad 40, which is beneficial to reduce the number of welding pads 40, reduce the occupied area of ​​the welding pads 40, and improve the space utilization of the display panel.

[0104] Continue to refer Fig.13 In some optional embodiments, the pad 40 includes a third pad 43 and a fourth pad 44, and the second high level signal line H2 and the third high level signal line H3 are both electrically connected to the third pad 43 and the fourth pad 44;

[0105] Along the first direction X, the third pad 43 and the fourth pad 44 are respectively located at two ends of the display panel.

[0106] Specifically, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32, along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are respectively located on both sides of the display panel, the third high-level signal line H3 includes a third sub-power signal line H31 and a fourth sub-power signal line H32, the first sub-shift register 331 is electrically connected to the third sub-power signal line H31, and the second sub-shift register 331 is electrically connected to the third sub-power signal line H31. The device 332 is electrically connected to the fourth sub-power signal line H32, and accordingly, along the first direction X, a third pad 43 and a fourth pad 44 are respectively set at both ends of the display panel, and the second high-level signal line H2 and the third high-level signal line H3 are electrically connected to the third pad 43 and the fourth pad 44, so that signals can be transmitted from the third pad 43 and the fourth pad 44 to the second high-level signal line H2 and the third high-level signal line H3 at the same time, which can effectively reduce the voltage drop and improve the uniformity of the signal transmitted to the second high-level signal line H2 and the third high-level signal line H3.

[0107] Fig.14 is a plan view of another display panel provided by the present disclosure, referring to Figure 2 and Fig.14 In some optional embodiments, the pixel circuit 10 further includes a third control module 15 and a fourth control module 16, the control end of the third control module 15 is electrically connected to the fourth control line S4, and the control end of the fourth control module 16 is connected to the fifth control line S5;

[0108] The display panel further includes a fourth shift register 34 and a fifth shift register 35, and output ends of the fourth shift register 34 and the fifth shift register 35 are electrically connected to a fourth control line S4 and a fifth control line S5, respectively;

[0109] The display panel further includes a fourth power signal line L4 and a fifth power signal line L5, and the fourth power signal line L4 and the fifth power signal line L5 are electrically connected to the fourth shift register 34 and the fifth shift register 35 respectively;

[0110] The first power signal line L1 is disconnected from the fourth power signal line L4 and the fifth power signal line L5, and the fourth and fifth power signal lines (L4, L5) and the first power signal line L1 are all connected to high level signals or low level signals.

[0111] Specifically, the pixel circuit 10 also includes a third control module 15, the control end of the third control module 15 is electrically connected to the fourth control line S4, the display panel also includes a fourth shift register 34, the output end of the fourth shift register 34 is electrically connected to the fourth control line S4, the display panel also includes a fourth power signal line L4, the fourth power signal line L4 is electrically connected to the fourth shift register 34, the fourth power signal line L4 can also be connected to the power signal, so that the power signal is transmitted to the fourth shift register 34 via the fourth power signal line L4, the fourth shift register 34 generates a fourth control signal (S2N signal) based on the signal including the power signal, and transmits the fourth control signal (S2N signal) to the control end of the third control module 15 via the fourth control line S4, thereby realizing the control of the state of the third control module 15.

[0112] The pixel circuit 10 also includes a fourth control module 16, the control end of the fourth control module 16 is electrically connected to the fifth control line S5, the display panel also includes a fifth shift register 35, the output end of the fifth shift register 35 is electrically connected to the fifth control line S5, the display panel also includes a fifth power signal line L5, the fifth power signal line L5 is electrically connected to the fifth shift register 35, the fifth power signal line L5 can also be connected to the power signal, so that the power signal is transmitted to the fifth shift register 35 via the fifth power signal line L5, the fifth shift register 35 generates a fifth control signal (S1N signal) based on the signal including the power signal, and transmits the fifth control signal (S1N signal) to the control end of the fourth control module 16 via the fifth control line S5, so that the state of the fourth control module 16 can be controlled.

[0113] The fourth power signal line L4, the fifth power signal line L5 and the first power signal line L1 are all connected to high-level signals or low-level signals, that is, the fourth power signal line L4, the fifth power signal line L5 and the first power signal line L1 are connected to the same signal, the fourth power signal line L4, the fifth power signal line L5 and the first power signal line L1 are all connected to high-level signals, or the fourth power signal line L4, the fifth power signal line L5 and the first power signal line L1 are all connected to low-level signals.

[0114] When the fourth power signal line L4, the fifth power signal line L5 and the first power signal line L1 are all connected to high-level signals, that is, the first power signal line L1 is a signal line used to connect to high-level power signals, and the fourth power signal line L4 and the fifth power signal line L5 are also signal lines used to connect to high-level power signals. At this time, the first power signal line L1 and the fourth power signal line L4, and the first power signal line L1 and the fifth power signal line L5 can be disconnected to prevent the signal on the first power signal line L1 from affecting the signals on the fourth power signal line L4 and the fifth power signal line L5.

[0115] Similarly, when the fourth power signal line L4, the fifth power signal line L5 and the first power signal line L1 are all connected to low-level signals, that is, the first power signal line L1 is a signal line used to connect to a low-level power signal, and the fourth power signal line L4 and the fifth power signal line L5 are also signal lines used to connect to a low-level power signal. At this time, the first power signal line L1 and the fourth power signal line L4, and the first power signal line L1 and the fifth power signal line L5 can be disconnected to prevent the signal on the first power signal line L1 from affecting the signals on the fourth power signal line L4 and the fifth power signal line L5.

[0116] Continue to refer Figure 2 and Fig.14 In some optional embodiments, the pixel circuit 10 also includes a threshold compensation module 151 and a gate reset module 161, the threshold compensation module 151 and the gate reset module 161 are electrically connected to the driving module 11, the third control module 15 includes the threshold compensation module 151, and the fourth control module 16 includes the gate reset module 161.

[0117] Specifically, the pixel circuit 10 further includes a threshold compensation module 151 and a gate reset module 161 . The control end of the threshold compensation module 151 is electrically connected to the fourth control line S4 , and the control end of the gate reset module 161 is electrically connected to the fifth control line S5 .

[0118] Optionally, the transistors included in the threshold compensation module 151 and the gate reset module 161 are oxide transistors, that is, the transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 are both oxide transistors. Optionally, the transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 are both N-type metal oxide transistors, such as IGZO (indium gallium zinc oxide) transistors.

[0119] Fig.15 is a plan view of another display panel provided by the present disclosure, referring to Fig.15 In some optional embodiments, at least two of the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 are electrically connected.

[0120] Specifically, when the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 are all connected to high-level signals or low-level signals, at least two of the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 can be electrically connected, so that the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 can be electrically connected to the driver chip by setting fewer pads 40. Optionally, the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 can be electrically connected, so that the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 can be connected through the same pad 40, which is conducive to reducing the number of pads 40, reducing the occupied area of ​​the pads 40, and improving the space utilization of the display panel. At the same time, the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 can share the same set of voltage settings, that is, the power signals provided to the second power signal line L2, the third power signal line L3, the fourth power signal line L4 and the fifth power signal line L5 can be provided by the same set of voltage regulation modules in the driver chip, which is conducive to reducing the design difficulty of the driver chip and reducing the production cost of the driver chip.

[0121] Continue to refer Figure 2 and Fig.14 In some optional embodiments, the second power signal line L2 is electrically connected to the third power signal line L3, the fourth power signal line L4 is electrically connected to the fifth power signal line L5, and the third power signal line L3 is disconnected from the fourth power signal line L4.

[0122] Specifically, the transistor T2 in the data writing module 141 is of the same type as the transistor T7 in the first reset module 131, so that the voltage setting of the driving signal for both can adopt the same setting, and the second shift register 32 electrically connected to the second power signal line L2 is used to input the second control signal (SPX signal) to the first reset module 131, and the third shift register 33 electrically connected to the third power signal line L3 is used to input the third control signal (SP signal) to the data writing module 141. The second power signal line L2 and the third power signal line L3 are electrically connected. At this time, the normal operation and reliability of the transistor T2 in the data writing module 141 and the transistor T7 in the first reset module 131 will not be affected.

[0123] The transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 are of the same type, so the voltage setting of the driving signal for both can adopt the same setting. The fourth shift register 34 electrically connected to the fourth power signal line L4 is used to input the fourth control signal (S2N signal) to the threshold compensation module 151, and the fifth shift register 35 electrically connected to the fifth power signal line L5 is used to input the fifth control signal (S1N signal) to the gate reset module 161. The fourth power signal line L4 and the fifth power signal line L5 are electrically connected. At this time, the normal operation and reliability of the transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 will not be affected.

[0124] The transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151 are of different types. The fourth shift register 34 electrically connected to the fourth power signal line L4 is used to input a fourth control signal (S2N signal) to the threshold compensation module 151. The third shift register 33 electrically connected to the third power signal line L3 is used to input a third control signal (SP signal) to the data writing module 141. The fourth power signal line L4 and the third power signal line L3 are disconnected, so that the signals connected to the third power signal line L3 and the fourth power signal line L4 can be controlled separately, thereby ensuring the normal operation and reliability of the transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151.

[0125] Continue to refer Fig.14 In some optional embodiments, the first to fifth power signal lines (L1-L5) are connected to low level signals.

[0126] Specifically, the first to fifth power signal lines (L1-L5) are all connected to low-level signals, that is, the first to fifth power signal lines (L1-L5) are all signal lines for connecting to low-level power signals. At this time, the first power signal line L1 and the second to fifth power signal lines (L2-L5) are disconnected, that is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second to fifth power signal lines (L2-L5), so that when the low-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the low-level power signal used to drive other control signals will not be coupled, so that other control signals will not have periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is conducive to improving display quality.

[0127] It should be noted that the low-level signals connected to the first to fifth power signal lines (L1-L5) can be completely the same, partially the same, or completely different, and can be set according to actual design requirements, which will not be elaborated in this disclosure. Fig.16 is a plan view of another display panel provided by the present disclosure, referring to Fig.16 In some optional embodiments, the display panel also includes first to fifth high-level signal lines (H1-H5), the first to fifth shift registers (31-35) are electrically connected to the first to fifth high-level signal lines (H1-H5), respectively, and the first high-level signal line H1 is disconnected from the second to fifth high-level signal lines (H2-H5).

[0128] Specifically, the display panel further comprises first to fifth high-level signal lines (H1-H5), the first to fifth shift registers (31-35) are electrically connected to the first to fifth high-level signal lines (H1-H5), and the first to fifth high-level signal lines (H1-H5) are signal lines for accessing high-level power supply signals. At this time, the first high-level signal line H1 is disconnected from the remaining high-level signal lines (H2-H5), that is, the high-level power supply signal transmitted on the first high-level signal line H1 will not affect the high-level power supply signal transmitted on the second to fifth high-level signal lines (H2-H5), so that when the high-level power supply signal used to drive the first control signal (EM signal) has a potential fluctuation in units of the first control signal (EM signal) period, the high-level power supply signal used to drive other control signals will not be coupled, so that other control signals will not have periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes of the display panel under low grayscale display, which is conducive to improving display quality.

[0129] It should be noted that the high-level signals connected to the first to fifth high-level signal lines (H1-H5) can be completely the same, partially the same, or completely different, and can be set according to actual design requirements, which will not be elaborated in this disclosure.

[0130] It should be noted that Fig.16 In order to clearly illustrate the arrangement of the first to fifth high-level signal lines (H1-H5), Fig.16 The first to fifth power signal lines (L1-L5) are not shown in the figure. The arrangement of the first to fifth power signal lines (L1-L5) in the display panel can be referred to. Fig.14 and Fig.15 The arrangement of the first to fifth power signal lines (L1-L5) will not be further described in this disclosure.

[0131] Continue to refer Figure 2 and Fig.16 In some optional embodiments, the second high level signal line H2 is electrically connected to the third high level signal line H3, the fourth high level signal line H4 is electrically connected to the fifth high level signal line H5, and the third high level signal line H3 is disconnected from the fourth high level signal line H4.

[0132] Specifically, the transistor T2 in the data writing module 141 is of the same type as the transistor T7 in the first reset module 131, so that the voltage setting of the driving signal for both can adopt the same setting, the second shift register 32 electrically connected to the second high-level signal line H2 is used to input the second control signal (SPX signal) to the first reset module 131, and the third shift register 33 electrically connected to the third high-level signal line H3 is used to input the third control signal (SP signal) to the data writing module 141, and the second high-level signal line H2 is electrically connected to the third high-level signal line H3. At this time, the normal operation and reliability of the transistor T2 in the data writing module 141 and the transistor T7 in the first reset module 131 will not be affected.

[0133] The transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 are of the same type, so the voltage setting of the driving signal for both can adopt the same setting. The fourth shift register 34 electrically connected to the fourth high-level signal line H4 is used to input the fourth control signal (S2N signal) to the threshold compensation module 151, and the fifth shift register 35 electrically connected to the fifth high-level signal line H5 is used to input the fifth control signal (S1N signal) to the gate reset module 161. The fourth high-level signal line H4 is electrically connected to the fifth high-level signal line H5. At this time, the normal operation and reliability of the transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 will not be affected.

[0134] The transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151 are of different types. The fourth shift register 34 electrically connected to the fourth high-level signal line H4 is used to input a fourth control signal (S2N signal) to the threshold compensation module 151. The third shift register 33 electrically connected to the third high-level signal line H3 is used to input a third control signal (SP signal) to the data writing module 141. The third high-level signal line H3 and the fourth high-level signal line H4 are disconnected, so that the signals connected to the third high-level signal line H3 and the fourth high-level signal line H4 can be controlled separately, thereby ensuring the normal operation and reliability of the transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151.

[0135] Fig.17 is a plan view of another display panel provided by the present disclosure, referring to Fig.17 In some optional embodiments, the second high level signal line H2, the third high level signal line H3, the fourth high level signal line H4 and the fifth high level signal line H5 are electrically connected.

[0136] Specifically, the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4 and the fifth high-level signal line H5 are all connected to the high-level signal, and the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4 and the fifth high-level signal line H5 can be electrically connected, so that the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4 and the fifth high-level signal line H5 can be connected through the same pad 40, which is conducive to reducing the number of pads 40, and is conducive to reducing the occupied area of ​​the pad 40, and improving the space utilization rate of the display panel. At the same time, the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4 and the fifth high-level signal line H5 can share the same set of voltage settings, that is, the power supply signal provided to the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4 and the fifth high-level signal line H5 by the same set of voltage adjustment modules in the driver chip is conducive to reducing the design difficulty of the driver chip and reducing the production cost of the driver chip.

[0137] It should be noted that Fig.17 In order to clearly illustrate the arrangement of the first to fifth high-level signal lines (H1-H5), Fig.17 The first to fifth power signal lines (L1-L5) are not shown in the figure. The arrangement of the first to fifth power signal lines (L1-L5) in the display panel can be referred to. Fig.14 and Fig.15 The arrangement of the first to fifth power signal lines (L1-L5) will not be further described in this disclosure.

[0138] like Fig.18 As shown, Fig.18 1 is a schematic plan view of a display device provided by the present disclosure. The present disclosure also provides a display device 1000, including a display panel 100 provided by any of the above embodiments. The display device may also include a housing for providing mechanical support and protection, a power management module located in the housing, an audio output module, etc. Fig.18 The embodiments provided only take mobile phones as an example to illustrate the display device. It can be understood that the display device provided in the embodiments of the present application can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present disclosure do not specifically limit this.

[0139] The display device 1000 provided in the embodiment of the present disclosure has the same technical features as the display panel 100 provided in the above embodiment, and can therefore solve the same technical problems and achieve the same technical effects.

[0140] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0141] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: An electrically connected pixel circuit and a light-emitting element, wherein the pixel circuit comprises a driving module, a light-emitting control module and a first control module, wherein a control end of the light-emitting control module is connected to a first control line, and a control end of the first control module is connected to a second control line; The display panel comprises a first shift register and a second shift register, wherein an output end of the first shift register is electrically connected to the first control line, and an output end of the second shift register is electrically connected to the second control line; The display panel further includes a first power signal line and a second power signal line, the first power signal line is electrically connected to the first shift register, the second power signal line is electrically connected to the second shift register, and the first power signal line and the second power signal line are isolated from each other; The first power signal line and the second power signal line are both connected to high level signals or are both connected to low level signals.

2. The display panel according to claim 1, characterized in that: The first control module includes a bias adjustment module, the bias adjustment module is electrically connected to the driving module, and the bias adjustment module is used to implement bias adjustment on the driving module.

3. The display panel according to claim 2, characterized in that: The first power signal line and the second power signal line are both connected to low level signals.

4. The display panel according to claim 3, characterized in that: The first shift register is electrically connected to a first high-level signal line, and the second shift register is electrically connected to a second high-level signal line. The first high-level signal line and the second high-level signal line are connected to the same high-level potential.

5. The display panel according to claim 4, characterized in that: The absolute values ​​of the low level signals connected to the first power signal line and the second power signal line are the same.

6. The display panel according to claim 3, characterized in that: The first shift register is electrically connected to a first high-level signal line, the second shift register is electrically connected to a second high-level signal line, and the first high-level signal line is disconnected from the second high-level signal line.

7. The display panel according to claim 2, characterized in that: The pixel circuit further includes a second control module, a control end of the second control module is connected to a third control line; The display panel further comprises a third shift register, wherein an output end of the third shift register is electrically connected to the third control line; The display panel further comprises a third power signal line, and the third power signal line is electrically connected to the third shift register; The second power signal line is electrically connected to the third power signal line, and the second power signal line and the third power signal line are both connected to a high level signal or are both connected to a low level signal.

8. The display panel according to claim 7, characterized in that: The pixel circuit further includes a data writing module, and the data writing module is used to write a data signal into the driving module; The second control module includes the data writing module.

9. The display panel according to claim 7, characterized in that: The third shift register includes a first sub-shift register and a second sub-shift register, the third power signal line includes a first sub-power signal line and a second sub-power signal line, and along the first direction, the first sub-shift register and the second sub-shift register are respectively located at two sides of the display panel; The first sub-shift register is electrically connected to the first sub-power signal line, and the second sub-shift register is electrically connected to the second sub-power signal line; The first sub power signal line and the second sub power signal line are connected on at least one side of the display panel along a second direction, wherein the first direction intersects with the second direction.

10. The display panel according to claim 9, characterized in that: The display panel includes a display area and a non-display area surrounding the display area, the non-display area includes a first non-display area and a second non-display area located on opposite sides of the display area, and the second power signal line and the third power signal line are electrically connected in the first non-display area and / or the second non-display area.

11. The display panel according to claim 9, characterized in that: The first sub power signal line, the second sub power signal line, and the second power signal line are electrically connected to the same first power bus.

12. The display panel according to claim 9, characterized in that: The display panel includes a plurality of pads, the pads include a first pad and a second pad, and the second power signal line and the third power signal line are both electrically connected to the first pad and the second pad; Along the first direction, the first pad and the second pad are respectively located at two ends of the display panel.

13. The display panel according to claim 7, characterized in that: The second power signal line and the third power signal line are both connected to a low level potential.

14. The display panel according to claim 13, characterized in that: The first shift register is electrically connected to the first high level signal line, the second shift register is electrically connected to the second high level signal line, the third shift register is electrically connected to the third high level signal line, and the first high level signal line is disconnected from the second high level signal line and the third high level signal line.

15. The display panel according to claim 14, characterized in that: The second power signal line is electrically connected to the third power signal line, and the second high level signal line is electrically connected to the third high level signal line.

16. The display panel according to claim 8, characterized in that: The pixel circuit further includes a third control module and a fourth control module, the control end of the third control module is connected to the fourth control line, and the control end of the fourth control module is connected to the fifth control line; The display panel further includes a fourth shift register and a fifth shift register, and output ends of the fourth shift register and the fifth shift register are electrically connected to the fourth control line and the fifth control line respectively; The display panel further comprises a fourth power signal line and a fifth power signal line, wherein the fourth power signal line and the fifth power signal line are electrically connected to the fourth shift register and the fifth shift register respectively; The first power signal line is disconnected from the fourth power signal line and the fifth power signal line, and the fourth, fifth power signal lines and the first power signal line are all connected to high level signals or low level signals.

17. The display panel according to claim 16, characterized in that: The pixel circuit further includes a threshold compensation module and a gate reset module, wherein the threshold compensation module and the gate reset module are electrically connected to the driving module, the third control module includes the threshold compensation module, and the fourth control module includes the gate reset module.

18. The display panel according to claim 17, characterized in that: At least two of the second power signal line, the third power signal line, the fourth power signal line, and the fifth power signal line are electrically connected.

19. The display panel according to claim 18, characterized in that: The second power signal line is electrically connected to the third power signal line, the fourth power signal line is electrically connected to the fifth power signal line, and the third power signal line is disconnected from the fourth power signal line.

20. The display panel according to claim 18 or 19, characterized in that: The first to fifth power signal lines are connected to low level signals.

21. The display panel according to claim 20, characterized in that: The display panel further includes first to fifth high level signal lines, the first to fifth shift registers are electrically connected to the first to fifth high level signal lines, respectively, and the first high level signal line is disconnected from the second to fifth high level signal lines.

22. The display panel according to claim 21, characterized in that: The second high level signal line is electrically connected to the third high level signal line, the fourth high level signal line is electrically connected to the fifth high level signal line, and the third high level signal line is disconnected from the fourth high level signal line.

23. The display panel according to claim 22, characterized in that: The transistors included in the threshold compensation module and the gate reset module are oxide transistors.

24. The display panel according to claim 1, characterized in that: In the low-frequency operation mode of the display panel, a holding period is inserted between two writing periods, and the control signal transmitted by the second control line includes at least one pulse in the holding period.

25. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1-24.

Images