Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and in particular to a display panel and a display device. The display panel comprises a pixel circuit and a light emitting element, the pixel circuit comprising a driving module, a light emitting control module and a first control module, the control end of the light emitting control module being connected with a first control line, and the control end of the first control module being connected with a second control line; the output end of a first shift register is electrically connected with the first control line, and the output end of a second shift register is electrically connected with the second control line; a first power signal line is electrically connected with the first shift register, and a second power signal line is electrically connected with the second shift register, and the first power signal line and the second power signal line are mutually isolated; the first power signal line and the second power signal line are both connected with a high level signal or both connected with a low level signal. The present disclosure effectively solves the problem that the display panel in the prior art is prone to regular bright and dark horizontal stripe phenomenon when displaying in low gray scale.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are current-driven organic light-emitting devices. They are devices that emit light through carrier injection and recombination when organic semiconductor materials and light-emitting materials are driven by an electric field. OLEDs have become a research hotspot in the display field due to their excellent color saturation, contrast, and response speed. Furthermore, their materials are thinner, more transparent, and flexible, enabling diverse designs.

[0003] However, existing organic light-emitting display panels are prone to exhibiting regular bright and dark horizontal stripes when displaying at low grayscale levels, which greatly affects the display quality. Summary of the Invention

[0004] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, this disclosure provides a display panel and a display device, which effectively solves the problem that in the prior art, display panels are prone to regular bright and dark horizontal stripes when displaying at low grayscale, resulting in the inability to effectively improve display quality.

[0005] This disclosure provides a display panel, including: a pixel circuit and a light-emitting element electrically connected to each other; the pixel circuit includes a driving module, a light-emitting control module, and a first control module; the control terminal of the light-emitting control module is connected to a first control line, and the control terminal of the first control module is connected to a second control line; the display panel includes a first shift register and a second shift register; the output terminal of the first shift register is electrically connected to the first control line, and the output terminal of the second shift register is electrically connected to the second control line; the display panel also includes a first power signal line and a second power signal line; the first power signal line is electrically connected to the first shift register, and the second power signal line is electrically connected to the second shift register; the first power signal line and the second power signal line are isolated from each other; both the first power signal line and the second power signal line are connected to a high-level signal or both are connected to a low-level signal.

[0006] This disclosure also provides a display device including the aforementioned display panel.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0008] In the display panel provided in this disclosure, the first power signal line and the second power signal line are isolated from each other, that is, the first power signal line and the second power signal line are disconnected. In other words, the power signal transmitted on the first power signal line will not affect the power signal transmitted on the second power signal line. Therefore, when the power signal used to drive the first control signal has a potential fluctuation in a period of the first control signal, the power signal used to drive the second control signal will not be coupled. Thus, the second control signal will not have periodic coupling fluctuations, which effectively improves the display problem of bright and dark horizontal stripes in low grayscale display and is conducive to improving display quality.

[0009] Correspondingly, the display device provided in this disclosure also has the above-mentioned technical effects. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a planar schematic diagram of a display panel in the prior art;

[0013] Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between pixel circuits and light-emitting elements in a provided display panel;

[0014] Figure 3 yes Figure 2 The corresponding signal timing diagram;

[0015] Figure 4 yes Figure 2 A timing diagram of the corresponding EM signal;

[0016] Figure 5 yes Figure 2 Another timing diagram of the corresponding EM signal;

[0017] Figure 6 yes Figure 1 A circuit diagram of a shift register unit in a provided display panel;

[0018] Figure 7 yes Figure 1 A schematic diagram showing the horizontal stripes on the display panel;

[0019] Figure 8 This is a plan view of a display panel provided in this disclosure;

[0020] Figure 9 This is a plan view of another display panel provided in this disclosure;

[0021] Figure 10 This is a plan view of yet another display panel provided in this disclosure;

[0022] Figure 11 This is a plan view of yet another display panel provided in this disclosure;

[0023] Figure 12 This is a plan view of yet another display panel provided in this disclosure;

[0024] Figure 13 This is a plan view of yet another display panel provided in this disclosure;

[0025] Figure 14 This is a plan view of yet another display panel provided in this disclosure;

[0026] Figure 15 This is a plan view of yet another display panel provided in this disclosure;

[0027] Figure 16 This is a plan view of yet another display panel provided in this disclosure;

[0028] Figure 17 This is a plan view of yet another display panel provided in this disclosure;

[0029] Figure 18 This is a plan view of a display device provided in this disclosure. Detailed Implementation

[0030] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0031] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0032] Figure 1 This is a planar schematic diagram of a display panel in the prior art. Figure 2 yes Figure 1 A schematic diagram of an electrical connection structure between pixel circuits and light-emitting elements in a provided display panel. Figure 3 yes Figure 2 The corresponding signal timing diagram, Figure 4 yes Figure 2 A timing diagram of the corresponding EM signal, Figure 5 yes Figure 2 Another timing diagram of the corresponding EM signal, Figure 6 yes Figure 1 A circuit diagram of a shift register unit in a provided display panel. Figure 7 yes Figure 1 The diagram illustrating the horizontal stripe phenomenon on the display panel is shown below. Figures 1-7 In existing technologies, display panels generally include an electrically connected pixel circuit 1 and a light-emitting element 2. The pixel circuit 1 can be an 8T1C pixel circuit, meaning that the pixel circuit 1 includes eight transistors (transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, and transistor T8) and one capacitor (capacitor Cst). Among them, transistors T4 and T5, which are electrically connected to the gate of transistor T3, are both N-type transistors, while the remaining transistors are P-type transistors. That is, transistors T4 and T5 conduct when their gate potential is high, while the gate potential of the remaining transistors is low. Figure 2 In the provided pixel circuit, the potential of node N4 is the anode potential of the OLED light-emitting element. The potential difference between the anode potential and the cathode potential of the OLED light-emitting element determines the magnitude of the current flowing through the OLED light-emitting element. Figure 2 The transistor T7 in the provided pixel circuit is used to reset the potential of node N4. It should be noted that this disclosure does not elaborate on the connection structure and working principle of the pixel circuit described above; for details, please refer to the explanations and descriptions of pixel circuits in related technologies.

[0033] In the display panel, the gate control signals for transistors T1 and T6 are EM signals, the gate control signal for transistor T2 is SP signals, the gate control signal for transistor T4 is S2N signals, the gate control signal for transistor T5 is S1N signals, and the gate control signals for transistors T7 and T8 are SPX signals. The switching levels of the EM, SP, S1N, S2N, and SPX signals are high / low levels. A high level is the effective signal controlling the conduction of transistors T4 and T5, while a low level is the effective signal controlling the conduction of other transistors besides T4 and T5. The SPX, EM, SP, S1N, S2N, and SPX signals are typically generated and provided by a gate on array (GOA), which includes multiple shift registers 3. The SPX, EM, SP, S1N, S2N, and SPX signals are usually generated and provided by different shift registers 3. Shift register 3 typically includes cascaded shift register units. The output signal of each shift register unit serves as both the control signal for the corresponding transistor in each row of pixel circuit 1 and the input signal for the next-stage bit register unit. The signal input for the first stage is generated through configuration by the driver chip. Correspondingly, in order to drive the output drive signals of each stage of shift register units, the driver chip needs to input a power supply signal to shift register 3. This power supply signal includes both high-level and low-level signals. For example, refer to... Figure 6 The driver chip provides power signals (VGL signal, VGH signal), clock signals (CK signal, XCK signal), and start signal (STV signal) to the shift register unit. This causes the output of the shift register unit to output corresponding control signals to the transistors in the connected pixel circuit, thereby controlling the state of the transistors in the pixel circuit. In the prior art, the power signal lines connected to the shift register 3 used for outputting the EM signal and the shift register 3 used for outputting the SPX signal are typically connected together.

[0034] It should be noted that, Figure 6 The circuitry shown in the example illustrates shift register units for outputting EM signals and shift register units for outputting SPX signals. Figure 6The circuit structure of the shift register unit is not detailed here; the connection structure and working principle of the shift register unit are explained in relevant technical documents. The circuits of the two may differ, but both require the use of power signals, clock signals, and start signals for signal generation and transmission. The display panel also includes shift register 3 for outputting the SP signal, shift register 3 for outputting the S1N signal, and shift register 3 for outputting the S2N signal. Similarly, the driver chip provides power signals (VGL signal, VGH signal), clock signals (CK signal and / or XCK signal), and start signals (STV signal) to the shift register units in these shift register units. This causes the output of the shift register unit to output corresponding control signals to the transistors in the connected pixel circuit, thereby controlling the state of the transistors in the pixel circuit. The specific circuit structure and working principle of the shift register units in these shift register units are not detailed here; the explanations of shift register units in relevant technical documents are provided for further details.

[0035] A display panel typically includes an active area and a porch area (this area is used for voltage conversion preparation; it can also be understood as a blanking area. In display technology, it refers to the area on the screen used for synchronization signal transmission, not for displaying images. Generally, the active area is followed by the porch area. The porch area is a specific time period during which the display device does not display any valid image information but is used for the transmission and processing of synchronization signals to ensure the correct synchronization and stable operation of the display device). The porch area is fixed. The EM signal is a drive signal with multiple pulses. Therefore, during display, different areas of the display panel will have corresponding EM signals falling on the porch area, resulting in the phenomenon of bright and dark horizontal stripes. Specifically, for example... Figure 4 As shown, the EM signal has a falling edge in the porch region. At this time, there is no actual transition load, which leads to a reduction in the transition load of the low-level signal used to drive the EM signal's falling edge. The voltage value of the low-level signal used to drive the EM signal is relatively lower than the set value, thus the difference between the low-level and high-level signals used to drive the EM signal becomes relatively larger. Since the power signal lines connected to shift register 3 for outputting the EM signal and shift register 3 for outputting the SPX signal are usually connected together, meaning the low-level signals used to drive the EM signal and the low-level signals used to drive the SPX signal are shared signals, when the difference between the low-level and high-level signals used to drive the EM signal becomes relatively larger, the SPX signal high-level coupling increases, the N4 node potential is higher, and the brightness is higher. Figure 5As shown, the falling edges of the EM signal are not in the porch region. Therefore, for the active area of ​​the display panel, the low-level signal driving the falling edge of the EM signal has an additional low-level load. The voltage value of the low-level signal driving the EM signal is relatively higher than the set value, thus the difference between the low-level and high-level signals driving the EM signal becomes relatively smaller. Since the power signal lines connected to shift register 3 for outputting the EM signal and shift register 3 for outputting the SPX signal are usually connected together, meaning the low-level signals driving the EM signal and the low-level signals driving the SPX signal are shared signals, when the difference between the low-level and high-level signals driving the EM signal becomes relatively smaller, the high-level coupling of the SPX signal decreases, the N4 node potential is lower, and the brightness is dimmer. The final display image presents... Figure 7 The display panel 100' in the prior art shown is prone to regular bright and dark horizontal lines.

[0036] As can be seen from the above, in the prior art, when the display panel displays at low grayscale, the state of the falling edge of the EM signal entering and exiting the porch area is different at different times. The low-level signal used to drive the falling edge of the EM signal exhibits potential fluctuations in units of the EM signal period. Since the low-level signal used to drive the EM signal and the low-level signal used to drive the SPX signal are shared signals, the coupling amount of the SPX signal also fluctuates periodically, resulting in bright and dark horizontal lines appearing in the low grayscale image.

[0037] Similarly, in the prior art, when the display panel is displaying at low grayscale, the state of the rising and falling edges of the EM signal entering and leaving the porch area is different at different times. The high-level signal used to drive the rising and falling edges of the EM signal exhibits potential fluctuations in units of the EM signal period. Since the high-level signal used to drive the EM signal and the high-level signal used to drive the SPX signal are shared signals, the coupling amount of the SPX signal also fluctuates periodically, resulting in bright and dark horizontal stripes appearing in the low grayscale image.

[0038] To address the aforementioned problems, this application proposes a display panel and display device that can improve the display of horizontal stripes and enhance display quality. Specific embodiments of the display panel and display device proposed in this application are described in detail below.

[0039] Figure 8 This is a plan view of a display panel provided in this disclosure. The structure of the pixel circuit in the display panel provided in this embodiment can be referenced. Figure 2 ,refer to Figure 2 and Figure 8This disclosure provides a display panel, which includes: a pixel circuit 10 and a light-emitting element 20 electrically connected. The pixel circuit 10 includes a driving module 11, a light-emitting control module 12 and a first control module 13. The control terminal of the light-emitting control module 12 is connected to a first control line S1, and the control terminal of the first control module 13 is connected to a second control line S2.

[0040] The display panel includes a first shift register 31 and a second shift register 32. The output terminal of the first shift register 31 is electrically connected to the first control line S1, and the output terminal of the second shift register 32 is electrically connected to the second control line S2.

[0041] The display panel also includes a first power signal line L1 and a second power signal line L2. The first power signal line L1 is electrically connected to the first shift register 31, and the second power signal line L2 is electrically connected to the second shift register 32. The first power signal line L1 and the second power signal line L2 are isolated from each other.

[0042] The first power signal line L1 and the second power signal line L2 are both connected to a high-level signal or both are connected to a low-level signal.

[0043] Specifically, the display panel provided in this embodiment is an OLED display panel. The display panel includes an electrically connected pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 is used to provide current to the light-emitting element 20 so as to realize the light emission of the light-emitting element 20.

[0044] The pixel circuit 10 includes a driving module 11, an emissive control module 12, and a first control module 13. The control terminal of the emissive control module 12 is connected to the first control line S1. The display panel includes a first shift register 31, the output terminal of which is electrically connected to the first control line S1. The display panel also includes a first power signal line L1, which is electrically connected to the first shift register 31. The first power signal line L1 can be connected to a power signal, so that the power signal is transmitted to the first shift register 31 via the first power signal line L1. The first shift register 31 generates a first control signal (EM signal) based on the signal including the power signal, and transmits the first control signal (EM signal) to the control terminal of the emissive control module 12 via the first control line S1, thereby realizing the control of the state of the emissive control module 12.

[0045] The control terminal of the first control module 13 is connected to the second control line S2. The display panel includes a second shift register 32, the output terminal of which is electrically connected to the second control line S2. The display panel also includes a second power signal line L2, which is electrically connected to the second shift register 32. The second power signal line L2 can also be connected to a power signal, so that the power signal is transmitted to the second shift register 32 via the second power signal line L2. The second shift register 32 generates a second control signal (SPX signal) based on the signal including the power signal, and transmits the second control signal (SPX signal) to the control terminal of the first control module 13 via the second control line S2, thereby realizing the control of the state of the first control module 13.

[0046] Because the state of the falling edge and / or rising edge of the first control signal (EM signal) entering and leaving the porch area is different at different times when the display panel is displaying at low grayscale, the power supply signal used to drive the first control signal (EM signal) will have potential fluctuations in units of the first control signal (EM signal) cycle.

[0047] In this embodiment, the first power signal line L1 and the second power signal line L2 are isolated from each other, that is, the first power signal line L1 and the second power signal line L2 are disconnected. This means that the power signal transmitted on the first power signal line L1 will not affect the power signal transmitted on the second power signal line L2. Therefore, when the power signal used to drive the first control signal (EM signal) experiences potential fluctuations in units of the first control signal (EM signal) period, the power signal used to drive the second control signal (SPX signal) will not be coupled. As a result, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is beneficial to improving display quality.

[0048] Both the first power signal line L1 and the second power signal line L2 can be connected to high-level signals. That is, the first power signal line L1 can be used to receive a high-level power signal, and the second power signal line L2 can also be used to receive a high-level power signal. At this time, the first power signal line L1 and the second power signal line L2 are disconnected. That is, the high-level power signal transmitted on the first power signal line L1 will not affect the high-level power signal transmitted on the second power signal line L2. Therefore, when the high-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in a periodic manner, the high-level power signal used to drive the second control signal (SPX signal) will not be coupled. Thus, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is conducive to improving display quality.

[0049] Similarly, both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals. That is, the first power signal line L1 can be used to connect to a low-level power signal, and the second power signal line L2 can be used to connect to a low-level power signal. At this time, disconnecting the first power signal line L1 and the second power signal line L2 means that the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2. Therefore, when the low-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in a periodic manner, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled. As a result, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is beneficial to improving display quality.

[0050] Continue to refer to Figure 2 and Figure 8 Optionally, the first control module 13 includes a first reset module 131. The control terminal of the first reset module 131 is connected to the second control line S2. The first terminal of the first reset module 131 is connected to the REF2 signal, and the second terminal of the first reset module 131 is connected to the N4 node. The potential of the N4 node in the pixel circuit 10 is the anode potential of the light-emitting element 20. The first reset module 131 in the pixel circuit 10 is used to reset the potential of the N4 node. Disconnecting the first power signal line L1 and the second power signal line L2 means that the power signal transmitted on the first power signal line L1 will not affect the power signal transmitted on the second power signal line L2. Therefore, when the power signal used to drive the first control signal (EM signal) experiences potential fluctuations in units of the first control signal (EM signal) period, the power signal used to drive the second control signal (SPX signal) will not be coupled. Thus, the second control signal (SPX signal) will not experience periodic coupling fluctuations, thereby not affecting the potential of the N4 node. This effectively improves the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is beneficial to improving display quality.

[0051] Continue to refer to Figure 2 and Figure 8 In some optional embodiments, the first control module 13 includes a bias adjustment module 132, which is electrically connected to the drive module 11 and is used to adjust the bias of the drive module 11.

[0052] Specifically, the first control module 13 includes a bias adjustment module 132. The control terminal of the bias adjustment module 132 is connected to the second control line S2. The first terminal of the bias adjustment module 132 is connected to the DVH signal. The second terminal of the bias adjustment module 132 is electrically connected to the drive module 11. The bias adjustment module 132 can be used to adjust the bias of the drive module 11.

[0053] The control terminal of the first reset module 131 can reuse the second control signal (SPX signal) transmitted to the control terminal of the bias adjustment module 132. That is, both the control terminal of the bias adjustment module 132 and the control terminal of the first reset module 131 can be connected to the second control line S2, which helps to reduce circuit complexity and wiring difficulty.

[0054] The timing of the pixel circuit provided in the embodiments of this disclosure can be referenced. Figure 3 ,refer to Figure 2 , Figure 3 and Figure 8 In some alternative embodiments, in the low-frequency operating mode of the display panel, a hold period t2 is inserted between two write periods t1, and the control signal (SPX signal) transmitted by the second control line S2 includes at least one pulse during the hold period t2.

[0055] Specifically, the first control module 13 includes a bias adjustment module 132. The control terminal of the bias adjustment module 132 is connected to the second control line S2. The first terminal of the bias adjustment module 132 is connected to the DVH signal, and the second terminal of the bias adjustment module 132 is electrically connected to the drive module 11. The bias adjustment module 132 can be used to adjust the bias of the drive module 11. In the low-frequency operating mode of the display panel, a hold period t2 is inserted between two write periods t1. The control signal (SPX signal) transmitted by the second control line S2 includes at least one pulse in the hold period t2. Therefore, in the hold period t2, the bias adjustment module 132 can adjust the bias of the drive module 11, which can effectively reduce the image retention effect caused by long-term static images in the low-frequency operating mode of the display panel.

[0056] Continue to refer to Figure 2 and Figure 8 In some alternative embodiments, both the first power signal line L1 and the second power signal line L2 are connected to a low-level signal.

[0057] Specifically, when the second control signal (SPX signal) is a low-level signal, the first control module 13 is turned on. In this case, the fluctuation of the low-level power supply signal used to drive the second control signal (SPX signal) has a significant impact on the display of bright and dark horizontal stripes on the display panel under low grayscale display.

[0058] Both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals. That is, the first power signal line L1 is used to connect to a low-level power signal, and the second power signal line L2 is also used to connect to a low-level power signal. In this case, the first power signal line L1 and the second power signal line L2 are disconnected. That is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2. Therefore, when the low-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in a periodic manner, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled. Thus, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is conducive to improving display quality.

[0059] Figure 9 This is a plan view of another display panel provided in this disclosure, for reference. Figure 2 and Figure 9 In some optional embodiments, both the first power signal line L1 and the second power signal line L2 are connected to a low-level signal, and the first shift register 31 is electrically connected to the first high-level signal line H1, and the second shift register 32 is electrically connected to the second high-level signal line H2. The high-level potentials connected to the first high-level signal line H1 and the second high-level signal line H2 are the same.

[0060] Specifically, when both the first power signal line L1 and the second power signal line L2 in the display panel are connected to a low-level signal, the display panel also includes a first high-level signal line H1. The first high-level signal line H1 is electrically connected to the first shift register 31. The first high-level signal line H1 can be connected to a high-level power signal, so that the power signal is transmitted to the first shift register 31 through the first high-level signal line H1. The first shift register 31 generates a first control signal (EM signal) based on the signal including the power signal, and transmits the first control signal (EM signal) to the control terminal of the light-emitting control module 12 through the first control line S1, thereby realizing the control of the state of the light-emitting control module 12.

[0061] The display panel also includes a second high-level signal line H2, which is electrically connected to the second shift register 32. The second high-level signal line H2 can be connected to a high-level power signal, so that the power signal is transmitted to the second shift register 32 via the second high-level signal line H2. The second shift register 32 generates a second control signal (SPX signal) based on the signal including the power signal, and transmits the second control signal (SPX signal) to the control terminal of the first control module 13 via the second control line S2, thereby realizing the control of the state of the first control module 13.

[0062] The first high-level signal line H1 and the second high-level signal line H2 are connected to the same high-level potential, that is, the first high-level signal line H1 and the second high-level signal line H2 can share the same set of voltage settings. That is, the high-level potential provided to the first high-level signal line H1 and the second high-level signal line H2 can be provided by the same set of voltage adjustment modules in the driver chip, which helps to reduce the design difficulty of the driver chip and reduce the production cost of the driver chip.

[0063] Continue to refer to Figure 2 and Figure 9 In some alternative embodiments, the absolute values ​​of the low-level signals connected to the first power signal line L1 and the second power signal line L2 are the same.

[0064] Specifically, both the first power signal line L1 and the second power signal line L2 can be connected to a low-level signal. That is, the first power signal line L1 is a signal line used to connect to a low-level power signal, and the second power signal line L2 is also a signal line used to connect to a low-level power signal. The first power signal line L1 and the second power signal line L2 are disconnected from each other. However, the absolute value of the low-level signal connected to the first power signal line L1 and the second power signal line L2 is the same. That is, the first power signal line L1 and the second power signal line L2 can connect to the same low-level signal, which means that the first power signal line L1 and the second power signal line L2 can share the same set of voltage settings. This means that the low-level potential provided to the first power signal line L1 and the second power signal line L2 can be provided by the same set of voltage adjustment modules in the driver chip. This helps to reduce the design difficulty of the driver chip and reduce the production cost of the driver chip.

[0065] Continue to refer to Figure 9 The first high-level signal line H1 and the second high-level signal line H2 can be connected, so that the first high-level signal line H1 and the second high-level signal line H2 can be connected through the same pad 40, which helps to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0066] Optionally, the first high-level signal line H1 and the second high-level signal line H2 can be connected by the first connecting line 61, and the first connecting line 61 can be set on the side of the display panel away from the pad 40 along the second direction Y, so as to avoid the setting of the first connecting line 61 affecting the arrangement of the signal lines connected to each pad 40.

[0067] Figure 10 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 10In some optional embodiments, both the first power signal line L1 and the second power signal line L2 are connected to a low-level signal, the first power signal line L1 and the second power signal line L2 are disconnected, and the first shift register 31 is electrically connected to the first high-level signal line H1, the second shift register 32 is electrically connected to the second high-level signal line H2, and the first high-level signal line H1 is disconnected from the second high-level signal line H2.

[0068] Specifically, when both the first power signal line L1 and the second power signal line L2 in the display panel are connected to a low-level signal, both the first high-level signal line H1 and the second high-level signal line H2 can be connected to a high-level signal. That is, the first high-level signal line H1 is used to connect to a high-level power signal, and at the same time, the second high-level signal line H2 is also used to connect to a high-level power signal. At this time, the connection between the first high-level signal line H1 and the second high-level signal line H2 is disconnected. That is, the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signal transmitted on the second high-level signal line H2. As a result, the high-level power signal used to drive the first control signal (EM signal) will have a potential in units of the first control signal (EM signal) period. During fluctuations, the high-level power signal used to drive the second control signal (SPX signal) will not be coupled. At the same time, the first power signal line L1 and the second power signal line L2 are disconnected. That is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2. Therefore, when the low-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in units of the first control signal (EM signal) period, the low-level power signal used to drive the second control signal (SPX signal) will also not be coupled. Thus, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is conducive to improving display quality.

[0069] Figure 11 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 2 and Figure 11 In some optional embodiments, the pixel circuit 10 further includes a second control module 14, the control terminal of which is connected to a third control line S3.

[0070] The display panel also includes a third shift register 33, the output of which is electrically connected to the third control line S3;

[0071] The display panel also includes a third power signal line L3, which is electrically connected to the third shift register 33.

[0072] The second power signal line L2 and the third power signal line L3 are electrically connected. Both the second power signal line L2 and the third power signal line L3 are connected to a high-level signal or both are connected to a low-level signal.

[0073] Specifically, in the display panel, both the first power signal line L1 and the second power signal line L2 are connected to a high-level signal or both are connected to a low-level signal. At this time, the first power signal line L1 and the second power signal line L2 are isolated from each other. That is, the power signal transmitted on the first power signal line L1 will not affect the power signal transmitted on the second power signal line L2. Therefore, when the power signal used to drive the first control signal (EM signal) has a potential fluctuation in a periodic manner, the power signal used to drive the second control signal (SPX signal) will not be coupled. Thus, the second control signal (SPX signal) will not have periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes in low grayscale display and helping to improve display quality.

[0074] The pixel circuit 10 also includes a second control module 14, the control terminal of the second control module 14 is connected to the third control line S3, the display panel also includes a third shift register 33, the output terminal of the third shift register 33 is electrically connected to the third control line S3, the display panel also includes a third power signal line L3, the third power signal line L3 is electrically connected to the third shift register 33, the third power signal line L3 can also be connected to a power signal, so that the power signal is transmitted to the third shift register 33 through the third power signal line L3, the third shift register 33 generates a third control signal (SP signal) based on the signal including the power signal, and transmits the third control signal (SP signal) to the control terminal of the second control module 14 through the third control line S3, thereby realizing the control of the state of the second control module 14.

[0075] The first power signal line L1, the second power signal line L2, and the third power signal line L3 are all connected to a high-level signal or all connected to a low-level signal. That is, the second power signal line L2 and the third power signal line L3 are connected to the same signal, the first power signal line L1, the second power signal line L2, and the third power signal line L3 are all connected to a high-level signal, or the first power signal line L1, the second power signal line L2, and the third power signal line L3 are all connected to a low-level signal.

[0076] When the first power signal line L1, the second power signal line L2, and the third power signal line L3 are all connected to a high-level signal (i.e., the first power signal line L1, the second power signal line L2, and the third power signal line L3 are all connected to a high-level power signal), the second power signal line L2 and the third power signal line L3 can be electrically connected, meaning the third power signal line L3 is disconnected from the first power signal line L1. This allows the power signal used to drive the first control signal (EM signal) to appear. When the potential fluctuation of the (EM signal) is in units of period, the power signal used to drive the third control signal (SP signal) will not be coupled, so the third control signal (SP signal) will not have periodic coupling fluctuations. At the same time, when the high-level signals required to be connected to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected. Thus, the second power signal line L2 and the third power signal line L3 can be connected through the same pad 40, which helps to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0077] Similarly, when the first power signal line L1, the second power signal line L2, and the third power signal line L3 are all connected to a low-level signal—that is, the first power signal line L1 is used to connect a low-level power signal, the second power signal line L2 is used to connect a low-level power signal, and the third power signal line L3 is also used to connect a low-level power signal—then the second power signal line L2 and the third power signal line L3 can be electrically connected, that is, the third power signal line L3 is disconnected from the first power signal line L1. This allows the power signal used to drive the first control signal (EM signal) to appear in order to trigger the first control signal. When the potential fluctuation of the signal (EM signal) is a unit period, the power signal used to drive the third control signal (SP signal) will not be coupled, so the third control signal (SP signal) will not have periodic coupling fluctuations. At the same time, when the low-level signals required to be connected to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected. Thus, the second power signal line L2 and the third power signal line L3 can be connected through the same pad 40, which helps to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0078] Optionally, when the transistors electrically connected to the second control line S2 and the third control line S3 are of the same type, the requirements for a high level in the drive signal required for the transistor electrically connected to the second control line S2 and the high level in the drive signal required for the transistor electrically connected to the third control line S3 are the same, and the requirements for a low level in the drive signal required for the transistor electrically connected to the second control line S2 and the low level in the drive signal required for the transistor electrically connected to the third control line S3 are the same, thereby allowing the second power supply signal line L2 and the third power supply signal line L3 to be electrically connected.

[0079] Continue to refer to Figure 2 and Figure 11 In some optional embodiments, the pixel circuit 10 further includes a data writing module 141, which is used to write a data signal (DATA signal) into the driving module 11.

[0080] The second control module 14 includes a data writing module 141.

[0081] Specifically, the pixel circuit 10 also includes a data writing module 141. The second control module 14 includes the data writing module 141. The control terminal of the data writing module 141 is connected to the third control line S3. The first terminal of the data writing module 141 is connected to the DATA signal, and the second terminal of the data writing module 141 is connected to the drive module 11. The data writing module 141 is used to write the data signal (DATA signal) into the drive module 11. The transistor T2 in the data writing module 141 is of the same type as the transistor T7 in the first reset module 131, so they can use the same voltage setting for the drive signal. The second shift register 32, which is electrically connected to the second power signal line L2, is used to input the second control signal (SPX signal) to the first reset module 131. The third shift register 33, which is electrically connected to the third power signal line L3, is used to input the third control signal (SP signal) to the data writing module 141. The second power signal line L2 and the third power signal line L3 are electrically connected. At this time, it will not affect the normal operation and reliability of the transistor T2 in the data writing module 141 and the transistor T7 in the first reset module 131.

[0082] Continue to refer to Figure 2 and Figure 11 In some optional embodiments, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, and the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32. Along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are located on both sides of the display panel.

[0083] The first sub-shift register 331 is electrically connected to the first sub-power signal line L31, and the second sub-shift register 332 is electrically connected to the second sub-power signal line L32.

[0084] Along the second direction Y, the first sub-power signal line L31 and the second sub-power signal line L32 are connected on at least one side of the display panel, wherein the first direction X and the second direction Y intersect. Optionally, the first direction X and the second direction Y are perpendicular.

[0085] Specifically, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, and the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32. Along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are located on both sides of the display panel. The first sub-shift register 331 and the second sub-shift register 332 are both connected to the third control line S3. The third control line S3, which is connected to the pixel circuits 10 arranged in the same row along the first direction X, is electrically connected to the first sub-shift register 331 and the second sub-shift register 332. That is, by inputting the third control signal (SP signal) to the data writing module 141 in the pixel circuit 10 through the dual-drive structure, more pixel circuits 10 can be driven at the same time, reducing signal transmission delay and improving response speed.

[0086] The first sub-shift register 331 is electrically connected to the first sub-power signal line L31, and the second sub-shift register 332 is electrically connected to the second sub-power signal line L32. The first sub-shift register 331 and the second sub-shift register 332 are used to simultaneously input a third control signal (SP signal) to the data writing module 141 in the pixel circuit 10. Thus, the first sub-power signal line L31, which is electrically connected to the first sub-shift register 331, and the second sub-power signal line L32, which is electrically connected to the second sub-shift register 332, can be electrically connected. Along the second direction Y, the first sub-power signal line L31 and the second sub-power signal line L32 are connected to at least one side of the display panel.

[0087] Continue to refer to Figure 2 and Figure 11 In some alternative embodiments, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA. A second power signal line L2 and a third power signal line L3 are electrically connected to the first non-display area NA1 and / or the second non-display area NA2.

[0088] Specifically, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA is used for display, while the non-display area NA is not used for display and is used to set up structures such as drive circuits. The non-display area NA includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA. The second power signal line L2 and the third power signal line L3 can be electrically connected in the first non-display area NA1 and / or the second non-display area NA2 through the first connecting line 61, thereby achieving the electrical connection between the second power signal line L2 and the third power signal line L3 without affecting the settings of the display area AA.

[0089] It should be noted that, Figure 11 The example shows the second power signal line L2 and the third power signal line L3 being electrically connected in the first non-display area NA1. In other embodiments of this disclosure, refer to Figure 12 , Figure 12 This is a plan view of another display panel provided in this disclosure. The second power signal line L2 and the third power signal line L3 are electrically connected in both the first non-display area NA1 and the second non-display area NA2. Of course, the second power signal line L2 and the third power signal line L3 can also be electrically connected in the second non-display area NA2, thereby improving the stability and uniformity of the potential at each point in the second power signal line L2 and the third power signal line L3. This disclosure will not elaborate further here.

[0090] Continue to refer to Figure 12 In some optional embodiments, the first sub-power signal line L31, the second sub-power signal line L32, and the second power signal line L2 are electrically connected to the same first power bus 50. This achieves electrical connection between the first sub-power signal line L31, the second sub-power signal line L32, and the second power signal line L2, and the first power bus 50 simplifies complex wiring designs, saves wiring space, and improves space utilization.

[0091] Continue to refer to Figure 11 In some alternative embodiments, the display panel includes a plurality of pads 40, the pads 40 including a first pad 41 and a second pad 42, and the second power signal line L2 and the third power signal line L3 are both electrically connected to the first pad 41 and the second pad 42.

[0092] Along the first direction X, the first pad 41 and the second pad 42 are located at both ends of the display panel, respectively.

[0093] Specifically, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332, and the third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32. Along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are located on both sides of the display panel. The first sub-shift register 331 is electrically connected to the first sub-power signal line L31, and the second sub-shift register 332 is electrically connected to the second sub-power signal line L32. Correspondingly, along the first direction X, a first pad 41 and a second pad 42 are respectively provided at both ends of the display panel. The second power signal line L2 and the third power signal line L3 are both electrically connected to the first pad 41 and the second pad 42, so that signals can be transmitted simultaneously from the first pad 41 and the second pad 42 to the second power signal line L2 and the third power signal line L3. This can effectively reduce voltage drop and improve the uniformity of signals transmitted to the second power signal line L2 and the third power signal line L3.

[0094] Optionally, at least one of the first sub-power signal line L31 and the second sub-power signal line L32, and the second power signal line L2, are electrically connected to the same first power bus 50. For example, refer to... Figure 11 When the second power signal line L2 and the third power signal line L3 are electrically connected to the first non-display area NA1 via the first connecting line 61, the first sub-power signal line L31 is electrically connected to the first pad 41, and the second sub-power signal line L32 and the second power signal line L2 are electrically connected to the second pad 42 via the same first power bus 50. Of course, in other embodiments of this disclosure, the first sub-power signal line L31 and the second power signal line L2 may also be electrically connected to the same first power bus 50, or the first sub-power signal line L31, the second sub-power signal line L32, and the second power signal line L2 may all be electrically connected to the same first power bus 50. These configurations will not be elaborated upon here.

[0095] Continue to refer to Figure 11 In some alternative embodiments, both the second power signal line L2 and the third power signal line L3 are connected to a low-level potential.

[0096] Specifically, both the first power signal line L1 and the second power signal line L2 can be connected to low-level signals. That is, the first power signal line L1 is used to connect to a low-level power signal, and the second power signal line L2 is also used to connect to a low-level power signal. At this time, the first power signal line L1 and the second power signal line L2 are disconnected. That is, the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signal transmitted on the second power signal line L2. Therefore, when the low-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in a periodic manner, the low-level power signal used to drive the second control signal (SPX signal) will not be coupled. Thus, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is conducive to improving display quality.

[0097] Meanwhile, the third power signal line L3 is also connected to a low-level potential. That is, the third power signal line L3 is also a signal line used to connect to a low-level power signal. When the low-level signals required to connect to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected. Thus, the second power signal line L2 and the third power signal line L3 can be connected through the same pad 40, which helps to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0098] Figure 13 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 2 and Figure 13 In some optional embodiments, the first shift register 31 is electrically connected to the first high-level signal line H1, the second shift register 32 is electrically connected to the second high-level signal line H2, the third shift register 33 is electrically connected to the third high-level signal line H3, and the first high-level signal line H1 is disconnected from the second high-level signal line H2 and the third high-level signal line H3.

[0099] Specifically, both the first high-level signal line H1 and the second high-level signal line H2 can be connected to high-level signals. That is, the first high-level signal line H1 is a signal line used to connect to a high-level power signal, and the second high-level signal line H2 is also a signal line used to connect to a high-level power signal. At this time, the connection between the first high-level signal line H1 and the second high-level signal line H2 is disconnected. That is, the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signal transmitted on the second high-level signal line H2. Therefore, when the high-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in units of the first control signal (EM signal) period, the high-level power signal used to drive the second control signal (SPX signal) will not be coupled. Thus, the second control signal (SPX signal) will not experience periodic coupling fluctuations, effectively improving the display problem of bright and dark horizontal stripes on the display panel under low grayscale display, which is conducive to improving display quality.

[0100] The third high-level signal line H3 can be connected to a high-level signal, meaning that the third high-level signal line H3 is also a signal line used to connect a high-level power signal. The first high-level signal line H1 is disconnected from the third high-level signal line H3, meaning that the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signal transmitted on the third high-level signal line H3. Therefore, when the high-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in units of the first control signal (EM signal) period, it will not affect the signal on the third high-level signal line H3.

[0101] Continue to refer to Figure 2 and Figure 13 In some alternative embodiments, the second power signal line L2 and the third power signal line L3 are electrically connected, and the second high-level signal line H2 and the third high-level signal line H3 are electrically connected.

[0102] Specifically, both the second power signal line L2 and the third power signal line L3 are connected to a low-level signal. That is, the second power signal line L2 is a signal line used to connect to a low-level power signal, and the third power signal line L3 is also a signal line used to connect to a low-level power signal. When the low-level signals required to connect to the second power signal line L2 and the third power signal line L3 are the same, the second power signal line L2 and the third power signal line L3 can be electrically connected. Thus, the second power signal line L2 and the third power signal line L3 can be connected through the same pad 40, which helps to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0103] Similarly, both the second high-level signal line H2 and the third high-level signal line H3 are connected to high-level signals. That is, the second high-level signal line H2 is a signal line used to connect to a high-level power signal, and the third high-level signal line H3 is also a signal line used to connect to a high-level power signal. When the high-level signals required to connect to the second high-level signal line H2 and the third high-level signal line H3 are the same, the second high-level signal line H2 and the third high-level signal line H3 can be electrically connected. Thus, the second high-level signal line H2 and the third high-level signal line H3 can be connected through the same pad 40, which helps to reduce the number of pads 40, reduce the area occupied by the pads 40, and improve the space utilization of the display panel.

[0104] Continue to refer to Figure 13 In some alternative embodiments, pad 40 includes a third pad 43 and a fourth pad 44, and the second high-level signal line H2 and the third high-level signal line H3 are both electrically connected to the third pad 43 and the fourth pad 44.

[0105] Along the first direction X, the third pad 43 and the fourth pad 44 are located at both ends of the display panel.

[0106] Specifically, the third shift register 33 includes a first sub-shift register 331 and a second sub-shift register 332. The third power signal line L3 includes a first sub-power signal line L31 and a second sub-power signal line L32. Along the first direction X, the first sub-shift register 331 and the second sub-shift register 332 are located on both sides of the display panel. The third high-level signal line H3 includes a third sub-power signal line H31 and a fourth sub-power signal line H32. The first sub-shift register 331 is electrically connected to the third sub-power signal line H31. The second sub-shift register... Device 332 is electrically connected to the fourth sub-power signal line H32. Correspondingly, along the first direction X, a third pad 43 and a fourth pad 44 are respectively provided at both ends of the display panel. The second high-level signal line H2 and the third high-level signal line H3 are both electrically connected to the third pad 43 and the fourth pad 44, so that signals can be transmitted from the third pad 43 and the fourth pad 44 to the second high-level signal line H2 and the third high-level signal line H3 at the same time. This can effectively reduce the voltage drop and improve the uniformity of the signals transmitted to the second high-level signal line H2 and the third high-level signal line H3.

[0107] Figure 14 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 2 and Figure 14 In some optional embodiments, the pixel circuit 10 further includes a third control module 15 and a fourth control module 16, wherein the control terminal of the third control module 15 is electrically connected to the fourth control line S4, and the control terminal of the fourth control module 16 is connected to the fifth control line S5.

[0108] The display panel also includes a fourth shift register 34 and a fifth shift register 35, the outputs of which are electrically connected to the fourth control line S4 and the fifth control line S5, respectively.

[0109] The display panel also includes a fourth power signal line L4 and a fifth power signal line L5, which are electrically connected to the fourth shift register 34 and the fifth shift register 35, respectively.

[0110] The first power signal line L1 is disconnected from the fourth power signal line L4 and the fifth power signal line L5. The fourth and fifth power signal lines (L4 and L5) and the first power signal line L1 are all connected to a high-level signal or a low-level signal.

[0111] Specifically, the pixel circuit 10 also includes a third control module 15, the control terminal of the third control module 15 is electrically connected to the fourth control line S4, the display panel also includes a fourth shift register 34, the output terminal of the fourth shift register 34 is electrically connected to the fourth control line S4, the display panel also includes a fourth power signal line L4, the fourth power signal line L4 is electrically connected to the fourth shift register 34, the fourth power signal line L4 can also be connected to a power signal, so that the power signal is transmitted to the fourth shift register 34 through the fourth power signal line L4, the fourth shift register 34 generates a fourth control signal (S2N signal) based on the signal including the power signal, and transmits the fourth control signal (S2N signal) to the control terminal of the third control module 15 through the fourth control line S4, thereby realizing the control of the state of the third control module 15.

[0112] The pixel circuit 10 also includes a fourth control module 16, the control terminal of which is electrically connected to the fifth control line S5. The display panel also includes a fifth shift register 35, the output terminal of which is electrically connected to the fifth control line S5. The display panel also includes a fifth power signal line L5, which is electrically connected to the fifth shift register 35. The fifth power signal line L5 can also be connected to a power signal, so that the power signal is transmitted to the fifth shift register 35 via the fifth power signal line L5. The fifth shift register 35 generates a fifth control signal (S1N signal) based on the signal including the power signal, and transmits the fifth control signal (S1N signal) to the control terminal of the fourth control module 16 via the fifth control line S5, thereby realizing the control of the state of the fourth control module 16.

[0113] The fourth power signal line L4, the fifth power signal line L5, and the first power signal line L1 are all connected to a high-level signal or all to a low-level signal. That is, the fourth power signal line L4, the fifth power signal line L5, and the first power signal line L1 are connected to the same signal, the fourth power signal line L4, the fifth power signal line L5, and the first power signal line L1 are all connected to a high-level signal, or the fourth power signal line L4, the fifth power signal line L5, and the first power signal line L1 are all connected to a low-level signal.

[0114] When the fourth power signal line L4, the fifth power signal line L5, and the first power signal line L1 are all connected to a high-level signal, that is, when the first power signal line L1 is a signal line used to connect to a high-level power signal, and the fourth power signal line L4 and the fifth power signal line L5 are also signal lines used to connect to a high-level power signal, the connection between the first power signal line L1 and the fourth power signal line L4, and between the first power signal line L1 and the fifth power signal line L5, can be disconnected to prevent the signal on the first power signal line L1 from affecting the signals on the fourth power signal line L4 and the fifth power signal line L5.

[0115] Similarly, when the fourth power signal line L4, the fifth power signal line L5, and the first power signal line L1 are all connected to low-level signals, that is, when the first power signal line L1 is a signal line used to connect to a low-level power signal, and the fourth power signal line L4 and the fifth power signal line L5 are also signal lines used to connect to a low-level power signal, then the connection between the first power signal line L1 and the fourth power signal line L4, as well as between the first power signal line L1 and the fifth power signal line L5, can be disconnected to prevent the signal on the first power signal line L1 from affecting the signals on the fourth power signal line L4 and the fifth power signal line L5.

[0116] Continue to refer to Figure 2 and Figure 14 In some optional embodiments, the pixel circuit 10 further includes a threshold compensation module 151 and a gate reset module 161, which are electrically connected to the driving module 11. The third control module 15 includes the threshold compensation module 151, and the fourth control module 16 includes the gate reset module 161.

[0117] Specifically, the pixel circuit 10 also includes a threshold compensation module 151 and a gate reset module 161. The control terminal of the threshold compensation module 151 is electrically connected to the fourth control line S4, and the control terminal of the gate reset module 161 is electrically connected to the fifth control line S5.

[0118] Optionally, the transistors included in the threshold compensation module 151 and the gate reset module 161 are oxide transistors, that is, transistor T4 in the threshold compensation module 151 and transistor T5 in the gate reset module 161 are both oxide transistors. Optionally, transistor T4 in the threshold compensation module 151 and transistor T5 in the gate reset module 161 are both N-type metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors.

[0119] Figure 15 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 15 In some alternative embodiments, at least two of the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 are electrically connected.

[0120] Specifically, when the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 are all connected to a high-level signal or all to a low-level signal, at least two of the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 can be electrically connected. This allows for electrical connection between the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 and the driver chip using fewer pads 40. Optionally, the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 can be electrically connected, allowing them to be connected using the same pads 40. This reduces the number of pads 40, reduces the area occupied by the pads 40, and improves the space utilization of the display panel. Meanwhile, the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 can share the same set of voltage settings. That is, the power signals provided to the second power signal line L2, the third power signal line L3, the fourth power signal line L4, and the fifth power signal line L5 can be provided through the same set of voltage adjustment modules in the driver chip. This helps to reduce the design difficulty of the driver chip and reduce the production cost of the driver chip.

[0121] Continue to refer to Figure 2 and Figure 14 In some alternative embodiments, the second power signal line L2 and the third power signal line L3 are electrically connected, the fourth power signal line L4 and the fifth power signal line L5 are electrically connected, and the third power signal line L3 and the fourth power signal line L4 are disconnected.

[0122] Specifically, transistor T2 in data writing module 141 is of the same type as transistor T7 in first reset module 131, so they can use the same voltage setting for the drive signal. The second shift register 32, which is electrically connected to the second power signal line L2, is used to input the second control signal (SPX signal) to the first reset module 131. The third shift register 33, which is electrically connected to the third power signal line L3, is used to input the third control signal (SP signal) to data writing module 141. The second power signal line L2 and the third power signal line L3 are electrically connected. At this time, it will not affect the normal operation and reliability of transistor T2 in data writing module 141 and transistor T7 in first reset module 131.

[0123] The transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 are of the same type, so they can use the same voltage setting for the drive signal. The fourth shift register 34, which is electrically connected to the fourth power supply signal line L4, is used to input the fourth control signal (S2N signal) to the threshold compensation module 151, and the fifth shift register 35, which is electrically connected to the fifth power supply signal line L5, is used to input the fifth control signal (S1N signal) to the gate reset module 161. The fourth power supply signal line L4 and the fifth power supply signal line L5 are electrically connected. At this time, it will not affect the normal operation and reliability of the transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161.

[0124] The transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151 are of different types. The fourth shift register 34, which is electrically connected to the fourth power signal line L4, is used to input the fourth control signal (S2N signal) to the threshold compensation module 151. The third shift register 33, which is electrically connected to the third power signal line L3, is used to input the third control signal (SP signal) to the data writing module 141. The fourth power signal line L4 and the third power signal line L3 are disconnected, so that the signals connected to the third power signal line L3 and the fourth power signal line L4 can be controlled independently, which can ensure the normal operation and reliability of the transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151.

[0125] Continue to refer to Figure 14 In some alternative embodiments, the first to fifth power signal lines (L1-L5) are connected to a low-level signal.

[0126] Specifically, the first to fifth power signal lines (L1-L5) are all connected to low-level signals, meaning they are all signal lines used to connect to low-level power signals. In this case, disconnecting the first power signal line L1 and the second to fifth power signal lines (L2-L5) ensures that the low-level power signal transmitted on the first power signal line L1 will not affect the low-level power signals transmitted on the second to fifth power signal lines (L2-L5). Therefore, when the low-level power signal used to drive the first control signal (EM signal) experiences potential fluctuations in a periodic manner, the low-level power signals used to drive other control signals will not couple, thus preventing periodic coupling fluctuations in other control signals. This effectively improves the display problem of bright and dark horizontal lines on the display panel under low grayscale display conditions, contributing to improved display quality.

[0127] It should be noted that the low-level signals connected to the first to fifth power signal lines (L1-L5) can be completely the same, partially the same, or completely different. They can be set according to actual design requirements, and this disclosure will not elaborate further here. Figure 16 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 16 In some optional embodiments, the display panel further includes first to fifth high-level signal lines (H1-H5), first to fifth shift registers (31-35) are electrically connected to the first to fifth high-level signal lines (H1-H5) respectively, and the first high-level signal line H1 is disconnected from the second to fifth high-level signal lines (H2-H5).

[0128] Specifically, the display panel also includes first to fifth high-level signal lines (H1-H5), and first to fifth shift registers (31-35) are electrically connected to the first to fifth high-level signal lines (H1-H5) respectively. The first to fifth high-level signal lines (H1-H5) are all signal lines used to input high-level power signals. At this time, the first high-level signal line H1 is disconnected from the other high-level signal lines (H2-H5), that is, the high-level power signal transmitted on the first high-level signal line H1 will not affect the high-level power signals transmitted on the second to fifth high-level signal lines (H2-H5). Therefore, when the high-level power signal used to drive the first control signal (EM signal) has a potential fluctuation in a periodic manner, the high-level power signals used to drive other control signals will not be coupled, so that other control signals will not have periodic coupling fluctuations. This effectively improves the display problem of bright and dark horizontal stripes in low grayscale display and is conducive to improving display quality.

[0129] It should be noted that the high-level signals connected to the first to fifth high-level signal lines (H1-H5) can be completely the same, partially the same, or completely different. They can be set according to actual design requirements, and this disclosure will not elaborate further here.

[0130] It should be noted that, Figure 16 To clearly illustrate the arrangement of the first to fifth high-level signal lines (H1-H5), Figure 16 The first to fifth power signal lines (L1-L5) are not shown in the diagram. The arrangement of the first to fifth power signal lines (L1-L5) in the display panel can be found in [reference needed]. Figure 14 and Figure 15 The arrangement of the first to fifth power signal lines (L1-L5) is not described in detail here.

[0131] Continue to refer to Figure 2 and Figure 16 In some alternative embodiments, the second high-level signal line H2 is electrically connected to the third high-level signal line H3, the fourth high-level signal line H4 is electrically connected to the fifth high-level signal line H5, and the third high-level signal line H3 is disconnected from the fourth high-level signal line H4.

[0132] Specifically, transistor T2 in data writing module 141 and transistor T7 in first reset module 131 are of the same type, so they can use the same voltage setting for the drive signal. The second shift register 32, which is electrically connected to the second high-level signal line H2, is used to input the second control signal (SPX signal) to the first reset module 131. The third shift register 33, which is electrically connected to the third high-level signal line H3, is used to input the third control signal (SP signal) to data writing module 141. The second high-level signal line H2 and the third high-level signal line H3 are electrically connected. At this time, it will not affect the normal operation and reliability of transistor T2 in data writing module 141 and transistor T7 in first reset module 131.

[0133] The transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161 are of the same type, so they can use the same voltage setting for the drive signal. The fourth shift register 34, which is electrically connected to the fourth high-level signal line H4, is used to input the fourth control signal (S2N signal) to the threshold compensation module 151, and the fifth shift register 35, which is electrically connected to the fifth high-level signal line H5, is used to input the fifth control signal (S1N signal) to the gate reset module 161. The fourth high-level signal line H4 and the fifth high-level signal line H5 are electrically connected. At this time, it will not affect the normal operation and reliability of the transistor T4 in the threshold compensation module 151 and the transistor T5 in the gate reset module 161.

[0134] The transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151 are of different types. The fourth shift register 34, which is electrically connected to the fourth high-level signal line H4, is used to input the fourth control signal (S2N signal) to the threshold compensation module 151. The third shift register 33, which is electrically connected to the third high-level signal line H3, is used to input the third control signal (SP signal) to the data writing module 141. The third high-level signal line H3 and the fourth high-level signal line H4 are disconnected, so that the signals connected to the third high-level signal line H3 and the fourth high-level signal line H4 can be controlled independently, which can ensure the normal operation and reliability of the transistor T7 in the first reset module 131 and the transistor T4 in the threshold compensation module 151.

[0135] Figure 17 This is a plan view of yet another display panel provided in this disclosure, for reference. Figure 17 In some alternative embodiments, the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4, and the fifth high-level signal line H5 are electrically connected.

[0136] Specifically, the second high-level signal line H2, the third high-level signal line H3, the fourth high-level signal line H4, and the fifth high-level signal line H5 are all connected to a high-level signal. These lines can be electrically connected, allowing them to share the same pad 40. This reduces the number of pads 40 and their occupied area, improving the space utilization of the display panel. Furthermore, these lines can share the same voltage setting, meaning the power signals provided to them can be obtained through the same voltage regulation module in the driver chip. This reduces the design complexity and production cost of the driver chip.

[0137] It should be noted that, Figure 17 To clearly illustrate the arrangement of the first to fifth high-level signal lines (H1-H5), Figure 17 The first to fifth power signal lines (L1-L5) are not shown in the diagram. The arrangement of the first to fifth power signal lines (L1-L5) in the display panel can be found in [reference needed]. Figure 14 and Figure 15 The arrangement of the first to fifth power signal lines (L1-L5) is not described in detail here.

[0138] like Figure 18 As shown, Figure 18 This is a plan view of a display device provided in this disclosure. Embodiments of this disclosure also provide a display device 1000, including the display panel 100 provided in any of the above embodiments. The display device may further include a housing for providing mechanical support and protection, a power management module located within the housing, an audio output module, etc. Figure 18 The provided embodiments use mobile phones as an example to illustrate the display device. It is understood that the display device provided in the embodiments of this disclosure can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. The embodiments of this disclosure do not make any special limitations on this.

[0139] The display device 1000 provided in this embodiment has the same technical features as the display panel 100 provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0140] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0141] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: A pixel circuit and a light-emitting element are electrically connected. The pixel circuit includes a driving module, a light-emitting control module, and a first control module. The control terminal of the light-emitting control module is connected to a first control line, and the control terminal of the first control module is connected to a second control line. The first control module includes a bias adjustment module, which is electrically connected to the drive module and is used to adjust the bias of the drive module. The display panel includes a first shift register and a second shift register. The output terminal of the first shift register is electrically connected to the first control line, and the output terminal of the second shift register is electrically connected to the second control line. The display panel further includes a first power signal line and a second power signal line. The first power signal line is electrically connected to the first shift register, and the second power signal line is electrically connected to the second shift register. The first power signal line and the second power signal line are isolated from each other. Both the first power signal line and the second power signal line are connected to a high-level signal or both are connected to a low-level signal.

2. The display panel according to claim 1, characterized in that, Both the first power signal line and the second power signal line are connected to a low-level signal.

3. The display panel according to claim 2, characterized in that, The first shift register is electrically connected to the first high-level signal line, and the second shift register is electrically connected to the second high-level signal line. The high-level potentials of the first high-level signal line and the second high-level signal line are the same.

4. The display panel according to claim 3, characterized in that, The absolute values ​​of the low-level signals connected to the first power signal line and the second power signal line are the same.

5. The display panel according to claim 2, characterized in that, The first shift register is electrically connected to the first high-level signal line, the second shift register is electrically connected to the second high-level signal line, and the first high-level signal line is disconnected from the second high-level signal line.

6. The display panel according to claim 1, characterized in that, The pixel circuit also includes a second control module, the control terminal of which is connected to a third control line; The display panel also includes a third shift register, the output of which is electrically connected to the third control line; The display panel also includes a third power signal line, which is electrically connected to the third shift register. The second power signal line and the third power signal line are electrically connected, and both the second power signal line and the third power signal line are connected to a high-level signal or both are connected to a low-level signal.

7. The display panel according to claim 6, characterized in that, The pixel circuit also includes a data writing module, which is used to write data signals into the driving module. The second control module includes the data writing module.

8. The display panel according to claim 6, characterized in that, The third shift register includes a first sub-shift register and a second sub-shift register, and the third power signal line includes a first sub-power signal line and a second sub-power signal line. Along the first direction, the first sub-shift register and the second sub-shift register are located on both sides of the display panel. The first sub-shift register is electrically connected to the first sub-power signal line, and the second sub-shift register is electrically connected to the second sub-power signal line; Along the second direction, the first sub-power signal line and the second sub-power signal line are connected to at least one side of the display panel, wherein the first direction and the second direction intersect.

9. The display panel according to claim 8, characterized in that, The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a first non-display area and a second non-display area located on opposite sides of the display area. The second power signal line and the third power signal line are electrically connected in the first non-display area and / or the second non-display area.

10. The display panel according to claim 8, characterized in that, The first sub-power signal line, the second sub-power signal line, and the second power signal line are electrically connected to the same first power bus.

11. The display panel according to claim 8, characterized in that, The display panel includes multiple pads, including a first pad and a second pad, and the second power signal line and the third power signal line are both electrically connected to the first pad and the second pad. Along the first direction, the first pad and the second pad are located at opposite ends of the display panel.

12. The display panel according to claim 6, characterized in that, Both the second power signal line and the third power signal line are connected to a low-level potential.

13. The display panel according to claim 12, characterized in that, The first shift register is electrically connected to the first high-level signal line, the second shift register is electrically connected to the second high-level signal line, and the third shift register is electrically connected to the third high-level signal line. The first high-level signal line is disconnected from the second high-level signal line and the third high-level signal line.

14. The display panel according to claim 13, characterized in that, The second power signal line and the third power signal line are electrically connected, and the second high-level signal line and the third high-level signal line are electrically connected.

15. The display panel according to claim 7, characterized in that, The pixel circuit further includes a third control module and a fourth control module, wherein the control terminal of the third control module is connected to the fourth control line, and the control terminal of the fourth control module is connected to the fifth control line; The display panel further includes a fourth shift register and a fifth shift register, the output terminals of which are electrically connected to the fourth control line and the fifth control line, respectively. The display panel further includes a fourth power signal line and a fifth power signal line, which are electrically connected to the fourth shift register and the fifth shift register, respectively. The first power signal line is disconnected from the fourth and fifth power signal lines, and the fourth and fifth power signal lines and the first power signal line are all connected to a high-level signal or a low-level signal.

16. The display panel according to claim 15, characterized in that, The pixel circuit further includes a threshold compensation module and a gate reset module, which are electrically connected to the driving module. The third control module includes the threshold compensation module, and the fourth control module includes the gate reset module.

17. The display panel according to claim 16, characterized in that, The second power signal line, the third power signal line, the fourth power signal line, and the fifth power signal line are at least two electrically connected.

18. The display panel according to claim 17, characterized in that, The second power signal line and the third power signal line are electrically connected, the fourth power signal line and the fifth power signal line are electrically connected, and the third power signal line and the fourth power signal line are disconnected.

19. The display panel according to claim 17 or 18, characterized in that, The first to fifth power signal lines are connected to low-level signals.

20. The display panel according to claim 19, characterized in that, The display panel also includes a first to a fifth high-level signal line, the first to a fifth shift registers are electrically connected to the first to a fifth high-level signal line respectively, and the first high-level signal line is disconnected from the second to a fifth high-level signal line.

21. The display panel according to claim 20, characterized in that, The second high-level signal line is electrically connected to the third high-level signal line, the fourth high-level signal line is electrically connected to the fifth high-level signal line, and the third high-level signal line is disconnected from the fourth high-level signal line.

22. The display panel according to claim 21, characterized in that, The threshold compensation module and the gate reset module contain oxide transistors.

23. The display panel according to claim 1, characterized in that, In the low-frequency operating mode of the display panel, a hold period is inserted between two write periods, and the control signal transmitted by the second control line includes at least one pulse during the hold period.

24. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-23.

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