Gate drive circuit and display panel

Abstract

The present application discloses a gate drive circuit and a display panel, wherein the gate drive circuit includes: a plurality of cascaded gate drive units, each of which includes at least: a first output unit for outputting a first pulse signal; a second output unit for outputting a second pulse signal; a cascade unit connected to the first output unit of the gate drive unit of the previous level, for receiving the first pulse signal of the previous level; a first drive unit arranged between the cascade unit and the control end of the first output unit; and a second drive unit arranged between the cascade unit and the control end of the second output unit, for causing the second output unit to output a high-potential pulse of the second pulse signal when the first output unit outputs a low-potential pulse of the first pulse signal. Through the above circuit, the output of different scanning signals is achieved.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate drive circuit and a display panel. Background Art

[0002] With the development of display technology, OLED (Organic Light Emitting Display) has begun to move towards the small-size mainstream display market. Small-size OLED display products usually use GOA (gate on array) circuits to generate and process the scanning signals required by pixel driving circuits.

[0003] In order to achieve the low refresh rate function, it is necessary to extend the holding time of the gate voltage of the driving transistor in principle. The current mainstream solution is to introduce a new material with lower Ioff (leakage current) characteristics, indium gallium zinc oxide (IGZO) to make transistors, or to adopt phosphorus channel doping process to make different types of transistors.

[0004] To further reduce leakage, P is implanted into MOS (transistors) based on IGZO to form NMOS (N-type transistors) with lower carrier mobility. NMOS requires a positive pulse to drive, contrary to other PMOS (P-type transistors). Therefore, in the design of the GOA circuit, in addition to the switching pulse (EM) and the low-level pulse (Pscan), an additional GOA circuit for generating a high-level pulse (Nscan) is required. However, the additional GOA circuit for generating a high-level pulse will occupy a large area of ​​the frame. Summary of the Invention

[0005] The main technical problem solved by the present application is to provide a gate drive circuit and a display panel to realize the output of different scanning signals.

[0006] To solve the above problems, the present application provides a gate drive circuit in the first aspect, wherein the gate drive circuit includes: a plurality of cascaded gate drive units, each of the gate drive units including at least: a first output unit for outputting a first pulse signal; wherein the first pulse signal is a low-potential pulse signal with a normal high potential; a second output unit for outputting a second pulse signal; wherein the second pulse signal is a high-potential pulse signal with a normal low potential; a cascade unit connected to the first output unit of the gate drive unit of the previous level, for receiving the first pulse signal of the previous level; a first drive unit, arranged between the cascade unit and the control end of the first output unit, for providing a drive signal to the first output unit according to the cascade signal of the cascade unit, so that the first output unit outputs the first pulse signal; a second drive unit, arranged between the cascade unit and the control end of the second output unit, for providing a drive signal to the second output unit according to the cascade signal of the cascade unit, so that the second output unit outputs the second pulse signal, and causes the second output unit to output a high-potential pulse of the second pulse signal when the first output unit outputs a low-potential pulse of the first pulse signal.

[0007] Wherein, the pulse width of the second pulse signal is greater than the pulse width of the first pulse signal.

[0008] Wherein, the first output unit includes a first sub-output unit and a first pulse output holding unit; the input end of the first sub-output unit is connected to the first jump signal line, and the control end of the first sub-output unit is connected to the output end of the first driving unit, for outputting high-potential pulses and low-potential pulses of the first pulse signal according to the driving signal provided by the first driving unit; the input end of the first pulse output holding unit is connected to the high-potential signal line, and the control end of the first pulse output holding unit is connected to the output end of the first driving unit, for maintaining the output of the high-potential pulse of the first pulse signal according to the driving signal provided by the first driving unit; the second output unit includes a second sub-output unit and a second pulse output holding unit; the input end of the second sub-output unit is connected to the high-potential signal line, and the control end of the second sub-output unit is connected to the output end of the second driving unit, for outputting the high-potential pulse of the second pulse signal according to the driving signal provided by the second driving unit; the input end of the second pulse output holding unit is connected to the low-potential signal line, and the control end of the second pulse output holding unit is connected to the output end of the second driving unit, for maintaining the output of the low-potential pulse of the second pulse signal according to the driving signal provided by the second driving unit.

[0009] Wherein, the first driving unit includes: a first storage unit, the first electrode plate of the first storage unit is connected to the output end of the cascade unit, the control end of the first sub-output unit, and the control end of the first pulse output holding unit, and the second electrode plate of the first storage unit is connected to the output end of the first output unit, for storing the voltage signal charged by the cascade unit and controlling the operation of the first sub-output unit or the first pulse output holding unit according to the stored voltage signal; a first charging control unit, the first charging control unit is arranged between the cascade unit and the first electrode plate of the first storage unit, for controlling the cascade unit to charge the voltage signal into the first storage unit.

[0010] Wherein, the control end of the first charging control unit is connected to the low-potential signal line.

[0011] Wherein, the second driving unit includes: a second storage unit, wherein the first electrode plate of the second storage unit is connected to the output end of the cascade unit and the input end of the first charging control unit, and the second electrode plate of the second storage unit is connected to the low-potential signal line, and is used to store the voltage signal charged by the cascade unit or the first storage unit; a second charging control unit, wherein the second charging control unit is arranged between the output end of the cascade unit and / or the input end of the first charging control unit and the second storage unit, and is used to control the cascade unit and / or the first storage unit to charge the voltage signal to the second storage unit; a third storage unit, wherein the first electrode plate of the third storage unit It is connected to the first plate of the second storage unit, the control end of the second sub-output unit, and the control end of the second pulse output holding unit, and the second plate of the third storage unit is connected to the high-potential signal line, and is used to store the voltage signal charged by the second storage unit and control the second sub-output unit or the second pulse output holding unit to operate according to the stored voltage signal; the third charging control unit is arranged between the first plate of the second storage unit and the third storage unit, the control end of the second sub-output unit, and the control end of the second pulse output holding unit, and is used to control the second storage unit to charge the voltage signal into the first plate of the third storage unit.

[0012] The control end of the cascade unit is connected to a second jump signal line; wherein the signal jump frequencies on the second jump signal line and the first jump signal line are the same and the phases are opposite.

[0013] Wherein, the control end of the second charging control unit is connected to the third jump signal line; wherein, the high-potential signal pulse width on the third jump signal line is greater than the low-potential signal pulse width on the first jump signal line or the high-potential signal pulse width on the second jump signal line; wherein, the high-potential signal pulse width on the third jump signal line is the same as the high-potential pulse width of the second pulse signal.

[0014] Wherein, the control end of the third charging control unit is connected to the first jump signal line.

[0015] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0016] The beneficial effect of the present application is that, by designing the cascade unit, while minimizing the use of input signals, a GOA circuit can output different first pulse signals and second pulse signals to different types of transistors (TFTs) in the pixel unit, thereby saving circuit expenses and reducing the border width. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic structural diagram of an embodiment of a gate drive circuit provided in this application;

[0019] Figure 2 A timing diagram of the first pulse signal and the second pulse signal provided in this application;

[0020] Figure 3 This is a schematic structural diagram of a first specific embodiment of a gate driving unit provided in this application;

[0021] Figure 4 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in this application;

[0022] Figure 5 A schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application;

[0023] Figure 6 A driving timing diagram of a specific embodiment of the gate driving unit provided in this application;

[0024] Figure 7A circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in this application;

[0025] Figure 8 A circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in this application;

[0026] Figure 9 A circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application;

[0027] Figure 10 A circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application;

[0028] Figure 11 A circuit diagram of the fifth driving stage of a specific embodiment of the gate driving unit provided in this application;

[0029] Figure 12 This is a schematic structural diagram of an embodiment of a display panel provided in this application.

[0030] First output unit 11; second output unit 12; cascade unit 20; first drive unit 31; second drive unit 32; previous stage first pulse signal Pscan(n-1); first pulse signal Pscan(n); second pulse signal Nscan(n);

[0031] First sub-output unit 111; first pulse output holding unit 112; second sub-output unit 121; second pulse output holding unit 122; high potential signal line VGH; low potential signal line VGL;

[0032] First storage unit C1; first charging control unit 311; second storage unit C2; second charging control unit 312; third storage unit C3; third charging control unit 313; first jump signal line CK; second jump signal line XCK; third jump signal line CK2;

[0033] A first transistor T1; a second transistor T2; a third transistor T3; a fourth transistor T4; a fifth transistor T5; a sixth transistor T6; a seventh transistor T7; and an eighth transistor T8;

[0034] Display panel 100 ; display area 101 ; non-display area 102 . DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0037] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0038] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0039] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0040] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0041] It should be noted that the high-voltage signal line VGH is used to transmit a high-voltage signal, while the low-voltage signal line VGL is used to transmit a low-voltage signal. The input terminal of a transistor is also the source of the transistor, the output terminal of the transistor is also the drain of the transistor, and the control terminal of the transistor is also the gate of the transistor. The source and drain of a transistor are interchangeable. Turning off, cutoff, or disconnecting a transistor have the same meaning.

[0042] The present application provides a gate drive circuit, which includes: a plurality of cascaded gate drive units, for details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by this application. Figure 1 As shown, each gate driving unit at least includes: a first output unit 11 , a second output unit 12 , a cascade unit 20 , a first driving unit 31 , and a second driving unit 32 .

[0043] The first output unit 11 is used to output a first pulse signal Pscan(n), and the second output unit 12 is used to output a second pulse signal Nscan(n). The first pulse signal Pscan(n) is a low-voltage pulse signal with a normal high voltage. The second pulse signal Nscan(n) is a high-voltage pulse signal with a normal low voltage.

[0044] The cascade unit 20 is connected to the first output unit 11 of the previous-stage gate driving unit GOA(n-1) and is configured to receive the previous-stage first pulse signal Pscan(n-1).

[0045] The first driving unit 31 is provided between the cascade unit 20 and the control terminal of the first output unit 11, and is configured to provide a driving signal to the control terminal of the first output unit 11 according to the cascade signal of the cascade unit 20, so that the first output unit 11 outputs the first pulse signal Pscan(n). The cascade signal includes a high-potential pulse signal and a low-potential pulse signal of the first pulse signal Pscan(n-1) of the previous stage.

[0046] The second driving unit 32 is arranged between the cascade unit 20 and the control end of the second output unit 12, and is used to provide a driving signal to the control end of the second output unit 12 according to the cascade signal of the cascade unit 20, so that the second output unit 12 outputs the second pulse signal Nscan(n), and when the first output unit 11 outputs the low-voltage pulse of the first pulse signal Pscan(n), the second output unit 12 outputs the high-voltage pulse of the second pulse signal Nscan(n), that is, the first pulse signal Pscan(n) and the second pulse signal Nscan(n) are triggered and output at the same time.

[0047] In a specific embodiment, the pulse width of the second pulse signal Nscan(n) is greater than the pulse width of the first pulse signal Pscan(n). Figure 2 , Figure 2 This is a timing diagram of the first pulse signal and the second pulse signal provided in this application. Figure 2 As shown, the low-level pulse of the first pulse signal Pscan(n) and the high-level pulse of the second pulse signal Nscan(n) are triggered and output simultaneously, and the pulse width of the second pulse signal Nscan(n) is greater than the pulse width of the first pulse signal Pscan(n). Specifically, the pulse width of the second pulse signal Nscan(n) can be adjusted according to design requirements. The pulse width of the second pulse signal Nscan(n) refers to the duration (duty cycle) of the high-level output phase of the second pulse signal Nscan(n). The pulse width of the first pulse signal Pscan(n) refers to the duration of the low-level output phase of the first pulse signal Pscan(n).

[0048] like Figure 2 As shown, the driving timing includes a P output phase and an N output phase. In the P output phase, the first pulse signal Pscan(n) outputs a low-potential pulse (low-potential voltage). In the other phases, the output voltage remains high. In the N output phase, the second pulse signal Nscan(n) outputs a high-potential pulse (low-potential voltage). In the other phases, the output voltage remains low.

[0049] In a preferred embodiment, the pulse width of the second pulse signal Nscan(n) is one or more times the pulse width of the first pulse signal Pscan(n).

[0050] Furthermore, the first output unit 11 includes a first sub-output unit 111 and a first pulse output holding unit 112. The second output unit 12 includes a second sub-output unit 121 and a second pulse output holding unit 122. Figure 3 , Figure 3 This is a schematic structural diagram of the first specific embodiment of the gate drive unit provided in this application. Figure 3As shown, the input end of the first sub-output unit 111 is connected to the first jump signal line CK, and the control end of the first sub-output unit 111 is connected to the output end of the first driving unit 31, and is configured to output high-potential pulses and low-potential pulses of the first pulse signal Pscan(n) according to the driving signal provided by the first driving unit 31. The driving signal includes a high-potential voltage and a low-potential voltage.

[0051] The input terminal of the first pulse output holding unit 112 is connected to the high-potential signal line VGH, and the control terminal of the first pulse output holding unit 112 is connected to the output terminal of the first driving unit 31. The first pulse output holding unit 112 is configured to maintain the output of the high-potential pulse of the first pulse signal Pscan(n) according to the driving signal provided by the first driving unit 31. Specifically, the first pulse output holding unit 112 maintains the output of the high-potential voltage (i.e., the high-potential pulse / voltage of the first pulse signal Pscan(n)) during the holding phase following the P output phase of the first pulse signal Pscan(n). The first pulse output holding unit 112 remains conductive during the holding phase following the P output phase of the first pulse signal Pscan(n).

[0052] The input terminal of the second sub-output unit 121 is connected to the high-potential signal line VGH, and the control terminal of the second sub-output unit 121 is connected to the output terminal of the second driving unit 32, and is configured to output a high-potential pulse of the second pulse signal Nscan(n) according to a driving signal provided by the second driving unit 32. The driving signal includes a high-potential voltage and a low-potential voltage.

[0053] The input terminal of the second pulse output holding unit 122 is connected to the low-potential signal line VGL, and the control terminal of the second pulse output holding unit 122 is connected to the output terminal of the second driving unit 32, so as to maintain the output of the low-potential pulse of the second pulse signal Nscan(n) according to the driving signal provided by the second driving unit 32. Specifically, the second pulse output holding unit 122 maintains the output of the low-potential voltage during the holding phase after the N output phase of the second pulse signal Nscan(n), that is, the second pulse output holding unit 122 remains conductive during the holding phase after the N output phase.

[0054] See further Figure 4 , Figure 4 This is a schematic diagram of the structure of the second specific embodiment of the gate drive unit provided in this application. Figure 4 As shown, the first driving unit 31 includes a first storage unit C1 and a first charging control unit 311 .

[0055] Specifically, the first plate of the first storage cell C1 is connected to the output terminal of the cascade unit 20, the control terminal of the first sub-output unit 111, and the control terminal of the first pulse output holding unit 112. The second plate of the first storage cell C1 is connected to the output terminal of the first output unit 11 (i.e., the output terminal of the first sub-output unit 111 and the output terminal of the first pulse output holding unit 112). The first storage cell C1 is used to store the voltage signal (including the high potential voltage and the low potential voltage) charged to the first plate of the first storage cell C1 by the cascade unit 20 and control the operation of the first sub-output unit 111 or the first pulse output holding unit 112 based on the stored voltage signal. Specifically, when the first sub-output unit 111 is controlled to operate, the first pulse output holding unit 112 is controlled to be inactive; when the first pulse output holding unit 112 is controlled to operate, the first sub-output unit 111 is controlled to be inactive.

[0056] Specifically, the first sub-output unit 111 and the first pulse output holding unit 112 include a group of transistors with opposite driving characteristics, one being an N-type transistor and the other being a P-type transistor.

[0057] The first charging control unit 311 is disposed between the cascade unit 20 and the first plate of the first storage unit C1. It is used to control the cascade unit 20 to charge the voltage signal into the first storage unit C1. The second plate of the first storage unit C1 is also connected to the output of the first output unit 11 (or the first sub-output unit 111), enabling the first storage unit C1 to function as a storage device and controlling the output state (operating state) of the first sub-output unit 111. It should be noted that in the first phase (sampling phase), the first jump signal line CK outputs a high potential, the first pulse signal Pscan(n) is controlled by the first sub-output unit 111 to output a high potential pulse, the second plate of the first storage cell C1 is at a high potential, and the first plate of the first storage cell C1 can store a low potential. In the second phase (P output phase), the first jump signal line CK outputs a low potential, the first pulse signal Pscan(n) is controlled by the first sub-output unit 111 to output a low potential pulse, and the second plate of the first storage cell C1 is at a low potential. During the low potential output process, the low potential of the first plate of the first storage cell C1 gradually decreases, thereby pulling the control terminal (gate) of the first charging control unit 311 low, ensuring that the transistor in the first charging control unit 311 is turned on. In other embodiments, the second plate of the first storage cell C1 can also be connected to a fixed signal line, such as the high potential signal line VGH or the low potential signal line VGL, which is not limited here.

[0058] In this specific embodiment, the control terminal of the first charging control unit 311 is connected to the low-potential signal line VGL. The first charging control unit 311 remains in a normally-on state under the control of the low-potential signal line VGL. The second driving unit 32 is disposed at the end of the first charging control unit 311 away from the first storage unit C1. The first storage unit C1 also provides a driving signal to the second driving unit 32 through the first charging control unit 311.

[0059] The second driving unit 32 includes a second storage unit C2 , a second charging control unit 312 , a third storage unit C3 , and a third charging control unit 313 .

[0060] The first electrode plate of the second storage unit C2 is connected to the output end of the cascade unit 20 and the input end of the first charging control unit 311, and the second electrode plate of the second storage unit C2 is connected to the low potential signal line VGL, which is used to store the voltage signal charged by the cascade unit 20 or the first storage unit C1.

[0061] The second charging control unit 312 is arranged between the output end of the cascade unit 20 and / or the input end of the first charging control unit 311 and the second storage unit C2, and is used to control the cascade unit 20 and / or the input end of the first charging control unit 311 and the second storage unit C2, and is used to control the cascade unit 20 and / or the first storage unit C1 to charge the voltage signal into the first plate of the second storage unit C2.

[0062] The first plate of the third storage cell C3 is connected to the first plate of the second storage cell C2, the control terminal of the second sub-output unit 121, and the control terminal of the second pulse output holding unit 122. The second plate of the third storage cell C3 is connected to the high-potential signal line VGH. The third storage cell C3 is used to store the voltage signal charged by the second storage cell C2 and control the operation of the second sub-output unit 121 or the second pulse output holding unit 122 based on the stored voltage signal. Specifically, when the second sub-output unit 121 is controlled to operate, the second pulse output holding unit 122 is controlled to be inoperative; when the second pulse output holding unit 122 is controlled to operate, the second sub-output unit 121 is controlled to be inoperative.

[0063] The third charging control unit 313 is arranged between the first plate of the second storage unit C2 and the first plate of the third storage unit C3, the control end of the second sub-output unit 121, and the control end of the second pulse output holding unit 122, and is used to control the second storage unit C2 to charge the voltage signal into the first plate of the third storage unit C3.

[0064] Furthermore, the control terminal of the cascade unit 20 is connected to the second transition signal line XCK. The second transition signal line XCK has the same transition frequency as the first transition signal line CK, but an opposite phase. Specifically, both the first transition signal line CK and the second transition signal line XCK transition between a high potential and a low potential. When the first transition signal line CK outputs a high potential, the second transition signal line XCK outputs a low potential; when the first transition signal line CK outputs a low potential, the second transition signal line XCK outputs a high potential. The high and low potential pulse widths on the first and second transition signal lines CK and XCK are identical.

[0065] Furthermore, the control end of the second charging control unit 312 is connected to the third jump signal line CK2. The high-potential signal pulse width on the third jump signal line CK2 is the same as the high-potential pulse width of the second pulse signal Nscan(n). The high-potential pulse width of the second pulse signal Nscan(n) is controlled by the high-potential signal pulse width on the third jump signal line CK2. It should be noted that the pulse width of the second pulse signal Nscan(n) refers to the high-potential pulse width of the second pulse signal Nscan(n), and the pulse width of the first pulse signal Pscan(n) refers to the low-potential pulse width of the first pulse signal Pscan(n).

[0066] In a preferred embodiment, the high-potential signal pulse width on the third transition signal line CK2 is greater than the low-potential signal pulse width on the first transition signal line CK or the high-potential signal pulse width on the second transition signal line XCK. The high-potential signal pulse width on the third transition signal line CK2 is greater than the low-potential signal pulse width on the third transition signal line CK2.

[0067] In a further embodiment, the control terminal of the third charging control unit 313 is connected to the first jump signal line CK. In other embodiments, the control terminal of the third charging control unit 313 may also be connected to the second jump signal line XCK, which is not limited here.

[0068] This application also provides a gate drive unit circuit structure. Figure 5 , Figure 5 This is a schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application. Figure 5 shown.

[0069] The cascade unit 20 includes a first transistor T1, the first charging control unit 311 includes a second transistor T2, the first sub-output unit 111 includes a third transistor T3, the first pulse output holding unit 112 includes a fourth transistor T4, the second charging control unit 312 includes a fifth transistor T5, the third charging control unit 313 includes a sixth transistor T6, the second sub-output unit 121 includes a seventh transistor T7, and the second pulse output holding unit 122 includes an eighth transistor T8.

[0070] In this specific embodiment, the fourth transistor T4 and the seventh transistor T7 are N-type transistors, and the other transistors are P-type transistors.

[0071] This application also provides a driving timing diagram of a specific embodiment of a gate driving unit. Figure 6 , Figure 6 This is a driving timing diagram of a specific embodiment of the gate driving unit provided in this application. The driving phase includes a sampling phase, a P output phase, an N output phase, a P hold phase, and an N hold phase. For further details, please refer to Figures 7 to 11 . Figure 7 This is a circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 8 This is a circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 9 This is a circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 10 This is a circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 11 This is a circuit diagram of the fifth driving stage of a specific embodiment of the gate driving unit provided in this application.

[0072] During the first phase (also known as the sampling phase), the previous-stage first pulse signal Pscan(n-1) is a low-level signal. The first transition signal line CK transmits a high-level signal, the second transition signal line XCK transmits a low-level signal, and the third transition signal line CK2 transmits a low-level signal. The second transition signal line XCK controls the conduction of the first transistor T1, and the low-level signal line VGL controls the conduction of the second transistor T2. The low-level pulse signal of the previous-stage first pulse signal Pscan(n-1) is transmitted through the first and second transistors T1 and T2 to the gate of the third transistor T3, the gate of the fourth transistor T4, and the first plate of the first storage cell C1 for storage. Simultaneously, the low-level signal controls the conduction of the third transistor T3 and the cutoff of the fourth transistor T4. The high-level signal of the first transition signal line CK is output through the third transistor T3, thereby causing the first pulse signal Pscan(n) to output a high-level pulse. The third jump signal line CK2 controls the fifth transistor T5 to turn on. The low-level pulse signal of the previous stage first pulse signal Pscan(n-1) is charged into the first electrode plate of the second storage unit C2 through the fifth transistor T5 and stored. The first electrode plate of the third storage unit C3 stores a high-level signal in the previous frame, which controls the seventh transistor T7 to turn on and the eighth transistor T8 to turn off. The low-level signal on the low-level signal line VGL is output through the seventh transistor T7, thereby outputting the second pulse signal Nscan(n) as a low-level pulse. For details, please refer to Figure 7 , Figure 7 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0073] In the second phase (also known as the P output phase or the N output phase), the previous-stage first pulse signal Pscan(n-1) is high, the first transition signal line CK transmits a low signal, the second transition signal line XCK transmits a high signal, and the third transition signal line CK2 transmits a high signal. The second transition signal line XCK turns off the first transistor T1, and the low signal line VGL turns on the second transistor T2. The first plate of the first storage cell C1 stores a low voltage signal in the previous phase, turning on the third transistor T3 and turning off the fourth transistor T4. The first transition signal line CK transmits a low pulse signal through the third transistor T3, causing the first pulse signal Pscan(n) to be output as a low pulse. Simultaneously, the third transition signal line CK2 turns off the fifth transistor T5. Simultaneously, the first transition signal line CK turns off the sixth transistor T6. The low voltage stored in the first plate of the second storage cell C2 in the previous phase is charged to the first plate of the third storage cell C3 via the sixth transistor T6, turning on the eighth transistor T8 and turning off the seventh transistor T7. The high potential signal line VGH outputs a high potential signal through the eighth transistor T8, thereby making the second pulse signal Nscan(n) output a high potential pulse. Figure 8 , Figure 8 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0074] In the third phase (also known as the N output phase or the P hold phase), the previous-stage first pulse signal Pscan(n-1) is a high-level signal. The first transition signal line CK transmits a high-level signal, the second transition signal line XCK transmits a low-level signal, and the third transition signal line CK2 transmits a high-level signal. The second transition signal line XCK controls the conduction of the first transistor T1, and the low-level signal line VGL controls the conduction of the second transistor T2. The low-level pulse signal of the previous-stage first pulse signal Pscan(n-1) is transmitted through the first and second transistors T1 and T2 to the gates of the third and fourth transistors T3 and T4, and to the first plate of the first storage cell C1 for storage. Simultaneously, the low-level pulse signal of the previous-stage first pulse signal Pscan(n-1) is turned off and the fourth transistor T4 is turned on, activating the fourth transistor T4. The high-level signal of the high-level signal line VGH is output to the output terminal of the first output cell through the fourth transistor T4, maintaining the operating output of the fourth transistor T4 in the subsequent phase. Consequently, the first pulse signal Pscan(n) maintains a high-level pulse output during the P hold phase following the second phase. The third jump signal line CK2 controls the fifth transistor T5 to be turned off, and the first jump signal line CK controls the sixth transistor T6 to be turned off. The first electrode plate of the third storage unit C3 stores a low-level signal in the previous stage, thereby controlling the eighth transistor T8 to be turned on and the seventh transistor T7 to be turned off. The high-level signal line VGH outputs a high-level signal through the eighth transistor T8, thereby making the second pulse signal Nscan(n) output a high-level pulse. For details, please refer to Figure 9 , Figure 9 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0075] In the fourth stage (also known as the P hold stage or the N hold stage), the previous stage's first pulse signal Pscan(n-1) is a high-voltage signal. The first transition signal line CK transmits a low-voltage signal, the second transition signal line XCK transmits a high-voltage signal, and the third transition signal line CK2 transmits a low-voltage signal. The second transition signal line XCK controls the first transistor T1 to be turned off, while the low-voltage signal line VGL controls the second transistor T2 to be turned on. The first plate of the first storage cell C1 stores a high-voltage voltage in the previous stage, thereby controlling the third transistor T3 to remain off and the fourth transistor T4 to remain on. The high-voltage signal on the high-voltage signal line VGH is output to the output terminal of the first output unit through the fourth transistor T4, maintaining the operating output of the fourth transistor T4 in subsequent stages. As a result, the first pulse signal Pscan(n) maintains a high-voltage pulse output during the P hold stage following the second stage. The third jump signal line CK2 controls the conduction of the fifth transistor T5, and the first jump signal line CK controls the conduction of the sixth transistor T6. In the N hold phase, the high potential voltage stored on the first plate of the first storage unit C1 in the previous phase is transmitted to the first plate of the second storage unit C2 through the fifth transistor T5 and stored, and then transmitted to the first plate of the third storage unit C3 through the sixth transistor T6 and stored. At the same time, the seventh transistor T7 is controlled to be turned on and the eighth transistor T8 is turned off. The low potential signal line VGL is output to the output end of the second output unit through the seventh transistor T7, thereby outputting the second pulse signal Nscan(n) as a low potential pulse. In the subsequent phase, the seventh transistor T7 is kept working, which also keeps the second pulse signal Nscan(n) output as a low potential pulse. For details, please refer to Figure 10 , Figure 10 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0076] In the fifth stage (also known as the P hold stage or the N hold stage), the previous stage's first pulse signal Pscan(n-1) is a high-voltage signal. The first transition signal line CK transmits a high-voltage signal, the second transition signal line XCK transmits a low-voltage signal, and the third transition signal line CK2 transmits a high-voltage signal. The second transition signal line XCK controls the conduction of the first transistor T1, and the low-voltage signal line VGL controls the conduction of the second transistor T2. The low-voltage pulse signal of the previous stage's first pulse signal Pscan(n-1) is transmitted through the first and second transistors T1 and T2 to the gates of the third and fourth transistors T3 and T4, and to the first plate of the first storage cell C1 for storage. Simultaneously, the third transistor T3 is turned off and the fourth transistor T4 is turned on, activating the fourth transistor T4. The high-voltage signal of the high-voltage signal line VGH is output to the output terminal of the first output unit through the fourth transistor T4, maintaining the operating output of the fourth transistor T4 in subsequent stages. Consequently, the first pulse signal Pscan(n) maintains a high-voltage pulse output during the P hold stage following the second stage. The third jump signal line CK2 controls the fifth transistor T5 to be turned off, and the first jump signal line CK controls the sixth transistor T6 to be turned off. In the N holding phase, the first electrode plate of the third storage unit C3 stores a high-voltage signal in the previous phase, thereby controlling the seventh transistor T7 to be turned on and the eighth transistor T8 to be turned off. The low-voltage signal line VGL is output to the output end of the second output unit through the seventh transistor T7, thereby making the second pulse signal Nscan(n) output a low-voltage pulse. In the subsequent phase, the seventh transistor T7 is kept working, which also keeps the second pulse signal Nscan(n) output as a low-voltage pulse. For details, please refer to Figure 11 , Figure 11 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0077] The sampling phase is the first phase, the P output phase includes the second phase, the N output phase includes the second and third phases, the P hold phase includes at least the third through fifth phases, and the N hold phase includes at least the fourth and fifth phases. It should be noted that the P hold phase is the phase following the third phase (including the third, fourth, and fifth phases), and the N hold phase is the phase following the fourth phase (including the fourth and fifth phases). The timing diagrams for the subsequent sixth and seventh phases refer to the timing diagrams for the fourth and fifth phases and are not intended to be limiting here.

[0078] The N output stage is controlled by the width of the high-potential pulse signal output by the third jump signal line CK2.

[0079] This application also provides a display panel. Figure 12 , Figure 12This is a schematic diagram of the structure of an embodiment of a display panel provided by this application. Figure 12 As shown, the display panel 100 includes a display area 101 and a non-display area 102. The non-display area 102 on one side or opposite sides of the display panel 100 is provided with a gate drive circuit as described in any of the above embodiments. The gate drive circuit includes multiple cascaded gate drive units. The gate drive circuit sequentially transmits a first scan signal and a second scan signal to each row of pixel units in the display area 101. The first scan signal is a first pulse signal Pscan(n) of a low-potential pulse with a normally high potential, and the second scan signal is a second pulse signal Nscan(n) of a high-potential pulse with a normally low potential.

[0080] Furthermore, the driving circuit in each pixel unit of the display area 101 includes an N-type transistor and a P-type transistor. By sequentially outputting the first scanning signal and the second scanning signal to the driving unit of the pixel unit, the requirement of outputting different scanning signals to different types of transistors (TFTs) in the pixel unit is met.

[0081] By designing the above-mentioned gate drive circuit, the present application enables a GOA circuit to output different scanning signals to different types of transistors (TFTs) in the pixel unit while minimizing the use of input signals, thereby saving circuit expenses and reducing the border width.

[0082] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded gate drive units, each of the gate drive units comprising at least: a cascade unit, connected to the first output unit of the gate driving unit of the previous stage, and configured to receive the first pulse signal of the previous stage; a first driving unit, connected to the cascade unit, and configured to provide a driving signal according to the cascade signal of the cascade unit; a second driving unit, connected to the cascade unit, and configured to provide a driving signal according to the cascade signal of the cascade unit; a first output unit connected to the first driving unit, and configured to output a first pulse signal according to a driving signal provided by the first driving unit; wherein the first pulse signal is a low-potential pulse signal with a normally high potential; the first output unit comprises a first sub-output unit and a first pulse output holding unit, wherein the input end of the first sub-output unit is connected to the first jump signal line, and the control end of the first sub-output unit is connected to the output end of the first driving unit, and configured to output high-potential pulses and low-potential pulses of the first pulse signal according to the driving signal provided by the first driving unit; the input end of the first pulse output holding unit is connected to the high-potential signal line, and the control end of the first pulse output holding unit is connected to the output end of the first driving unit, and configured to maintain outputting high-potential pulses of the first pulse signal according to the driving signal provided by the first driving unit; A second output unit is connected to the second driving unit and is used to output a second pulse signal according to the driving signal provided by the second driving unit; wherein the second pulse signal is a high-potential pulse signal with a normal low potential, and the high-potential pulse of the second pulse signal is triggered simultaneously with the low-potential pulse of the first pulse signal; the second output unit includes a second sub-output unit and a second pulse output holding unit; the input end of the second sub-output unit is connected to the high-potential signal line, and the control end of the second sub-output unit is connected to the output end of the second driving unit, and is used to output the high-potential pulse of the second pulse signal according to the driving signal provided by the second driving unit; the input end of the second pulse output holding unit is connected to the low-potential signal line, and the control end of the second pulse output holding unit is connected to the output end of the second driving unit, and is used to maintain the output of the low-potential pulse of the second pulse signal according to the driving signal provided by the second driving unit.

2. The gate drive circuit according to claim 1, wherein: The pulse width of the second pulse signal is greater than the pulse width of the first pulse signal.

3. The gate drive circuit according to claim 1 or 2, characterized in that: The first driving unit includes: a first storage unit, wherein a first plate of the first storage unit is connected to the output terminal of the cascade unit, the control terminal of the first sub-output unit, and the control terminal of the first pulse output holding unit, and a second plate of the first storage unit is connected to the output terminal of the first output unit, and is used to store the voltage signal charged by the cascade unit and control the operation of the first sub-output unit or the first pulse output holding unit according to the stored voltage signal; A first charging control unit is provided between the output end of the cascade unit and the first plate of the first storage unit, and is used for controlling the cascade unit to charge the voltage signal into the first storage unit.

4. The gate driving circuit according to claim 3, wherein: The control end of the first charging control unit is connected to the low-potential signal line.

5. The gate driving circuit according to claim 4, wherein: The second driving unit includes: a second storage unit, wherein a first electrode plate of the second storage unit is connected to the output end of the cascade unit and the input end of the first charging control unit, and a second electrode plate of the second storage unit is connected to the low-potential signal line, and is used to store the voltage signal charged by the cascade unit or the first storage unit; a second charging control unit, the second charging control unit being arranged between the output end of the cascade unit and / or the input end of the first charging control unit and the second storage unit, and being configured to control the cascade unit and / or the first storage unit to charge a voltage signal into the second storage unit; a third storage unit, wherein a first electrode plate of the third storage unit is connected to the first electrode plate of the second storage unit, the control terminal of the second sub-output unit, and the control terminal of the second pulse output holding unit, and a second electrode plate of the third storage unit is connected to the high-potential signal line, and is used to store the voltage signal charged in the second storage unit and control the second sub-output unit or the second pulse output holding unit to operate according to the stored voltage signal; A third charging control unit is arranged between the first plate of the second storage unit and the first plate of the third storage unit, the control end of the second sub-output unit, and the control end of the second pulse output holding unit, and is used to control the second storage unit to charge the voltage signal into the first plate of the third storage unit.

6. The gate driving circuit according to claim 5, wherein: The control end of the cascade unit is connected to the second jump signal line; The signal hopping frequency of the second hopping signal line is the same as that of the first hopping signal line, but the phase is opposite.

7. The gate driving circuit according to claim 6, wherein: The control terminal of the second charging control unit is connected to the third jump signal line; Wherein, the high potential signal pulse width on the third jump signal line is greater than the low potential signal pulse width on the first jump signal line or the high potential signal pulse width on the second jump signal line; The high-potential signal pulse width on the third jump signal line is the same as the high-potential pulse width of the second pulse signal.

8. The gate driving circuit according to claim 7, wherein: The control end of the third charging control unit is connected to the first jump signal line.

9. A display panel, characterized in that: The display panel includes the gate driving circuit according to any one of claims 1 to 8.

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