Dynamic random access memory device and method thereof

Abstract

The invention provides a dynamic random access memory device and a method thereof. The dynamic random access memory device includes a first physical memory region corresponding to a first memory pad, a second physical memory region corresponding to a second memory pad, a bit line pair, a switch pair, and a sense amplifier. The first physical memory region and the second physical memory region include memory cells of the first memory bank and memory cells of the second memory bank, which are alternately arranged. A sense amplifier of the first storage bank is electrically connected to a first bank bit line pair in a first physical memory region and a second physical memory region during a first row cycle time period. The sense amplifier is configured to perform memory operations on memory cells connected to the first bank line pair during a first row cycle time period.

Description

Technical Field

[0001] The present disclosure relates to a memory device, and more particularly to a dynamic random-access memory (DRAM) device with a small occupied area and a method thereof. Background Art

[0002] Dynamic random access memory devices are widely used in many electronic devices to store data. DRAM devices can be manufactured using wafer dies. To save manufacturing costs, it is desirable to increase the number of DRAM devices per wafer die. Conventional DRAM devices include a plurality of sense amplifiers, each of which is coupled to a pair of bit lines of the DRAM device. However, the sense amplifiers occupy a large portion of the area of ​​the DRAM device on the wafer die. Therefore, it is desirable to develop a DRAM device architecture that can reduce the area of ​​the sense amplifiers, so as to reduce the area occupied by the DRAM device and improve the competitiveness of the wafer die. Summary of the invention

[0003] In some embodiments of the present disclosure, a dynamic random access memory device includes a first physical memory area corresponding to a first memory mat and a second physical memory area corresponding to a second memory mat. Each of the first physical memory area and the second physical memory area includes a plurality of memory cells, wherein the memory cells include memory cells of a first memory bank and memory cells of a second memory bank. The memory cells of the first memory bank and the memory cells of the second memory bank are alternately arranged in each of the first physical memory area and the second physical memory area. The bit line pair includes a first bank bit line pair and a second bank bit line pair, the first bank bit line pair is connected to the memory cells of the first memory bank in the physical memory area, and the second bank bit line pair is connected to the memory cells of the second memory bank in the physical memory area. The sense amplifier is connected to the bit line pair through a switch pair, and each sense amplifier is connected to at least two bit line pairs through at least two switch pairs. The switch pair is configured to electrically connect the sense amplifier to the first bank bit line pair in the first physical memory area and the second physical memory area during a first row cycle time period. The sense amplifier is configured to perform a memory operation on memory cells connected to the first bank bit line pair in the first physical memory region and the second physical memory region during a first row cycle time period.

[0004] In some embodiments, a dynamic random access memory device includes a plurality of memory cells, a plurality of bit line pairs, a plurality of switch pairs, and a plurality of sense amplifiers. The memory cells include a first selected memory cell and a second selected memory cell for memory operation. The bit line pairs include a first library bit line pair and a second library bit line pair, wherein the first library bit line pair is connected to the first selected memory cell, and the second library bit line pair is connected to the second selected memory cell. The switch pair includes a first library switch pair and a second library switch pair, wherein the first library switch pair is connected to the first library bit line pair and the second library switch pair is connected to the second library bit line pair. The sense amplifier is connected to the bit line pair through the switch pair, and each sense amplifier is connected to at least two bit line pairs through at least two switch pairs. The first library switch pair is configured to electrically connect the sense amplifier to the first library bit line pair, and the sense amplifier is configured to perform a memory operation on the first selected memory cell connected to the first library bit line pair during a first row cycle time period. The second library switch pair is configured to electrically connect the sense amplifier to the second library bit line pair, and the sense amplifier is configured to perform a memory operation on the second selected memory cell connected to the second library bit line pair during a second row cycle time period.

[0005] In some embodiments, a method of a dynamic random access memory device includes a first physical memory region corresponding to a first memory pad and a second physical memory region corresponding to a second memory pad, a plurality of sense amplifiers, a plurality of bit line pairs, and a plurality of switch pairs. The method includes the following steps: selecting a plurality of memory cells for memory operation, wherein the memory cells include memory cells of a first memory bank and memory cells of a second memory bank, and the memory cells of the first memory bank and the memory cells of the second memory bank are alternately arranged in each of the first physical memory region and the second physical memory region; controlling the switch pair of the first memory bank to electrically connect the sense amplifier to the first bit line pair in the first physical memory region and the second physical memory region during a first row cycle time period; and performing memory operation on the memory cells connected to the first bit line pair in the first physical memory region and the second physical memory region during the first row cycle time period.

[0006] In summary, each sense amplifier of the DRAM device is connected to at least two bit line pairs through at least two switch pairs. During the first row cycle time period of the DRAM device, the switch pair is configured to electrically connect each sense amplifier to one bit line pair among the at least two bit line pairs. During the second row cycle time period of the DRAM device, the switch pair is configured to electrically connect each sense amplifier to another bit line pair among the at least two bit line pairs. In this way, the number of sense amplifiers in the DRAM device is reduced, and the DRAM device has a small footprint. In addition, the sense amplifier and switch pair of the DRAM device can be operated in conjunction with the bank group concept. In the bank group concept, the memory banks of the DRAM device are grouped into bank groups. In the same bank group, the same physical memory area may include memory cells of different banks arranged alternately, and the rows of memory cells in the physical memory area are connected to shared word lines. When the bank group concept is used to perform a memory operation on a selected memory cell, the memory operation can be performed on all selected memory cells within one row cycle time period of the DRAM device. In this way, the DRAM device can have a reduced footprint without degrading the processing time of the memory operation.

[0007] In order to make the features and advantages provided in one or more embodiments of the present disclosure more easily understood, several embodiments attached with the drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a DRAM device according to some embodiments;

[0009] Figure 2 is a schematic diagram of a DRAM device including a physical memory region corresponding to a memory pad according to some embodiments;

[0010] Figure 3 is a schematic diagram of a bank group concept of a DRAM device according to some embodiments;

[0011] FIG. 4A to FIG. 4C is a schematic diagram of a DRAM device having a bank group concept according to some embodiments;

[0012] Figure 5 is a timing diagram for accessing a memory bank in a DRAM device according to some embodiments;

[0013] Figure 6 is a flow chart of a method applicable to a DRAM device according to some embodiments.

[0014] Description of Figure Numbers

[0015] 100, 200, 300: DRAM devices;

[0016] 110, BANK0, BANK1, BANK2, BANK3, BANK4, BANK5, BANK6, BANK7, BANK8, BANK9, BANK10, BANK11, BANK12, BANK13, BANK14, BANK15: storage repository;

[0017] 111_1, 111_2, 121_1, 121_2: sense amplifiers;

[0018] 113, 115: storage pads;

[0019] 213, 413, 423: physical memory area;

[0020] 301: Library Group / Group;

[0021] 302, 303, 304: library groups;

[0022] 610, 620, 630: blocks;

[0023] 2131, 2133: area;

[0024] BANK0_MAT0_BL0, BANK0_MAT0_BL1, BANK0_MAT0_BL2, BANK0_MAT0_BL3, BANK0_MAT0_BL4, BANK0_MAT0_BL5, BANK0_MAT0_BL6, BANK0_MAT0_BL7, BANK1_MAT0_ BL0, BANK1_MAT0_BL1, BANK1_MAT0_BL2, BANK1_MAT0_BL3, BANK1_MAT0_BL4, BANK1_MAT0_BL5, BANK1_MAT0_BL6, BANK1_MAT0_BL7, BLT0, BLT1, BLT2, BLT3: bit lines;

[0025] BANK0_MAT0_BLB0, BANK0_MAT0_BLB2, BANK0_MAT0_BLB4, BANK0_MAT0_BLB6, BANK1_MAT0_BLB0, BANK1_MAT0_BLB2, BANK1_MAT0_BLB4, BANK1_MAT0_BLB6, BLB0, BLB1, BLB2, BLB3: inverted bit lines;

[0026] BANK0 / 1_MAT0_WL0, BANK0 / 1_MAT0_WL1, BANK0 / 1_MAT0_WL2, BANK0 / 1_MAT0_WL3: shared word lines;

[0027] BANK_SEL0, BANK_SEL1: bank selection signal / selection signal;

[0028] BANK_SEL2, BANK_SEL3, BANK_SEL4, BANK_SEL5, BANK_SEL6, BANK_SEL7, BANK_SEL8, BANK_SEL9, BANK_SEL10, BANK_SEL11, BANK_SEL12, BANK_SEL13, BANK_SEL14, BANK_SEL15: bank selection signal;

[0029] MC: storage unit;

[0030] SW00, SW00', SW01, SW01', SW10, SW10', SW11, SW11', SW20, SW20', SW21, SW21', SW30, SW30', SW31, SW31': switch;

[0031] t1, t2, t3, t4, t5: time;

[0032] tRC: First row cycle time period / second row cycle time period / row cycle time period. DETAILED DESCRIPTION

[0033] refer to Figure 1 , the DRAM device 100 includes a memory bank 110, wherein the memory bank 110 may include a plurality of sense amplifiers 111_1 and 111_2, a plurality of bit line pairs (BLT0, BLB0) to (BLT3, BLB3), a plurality of switch pairs (SW00, SW01) to (SW30, SW31), and a plurality of memory pads 113 and 115. Each of the memory pads 113 and 115 of the memory bank 110 may include a plurality of memory cells arranged in rows and columns. The memory cells of the memory pad 113 are electrically connected to the bit lines BLT0 to BLT3, and the memory cells of the memory pad 115 are electrically connected to the inverted bit lines BLB0 to BLB3. Each of the memory pads 113 and 115 of the memory bank 110 may correspond to a physical memory area (not shown). Each bit line pair is formed by one bit line among the bit lines BLT0 to BLT3 and one inverted bit line among the inverted bit lines BLB0 to BLB3. For example, the bit line pair (BLT0, BLB0) includes bit line BLT0 and inverted bit line BLB0, the bit line pair (BLT1, BLB1) includes bit line BLT1 and inverted bit line BLB1, the bit line pair (BLT2, BLB2) includes bit line BLT2 and inverted bit line BLB2, and the bit line pair (BLT3, BLB3) includes bit line BLT3 and inverted bit line BLB3.

[0034] Each of the switch pairs (SW00, SW01) to (SW30, SW31) is controlled by one of the bank selection signals BANK_SEL0 and BANK_SEL1. For example, the switch pairs (SW00, SW01), (SW20, SW21) are controlled by the bank selection signal BANK_SEL0, and the switch pairs (SW10, SW11), (SW30, SW31) are controlled by the bank selection signal BANK_SEL1. In some embodiments, each switch pair corresponds to one of the bit line pairs. For example, the switch pair (SW00, SW01) corresponds to the bit line pair (BLT0, BLB0), and the switch pair (SW30, SW31) corresponds to the bit line pair (BLT3, BLB3).

[0035] Each of the sense amplifiers 111_1 and 111_2 is connected to the at least two bit line pairs through at least two switch pairs corresponding to the at least two bit line pairs. For example, the sense amplifier 111_1 is connected to the bit line pairs (BLT0, BLB0) and (BLT1, BLB1) through the switch pairs (SW00, SW01) and (SW10, SW11); and the sense amplifier 111_2 is connected to the bit line pairs (BLT2, BLB2) and (BLT3, BLB3) through the switch pairs (SW20, SW21) and (SW30, SW31).

[0036] The switch pair is configured to control the electrical connection between the sense amplifiers 111_1 and 111_2 and the bit line pair based on the bank selection signals BANK_SEL0 and BANK_SEL1. When the selection signal BANK_SEL0 is asserted to the memory bank 110, the sense amplifiers 111_1 and 111_2 are electrically connected to the bit line pairs (BLT0, BLB0) and (BLT2, BLB2). Therefore, the sense amplifiers 111_1 and 111_2 can perform memory operations (i.e., active-read / write-precharge (ACTIVE-RD / WT-PRECHARGE) operations) on the memory cells connected to the bit line pairs (BLT0, BLB0) and (BLT2, BLB2). The ACTIVE-RD / WT-PRECHARGE operations may include row activation operations, read or write operations, and precharge operations, which can be performed within a single row cycle time period (tRC) of the DRAM device. When the bank selection signal BANK_SEL1 is asserted to the memory bank 110, the sense amplifiers 111_1 and 111_2 are electrically connected to the bit line pairs (BLT1, BLB1) and (BLT3, BLB3). Therefore, the sense amplifiers 111_1 and 111_2 can perform memory operations on the memory cells connected to the bit line pairs (BLT1, BLB1) and (BLT3, BLB3). In some embodiments, the time interval when the bank selection signal BANK_SEL0 is asserted to the memory bank 110 does not overlap with the time interval when the bank selection signal BANK_SEL1 is asserted to the memory bank 110. For example, the bank selection signal BANK_SEL0 is asserted to the DRAM device in the first row cycle time period, and the bank selection signal BANK_SEL1 is asserted to the DRAM device in the second row cycle time period after the first row cycle time period. Since the switch pair can selectively select the bit line pair to be connected to the sense amplifier, the number of sense amplifiers required in the DRAM device is reduced, and the occupied area of ​​the DRAM device in the chip die is correspondingly reduced. The number of the plurality of sense amplifiers may be less than the number of the plurality of bit line pairs.

[0037] Figure 2 The DRAM device 200 includes a physical memory area 213 corresponding to a memory pad, a plurality of sense amplifiers 111_1, 111_2, a plurality of bit line pairs (BANK0_MAT0_BL0, BANK0_MAT0_BLB0) to (BANK1_MAT0_BL2, BANK1_MAT0_BLB2), and a plurality of switch pairs (SW00, SW01) to (SW30, SW31). Figure 2The sense amplifiers 111_1, 111_2, the bit line pairs (BANK0_MAT0_BL0, BANK0_MAT0_BLB0) to (BANK1_MAT0_BL2, BANK1_MAT0_BLB2) and the switch pairs (SW00, SW01) to (SW30, SW31) in the embodiment may be similar to those in FIG. Figure 1 The sense amplifiers 111_1, 111_2, the bit line pairs (BLT0, BLB0) to (BLT3, BLB3) and the switch pairs (SW00, SW01) to (SW30, SW31) in FIG.

[0038] The physical memory area 213 may include a plurality of memory cells MC. The memory cells MC in the physical memory area 213 may include memory cells of different memory banks. For example, the DRAM device 200 may include memory banks BANK0 and BANK1, and the memory cells MC in the physical memory area 213 include some memory cells of the memory bank BANK0 and some memory cells of the memory bank BANK1. The memory cells of the memory bank BANK0 and the memory cells of the memory bank BANK1 may be alternately arranged in the physical memory area 213. For example, the memory cells MC in the area 2131 of the physical memory area 213 are memory cells of the memory bank BANK0, and the memory cells MC in the area 2133 of the physical memory area 213 are memory cells of the memory bank BANK1.

[0039] The memory cells MC in the physical memory area 213 may be arranged in rows and columns. The rows of the memory cells MC are electrically connected to a plurality of shared word lines BANK0 / 1_MAT0_WL0 to BANK0 / 1_MAT0_WL3, which are shared between the memory pads (i.e., the first memory pad and the second memory pad) of the memory banks of the DRAM 200. Each of the shared word lines BANK0 / 1_MAT0_WL0 to BANK0 / 1_MAT0_WL3 may be electrically connected to a row of the first memory pad and a row of the second memory pad. In some embodiments, the columns of the memory cells MC in the physical memory area 213 are electrically connected to the bit lines of the memory bank BANK0 and the bit lines of the memory bank BANK1. The bit lines of the memory bank BANK0 and the bit lines of the memory bank BANK1 are alternately arranged in the physical memory area 213. Figure 2As shown, bit lines BANK0_MAT0_BL0 and BANK0_MAT0_BL2 are bit lines of bank BANK0, and bit lines BANK0_MAT0_BL0 and BANK0_MAT0_BL2 may be referred to as first bank bit lines. Bit lines BANK1_MAT0_BL0 and BANK1_MAT0_BL2 are bit lines of bank BANK1, and bit lines BANK1_MAT0_BL0 and BANK1_MAT0_BL2 may be referred to as second bank bit lines. Similarly, inverted bit lines BANK0_MAT0_BLB0 and BANK0_MAT0_BLB2 are inverted bit lines of bank BANK0 and are also referred to as first bank inverted bit lines, and inverted bit lines BANK1_MAT0_BLB0 and BANK1_MAT0_BLB2 are inverted bit lines of bank BANK1 and are also referred to as second bank inverted bit lines. The switch pair coupled to the first bank bit line is also referred to as a first bank switch pair; and the switch pair coupled to the second bank bit line is also referred to as a second bank switch pair.

[0040] In some embodiments, the DRAM device 200 does not perform memory operations on all selected memory cells at the same time. Instead, the DRAM device 200 may perform memory operations on some portions of the selected memory cells in a first row cycle time period (tRC), and then perform memory operations on other portions of the selected memory cells in a second row cycle time period (tRC). For example, in the first row cycle time period, the bank select signal BANK_SEL0 may be asserted to the DRAM device 200 to electrically connect the sense amplifiers 111_1 and 111_2 to the bit line pairs (BANK0_MAT0_BL0, BANK0_MAT0_BLB0) and (BANK0_MAT0_BL2, BANK0_MAT0_BLB2). The sense amplifiers 111_1 and 111_2 may perform a memory operation on the selected memory cells connected to the bit line pairs (BANK0_MAT0_BL0, BANK0_MAT0_BLB0) and (BANK0_MAT0_BL2, BANK0_MAT0_BLB2) in the first row cycle time period. Next, in the second row cycle time period, the bank selection signal BANK_SEL1 may be asserted to the DRAM device 200 to electrically connect the sense amplifiers 111_1 and 111_2 to the bit line pairs (BANK1_MAT0_BL0, BANK1_MAT0_BLB0) and (BANK1_MAT0_BL2, BANK1_MAT0_BLB2). In the second row cycle time period, the sense amplifiers 111_1 and 111_2 may perform a memory operation on the selected memory cells connected to the bit line pairs (BANK1_MAT0_BL0, BANK1_MAT0_BLB0) and (BANK1_MAT0_BL2, BANK1_MAT0_BLB2). In this way, the DRAM device 200 may spend more than one row cycle time period (tRC) to perform a memory operation on all selected memory cells for the memory operation. In addition, the architecture of the DRAM device 200 reduces the number of sense amplifiers in the DRAM device 200.

[0041] Figure 3 FIG. 3 is a schematic diagram of a bank group concept in a DRAM device 300 according to some embodiments.

[0042] The DRAM device 300 may include a plurality of banks BANK0 to BANK15.

[0043] BANK15 is grouped into different bank groups 301, 302, 303 and 304. The banks BANK0 to BANK15 in the bank groups 301, 302, 303 and 304 are controlled by bank selection signals BANK_SEL0 to BANK_SEL15. The bank group 301 includes banks BANK0 to BANK3 controlled by bank selection signals BANK_SEL0 to BANK_SEL3. The bank group 302 includes banks BANK4 to BANK7 controlled by bank selection signals BANK_SEL4 to BANK_SEL7. The bank group 303 includes banks BANK8 to BANK11 controlled by bank selection signals BANK_SEL8 to BANK_SEL11. The bank group 304 includes banks BANK12 to BANK15 controlled by bank selection signals BANK_SEL12 to BANK_SEL15. It should be noted that in the present disclosure, the number of memory banks and the number of bank groups in the DRAM device 300 are not limited.

[0044] Figure 4A is a schematic diagram of a DRAM device 300 including physical memory regions 413 and 423 corresponding to first and second memory pads of a memory bank according to some embodiments. The DRAM device 300 may also include a plurality of sense amplifiers and a plurality of switch pairs corresponding to the physical memory regions 413 and 423. Figure 4A , the sense amplifiers 111_1 and 111_2 and the switch pairs (SW00, SW01), (SW10, SW11), (SW20, SW21), and (SW30, SW31) correspond to the physical memory region 413; and the sense amplifiers 121_1 and 121_2 and the switch pairs (SW00', SW01'), (SW10', SW11'), (SW20', SW21'), and (SW30', SW31') correspond to the physical memory region 423. The switch pairs (SW00, SW01), (SW10, SW11), (SW20, SW21), and (SW30, SW31) and the switch pairs (SW00', SW01'), (SW10', SW11'), (SW20', SW21'), and (SW30', SW31') are controlled by the bank selection signals BANK_SEL0 and BANK_SEL1.

[0045] Each of the physical memory areas 413 and 423 may include a plurality of memory cells of different memory banks. For example, the memory cells in each of the physical memory areas 413 and 423 may include some memory cells of the memory bank BANK0 and some memory cells of the memory bank BANK1. The memory cells of the memory bank BANK0 and the memory cells of the memory bank BANK1 may be alternately arranged in each of the physical memory areas 413 and 423. Figure 4A The arrangement of the storage cells in each of the physical memory areas 413 and 423 in Figure 2 The arrangement of the storage units in the physical memory area 213 is described below, and therefore the detailed description of the arrangement of the storage units is omitted below.

[0046] The rows of the physical memory area 413 and the rows of the physical memory area 423 are connected to the shared word lines BANK0 / 1_MAT0_WL0 to BANK0 / 1_MAT0_WL3. In other words, each of the shared word lines BANK0 / 1_MAT0_WL0 to BANK0 / 1_MAT0_WL3 is connected to one row of the physical memory area 413 and one row of the physical memory area 423. In this way, when a word line selection signal is asserted to a specific shared word line to select a memory cell for a memory operation, one row of the physical memory area 413 and one row of the physical memory area 423 are simultaneously selected for the memory operation.

[0047] The columns of each of the physical memory regions 413 and 423 are connected to the bit lines of BANK0 and BANK1. For example, the columns of the physical memory region 413 are connected to the bit lines of BANK0 (i.e., bit lines BANK0_MAT0_BL0 to BANK0_MAT0_BL3) and the bit lines of BANK1 (BANK1_MAT0_BL0 to BANK1_MAT0_BL3). The columns of the physical memory region 423 are connected to the bit lines of BANK0 (i.e., bit lines BANK0_MAT0_BL4 to BANK0_MAT0_BL7) and the bit lines of BANK1 (BANK1_MAT0_BL4 to BANK1_MAT0_BL7). The bit lines of BANK0 and the bit lines of BANK1 are alternately arranged in each of the physical memory regions 413 and 423.

[0048] The sense amplifier 111_1 is connected to the bit line pair (BANK0_MAT0_BL0, BANK0_MAT0_BLB0) and (BANK1_MAT0_BL0, BANK1_MAT0_BLB0) through the switch pair (SW00, SW01) and (SW10, SW11); and the sense amplifier 111_2 is connected to the bit line pair (BANK0_MAT0_BL2, BANK0_MAT0_BLB2) and (BANK1_MAT0_BL2, BANK1_MAT0_BLB2) through the switch pair (SW20, SW21) and (SW30, SW31). The switch pair (SW00, SW01) and (SW20, SW21) are controlled by the bank selection signal BANK_SEL0, and the switch pair (SW10, SW11) and (SW30, SW31) are controlled by the bank selection signal BANK_SEL1. The sense amplifier 121_1 is connected to the bit line pairs (BANK1_MAT0_BL4, BANK1_MAT0_BLB4) and (BANK0_MAT0_BL4, BANK0_MAT0_BLB4) through the switch pairs (SW00', SW01') and (SW10', SW11'); and the sense amplifier 121_2 is connected to the bit line pairs (BANK1_MAT0_BL6, BANK1_MAT0_BLB6) and (BANK0_MAT0_BL6, BANK0_MAT0_BLB6) through the switch pairs (SW20', SW21') and (SW30', SW31'). The switch pairs (SW00', SW01') and (SW20', SW21') are controlled by the bank selection signal BANK_SEL1, and the switch pairs (SW10', SW11') and (SW30', SW31') are controlled by the bank selection signal BANK_SEL0.

[0049] In the operation of the DRAM device 300, when the selection signal BANK_SEL0 is asserted to the physical memory areas 413 and 423 of the memory bank, the switch pairs (SW00, SW01), (SW20, SW21), (SW10', SW11'), (SW30', SW31') are turned on and the switch pairs (SW10, SW11), (SW30, SW31), (SW00', SW01'), (SW20', SW21') are turned off. Figure 4BThe DRAM device 300 is shown when the selection signal BANK_SEL0 is asserted to the physical memory areas 413 and 423 of the bank of the DRAM device 300. The sense amplifiers 111_1 and 111_2 are electrically connected to the bit line pair (BANK0_MAT0_BL0, BANK0_MAT0_BLB0) and the bit line pair (BANK0_MAT0_BL2, BANK0_MAT0_BLB2), respectively. At the same time, the sense amplifiers 121_1 and 121_2 are electrically connected to the bit line pair (BANK0_MAT0_BL4, BANK0_MAT0_BLB4) and the bit line pair (BANK0_MAT0_BL6, BANK0_MAT0_BLB6), respectively. The sense amplifiers 111_1, 111_2, 121_1, and 121_2 may perform a memory operation on selected memory cells connected to the bit line pairs (BANK0_MAT0_BL0, BANK0_MAT0_BLB0), (BANK0_MAT0_BL2, BANK0_MAT0_BLB2), (BANK0_MAT0_BL4, BANK0_MAT0_BLB4), and (BANK0_MAT0_BL6, BANK0_MAT0_BLB6) within one row cycle time period (tRC). In other words, the DRAM device 300 may perform a memory operation (or an ACTIVE-RD / WT-PRECHARGE operation) on all selected memory cells of the memory bank within one single row cycle time period (tRC).

[0050] When the selection signal BANK_SEL1 is asserted to the physical memory areas 413 and 423 of the storage library, the switch pairs (SW10, SW11), (SW30, SW31), (SW00', SW01'), (SW20', SW21') are turned on and the switch pairs (SW00, SW01), (SW20, SW21), (SW10', SW11'), (SW30', SW31') are turned off. Figure 4CThe DRAM device 300 is shown when the selection signal BANK_SEL1 is asserted to the physical memory areas 413 and 423 of the bank of the DRAM device 300. The sense amplifiers 111_1 and 111_2 are electrically connected to the bit line pair (BANK1_MAT0_BL0, BANK1_MAT0_BLB0) and the bit line pair (BANK1_MAT0_BL2, BANK1_MAT0_BLB2). At the same time, the sense amplifiers 121_1 and 121_2 are electrically connected to the bit line pair (BANK1_MAT0_BL4, BANK1_MAT0_BLB4) and the bit line pair (BANK1_MAT0_BL6, BANK1_MAT0_BLB6). The sense amplifiers 111_1, 111_2, 121_1, and 121_2 may perform a memory operation on selected memory cells connected to the bit line pairs (BANK1_MAT0_BL0, BANK1_MAT0_BLB0), (BANK1_MAT0_BL2, BANK1_MAT0_BLB2), (BANK1_MAT0_BL4, BANK1_MAT0_BLB4), and (BANK1_MAT0_BL6, BANK1_MAT0_BLB6) within one row cycle time period (tRC). In other words, the DRAM device 300 may perform a memory operation (or an ACTIVE-RD / WT-PRECHARGE operation) on all selected memory cells of the memory bank within one single row cycle time period (tRC).

[0051] When the memory banks of a DRAM device are grouped according to the bank group concept, the DRAM device can perform ACTIVE-RD / WT-PRECHARGE operations on all selected memory cells of the memory bank in one row cycle time period. In this way, the number of sense amplifiers in the DRAM device can be reduced without degrading the performance of the DRAM device in terms of processing time.

[0052] Figure 5 is a timing diagram for accessing memory banks of different bank groups in a DRAM device according to some embodiments. Figure 3 and Figure 5, the DRAM device may include bank groups 301 to 304, wherein banks BANK0 to BANK3 are grouped into bank group 301, banks BANK4 to BANK7 are grouped into bank group 302, banks BANK8 to BANK11 are grouped into bank group 303, and banks BANK12 to BANK15 are grouped into bank group 304. When the banks of the DRAM device are grouped into different bank groups according to the bank group concept, the banks of the same bank group may be accessed after one row cycle time period (tRC). For example, bank BANK0 may be accessed at t1, and bank BANK1 in the same group 301 as bank BANK0 may be accessed at t4, wherein the time interval between t1 and t4 is equal to one row cycle time period (tRC). Bank BANK1 may be accessed during one row cycle time period from t4 to t5. In addition, when the banks of the DRAM device are grouped according to the bank group concept, banks of different bank groups may be directly accessed after a certain delay. In other words, memory banks of different bank groups do not need to wait for one row cycle time period (tRC) to start enabling. For example, BANK4 of bank group 302 can be accessed at t2 after a certain delay from t1, and memory bank BANK8 of bank group 303 can be accessed at t3 after a certain delay from t2. In this way, a DRAM device with a reduced number of sense amplifiers can be efficiently accessed.

[0053] Figure 6 6 is a flow chart of a method applicable to a DRAM device according to some embodiments. The DRAM device includes a first physical memory region corresponding to a first memory pad and a second physical memory region corresponding to a second memory pad, a plurality of sense amplifiers, a plurality of bit line pairs, and a plurality of switch pairs. In block 610, a plurality of memory cells are selected for a memory operation. The memory cells may include memory cells of a first memory bank and memory cells of a second memory bank, and the memory cells of the first memory bank and the memory cells of the second memory bank are alternately arranged in each of the first physical memory region and the second physical memory region. In block 620, the switch pair of the first memory bank is controlled to electrically connect the sense amplifier to the first bit line pair in the first physical memory region and the second physical memory region during a first row cycle time period. In block 630, a memory operation is performed on the memory cells connected to the first bit line pair in the first physical memory region and the second physical memory region during the first row cycle time period.

[0054] According to the above embodiments, a switch pair is used to connect a bit line pair to a sense amplifier of a DRAM device. If each sense amplifier is connected to two bit line pairs through a switch pair, the number of sense amplifiers in the DRAM device is reduced by half. Each sense amplifier can be connected to more than two bit line pairs through a switch pair to further reduce the number of sense amplifiers in the DRAM device. In this way, the number of sense amplifiers in the DRAM device is reduced, and the occupied area of ​​the DRAM device on the chip die is reduced. In addition, the storage banks of the DRAM device can be grouped into library groups according to the library group concept, and the DRAM device can perform memory operations in conjunction with the library group concept. In the library group concept, the same physical memory area may include storage cells of different libraries, and the rows of storage cells in the physical memory area are connected to shared word lines. In this way, a DRAM device with a reduced number of sense amplifiers can perform memory operations (i.e., ACTIVE-RD / WT-PRECHARGE operations) in one row cycle time period.

[0055] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover various modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A dynamic random access memory device, comprising: a first physical memory region corresponding to a first memory pad; a second physical memory area corresponding to a second memory pad, wherein each of the first physical memory area and the second physical memory area includes a plurality of storage cells, the plurality of storage cells include storage cells of a first memory bank and storage cells of a second memory bank, and the storage cells of the first memory bank and the storage cells of the second memory bank are alternately arranged in each of the first physical memory area and the second physical memory area; a plurality of bit line pairs, including a first bank bit line pair and a second bank bit line pair, the first bank bit line pair being connected to the storage cells of the first memory bank in the first physical memory area and the second physical memory area, and the second bank bit line pair being connected to the storage cells of the second memory bank in the first physical memory area and the second physical memory area; a plurality of switch pairs connected to the plurality of bit line pairs; a plurality of sense amplifiers connected to the plurality of bit line pairs through the plurality of switch pairs, each of the plurality of sense amplifiers connected to at least two bit line pairs of the plurality of bit line pairs through at least two switch pairs of the plurality of switch pairs, wherein the plurality of switch pairs are configured to electrically connect the plurality of sense amplifiers to the first bank bit line pairs in the first physical memory region and the second physical memory region during a first row cycle time period, and The plurality of sense amplifiers are configured to perform memory operations on the memory cells connected to the first bank bit line pair in the first physical memory region and the second physical memory region during the first row cycle time period.

2. The dynamic random access memory device according to claim 1, further comprising: a plurality of shared word lines, wherein the plurality of shared word lines are shared between the first physical memory region and the second physical memory region, Each of the plurality of shared word lines is configured to select a row of memory cells in the first physical memory area and a row of memory cells in the second physical memory area for the memory operation.

3. The dynamic random access memory device according to claim 1, wherein The first storage location line pairs and the second storage location line pairs in each of the first physical memory area and the second physical memory area are arranged alternately.

4. The dynamic random access memory device according to claim 1, wherein The number of the plurality of sense amplifiers is less than the number of the plurality of bit line pairs.

5. The dynamic random access memory device according to claim 1, wherein The plurality of switch pairs include a first bank switch pair and a second bank switch pair, The first bank switch pair is connected to the first bank position line pair, The second bank switch pair is connected to the second bank position line pair, The first bank switch pair is controlled by a first bank select signal, and The second bank switch pair is controlled by a second bank select signal.

6. The dynamic random access memory device according to claim 5, wherein asserting the first bank select signal to the first bank switch pair during the first row cycle time period, The second bank select signal is asserted to the second bank switch pair during a second row cycle time period.

7. The dynamic random access memory device according to claim 6, wherein The plurality of switch pairs are configured to electrically connect the plurality of sense amplifiers to the second bank line pairs in the first physical memory region and the second physical memory region during the second row cycle time period, and The plurality of sense amplifiers are configured to perform the memory operation on the memory cells connected to the second bank bit line pair in the first physical memory region and the second physical memory region during the second row cycle time period.

8. The dynamic random access memory device according to claim 7, wherein The second row cycle time period starts after the first row cycle time period has elapsed.

9. A dynamic random access memory device comprising: a plurality of memory cells, including a first selected memory cell and a second selected memory cell for memory operation; a plurality of bit line pairs, including a first bit line pair and a second bit line pair, wherein the first bit line pair is connected to the first selected storage unit, and the second bit line pair is connected to the second selected storage unit; a plurality of switch pairs, including a first bank switch pair and a second bank switch pair, wherein the first bank switch pair is connected to the first bank position line pair and the second bank switch pair is connected to the second bank position line pair; as well as a plurality of sense amplifiers connected to the plurality of bit line pairs through the plurality of switch pairs, each of the plurality of sense amplifiers connected to at least two bit line pairs of the plurality of bit line pairs through at least two switch pairs of the plurality of switch pairs, wherein the first bank switch pair is configured to electrically connect the plurality of sense amplifiers to the first bank bit line pair during a first row cycle time period, and the plurality of sense amplifiers are configured to perform the memory operation on the first selected memory cell connected to the first bank bit line pair during the first row cycle time period, and The second bank switch pair is configured to electrically connect the plurality of sense amplifiers to the second bank bit line pair during a second row cycle time period, and the plurality of sense amplifiers are configured to perform the memory operation on the second selected memory cell connected to the second bank bit line pair during the second row cycle time period. 10 . The DRAM device of claim 9 , wherein the number of the plurality of sense amplifiers is less than the number of the plurality of bit line pairs.

11. The dynamic random access memory device according to claim 9, wherein The first bank switch pair is controlled by a first bank selection signal, The second bank switch pair is controlled by a second bank select signal, and After asserting the first bank select signal to the first bank switch pair, asserting the second bank select signal to the second bank switch pair.

12. The dynamic random access memory device according to claim 9, wherein: When the memory banks of the dynamic random access memory device are grouped according to the bank group concept, the dynamic random access memory device directly accesses memory banks of different bank groups after a certain delay.

13. A method for a dynamic random access memory device, the dynamic random access memory device comprising a first physical memory region corresponding to a first memory pad and a second physical memory region corresponding to a second memory pad, a plurality of sense amplifiers, a plurality of bit line pairs, and a plurality of switch pairs, the method comprising: selecting a plurality of storage cells for a memory operation, wherein the plurality of storage cells include storage cells of a first memory bank and storage cells of a second memory bank, and the storage cells of the first memory bank and the storage cells of the second memory bank are alternately arranged in each of the first physical memory area and the second physical memory area; controlling a switch pair of the first memory bank among the plurality of switch pairs to electrically connect the plurality of sense amplifiers to a first bank bit line pair in the first physical memory region and the second physical memory region during a first row cycle time period; as well as The memory operation is performed on the plurality of memory cells connected to the first bin line pair in the first physical memory area and the second physical memory area during the first row cycle time period.

14. The method of claim 13, wherein the dynamic random access memory device further comprises: a plurality of shared word lines, wherein the plurality of shared word lines are shared between the first physical memory region and the second physical memory region, Each of the plurality of shared word lines is configured to select a row of memory cells in the first physical memory area and a row of memory cells in the second physical memory area for the memory operation.

15. The method according to claim 13, wherein The plurality of switch pairs include a first bank switch pair and a second bank switch pair, The first bank switch pair is connected to the first bank position line pair, The second bank switch pair is connected to the second bank position line pair, The first bank switch pair is controlled by a first bank select signal, and The second bank switch pair is controlled by a second bank select signal.

16. The method according to claim 15, wherein The first bank select signal is asserted to the first bank switch pair during the first row cycle time period.

17. The method according to claim 15, further comprising: asserting the second bank select signal to the second bank switch pair during a second row cycle time period; electrically connecting the plurality of sense amplifiers to the second bank bit line pairs in the first physical memory region and the second physical memory region during the second row cycle time period; as well as The memory operation is performed on the memory cells connected to the second bin line pair in the first physical memory area and the second physical memory area during the second row cycle time period.

Images