Storage module, storage array, storage device and in-storage calculation programming method

Abstract

The invention relates to a memory module, a memory array, a memory device and an in-memory computing programming method. The storage module comprises a storage unit and an in-storage calculation unit. The memory cell connects the word line, the bit line, and the source line, and is configured to perform data programming, data reading, or data deletion based on the word line, the bit line, and the source line in a memory mode. The in-memory calculation unit is connected with the storage unit, is used for connecting the timing word line, the calculation word line and the calculation source line, and is configured as follows: in the first stage of the in-memory calculation mode, the storage data of the storage unit is obtained based on the bit line and the timing word line; and, in a second stage of the in-memory calculation mode, performing in-memory calculation based on the calculation word line and the calculation source line. The method not only has the advantages of non-volatility, high switch ratio, extremely low turn-on current and capability of eliminating a direct-current path and compensating mismatch of a discharge transistor in the calculation process, but also can effectively improve the parallelism, linearity and energy efficiency of in-memory calculation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor storage and computing, and in particular to a storage module, a storage array, a storage device, and an in-memory computing programming method. Background Art

[0002] Compute-in-Memory (CIM) is a new technology that breaks through the traditional computing architecture. Its core idea is to process data directly inside the storage module, rather than the traditional computing model of moving data from storage (memory) to the processor (CPU / GPU) for calculation. This technology can greatly improve computing efficiency and energy efficiency by eliminating the "storage wall" (i.e. the delay and energy consumption caused by data movement), and is particularly suitable for scenarios that require processing massive amounts of data (such as artificial intelligence, big data analysis, etc.). Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide a storage module, a storage array, a storage device and an in-memory computing programming method, which not only have the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC paths during the calculation process, and compensation for discharge transistor mismatch, but also can effectively improve the parallelism, linearity and energy efficiency of in-memory computing.

[0004] In order to achieve the above-mentioned purpose, in a first aspect, some embodiments of the present disclosure provide a storage module, including a storage unit and an in-memory computing unit. The storage unit is used to connect word lines, bit lines and source lines, and is configured to: in a storage mode, perform data programming, data reading or data deletion based on the word lines, the bit lines and the source lines. The in-memory computing unit connects the storage unit and is used to connect the timing word lines, the computing word lines and the computing source lines, and is configured to: in the first stage of the in-memory computing mode, obtain the storage data of the storage unit based on the bit lines and the timing word lines; and, in the second stage of the in-memory computing mode, perform in-memory computing based on the computing word lines and the computing source lines.

[0005] In some embodiments of the present disclosure, the storage unit includes: a first transistor and a resistive memory, wherein the gate of the first transistor is connected to the word line, the first electrode of the first transistor is connected to the source line, the second electrode of the first transistor is connected to the first end of the resistive memory, and the second end of the resistive memory is connected to the bit line.

[0006] In some embodiments of the present disclosure, the in-memory computing unit includes: a second transistor, a third transistor, a capacitor, and a fourth transistor. The gate of the second transistor is connected to the timing word line; the first electrode of the second transistor is connected to the storage unit; the second electrode of the second transistor, the gate of the third transistor, and the first electrode of the capacitor are connected as a recovery node; the first electrode of the third transistor and the second electrode of the capacitor are connected and connected to the ground voltage terminal; the second electrode of the third transistor is connected to the first electrode of the fourth transistor; the gate of the fourth transistor is connected to the computing word line, and the second electrode of the fourth transistor is connected to the computing source line.

[0007] In a second aspect, some embodiments of the present disclosure further provide a storage array, comprising a plurality of storage units arranged in an array. The storage unit comprises a plurality of storage modules as described in any of the above embodiments and arranged in a row along a first direction. Wherein, the recovery nodes of each storage module in each storage unit are connected to each other and to a shared capacitor, and the shared capacitor is configured to: in an in-memory computing mode, obtain storage data corresponding to a target storage module in the storage unit in response to an in-memory computing control instruction.

[0008] In some embodiments of the present disclosure, the storage units are arranged in a row along a second direction, and the second direction intersects with the first direction; wherein at least one column of the storage units is a virtual column storage unit; and each of the storage modules in the virtual column storage unit stores calibration pre-stored data.

[0009] In a third aspect, some embodiments of the present disclosure further provide a storage device, comprising: a storage array, a read-write control circuit, and an in-memory calculation control circuit as described in any of the above embodiments. The read-write control circuit is connected to each of the storage units in the storage array through a bit line driving circuit, a word line driving circuit, and a source line driving circuit, and is configured to: in a storage mode, send storage control instructions to the bit line driving circuit, the word line driving circuit, and the source line driving circuit respectively to select the target storage module to perform data programming, data reading, or data deletion. The in-memory calculation control circuit is connected to each of the storage units in the storage array through a timing word line driving circuit, a calculation word line pulse generation and driving circuit, and a calculation source line processing circuit, and is configured to: in the first stage of the in-memory calculation mode, send a first in-memory calculation control instruction to the timing word line driving circuit to obtain the storage data of multiple target storage modules; and, in the second stage of the in-memory calculation mode, send a second in-memory calculation control instruction to the calculation word line pulse generation and driving circuit and the calculation source line processing circuit to perform in-memory calculation on the storage data of multiple target storage modules.

[0010] In some embodiments of the present disclosure, the storage device further includes a delay circuit connected to the bit line driving circuit and the timing word line driving circuit, and configured to: control the charging time of the shared capacitor in the in-memory calculation mode.

[0011] In some embodiments of the present disclosure, the storage device further includes a calculation post-processing circuit connected to the calculation source line processing circuit and configured to: in the in-memory calculation mode, post-process the operation structure of the in-memory calculation and output the post-processing result.

[0012] In a fourth aspect, some embodiments of the present disclosure further provide an in-memory computing programming method, which is applied to the storage device described in any of the above embodiments. The programming method includes:

[0013] Selecting a plurality of target memory modules in a first target row from the memory array as a group to be programmed;

[0014] In a storage mode, performing a first data programming on each of the target storage modules in the to-be-programmed group through the bit line driving circuit, the word line driving circuit and the source line driving circuit;

[0015] In the first stage of the in-memory calculation mode, the storage data of each target storage module in the to-be-programmed group is restored to the corresponding shared capacitor through the bit line driving circuit and the timing word line driving circuit;

[0016] In the second stage of the in-memory computing mode, the discharge of the shared capacitor is controlled by the computing word line pulse generation and driving circuit and the computing source line processing circuit, and whether the discharge current of the shared capacitor meets a preset condition is detected;

[0017] Wherein, in response to the discharge current of the shared capacitor satisfying the preset condition, a plurality of the target memory modules in the second target row are selected from the memory array as a group to be programmed;

[0018] In response to the discharge current of the shared capacitor not satisfying the preset condition, data programming is performed a second time on each of the target storage modules in the group to be programmed in the storage mode, and in the in-memory calculation mode, the storage data of each of the target storage modules in the group to be programmed is restored to the corresponding shared capacitor to detect again whether the discharge current of the shared capacitor satisfies the preset condition.

[0019] In some embodiments of the present disclosure, a programming accuracy of the second data programming is higher than a programming accuracy of the first data programming.

[0020] The embodiments of the present disclosure may or at least have the following advantages:

[0021] In the disclosed embodiment, the storage module includes a storage unit and an in-memory computing unit, and the storage unit is configured to connect the word line, the bit line and the source line, so as to perform data programming, data reading or data deletion based on the word line, the bit line and the source line in the storage mode, and the in-memory computing unit is configured to connect the storage unit, the timing word line, the computing word line and the computing source line, so as to obtain the storage data of the storage unit based on the bit line and the timing word line in the first stage of the in-memory computing mode, and perform in-memory computing based on the computing word line and the computing source line in the second stage of the in-memory computing mode. The disclosed embodiment is easy to decouple the working path of the storage module in the storage mode and the in-memory computing mode, so as to facilitate the effective improvement of the parallelism, linearity and energy efficiency of the in-memory computing while ensuring that the storage module has the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC path during the computing process and compensation of discharge transistor mismatch.

[0022] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 Schematic diagram of some in-memory computing circuits provided in some embodiments;

[0025] Figure 2 is a structural block diagram of a storage module provided in some embodiments;

[0026] Figure 3 is a schematic diagram of an equivalent circuit of a storage module provided in some embodiments;

[0027] Figure 4 A schematic diagram of the working principle of a storage module in a storage mode provided in some embodiments;

[0028] Figure 5 A schematic diagram of the working principle of a storage module in the first stage of the in-memory computing mode provided in some embodiments;

[0029] Figure 6 A waveform diagram of voltage change of a storage module in the first stage of an in-memory computing mode provided in some embodiments;

[0030] Figure 7 A schematic diagram of the working principle of a storage module in the second stage of the in-memory computing mode provided in some embodiments;

[0031] Figure 8 A waveform diagram of current change of a storage module in the second stage of an in-memory computing mode provided in some embodiments;

[0032] Fig. 9 A structural block diagram of a storage array provided in some embodiments;

[0033] Fig.10 is a structural block diagram of a storage device provided in some embodiments;

[0034] Fig.11 A schematic diagram of the working principle of a storage device in a storage mode provided in some embodiments;

[0035] Fig.12 A schematic diagram of the working principle of a storage device in the first stage of an in-memory computing mode provided in some embodiments;

[0036] Fig.13 A schematic diagram of the working principle of a storage device in the second stage of the in-memory computing mode provided in some embodiments;

[0037] Fig.14 A flowchart of an in-memory computing programming method provided in some embodiments.

[0038] Description of reference numerals:

[0039] HRC-storage module, 1-storage unit, 2-in-memory computing unit, WL-word line, BL-bit line, SL-source line, TWL-timing word line, CWL-computation word line, CSL-computation source line, N0-first transistor, R-resistive random access memory, N1-second transistor, N2-third transistor, N3-fourth transistor, C-capacitor, 3-read and write control circuit, 31-bit line drive circuit, 32-word line drive circuit and source line drive circuit, 33-delay circuit, 4-in-memory computing control circuit, 41-timing word line drive circuit, 42-computation word line pulse generation and drive circuit, 43-computation source line processing circuit, 44-computation post-processing circuit. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0042] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0043] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0044] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Non-volatile memory includes, for example, flash memory (FLASH), resistive random access memory (RRAM), and phase-change random access memory (PCRAM). Volatile memory includes, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). Non-volatile compute-in-memory (NvCIM) refers to in-memory computing based on non-volatile memory. Compared with in-memory computing based on volatile memory, NvCIM can retain data during power outages, which can effectively reduce the power consumption required for data backup and data recovery.

[0046] Currently, among the emerging non-volatile memories, RRAM has attracted widespread attention due to its advantages of multi-bit storage, high scalability, low power consumption, and compatibility with advanced CMOS processes.

[0047] For example, in an existing RRAM-based non-volatile in-memory computing (NvCIM) method, please combine Figure 1 As shown in Figure (a), the read current can be accumulated in the storage array according to Kirchhoff's law and read through the analog-to-digital converter (ADC). However, this method faces multiple challenges as follows: 1) During the calculation process, there is a direct current (DC) path in the RRAM and the read circuit, which has significant energy consumption and can easily weaken the energy efficiency advantage of CIM; 2) The switching ratio of RRAM is limited, and the IR-drop on the metal wire caused by the large accumulated current can easily lead to nonlinearity and reduce the calculation accuracy; 3) The peripheral circuit tends to occupy a large area and consume a large amount of power.

[0048] For example, in another existing RRAM-based non-volatile in-memory computing (NvCIM) method, please combine Figure 1 As shown in Figure (b), the basic principle is still current summation. However, the discharge of the summation current comes from the parasitic capacitance (C BL), rather than being powered directly from the power supply voltage (VDD). This way, by quantizing the voltage on the bit line to obtain the in-memory calculation results, it can provide better energy efficiency by eliminating the DC path in the calculation process, but it still has significant limitations: 1) In order to avoid read interference of RRAM, the maximum voltage on the bit line will be limited; 2) The parasitic capacitance on the bit line is not enough to achieve high parallel discharge, and it is easily further deteriorated by the limitation of the voltage swing on the bit line; 3) The discharge current flowing through RRAM is proportional to the voltage on the bit line, which inherently introduces nonlinear problems (although there are ways to alleviate such nonlinear problems, it will inevitably bring overhead in area and power consumption).

[0049] In order to solve the above problems, the applicant has found an alternative method through research, which is to use a transistor for discharge, for example Figure 1 As shown in Figure (c) in Figure 1. This method decouples RRAM from the discharge path and eliminates the risk of read disturbance. In addition, the discharge current can be controlled by the gate voltage of the transistor, so that the operation can be performed in the subthreshold region of the transistor, which can significantly reduce the discharge current. In addition, the subthreshold swing (SS) of the transistor can be used to enhance the switching ratio of the cell. Furthermore, based on the characteristics of the transistor when it operates in the saturation region, the voltage drop on the bit line has little effect on the discharge current. However, transistor mismatch caused by process fluctuations may have an adverse effect on the accuracy of in-memory calculations, especially when the transistor operates in the subthreshold region. Among them, for memory cells composed of SRAM and DRAM, the voltage of its storage node (denoted as "Q") can be directly applied to the gate terminal of the discharge transistor; however, in addition to the volatility feature, the significant limitation of these designs is that there is no way to eliminate the impact of transistor mismatch. However, for memory cells composed of non-volatile memory, such as RRAM, information is stored in the form of resistance, and the information needs to be converted into voltage form first, so that a read voltage is applied to the memory cell, which can then be divided by the transistor and RRAM to establish a stable Q point voltage. A significant disadvantage of this approach is the lack of a dielectric to retain the Q-point voltage, so once the read voltage across the memory cell is removed, the established Q-point voltage is lost; therefore, a DC path is still required for the bit line capacitance to discharge through the transistor, which weakens the energy efficiency advantage of this approach, but this approach can take advantage of the non-volatility and multi-bit storage capabilities of RRAM, allowing the RRAM to be fine-tuned to compensate for the mismatch of the discharge transistor.

[0050] Based on this, the embodiments of the present disclosure provide a storage module, a storage array, a storage device and an in-memory computing programming method, which not only have the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC paths during the calculation process, and compensation for discharge transistor mismatch, but also can effectively improve the parallelism, linearity and energy efficiency of in-memory computing.

[0051] See also Figure 2 Some embodiments of the present disclosure provide a storage module HRC, including a storage unit 1 and an in-memory computing unit 2.

[0052] The memory cell 1 is used to connect the word line WL, the bit line BL and the source line SL, and is configured to perform data programming, data reading or data deletion based on the word line WL, the bit line BL and the source line SL in a storage mode.

[0053] The in-memory computing unit 2 is connected to the storage unit 1 and is used to connect the timing word line TWL, the computing word line CWL, and the computing source line CSL, and is configured to: in the first stage of the in-memory computing mode, obtain the storage data of the storage unit 1 based on the bit line BL and the timing word line TWL; and, in the second stage of the in-memory computing mode, perform in-memory computing based on the computing word line CWL and the computing source line CSL.

[0054] For example, the in-memory computation includes but is not limited to a multiply-accumulate operation (MAC).

[0055] See also Figure 3 In some embodiments of the present disclosure, the storage unit 1 includes: a first transistor N0 and a resistive memory R (for example Figure 3 1T1R part in the figure). The gate of the first transistor N0 is connected to the word line WL. The first electrode of the first transistor N0 is connected to the source line SL. The second electrode of the first transistor N0 is connected to the first end of the resistive memory R. The second end of the resistive memory R is connected to the bit line BL.

[0056] Please continue reading Figure 3 In some embodiments of the present disclosure, the in-memory computing unit 2 includes: a second transistor N1, a third transistor N2, a capacitor C (e.g. Figure 3 2T1C part) and the fourth transistor N3 (e.g. Figure 3 The discharge control part in the embodiment of the present invention). The gate of the second transistor N1 is connected to the timing word line TWL. The first electrode of the second transistor N1 is connected to the storage unit 1, for example, the first end of the resistive memory R in the storage unit 1. The second electrode of the second transistor N1, the gate of the third transistor N2 and the first electrode of the capacitor C are connected as a recovery node Node. The first electrode of the third transistor N2 is connected to the second electrode of the capacitor C and is connected to the ground voltage terminal. The second electrode of the third transistor N2 is connected to the first electrode of the fourth transistor N3. The gate of the fourth transistor N3 is connected to the calculation word line CWL. The second electrode of the fourth transistor N3 is connected to the calculation source line CSL.

[0057] Here, combined with Figure 3It can be understood that the second transistor N1, the third transistor N2, the capacitor C and the fourth transistor N3 in the in-memory computing unit 2 can be divided into Figure 3 The 2T1C part and the discharge control part shown in FIG. 1 , wherein the second transistor N1 , the third transistor N2 and the capacitor C constitute the 2T1C part, and the fourth transistor N3 constitutes the discharge control part.

[0058] It should be added that the above storage module HRC has two working modes: storage mode and in-memory computing mode; wherein the in-memory computing mode can be divided into a first stage (eg, a recovery stage RESTORE) and a second stage (eg, a discharge stage DISCHARGE).

[0059] See also Figure 4 , in storage mode, storage unit 1 (e.g. Figure 3 The 1T1R part in the resistive memory R is activated. By driving the word line WL, the bit line BL and the source line SL, data programming (e.g., setting SET), data reading (READ) or data deletion (e.g., resetting RESET) can be performed on the resistive memory R. Here, the driving control of the word line WL, the bit line BL and the source line SL can be performed with reference to the driving of the resistive memory R in the related art, and the embodiments of the present disclosure are not limited to this.

[0060] Optionally, in the storage mode, the calculation word line CWL, the timing word line TWL and the calculation source line CSL are all connected to the ground voltage terminal.

[0061] See also Figure 5 In the first stage of the in-memory computing mode (eg, the restoration stage RESTORE), the storage data of the memory cell 1 is obtained based on the bit line BL and the timing word line TWL. Specifically, the data stored in the resistive memory R is converted into the charge on the capacitor C.

[0062] For example, the first phase of the in-memory computing mode includes three sub-phases, such as Figure 6 Sub-stage-I, sub-stage-II and sub-stage-III shown in.

[0063] In the sub-phase-I, the voltage on the timing word line TWL is pulled up to the power supply voltage VDD (eg, a high level voltage), the bit line BL is connected to the ground voltage terminal, and the residual charge on the capacitor C is cleared.

[0064] In sub-phase-II, the bit line BL is charged to a preset voltage, and the timing word line TWL is maintained at the power supply voltage VDD. The second transistor N1 is activated to turn on the resistive memory R and the capacitor C, that is, the recovery node Node is allowed to be charged through the RC path to improve efficiency based on the RC delay mechanism. At this time, the charging rate of the recovery node Node can vary significantly depending on the resistance value of the resistive memory R.

[0065] Optionally, the preset voltage is not greater than 400 mV to ensure that the third transistor N2 can operate in a subthreshold region and prevent read interference to the resistive memory R.

[0066] In sub-phase-III, the voltage on the timing word line TWL is pulled down to cut off the aforementioned RC path. At this point, the data stored in the resistive memory R has been successfully converted into the charge on the capacitor C, and the second phase of the in-memory computing mode (eg, the discharge phase DISCHARGE) can be executed in sequence.

[0067] Optionally, in the sub-phase-III, the voltage on the bit line BL is maintained at a preset voltage, which is beneficial to ensure that the voltage of the restoration node Node is maintained for a longer time.

[0068] In an example, see Figure 6 , taking the on-off ratio of the resistive memory R as N (i.e., the low resistance state (LRS) resistance of the resistive memory R is 1 / N of its high resistance state (HRS) resistance) as an example, accordingly, the voltage V of the recovery node Node when the resistive memory R is in the aforementioned low resistance state (LRS) LRS-Node and the voltage V of the restore node Node when the resistive memory R is in the aforementioned high resistance state (HRS) HRS-Node Ability to show certain differences at the end of sub-stage-III (i.e., the end of the first stage of the in-memory computing mode).

[0069] Here, the resistance ratio of the resistive memory R in the low resistance state (LRS) and the high resistance state (HRS) in the embodiment of the present disclosure is only used to illustrate: at the end of the first stage of the in-memory computing mode, the voltage of the recovery node Node can have obvious differences due to the difference in the data stored in the resistive memory R; and it does not serve as a relevant limitation on the embodiment of the present disclosure.

[0070] For some examples, see Figure 5 The computing source line CSL is also connected to a CSL pre-charging circuit, and the computing source line CSL can be charged through the CSL pre-charging circuit in the first stage of the in-memory computing mode.

[0071] In the second phase of the in-memory computing mode (e.g., the discharge phase DISCHARGE), see Figure 7, performing in-memory calculation based on the calculation word line CWL and the calculation source line CSL. Specifically, after the fourth transistor N3 is turned on by controlling the calculation word line CWL, the calculation source line CSL can be discharged through the cascade structure of the third transistor N2 and the fourth transistor N3.

[0072] In the embodiment of the present disclosure, the following three key functions can be realized based on the fourth transistor N3:

[0073] 1) The fourth transistor N3 is used as the input terminal of the in-memory calculation, allowing different pulse widths proportional to the input value to be applied to change the discharge time, thereby realizing multi-bit multiplication by one-bit calculation within a storage module HRC.

[0074] 2) By properly selecting the pulse voltage of the word line CWL, the risk of current degradation of the source line CSL during the discharge process can be minimized, thereby ensuring that the internal calculation of the storage module HRC has a high linearity. CWL = 500mV, calculate the voltage V of the source line CSL CSL The current when discharging to 0.2V is only slightly greater than the voltage V of the source line CSL. CSL The current when discharging to 0.9V is 3.5% lower.

[0075] 3) The fourth transistor N3 can shield the coupling effect from the computing source line CSL to the recovery node Node. For example, under the action of the subthreshold swing (SS) of the third transistor N2, the voltage difference on the recovery node Node (i.e., the voltage V HRS-Node and voltage V LRS-Node The difference between the two) can be converted into a discharge current difference ΔI greater than 10×N times in the second stage of the in-memory computing mode, thereby effectively amplifying the switching ratio (N) of the memory cell, for example Figure 8 as shown in .

[0076] In addition, the storage module HRC provided in the embodiment of the present disclosure can suppress the amplitude of the discharge current to less than 100nA, thereby easily realizing high parallelism of in-memory computing. Moreover, in the storage module HRC provided in the embodiment of the present disclosure, the parasitic capacitance of the computing source line CSL is sufficient to realize high parallelism discharge, and can even be accumulated in the process of activating the computing word line CWL in parallel for multiple times, thereby further improving energy efficiency.

[0077] From the above, in the disclosed embodiment, the storage module includes a storage unit 1 and an in-memory calculation unit 2, and the storage unit 1 is set to connect the word line WL, the bit line BL and the source line SL, so as to perform data programming, data reading or data deletion based on the word line WL, the bit line BL and the source line SL in the storage mode, and the in-memory calculation unit 2 is set to connect the storage unit 1, the timing word line TWL, the calculation word line CWL, and the calculation source line CSL, so as to obtain the storage data of the storage unit 1 based on the bit line BL and the timing word line TWL in the first stage of the in-memory calculation mode, and perform in-memory calculation based on the calculation word line CWL and the calculation source line CSL in the second stage of the in-memory calculation mode. The disclosed embodiment is easy to decouple the working path of the storage module HRC in the storage mode and the in-memory calculation mode, which is convenient for effectively improving the parallelism, linearity and energy efficiency of the in-memory calculation while ensuring that the storage module HRC has the advantages of non-volatility, high switching ratio, extremely low turn-on current, elimination of DC path during calculation and compensation of discharge transistor mismatch.

[0078] See also Fig. 9 Some embodiments of the present disclosure further provide a storage array, including a plurality of storage units arranged in an array. The storage unit includes a plurality of storage modules HRC as described in any of the above embodiments and arranged in a row along a first direction. The storage array also has the technical advantages of the aforementioned storage modules, which will not be elaborated here.

[0079] Optionally, a plurality of consecutive storage modules HRC in each row constitute a storage unit. Fig. 9 In the example, eight storage modules HRC constitute a storage unit, but it is not limited to this. The number of storage modules HRC in a storage unit can also take other values. However, it can be understood that in the storage mode, each storage module HRC in a storage unit stores data independently.

[0080] For example, Fig. 9 As shown in , for an m×n storage array, taking 8 storage modules HRC forming a storage unit as an example, the number of bit lines BL and calculation word lines CWL connected to each storage module HRC is m, and the number of word lines WL, timing word lines TWL, source lines SL and calculation source lines CSL connected to each storage module HRC is 8n.

[0081] In some embodiments of the present disclosure, the recovery node Node of each storage module HRC in each storage unit is connected to each other and to a shared capacitor C0, and the shared capacitor C0 is configured to: in an in-memory computing mode (for example, the first stage of the in-memory computing mode), obtain the storage data of the target storage module HRC in the corresponding storage unit in response to the in-memory computing control instruction.

[0082] Optionally, the shared capacitor C0 includes, but is not limited to, a metal-oxide-metal (MOM) capacitor.

[0083] In the disclosed embodiment, each storage module HRC in any storage unit stores data independently. Therefore, in the first stage of the in-memory computing mode, by activating the timing word line connected to the target storage module, the storage data in the target storage module can be restored to the shared capacitor C0. This is conducive to ensuring and improving the storage density of the storage array.

[0084] It is worth mentioning that in some embodiments of the present disclosure, each storage unit is arranged in a row along the second direction, and the second direction intersects the first direction. Among them, at least one row of storage units is a virtual row of storage units. Each storage module HRC in the virtual row of storage units stores calibration pre-stored data.

[0085] Here, the calibration pre-stored data is not valid data for in-memory calculation, and can be subtracted from the in-memory calculation result of the storage array to calibrate the in-memory calculation result of the storage array, thereby obtaining better linearity.

[0086] Optionally, the virtual column storage unit is located at the leftmost side of the storage array, which may be the first column from left to right, but is not limited thereto, and the virtual column storage unit may also be, for example, a middle column or a rightmost column.

[0087] Optionally, the resistive random access memory R of each storage module HRC in the virtual column storage unit is configured to be in a high resistance state (HRS), so that the leakage current in the in-memory computing mode can be effectively monitored.

[0088] See also Fig.10 Some embodiments of the present disclosure further provide a storage device, including: a storage array as described in any of the above embodiments, a read / write control circuit 3, and an in-memory computing control circuit 4. The storage device also has the technical advantages of the aforementioned storage array, which will not be described in detail here.

[0089] The read / write control circuit 3 is connected to each storage unit in the storage array through the bit line driving circuit 31, the word line driving circuit and the source line driving circuit 32, and is configured as follows: in the storage mode, storage control instructions are sent to the bit line driving circuit 31, the word line driving circuit and the source line driving circuit 32 respectively to select the target storage module to perform data programming, data reading or data deletion.

[0090] The in-memory calculation control circuit 4 connects each storage unit in the storage array through a timing word line driving circuit 41, a calculation word line pulse generation and driving circuit 42 and a calculation source line processing circuit 43, and is configured as follows: in the first stage of the in-memory calculation mode, a first in-memory calculation control instruction is sent to the timing word line driving circuit 41 to obtain storage data of multiple target storage modules; and, in the second stage of the in-memory calculation mode, a second in-memory calculation control instruction is sent to the calculation word line pulse generation and driving circuit 42 and the calculation source line processing circuit 43 to perform in-memory calculation on the storage data of multiple target storage modules.

[0091] Optionally, the word line driving circuit and the source line driving circuit 32 are integrated into an integral structure.

[0092] Optionally, the computational source line processing circuit 43 includes, but is not limited to, a circuit having a pre-charging function, a voltage comparison function, and a voltage quantization function.

[0093] Please continue reading Fig.10 In some embodiments of the present disclosure, the storage device further includes a delay circuit 33. The delay circuit 33 is connected to the bit line driving circuit 31 and the timing word line driving circuit 41, and is configured to: in the in-memory calculation mode, control the charging time of the shared capacitor C0 (that is, the charging time of the recovery node Node).

[0094] Please continue reading Fig.10 In some embodiments of the present disclosure, the storage device further includes a calculation post-processing circuit 44. The calculation post-processing circuit 44 is connected to the calculation source line processing circuit 43 and is configured to: in the in-memory calculation mode, post-process the operation structure of the in-memory calculation and output the post-processing result.

[0095] Optionally, the calculation post-processing circuit 44, as an output circuit of the storage device, can perform post-processing on the calculation result (e.g., MAC result) in the memory, such as activation, biasing, quantization to low-precision representation, etc. The embodiment of the present disclosure does not specifically limit the circuit structure of the calculation post-processing circuit 44, so long as the corresponding post-processing function can be realized.

[0096] It should be added that the above storage device has two working modes: storage mode and in-memory computing mode; wherein the in-memory computing mode can be divided into a first stage (eg, a recovery stage RESTORE) and a second stage (eg, a discharge stage DISCHARGE).

[0097] See also Fig.11In the storage mode, the read / write control circuit 3, the bit line driving circuit 31, the word line driving circuit and the source line driving circuit 32 are working, and the delay circuit 33, the in-memory calculation control circuit 4, the timing word line driving circuit 41, the calculation word line pulse generation and driving circuit 42, the calculation source line processing circuit 43 and the calculation post-processing circuit 44 are all in the off state. Accordingly, the read / write control circuit 3 can drive the corresponding bit line BL, word line WL and source line SL respectively through the bit line driving circuit 31, word line driving circuit and source line driving circuit 32 to select the target storage module from the storage array to perform data programming (SET), data reading (READ) or data deletion (RESET).

[0098] See also Fig.12 In the first stage of the in-memory calculation mode, the read / write control circuit 3, the bit line driving circuit 31, the delay circuit 33, the in-memory calculation control circuit 4 and the timing word line driving circuit 41 are working, and the word line driving circuit and the source line driving circuit 32, the calculation word line pulse generation and driving circuit 42, the calculation source line processing circuit 43 and the calculation post-processing circuit 44 are all in the off state. Accordingly, the bit line BL is activated in parallel through the bit line driving circuit 31, and a timing word line TWL in each storage unit is activated in parallel through the timing word line driving circuit 41. At the same time, the charging time of the shared capacitor C0 (that is, the charging time of the recovery node Node) is controlled by the delay circuit 33, so that the storage data of the selected target storage module in each storage unit can be restored to the shared capacitor C0.

[0099] See also Fig.13 In the second stage of the in-memory calculation mode, the in-memory calculation control circuit 4, the calculation word line pulse generation and driving circuit 42, the calculation source line processing circuit 43 and the calculation post-processing circuit 44 are working, and the read-write control circuit 3, the bit line driving circuit 31, the word line driving circuit and the source line driving circuit 32, the delay circuit 33 and the timing word line driving circuit 41 are all turned off. Accordingly, the calculation word line pulse generation and driving circuit 42 receives the input value of the in-memory calculation, activates a certain number of calculation word lines CWL in parallel, and generates a pulse signal with a pulse width proportional to the input value. The parasitic capacitance on the calculation source line CSL is discharged through the cascade structure of the third transistor N2 and the fourth transistor N3 in the corresponding target storage module, so that the corresponding voltage can be converted into a digital value through the calculation source line processing circuit 43 as the in-memory calculation result (such as MAC result). Optionally, the in-memory calculation result is output after post-processing by the calculation post-processing circuit 44.

[0100] Some embodiments of the present disclosure also provide an in-memory computing programming method, which is applied to the storage device described in any of the above embodiments. The in-memory computing programming method also has the technical advantages of the above storage device, which will not be described in detail here.

[0101] See also Fig.14 , the programming method includes the following steps S100~S600.

[0102] S100, selecting a plurality of target memory modules in a first target row from a memory array as a group to be programmed.

[0103] For example, for a storage array consisting of m×n storage units, if i is the row number and numbering starts from 0, the first target row may be the storage unit row corresponding to i=0. Accordingly, step S100 may be performed as follows: initializing the storage array so that i=0 (i.e. programming starts from row 0).

[0104] For example, when programming the i-th row of storage units, the to-be-programmed group Group is first set to be a set of storage modules HRC to be programmed in the i-th row. Moreover, there is only one storage module HRC to be programmed in each storage unit as a target storage module.

[0105] S200 , in a storage mode, performing a first data programming on each target storage module in the to-be-programmed group through a bit line driving circuit, a word line driving circuit and a source line driving circuit.

[0106] Here, the first data programming can be performed as follows: roughly adjusting the resistance value of the resistive memory R in the target storage module; the purpose is to promote faster convergence of the subsequent discharge current when it meets the preset conditions. In addition, the operation of the first data programming can be implemented in combination with the operation of the storage device in the storage mode in some of the aforementioned embodiments, which will not be described in detail here.

[0107] S300, in the first stage of the in-memory calculation mode, the storage data of each target storage module in the to-be-programmed group is restored to the corresponding shared capacitor through the bit line driving circuit and the timing word line driving circuit.

[0108] Here, the operation of restoring the data stored in each target storage module can be implemented in combination with the first stage of the work of the storage device in the in-memory computing mode in some of the aforementioned embodiments, which will not be described in detail here.

[0109] S400, in the second stage of the in-memory calculation mode, the discharge of the shared capacitor is controlled by calculating the word line pulse generation and driving circuit and the source line processing circuit, and whether the discharge current of the shared capacitor meets the preset condition is detected.

[0110] Here, the discharge operation of the shared capacitor may be implemented in combination with the second phase of the operation of the storage device in the in-memory computing mode in some of the aforementioned embodiments, which will not be described in detail here.

[0111] For example, the preset condition may be set to match the allowable error range of the discharge current.

[0112] Accordingly, the programming method further includes the following steps S500 and S600.

[0113] S500 , in response to the discharge current of the shared capacitor satisfying a preset condition, selecting a plurality of target memory blocks in a second target row from the memory array as a group to be programmed.

[0114] In other words, if the discharge current of the shared capacitor meets the preset condition, the memory cells in the i-th row are programmed successfully, and the memory cells in the (i+1)-th row can be programmed.

[0115] S600, in response to the discharge current of the shared capacitor not meeting the preset condition, in the storage mode, data programming is performed a second time on each target storage module in the programming group, and in the in-memory calculation mode, the storage data of each target storage module in the programming group is restored to the corresponding shared capacitor to detect again whether the discharge current of the shared capacitor meets the preset condition.

[0116] In other words, if the discharge current of the shared capacitor does not meet the preset condition, the storage unit of the i-th row needs to be programmed for the second time. And after the second data programming, the execution of step S300 and step S400 can be returned. In this way, through the loop operation of the second data programming, it can be ensured that the storage units of any row are programmed successfully.

[0117] Exemplarily, the programming accuracy of the second data programming is higher than that of the first data programming. That is, the second data programming can be performed by fine-tuning the resistance value of the resistive memory R in the target storage module, which can be achieved by adjusting parameters such as the amplitude and width of the programming pulse.

[0118] In the disclosed embodiment, by selecting a group to be programmed to perform data programming in a storage mode, and combining the in-memory calculation mode to perform in-memory calculation simulation, it can be ensured that the discharge current of the successfully programmed storage unit can meet the preset conditions (i.e., be within the error range), thereby effectively compensating for the mismatch of the discharge transistor in the storage module to improve the linearity and calculation accuracy of the in-memory calculation.

[0119] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A storage module, characterized in that: include: A storage unit, connected to a word line, a bit line and a source line, and configured to: in a storage mode, perform data programming, data reading or data deletion based on the word line, the bit line and the source line; An in-memory computing unit is connected to the storage unit and is used to connect the timing word line, the computing word line, and the computing source line, and is configured to: in the first stage of the in-memory computing mode, obtain the storage data of the storage unit based on the bit line and the timing word line; and in the second stage of the in-memory computing mode, perform in-memory computing based on the computing word line and the computing source line.

2. The storage module according to claim 1, characterized in that: The storage unit comprises: a first transistor and a resistive memory; The gate of the first transistor is connected to the word line, the first electrode of the first transistor is connected to the source line, the second electrode of the first transistor is connected to the first end of the resistive memory, and the second end of the resistive memory is connected to the bit line.

3. The storage module according to claim 1, characterized in that: The in-memory computing unit includes: a second transistor, a third transistor, a capacitor and a fourth transistor; Among them, the gate of the second transistor is connected to the timing word line; the first electrode of the second transistor is connected to the storage unit; the second electrode of the second transistor, the gate of the third transistor and the first electrode of the capacitor are connected as a recovery node; the first electrode of the third transistor and the second electrode of the capacitor are connected and connected to the ground voltage terminal; the second electrode of the third transistor is connected to the first electrode of the fourth transistor; the gate of the fourth transistor is connected to the calculation word line, and the second electrode of the fourth transistor is connected to the calculation source line.

4. A storage array, characterized in that: A plurality of storage units are arranged in an array; the storage units include a plurality of storage modules as claimed in any one of claims 1 to 3 and are arranged in a row along a first direction; Among them, the recovery nodes of each storage module in each storage unit are connected and connected to a shared capacitor, and the shared capacitor is configured to: in an in-memory computing mode, obtain the storage data of the target storage module in the corresponding storage unit in response to an in-memory computing control instruction.

5. The storage array according to claim 4, characterized in that: The storage units are arranged in a row along a second direction, and the second direction intersects the first direction; wherein at least one row of the storage units is a virtual row of storage units; and each storage module in the virtual row of storage units stores calibration pre-stored data.

6. A storage device, characterized in that: include: The storage array as claimed in claim 4 or 5; A read / write control circuit is connected to each of the storage units in the storage array through a bit line driving circuit, a word line driving circuit and a source line driving circuit, and is configured to: in a storage mode, send a storage control instruction to the bit line driving circuit, the word line driving circuit and the source line driving circuit respectively to select the target storage module to perform data programming, data reading or data deletion; The in-memory calculation control circuit is connected to each of the storage units in the storage array through a timing word line driving circuit, a calculation word line pulse generating and driving circuit and a calculation source line processing circuit, and is configured to: in the first stage of the in-memory calculation mode, send a first in-memory calculation control instruction to the timing word line driving circuit to obtain the storage data of multiple target storage modules; and in the second stage of the in-memory calculation mode, send a second in-memory calculation control instruction to the calculation word line pulse generating and driving circuit and the calculation source line processing circuit to perform in-memory calculation on the storage data of multiple target storage modules.

7. The storage device according to claim 6, characterized in that: Also includes: The delay circuit is connected to the bit line driving circuit and the timing word line driving circuit, and is configured to: control the charging time of the shared capacitor in the in-memory calculation mode.

8. The storage device according to claim 6, characterized in that: Also includes: The calculation post-processing circuit is connected to the calculation source line processing circuit and is configured to: in the in-memory calculation mode, post-process the operation structure of the in-memory calculation and output the post-processing result.

9. An in-memory computing programming method, characterized in that: Applicable to the storage device according to any one of claims 6 to 8; the programming method comprises: Selecting a plurality of target memory modules in a first target row from the memory array as a group to be programmed; In a storage mode, performing a first data programming on each of the target storage modules in the to-be-programmed group through the bit line driving circuit, the word line driving circuit and the source line driving circuit; In the first stage of the in-memory calculation mode, the storage data of each target storage module in the to-be-programmed group is restored to the corresponding shared capacitor through the bit line driving circuit and the timing word line driving circuit; In the second stage of the in-memory computing mode, the discharge of the shared capacitor is controlled by the computing word line pulse generation and driving circuit and the computing source line processing circuit, and whether the discharge current of the shared capacitor meets a preset condition is detected; Wherein, in response to the discharge current of the shared capacitor satisfying the preset condition, a plurality of the target memory modules in the second target row are selected from the memory array as a group to be programmed; In response to the discharge current of the shared capacitor not satisfying the preset condition, data programming is performed a second time on each of the target storage modules in the group to be programmed in the storage mode, and the storage data of each of the target storage modules in the group to be programmed is restored to the corresponding shared capacitor in the in-memory calculation mode to detect again whether the discharge current of the shared capacitor satisfies the preset condition.

10. The in-memory computing programming method according to claim 9, characterized in that: The programming accuracy of the second data programming is higher than the programming accuracy of the first data programming.

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