Modulation circuit, demodulation circuit, isolation channel circuit, chip and method

Abstract

The invention relates to a modulation circuit, a demodulation circuit, an isolation channel circuit, a chip and a method. The modulation circuit comprises a first modulator configured to take power from a first power supply voltage and modulate a first signal or first data into a first output signal; the amplitude of the first output signal is determined according to the first power supply voltage; a second modulator configured to take power from a second power supply voltage and modulate a second signal or second data into a second output signal; the amplitude of the second output signal is determined according to the second power supply voltage and is different from the amplitude of the first output signal; wherein the first output end of the first modulator is connected with the second output end of the second modulator so as to obtain a composite signal; the composite signal includes a first signal portion having an amplitude corresponding to an amplitude of the first output signal and a second signal portion having an amplitude corresponding to an amplitude of the second output signal. The invention provides a new communication mechanism, and the occupied chip area can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a modulation circuit, a demodulation circuit, an isolation channel circuit, a chip and a method. Background Art

[0002] The isolated gate driver chip is a gate driver chip with isolation function, which is mainly composed of input part, output part and isolation part. The input part is mainly used to receive low-voltage control signals, the output part is mainly used to drive high-voltage power devices, and the isolation part is mainly used to isolate the low-voltage side from the high-voltage side. The isolation part generally uses optocouplers, electromagnetics or high-voltage capacitors for isolation to ensure the safety of the low-voltage control end.

[0003] Therefore, the isolated gate driver chip becomes the interface chip between the low-voltage control signal and the high-voltage power device. Through the isolated communication channel provided by the isolated gate driver chip, the signal and / or data can be transmitted between the low-voltage side and the high-voltage side. Therefore, as an indispensable interface chip in the isolation circuit, it is crucial to optimize the design of the isolated gate driver chip. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a modulation circuit, a demodulation circuit, an isolation channel circuit, a chip and a method to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a modulation circuit, the modulation circuit comprising:

[0006] A first modulator is configured to draw power from a first power supply voltage and modulate an input first signal or first data into a first output signal; the amplitude of the first output signal is determined according to the first power supply voltage; and

[0007] A second modulator is configured to draw power from a second power supply voltage and modulate an input second signal or second data into a second output signal; the amplitude of the second output signal is determined according to the second power supply voltage and is different from the amplitude of the first output signal;

[0008] wherein the first output terminal of the first modulator is connected to the second output terminal of the second modulator, and is used to combine the first output signal output from the first output terminal and the second output signal output from the second output terminal to obtain a composite signal;

[0009] The composite signal includes a first signal portion having an amplitude corresponding to the amplitude of the first output signal, and a second signal portion having an amplitude corresponding to the amplitude of the second output signal, so as to demodulate, during demodulation, a first target signal corresponding to the first signal or the first data, and a second target signal corresponding to the second signal or the second data from the composite signal according to the first signal portion and the second signal portion having different amplitudes.

[0010] In combination with the first aspect, in an optional implementation,

[0011] The modulation circuit is configured to output the first signal portion and the second signal portion alternately in time;

[0012] The first signal portion corresponds to part or all of the first signal or the information of the first data; the second signal portion corresponds to part or all of the second signal or the information of the second data.

[0013] In combination with the first aspect, in an optional implementation,

[0014] The first modulator is configured to modulate the PWM signal;

[0015] The second modulator is configured to modulate second data;

[0016] The modulation circuit is configured to output the second signal portion corresponding to part or all of the second data after a falling edge of the PWM signal and before a rising edge next to the falling edge.

[0017] In combination with the first aspect, in an optional implementation,

[0018] The frequency of the PWM signal is less than or equal to the frequency of the second data.

[0019] In combination with the first aspect, in an optional implementation,

[0020] The second modulator is further configured to modulate the second signal or second data based on the input clock signal to transmit a second signal portion corresponding to part or all of the second data between clock edges of the clock signal.

[0021] In a second aspect, an embodiment of the present application provides a demodulation circuit, the demodulation circuit comprising:

[0022] A first demodulator is configured to demodulate an input composite signal based on a first demodulation threshold to obtain a first target signal corresponding to a first signal or first data; the composite signal includes a first signal portion having an amplitude corresponding to an amplitude of a first output signal, and a second signal portion having an amplitude corresponding to an amplitude of a second output signal; the first output signal is modulated according to the first signal or the first data, and the second output signal is modulated according to a second signal or second data; the first demodulation threshold is between the amplitude of the first signal portion and the amplitude of the second signal portion;

[0023] a second demodulator configured to demodulate the input composite signal to obtain an intermediate signal based on a second demodulation threshold; the second demodulation threshold is lower than the amplitude of the second signal portion; and

[0024] The logic operation circuit is configured to perform a logic operation on the intermediate signal and the first target signal to obtain a second target signal corresponding to the second signal or the second data.

[0025] In conjunction with the second aspect, in an optional implementation,

[0026] The logic operation circuit includes a NOT gate circuit and an AND gate circuit;

[0027] The input end of the NOT gate circuit is configured to obtain the first signal or the first data, the output end of the NOT gate circuit is connected to the first input end of the AND gate circuit, the second input end of the AND gate circuit is configured to obtain the intermediate signal, and the output end of the AND gate circuit is configured to output the second signal or the second data.

[0028] In a third aspect, an embodiment of the present application provides an isolation channel circuit, which includes an isolation circuit and at least one of the modulation circuit as described in the first aspect and the demodulation circuit as described in the second aspect.

[0029] In a fourth aspect, an embodiment of the present application provides a chip, the chip comprising a first die and a second die;

[0030] The first die construction includes at least one of the following: one or more modulation circuits as described in the first aspect; one or more demodulation circuits as described in the second aspect;

[0031] The second die construction includes at least one of the following: one or more modulation circuits as described in the first aspect; one or more demodulation circuits as described in the second aspect;

[0032] Each modulation circuit of any one of the first die and the second die is connected to a demodulation circuit of the other die to form an isolation channel circuit.

[0033] In conjunction with the fourth aspect, in an optional implementation,

[0034] The chip further comprises one or more isolation circuits; each of the isolation circuits is connected between the modulation circuit and the demodulation circuit of one of the isolation channel circuits.

[0035] In conjunction with the fourth aspect, in an optional implementation,

[0036] The isolation circuit includes at least one of the following: a first capacitor constructed on the first die; a second capacitor constructed on the second die;

[0037] Wherein, the output end of the modulation circuit and the input end of the demodulation circuit are connected via a first capacitor and a second capacitor.

[0038] In a fifth aspect, an embodiment of the present application provides a method, the method comprising:

[0039] Modulating an input first signal or first data into a first output signal; the amplitude of the first output signal is determined according to a first power supply voltage;

[0040] modulating an input second signal or second data into a second output signal; the amplitude of the second output signal is determined according to a second power supply voltage and is different from the amplitude of the first output signal;

[0041] The first output signal and the second output signal are combined to obtain and output a composite signal; the composite signal includes a first signal portion having an amplitude corresponding to the amplitude of the first output signal, and a second signal portion having an amplitude corresponding to the amplitude of the second output signal, so as to demodulate a first target signal corresponding to the first signal or the first data, and a second target signal corresponding to the second signal or the second data from the composite signal according to the first signal portion and the second signal portion having different amplitudes during demodulation.

[0042] In conjunction with the fifth aspect, in an optional implementation,

[0043] The output composite signal includes:

[0044] The first signal portion and the second signal portion are output alternately in time.

[0045] In conjunction with the fifth aspect, in an optional implementation,

[0046] The step of combining the first output signal and the second output signal to obtain and output a composite signal comprises:

[0047] Combining a first output signal obtained by modulating the PWM signal and a second output signal obtained by modulating the second data to obtain a composite signal;

[0048] The second signal portion corresponding to part or all of the second data is output after the falling edge of the PWM signal and before the next rising edge of the falling edge.

[0049] In conjunction with the fifth aspect, in an optional implementation manner, the method further includes:

[0050] Based on a first demodulation threshold, demodulating the input composite signal to obtain a first target signal corresponding to the first signal or the first data; the first demodulation threshold is between the amplitude of the first signal part and the amplitude of the second signal part;

[0051] Demodulating the input composite signal to obtain an intermediate signal based on a second demodulation threshold, wherein the second demodulation threshold is lower than the amplitude of the second signal portion;

[0052] A logic operation is performed on the intermediate signal and the first target signal to obtain a second target signal corresponding to the second signal or the second data.

[0053] The beneficial effects of the technical solution provided by the embodiment of the present application include: by configuring the first modulator and the second modulator to take power from different first power supply voltages and second power supply voltages respectively, so that they can obtain different power supply voltages respectively, so as to obtain the first output signal and the second output signal of different amplitudes. And by connecting the output end of the first modulator and the output end of the second modulator, the first output signal and the second output signal are merged into the total composite signal for output, for example, output to the demodulation circuit through the isolation circuit, so that the composite signal can contain the first signal part and the second signal part corresponding to the amplitude of the first output signal and the second output signal respectively, so that the original signal and / or data, such as PWM signal and DATAS data, can be demodulated from the composite signal according to different levels during demodulation, forming a new communication mechanism, which can realize the merging of two channels, thereby reducing the number of channels of the isolated communication channel, and then realizing the optimization and improvement of the isolated gate driver chip with small chip area, less bonding wires and low packaging cost. And by including the first signal part and the second signal part in the composite signal, it is possible to avoid mutual interference when the first modulator and the second modulator are output at the same time and transmitted at the same time through the isolated communication channel, thereby improving the channel communication quality and capacity.

[0054] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0056] Figure 1 It is an internal schematic diagram of a specific example of an isolated gate driving chip in the related art;

[0057] Figure 2 A schematic diagram of a principle block diagram of a modulation circuit consistent with at least one embodiment of the present application;

[0058] Figure 3 A signal timing diagram of a specific example of the modulation process in the embodiment of the present application;

[0059] Figure 4 A schematic diagram of a principle block diagram of a specific example of a modulation circuit in an embodiment of the present application;

[0060] Figure 5 A schematic diagram of a principle block diagram of a demodulation circuit consistent with at least one embodiment of the present application;

[0061] Figure 6 A signal timing diagram of a specific example of a demodulation process in an embodiment of the present application;

[0062] Figure 7 A schematic diagram of a principle block diagram of a chip consistent with at least one embodiment of the present application;

[0063] Figure 8 A circuit diagram of a specific example of a chip in an embodiment of the present application;

[0064] Fig. 9 A flowchart of a method consistent with at least one embodiment of the present application;

[0065] Fig.10 The present invention is a flowchart of a specific example of the method in the embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the technical solutions and beneficial effects of the present application more obvious and easy to understand, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which the present application belongs.

[0067] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0068] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0069] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0070] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0071] In the embodiments of the present application, "plurality" refers to two or more.

[0072] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.

[0073] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0074] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0075] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0076] In some embodiments, the values ​​defined by high and low can be relative values, rather than absolute values, such as high speed and low speed, high voltage and low voltage, high level and low level, etc.

[0077] In the process of implementing this application, the inventor found that the related technology has the following problems:

[0078] Figure 1 The internal schematic diagram of a specific example of an isolation gate driver chip in the related art is shown. As shown in the figure, the isolation gate driver chip is usually mainly composed of two dies, namely a low-voltage side die and a high-voltage side die. It is understandable that the isolation gate driver chip can be named differently, such as an isolation gate driver, etc., and the name is not limited here.

[0079] Currently, the isolated gate driver chip with safety protection function generally includes four isolated communication channels, namely:

[0080] A PWM (Pulse Width Modulation) channel: transmits the PWM signal from the low-voltage side to the high-voltage side in real time to control the opening and closing of the high-voltage power device;

[0081] Two DATA channels: transmit chip configuration, control and other commands from the low-voltage side to the high-voltage side, and / or transmit status information from the high-voltage side back to the low-voltage side;

[0082] An INT (interrupt) channel: transmits the fault indication signal of the high voltage side to the low voltage side in real time.

[0083] In this way, the isolated gate driver chip uses an independent channel for the transmission of each signal or data. For example, this transmission uses OOK (On-Off Keying) modulation and demodulation technology, which leads to a large number of channels and a large chip area. In addition, the large number of channels also leads to a large number of bonding wires between the low-voltage side Die and the high-voltage side Die, and the packaging cost is high. In addition, the signal on the DATA channel is easily affected and interfered by the high noise of the signal on the PWM channel transmitted at the same time.

[0084] To this end, an embodiment of the present application provides a modulation circuit that can be applied to a transmitter in an isolated communication channel having a transmitter and a receiver, such as a transmitter in an isolated gate driver chip having the isolated communication channel (which can be located on the low-voltage side Die or the high-voltage side Die), to achieve transmission of signals and / or data between mutually isolated transmitters and receivers.

[0085] Figure 2 A schematic block diagram of a modulation circuit consistent with at least one embodiment of the present application is shown. As shown in the figure, the modulation circuit 10 includes:

[0086] A first modulator is configured to draw power from a first power supply voltage HVDD and modulate an input first signal or first data into a first output signal; the amplitude of the first output signal is determined according to the first power supply voltage HVDD; and

[0087] A second modulator is configured to draw power from a second power supply voltage LVDD and modulate an input second signal or second data into a second output signal; the amplitude of the second output signal is determined according to the second power supply voltage LVDD and is different from the amplitude of the first output signal;

[0088] wherein the first output terminal of the first modulator is connected to the second output terminal of the second modulator, and is used to combine the first output signal output from the first output terminal and the second output signal output from the second output terminal to obtain a composite signal;

[0089] The composite signal includes a first signal portion having an amplitude corresponding to the amplitude of the first output signal, and a second signal portion having an amplitude corresponding to the amplitude of the second output signal, so as to demodulate, during demodulation, a first target signal corresponding to the first signal or the first data, and a second target signal corresponding to the second signal or the second data from the composite signal according to the first signal portion and the second signal portion having different amplitudes.

[0090] In the embodiment of the present application, the first power supply voltage HVDD and the second power supply voltage LVDD may be different. For example, the first power supply voltage HVDD may be a high voltage, such as 5 V; and the second power supply voltage LVDD may be a low voltage, such as 1.8 V. Of course, this is not limited to this. On the contrary, it is also possible that the first power supply voltage HVDD is a low voltage and the second power supply voltage LVDD is a high voltage, which can be set according to actual needs.

[0091] The first target signal may be the same as or different from the first signal (or first data), and the second target signal may be the same as or different from the second data (or second signal).

[0092] Then, by utilizing different power supply voltages of the first modulator and the second modulator, the output amplitudes of the two first output signals and the second output signals (i.e., the amplitude of change on the time axis) obtained in this way can be different. In this way, the first signal or first data corresponding to the first output signal and the second signal or second data corresponding to the second output signal can be directly demodulated from the combined signal, i.e., the composite signal, according to different levels, thereby forming a new communication mechanism and improving decoding efficiency and communication efficiency.

[0093] The combination of the first output signal and the second output signal may be that the first signal part and the second signal part appear alternately in the composite signal in time division, so as to transmit and output the first output signal and the second output signal in turn; or, it may be that the composite signal is firstly and alternately one of the first signal part and the second signal part at a time division, and then the other of the first signal part and the second signal part at a time division, so as to transmit and output the first output signal and the second output signal one after another; and so on. Wherein, the amplitude of the first signal part corresponds to the amplitude of the first output signal, and the amplitude of the second signal part corresponds to the amplitude of the second output signal. For example, the amplitude of the first signal part may be the same as the amplitude of the first output signal, and the amplitude of the second signal part may be the same as the amplitude of the second output signal. In some examples, the combination of the first output signal and the second output signal may not result in the accumulation of the amplitudes of the two, for example, the amplitude of any one of the first signal part and the second signal part will not be equal to the sum of the amplitude of the first output signal and the amplitude of the second output signal.

[0094] In an exemplary embodiment, the first modulator can be input with a first signal, such as a PWM signal; the second modulator can be input with a second data, such as DATAS data, and the modulation circuit 10 can modulate the first signal and the second data and combine them into a composite signal for output, so that, for example, the first signal and the second data can be output alternately in time-sharing, or output one after another, or other output methods. Of course, it is not limited to this, and the modulation circuit 10 can also output the first signal and the second signal, or the first data and the second data, etc. alternately in time-sharing or other output methods, which can be set according to actual needs.

[0095] In the embodiment of the present application, an OOK modulation and demodulation method may be adopted, but it is not limited thereto, and the modulation and demodulation method may be set according to actual needs. In the case of adopting the OOK modulation method, both the first modulator and the second modulator are OOK modulators.

[0096] In this way, the embodiment of the present application configures the first modulator and the second modulator to take power from different first power supply voltages and second power supply voltages respectively, so that they can obtain different power supply voltages respectively, thereby obtaining the first output signal and the second output signal of different amplitudes. And by connecting the output end of the first modulator and the output end of the second modulator, the first output signal and the second output signal are merged into the total composite signal for output, for example, output to the demodulation circuit 30 through the isolation circuit 20, so that the composite signal can contain the first signal part and the second signal part corresponding to the amplitude of the first output signal and the second output signal respectively, so that the original signal and / or data, such as PWM signal and DATAS data, can be demodulated from the composite signal according to different levels during demodulation, forming a new communication mechanism, which can realize the merging of two channels, thereby reducing the number of channels of the isolated communication channel, and then realizing the optimization and improvement of the isolated gate driver chip with small chip area, less bonding wires and low packaging cost. And by including the first signal part and the second signal part in the composite signal, it is possible to avoid mutual interference when the first modulator and the second modulator are output at the same time and transmitted simultaneously through the isolated communication channel, thereby improving the channel communication quality and capacity.

[0097] In an optional embodiment, the modulation circuit 10 is configured to output the first signal portion and the second signal portion alternately in time;

[0098] The first signal portion corresponds to part or all of the first signal or the information of the first data; the second signal portion corresponds to part or all of the second signal or the information of the second data.

[0099] In the embodiment of the present application, the first modulator and the second modulator of the modulation circuit 10 can be modulated and output under the control of the control logic preset by the external control device, so that the modulation circuit 10 outputs the first signal part and the second signal part alternately in time, realizing asynchronous transmission of different signals. The control logic can be set according to actual needs, for example, according to the actual transmission requirements of the signal or data to be transmitted.

[0100] In some examples, if the input is two-way first data and second data, the control logic can control the first modulator to output a first output signal modulated by the first data within a first time to form a first signal portion in a composite signal; and can control the second modulator to output a second output signal modulated by the second data within a second time to form a second signal portion in a composite signal, thereby forming an output of the first signal portion and the second signal portion alternating in time, and realizing isolated channel transmission of the first data and the second data alternating in time and without affecting each other.

[0101] The first time and the second time may be continuous or separated by a set interval. The first signal portion within the first time may correspond to a portion or a complete first data, i.e., the output of a portion or a complete first data may be completed within the first time; similarly, the second signal portion within the second time may correspond to a portion or a complete second data, i.e., the output of a portion or a complete second data may be completed within the second time.

[0102] In other examples, the first signal and the second data of the two input paths, or other combinations of signals and data, may also be modulated to transmit the channels alternately and independently of each other in time. Figure 3 A signal timing diagram of a specific example of the modulation process in an embodiment of the present application is shown. As shown in the figure, in an optional embodiment, the first modulator is configured to modulate the PWM signal;

[0103] The second modulator is configured to modulate second data DATAS;

[0104] The modulation circuit 10 is configured to output the second signal portion corresponding to part or all of the second data DATAS after a falling edge of the PWM signal and before a rising edge next to the falling edge.

[0105] In an exemplary embodiment, reference Figure 3After the falling edge of the PWM signal is detected, the second data DATAS starts to be sent (output) in the form of the second signal part. And before the next rising edge of the falling edge arrives, the control stops sending. In some examples, if the rising edge of the PWM signal is detected during the sending process, the sending can be terminated immediately, and it can be reported to the host computer to indicate a communication error, and then the next falling edge of the PWM signal can be waited for to arrive, and the second data DATAS can be sent again.

[0106] In this way, the modulation of the PWM signal and the second data DATAS is realized in time-sharing alternating output without interfering with each other, thus improving the transmission quality and capacity of the isolation channel. In addition, the PWM signal and the second data DATAS can be modulated to different amplitudes, which can make the demodulation process more convenient, thus forming a new communication mechanism.

[0107] In an optional implementation manner, the frequency of the PWM signal is less than or equal to the frequency of the second data DATAS.

[0108] Figure 4 FIG. 1 is a schematic diagram showing a schematic diagram of a specific example of a modulation circuit in an embodiment of the present application. Figure 4 In an exemplary embodiment, the PWM signal may be a low-speed (low-frequency) signal, such as 100KHz, and accordingly, the first modulator may be an OOK LS (Low Speed) modulator. The second data DATAS may be a high-speed (high-frequency) signal, such as 40MBps, and accordingly, the second modulator may be an OOK HS (High Speed) modulator.

[0109] In an optional embodiment, the second modulator is further configured to modulate the second signal or second data based on the input clock signal CLK to transmit a second signal portion corresponding to part or all of the second data DATAS between clock edges of the clock signal CLK.

[0110] The clock edge may include at least one of a rising edge and a falling edge of the clock signal CLK. For example, 1 data bit may be transmitted between a rising edge and a rising edge (or a falling edge and a falling edge) of the clock signal CLK. Alternatively, 1 data bit may be transmitted between a rising edge and a falling edge of the clock signal CLK, such as Figure 3 As shown in the figure, DDR (double data rate) is used for transmission. Data can be transmitted on both edges (rising edge and falling edge) of a clock cycle, thereby doubling the data transmission rate. This can minimize the total time length of the data frame, so that more data bits can be transmitted between the falling edge and the rising edge of a PWM signal, thereby improving data transmission efficiency.

[0111] An embodiment of the present application also provides a demodulation circuit that can be applied to a receiving end in an isolated communication channel having a transmitting end and a receiving end, such as a receiving end in an isolated gate driver chip having the isolated communication channel (which can be located on the low-voltage side Die or the high-voltage side Die), to achieve transmission of signals and / or data between mutually isolated transmitting ends and receiving ends.

[0112] Figure 5 A schematic block diagram of a demodulation circuit consistent with at least one embodiment of the present application is shown. As shown in the figure, the demodulation circuit 30 includes:

[0113] A first demodulator is configured to demodulate an input composite signal based on a first demodulation threshold to obtain a first target signal corresponding to a first signal or first data; the composite signal includes a first signal portion having an amplitude corresponding to an amplitude of a first output signal, and a second signal portion having an amplitude corresponding to an amplitude of a second output signal; the first output signal is modulated according to the first signal or the first data, and the second output signal is modulated according to a second signal or second data; the first demodulation threshold is between the amplitude of the first signal portion and the amplitude of the second signal portion;

[0114] a second demodulator configured to demodulate the input composite signal to obtain an intermediate signal based on a second demodulation threshold; the second demodulation threshold is lower than the amplitude of the second signal portion; and

[0115] The logic operation circuit 31 is configured to perform a logic operation on the intermediate signal and the first target signal to obtain a second target signal corresponding to the second signal or the second data.

[0116] In the embodiment of the present application, based on the correspondence between the amplitude of the first signal portion and the amplitude of the first output signal, and the correspondence between the amplitude of the second signal portion and the amplitude of the second output signal, the amplitude of the first output signal may be higher than the amplitude of the second output signal. Of course, this is not limited to this. In other examples, the amplitude of the first output signal may also be lower than the amplitude of the second output signal.

[0117] In an exemplary embodiment, Figure 6 The signal timing diagram of a specific example of the demodulation process in the embodiment of the present application is shown. As shown in the figure, when the original first signal is a PWM signal, the first target signal LS_DeMOD demodulated and output by the first demodulator can be a PWM signal with the same or different amplitude as the original first signal, so that the first target signal can be the same or different from the first signal. In addition, the intermediate signal HS_DeMOD (including the PWM signal and the second data DATAS) demodulated and output by the second demodulator is subjected to a logic operation. The obtained second target signal may be the original second data DATAS.

[0118] If the amplitude of the first signal portion can be 5V, which is the same as the first power supply voltage HVDD, and the amplitude of the second signal portion can be 1.8V, which is the same as the second power supply voltage LVDD, then the first demodulation threshold can be in the range of 1.8V to 5V, so that the first signal or the first data can be directly demodulated by the first demodulator.

[0119] At the same time, the second demodulation threshold can be lower than 1.8V, so that the second demodulator can be used to demodulate and obtain an intermediate signal that contains information corresponding to the first signal or first data, and the second signal or second data, respectively. Then, by using a logic operation circuit, after logic operations such as AND, OR, NOT, XOR, etc., the second signal or second data can be finally obtained, the demodulation process is completed, and a new communication mechanism is formed.

[0120] In the embodiment of the present application, the first demodulator and the second demodulator may correspond to the first modulator and the second modulator respectively, for example, both may be OOK demodulators.

[0121] In this way, the embodiment of the present application realizes direct demodulation of at least one of the first signal part and the second signal part with different amplitudes in the composite signal through a first demodulator that demodulates based on a first demodulation threshold and a second demodulator that demodulates based on a second demodulation threshold. For example, the composite signal can be generated by the modulation circuit 10 in the isolated communication channel and transmitted to the demodulation circuit 30 via the isolation circuit 20 to obtain an original signal or data; and under the combination of the logical operation of the logic operation circuit, another original signal or data can also be demodulated, so that the original signal and / or data, such as PWM signal and DATAS data, can be demodulated from the composite signal according to different levels, forming a new communication mechanism, which can realize the merging of two channels, thereby reducing the number of channels of the isolated communication channel and avoiding mutual interference during synchronous signal transmission, thereby realizing the optimization and improvement of the isolated gate driver chip with small chip area, less bonding wires and low packaging cost.

[0122] In an optional implementation, the logic operation circuit 31 includes a NOT gate circuit U1 and an AND gate circuit U2;

[0123] The input end of the NOT gate circuit U1 is configured to obtain the first signal or the first data, the output end of the NOT gate circuit U1 is connected to the first input end of the AND gate circuit U2, the second input end of the AND gate circuit U2 is configured to obtain the intermediate signal, and the output end of the AND gate circuit U2 is configured to output the second signal or the second data.

[0124] In this way, compared with encoding and decoding methods, the original signal or data is finally obtained through the logic operation circuit of the simple NOT gate circuit U1 and the AND gate circuit U2, which simplifies the calculation process and circuit structure, makes the demodulation process more direct, and improves the demodulation efficiency.

[0125] In the embodiment of the present application, the NOT gate circuit U1, or inverter, and the AND gate circuit U2 can be configured with specific circuit structures according to actual needs. These are not the inventive points of the present application and will not be described in detail.

[0126] In an optional implementation, the first demodulator is configured to demodulate to obtain a PWM signal;

[0127] The logic operation circuit is configured to obtain second data DATAS by operation according to the intermediate signal demodulated by the second demodulator;

[0128] The frequency of the PWM signal is less than or equal to the frequency of the second data DATAS.

[0129] refer to Figure 4 In an exemplary embodiment, corresponding to the first modulator being an OOK LS modulator, the first demodulator may be an OOK LS demodulator. Corresponding to the second modulator being an OOK HS modulator, the second demodulator may be an OOK HS demodulator. The judgment thresholds of the OOK LS demodulator and the OOK HS demodulator are respectively an LS high threshold (corresponding to the first demodulation threshold) and a HS low threshold (corresponding to the second demodulation threshold).

[0130] An embodiment of the present application further provides an isolation channel circuit, which includes an isolation circuit and at least one of the modulation circuit described in the above embodiment and the demodulation circuit described in the above embodiment.

[0131] refer to Figure 2 , Figure 4 and Figure 5 The isolation channel circuit may include a modulation circuit 10 as described in the above embodiment, an isolation circuit 20, and a demodulation circuit 30 as described in the above embodiment, which are connected in sequence.

[0132] In this way, by adopting the modulation circuit 10 and / or the demodulation circuit 30, the two channels are merged into one channel, forming a new communication mechanism, thereby reducing the number of isolated communication channels and avoiding mutual interference during synchronous signal transmission, thereby achieving optimization and improvement of the isolated gate drive chip with small chip area, less bonding wires and low packaging cost.

[0133] In an exemplary embodiment, the isolation circuit may include at least one of the following: an optical coupling isolation circuit; an electromagnetic isolation circuit; a capacitive isolation circuit (eg, using a high-voltage capacitor).

[0134] The embodiment of the present application also provides a chip, which may be, for example, an isolated gate driver chip, or a packaged integrated circuit chip, etc. Figure 7 A schematic block diagram of a chip consistent with at least one embodiment of the present application is shown. As shown in the figure, the chip 1000 includes a first die Die1 and a second die Die2;

[0135] The first die Die1 is constructed to include at least one of the following: one or more modulation circuits 10 as described in the above embodiment; one or more demodulation circuits 30 as described in the above embodiment;

[0136] The second die Die2 is constructed to include at least one of the following: one or more modulation circuits 10 as described in the above embodiment; one or more demodulation circuits 30 as described in the above embodiment;

[0137] Each modulation circuit 10 of any one of the first die Die1 and the second die Die2 is connected to a demodulation circuit 30 of the other die to form an isolation channel circuit 100 .

[0138] In an exemplary embodiment, the first die Die1 may be a low-voltage side die of the isolation gate driver chip, and the second die Die2 may be a high-voltage side die of the isolation gate driver chip.

[0139] In some examples, an isolation channel circuit 100 can be formed by a modulation circuit 10 on the low-voltage side die and a demodulation circuit 30 on the high-voltage side die. Then, through the isolation channel circuit 100, the PWM signal on the low-voltage side can be transmitted to the high-voltage side in real time to control the opening and closing of the power device. And the chip configuration, control and other commands on the low-voltage side can be transmitted to the high-voltage side. Exemplarily, the chip configuration, control and other commands can be transmitted through the isolation channel circuit 100 in the form of the second data DATAS.

[0140] In some examples, a modulation circuit 10 on the high-voltage side die and a demodulation circuit 30 on the low-voltage side die can form another isolation channel circuit 100. Then, the status information of the high-voltage side can be transmitted back to the low-voltage side through the isolation channel circuit 100. The status information can be transmitted in the form of data DATAF through the isolation channel circuit 100. And the fault indication signal INT of the high-voltage side can be transmitted to the low-voltage side in real time.

[0141] In this way, the number of isolated communication channels can be reduced and mutual interference during synchronous signal transmission can be avoided, thereby reducing the area occupied by the chip, reducing the number of bonding wires, and reducing packaging costs.

[0142] In an optional implementation, the chip 1000 further includes one or more isolation circuits 20 ; each of the isolation circuits 20 is connected between the modulation circuit 10 and the demodulation circuit 30 of one of the isolation channel circuits 100 .

[0143] Figure 8 FIG. 1 is a circuit diagram showing a specific example of a chip in an embodiment of the present application. Figure 7 and Figure 8 In an optional implementation, the isolation circuit 20 includes at least one of the following: a first capacitor HVCAP1 constructed on the first die Die1; a second capacitor HVCAP2 constructed on the second die Die2;

[0144] The output end of the modulation circuit 10 and the input end of the demodulation circuit 30 are connected via a first capacitor HVCAP1 and a second capacitor HVCAP2.

[0145] In some examples, in an isolated communication channel from a low-voltage side die to a high-voltage side die, a first end of the first capacitor HVCAP1 can be connected to an output end of the modulation circuit 10, a second end of the first capacitor HVCAP1 can be connected to a first end of the second capacitor HVCAP2 via a bonding wire, and a second end of the second capacitor HVCAP2 can be connected to an input end of the demodulation circuit 30.

[0146] In other examples, in the isolated communication channel from the high-voltage side die to the low-voltage side die, the first end of the second capacitor HVCAP2 can be connected to the output end of the modulation circuit 10, the second end of the second capacitor HVCAP2 can be connected to the first end of the first capacitor HVCAP1 through a bonding wire, and the second end of the first capacitor HVCAP1 can be connected to the input end of the demodulation circuit 30.

[0147] In an exemplary embodiment, the first capacitor HVCAP1 and the second capacitor HVCAP2 may be high voltage capacitors, and may have a higher voltage resistance than ordinary or low voltage capacitors.

[0148] In the embodiment of the present application, the composite signal is transmitted through the bonding wire, and the first capacitor HVCAP1 and / or the second capacitor HVCAP2 are used to achieve isolated transmission of the composite signal, thereby improving the signal transmission quality and capability.

[0149] refer to Figure 8, the isolated gate driver chip may include two isolated channel circuits. For one of the isolated channel circuits, the low-voltage side die of the isolated gate driver chip may have two OOK modulators: OOK LS modulator and OOK HS modulator; the high-voltage side die of the isolated gate driver chip may also have two OOK demodulators: OOK LS demodulator and OOK HS demodulator, and the judgment thresholds of the two may be LS high threshold (corresponding to the first demodulation threshold) and HS low threshold (corresponding to the second demodulation threshold), respectively. The former can be used to demodulate low-speed PWM signals (e.g., 100KHz), and the latter can be used to demodulate high-speed DATA signals, i.e., second data DATAS (e.g., 40MBps).

[0150] For another isolation channel circuit, the high-voltage side die of the isolation gate driver chip can have two OOK modulators: OOK LS modulator and OOK HS modulator; the low-voltage side die of the isolation gate driver chip can also have two OOK demodulators: OOK LS demodulator and OOK HS demodulator, and the judgment thresholds of the two can be LS high threshold (corresponding to the first demodulation threshold) and HS low threshold (corresponding to the second demodulation threshold), respectively. The former can be used to demodulate the low-speed INT signal, and the latter can be used to demodulate the high-speed DATA signal, i.e., DATAF data.

[0151] The embodiment of the present application also provides a method that can implement the modulation and demodulation process of the isolation channel circuit and provide a new communication mechanism. Fig. 9 A flow chart of a method consistent with at least one embodiment of the present application is shown. As shown in the figure, the method includes:

[0152] S10: modulating an input first signal or first data into a first output signal; the amplitude of the first output signal is determined according to a first power supply voltage;

[0153] S20: modulating the input second signal or second data into a second output signal; the amplitude of the second output signal is determined according to the second power supply voltage and is different from the amplitude of the first output signal;

[0154] S30: Combine the first output signal and the second output signal to obtain and output a composite signal; the composite signal includes a first signal portion having an amplitude corresponding to the amplitude of the first output signal, and a second signal portion having an amplitude corresponding to the amplitude of the second output signal, so as to demodulate a first target signal corresponding to the first signal or the first data and a second target signal corresponding to the second signal or the second data from the composite signal according to the first signal portion and the second signal portion having different amplitudes during demodulation.

[0155] In an optional implementation manner, the outputting of the composite signal in step S30 includes:

[0156] S301: outputting the first signal part and the second signal part alternately in time.

[0157] In an optional implementation manner, the step of combining the first output signal and the second output signal in step S30 to obtain and output a composite signal includes:

[0158] S302: combining a first output signal obtained by modulating the PWM signal and a second output signal obtained by modulating the second data to obtain a composite signal;

[0159] S303: Outputting the second signal portion corresponding to part or all of the second data DATAS after the falling edge of the PWM signal and before the next rising edge of the falling edge.

[0160] Fig.10 A flow chart of a specific example of the method in the embodiment of the present application is shown. As shown in the figure, in an exemplary embodiment, after the chip completes power-on initialization, the low-voltage side starts to receive the PWM signal, and when the falling edge of the PWM signal is detected, the data frame of the second data DATAS starts to be sent. If the rising edge of the PWM signal is detected during the transmission of the data frame, the data frame transmission can be terminated immediately, and it can be reported to the host computer to indicate a communication error, and then the next falling edge of the PWM signal can be waited for to arrive, and the second data DATAS can be sent again. In this way, the transmission of the PWM signal and the second data DATAS of the merged channel is realized from the low-voltage side to the high-voltage side.

[0161] In other examples, the transmission of the INT signal and DATAF data of the combined channel from the high-voltage side to the low-voltage side can be similar to the transmission process of the PWM signal and the second data DATAS mentioned above. Part or all of the DATAF data can be transmitted after the falling edge of the INT signal and before the next rising edge of the falling edge (i.e., between the falling edge and the rising edge). The specific process can refer to the transmission process of the PWM signal and the second data DATAS mentioned above, and will not be repeated here.

[0162] It should be understood that the transmission of signals and data of the combined channel is not limited to being implemented based on PWM signals. Any signal with high and low level changes can also be used to control the transmission of data. For example, part or all of the data information can be transmitted when the signal is at a low level, and the signal can be transmitted when the signal is at a high level to stop the transmission of data.

[0163] In an optional implementation, the method further includes:

[0164] S40: based on a first demodulation threshold, demodulate the input composite signal to obtain a first target signal corresponding to the first signal or the first data; the first demodulation threshold is between the amplitude of the first signal part and the amplitude of the second signal part;

[0165] S50: demodulating the input composite signal to obtain an intermediate signal based on a second demodulation threshold, wherein the second demodulation threshold is lower than the amplitude of the second signal portion;

[0166] S60: Perform a logic operation on the intermediate signal and the first target signal to obtain a second target signal corresponding to the second signal or the second data.

[0167] In this way, by merging the two channels into one channel, a new communication mechanism is formed, which can reduce the number of isolated communication channels and avoid mutual interference during synchronous signal transmission, thereby achieving optimization and improvement of the isolated gate driver chip with small chip area, fewer bonding wires and low packaging cost.

[0168] In the embodiments of the present application, the circuit structures of the modulator and demodulator themselves can be set according to actual needs. These are not the inventive points of the present application and will not be introduced in detail.

[0169] This specification provides method operation steps such as embodiments or flow charts, but may include more or fewer operation steps based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the order of many steps and does not represent the only execution order. When the actual device, system or server product is executed, it can be executed in the order of the method shown in the embodiments or the drawings or in parallel (for example, in a parallel processor or multi-threaded processing environment).

[0170] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A modulation circuit, characterized in that: The modulation circuit comprises: A first modulator is configured to draw power from a first power supply voltage and modulate an input first signal or first data into a first output signal; the amplitude of the first output signal is determined according to the first power supply voltage; and A second modulator is configured to draw power from a second power supply voltage and modulate an input second signal or second data into a second output signal; the amplitude of the second output signal is determined according to the second power supply voltage and is different from the amplitude of the first output signal; wherein the first output terminal of the first modulator is connected to the second output terminal of the second modulator, and is used to combine the first output signal output from the first output terminal and the second output signal output from the second output terminal to obtain a composite signal; The composite signal includes a first signal portion having an amplitude corresponding to the amplitude of the first output signal, and a second signal portion having an amplitude corresponding to the amplitude of the second output signal, so as to demodulate, during demodulation, a first target signal corresponding to the first signal or the first data, and a second target signal corresponding to the second signal or the second data from the composite signal according to the first signal portion and the second signal portion having different amplitudes.

2. The modulation circuit according to claim 1, characterized in that: The modulation circuit is configured to output the first signal portion and the second signal portion alternately in time; The first signal portion corresponds to part or all of the first signal or the information of the first data; the second signal portion corresponds to part or all of the second signal or the information of the second data.

3. The modulation circuit according to claim 1, characterized in that: The first modulator is configured to modulate the PWM signal; The second modulator is configured to modulate second data; The modulation circuit is configured to output the second signal portion corresponding to part or all of the second data after a falling edge of the PWM signal and before a rising edge next to the falling edge.

4. The modulation circuit according to claim 3, characterized in that: The frequency of the PWM signal is less than or equal to the frequency of the second data.

5. The modulation circuit according to any one of claims 1 to 4, characterized in that: The second modulator is further configured to modulate the second signal or second data based on the input clock signal to transmit a second signal portion corresponding to part or all of the second data between clock edges of the clock signal.

6. A demodulation circuit, characterized in that: The demodulation circuit comprises: A first demodulator is configured to demodulate an input composite signal based on a first demodulation threshold to obtain a first target signal corresponding to a first signal or first data; the composite signal includes a first signal portion having an amplitude corresponding to an amplitude of a first output signal, and a second signal portion having an amplitude corresponding to an amplitude of a second output signal; the first output signal is modulated according to the first signal or the first data, and the second output signal is modulated according to a second signal or second data; the first demodulation threshold is between the amplitude of the first signal portion and the amplitude of the second signal portion; a second demodulator configured to demodulate the input composite signal to obtain an intermediate signal based on a second demodulation threshold; the second demodulation threshold is lower than the amplitude of the second signal portion; and The logic operation circuit is configured to perform a logic operation on the intermediate signal and the first target signal to obtain a second target signal corresponding to the second signal or the second data.

7. The demodulation circuit according to claim 6, characterized in that: The logic operation circuit includes a NOT gate circuit and an AND gate circuit; The input end of the NOT gate circuit is configured to obtain the first signal or the first data, the output end of the NOT gate circuit is connected to the first input end of the AND gate circuit, the second input end of the AND gate circuit is configured to obtain the intermediate signal, and the output end of the AND gate circuit is configured to output the second signal or the second data.

8. An isolation channel circuit, characterized in that: The isolation channel circuit includes an isolation circuit and at least one of the modulation circuit according to any one of claims 1 to 5 and the demodulation circuit according to claim 6 or 7.

9. A chip, characterized in that: The chip comprises a first die and a second die; The first die construction comprises at least one of the following: one or more modulation circuits according to any one of claims 1 to 5; one or more demodulation circuits according to claim 6 or 7; The second die construction comprises at least one of the following: one or more modulation circuits according to any one of claims 1 to 5; one or more demodulation circuits according to claim 6 or 7; Each modulation circuit of any one of the first die and the second die is connected to a demodulation circuit of the other die to form an isolation channel circuit.

10. The chip according to claim 9, characterized in that: The chip further comprises one or more isolation circuits; each of the isolation circuits is connected between the modulation circuit and the demodulation circuit of one of the isolation channel circuits.

11. The chip according to claim 10, characterized in that: The isolation circuit includes at least one of the following: a first capacitor constructed on the first die; a second capacitor constructed on the second die; Wherein, the output end of the modulation circuit and the input end of the demodulation circuit are connected via a first capacitor and a second capacitor.

12. A method, characterized in that The method comprises: Modulating an input first signal or first data into a first output signal; the amplitude of the first output signal is determined according to a first power supply voltage; modulating an input second signal or second data into a second output signal; the amplitude of the second output signal is determined according to a second power supply voltage and is different from the amplitude of the first output signal; The first output signal and the second output signal are combined to obtain and output a composite signal; the composite signal includes a first signal portion having an amplitude corresponding to the amplitude of the first output signal, and a second signal portion having an amplitude corresponding to the amplitude of the second output signal, so as to demodulate a first target signal corresponding to the first signal or the first data, and a second target signal corresponding to the second signal or the second data from the composite signal according to the first signal portion and the second signal portion having different amplitudes during demodulation.

13. The method according to claim 12, characterized in that The output composite signal includes: The first signal portion and the second signal portion are output alternately in time.

14. The method according to claim 12, characterized in that The step of combining the first output signal and the second output signal to obtain and output a composite signal comprises: Combining a first output signal obtained by modulating the PWM signal and a second output signal obtained by modulating the second data to obtain a composite signal; The second signal portion corresponding to part or all of the second data is output after the falling edge of the PWM signal and before the next rising edge of the falling edge.

15. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: Based on a first demodulation threshold, demodulating the input composite signal to obtain a first target signal corresponding to the first signal or the first data; the first demodulation threshold is between the amplitude of the first signal part and the amplitude of the second signal part; Demodulating the input composite signal to obtain an intermediate signal based on a second demodulation threshold, wherein the second demodulation threshold is lower than the amplitude of the second signal portion; A logic operation is performed on the intermediate signal and the first target signal to obtain a second target signal corresponding to the second signal or the second data.

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