A Carrier Synchronization Method, Device, Equipment and Storage Medium without Interconnection Lines

Abstract

The present invention discloses a carrier synchronization method, device, equipment and storage medium without interconnection lines, which relates to the technical field of power systems. The method includes: acquiring a voltage signal at the grid connection point, and using a logic state capture unit to determine a first interruption trigger moment according to the state of the voltage signal; using a phase-locked loop software to determine a clock reference moment corresponding to a target phase in the voltage phase, and determining an optimal time interval according to the first interruption trigger moment and the clock reference moment; determining the moment after the second interruption trigger moment passes through the optimal time interval as the carrier synchronization reference moment, and performing carrier synchronization at the carrier synchronization reference moment. The technical solution of the embodiment of the present invention realizes high-precision determination of the reference moment through the combination of software and hardware, and has a simple implementation, solves the problem of inaccurate reference time for carrier synchronization without interconnection lines, improves the carrier synchronization effect, and suppresses the parallel circulating current.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and particularly to a carrier synchronization method, device, equipment and storage medium without an interconnection line. Background Art

[0002] With the proposal of the goal of building a new type of power system, the proportion of new energy power generation will be further increased, and the application of string-type photovoltaic inverters and string-type energy storage converters is becoming more and more extensive. The application scenario of multiple photovoltaic inverters or energy storage converters connected in parallel at the AC side and then connected to a step-up transformer is increasing. However, when multiple inverters are connected in parallel at the AC side, it is easy to cause current circulating current of the switching frequency, which not only reduces the power quality of the output current, but also poses a threat to the safe operation of the inverter.

[0003] Currently, the core of the measures to suppress parallel circulating current is to achieve carrier synchronization between inverters. Carrier synchronization methods are mainly divided into carrier synchronization with an interconnection line and carrier synchronization without an interconnection line. The carrier synchronization method with an interconnection line usually needs to provide a reference time for the carriers of different inverters through a high-speed signal synchronization line or a communication line, and then perform carrier synchronization. When the number of inverters to be connected in parallel is too large or the distance is too far, the effectiveness of carrier synchronization with an interconnection line will be reduced and the cost will increase. Carrier synchronization without an interconnection line usually uses public grid information, such as grid voltage, grid current, etc., to provide a time reference for carrier synchronization, which is suitable for large-scale inverter parallel connection scenarios.

[0004] However, the conventional carrier synchronization method without an interconnection line has defects. For example, parameter differences in the hardware circuit will cause deviations in the reference time, thereby affecting the carrier synchronization effect. This method is applicable to the parallel connection of inverters with a low switching frequency. Summary of the Invention

[0005] The present invention provides a carrier synchronization method, device, equipment and storage medium without an interconnection line to solve the problem of inaccurate reference time for carrier synchronization without an interconnection line.

[0006] In a first aspect, the present invention provides a carrier synchronization method without an interconnection line, including:

[0007] Obtain the voltage signal at the grid connection point, and use a logic state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal;

[0008] Use a phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determine the optimal time interval according to the first interrupt trigger moment and the clock reference moment;

[0009] Determine the moment after the second interruption trigger moment has passed through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, where the second interruption trigger moment is an interruption trigger moment determined by the logical state capture unit and later than the first interruption trigger moment.

[0010] In a second aspect, the present invention provides a wire-free carrier synchronization device, including:

[0011] An interruption moment determination module, configured to obtain the voltage signal of the grid connection point, and use the logical state capture unit to determine the first interruption trigger moment according to the state of the voltage signal;

[0012] An optimal interval module, configured to use the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determine the optimal time interval according to the first interruption trigger moment and the clock reference moment;

[0013] A carrier synchronization module, configured to determine the moment after the second interruption trigger moment has passed through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, where the second interruption trigger moment is an interruption trigger moment determined by the logical state capture unit and later than the first interruption trigger moment.

[0014] In a third aspect, the present invention provides an electronic device, which includes:

[0015] At least one processor;

[0016] And a memory communicatively connected to at least one processor;

[0017] Wherein, the memory stores a computer program executable by at least one processor, and the computer program is executed by at least one processor so that at least one processor can execute the wire-free carrier synchronization method in the first aspect above.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium, which stores computer instructions for causing a processor to implement the wire-free carrier synchronization method in the first aspect above when executed.

[0019] The carrier synchronization scheme without interconnection lines provided by the present invention acquires the voltage signal at the grid connection point, and uses a logical state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal, uses a phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determines the optimal time interval according to the first interrupt trigger moment and the clock reference moment. The moment after the second interrupt trigger moment passes through the optimal time interval is determined as the carrier synchronization reference moment, and carrier synchronization is performed at the carrier synchronization reference moment. Among them, the second interrupt trigger moment is an interrupt trigger moment determined by the logical state capture unit and later than the first interrupt trigger moment. By adopting the above technical solution, taking advantage of the relatively accurate determination of the voltage phase by the PLL (Phase Locked Loop) software, the time deviation of the key signal (such as the zero-crossing point of the voltage) captured by the hardware logical state capture unit triggering the interrupt is compensated. High-precision determination of the reference moment is achieved through the combination of software and hardware, and the implementation is simple. The problem of inaccurate reference time for carrier synchronization without interconnection lines is solved, the carrier synchronization effect is improved, and the parallel circulating current is suppressed.

[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 is a flowchart of a carrier synchronization method without interconnection lines according to Embodiment 1 of the present invention;

[0023] Figure 2 is a circuit diagram of multiple inverters connected in parallel to the grid according to Embodiment 1 of the present invention;

[0024] Figure 3 is a schematic diagram of a carrier slow change mode according to Embodiment 1 of the present invention;

[0025] Figure 4 is a flowchart of a carrier synchronization method without interconnection lines according to Embodiment 2 of the present invention;

[0026] Figure 5 is a waveform schematic diagram according to Embodiment 2 of the present invention;

[0027] Figure 6 It is a waveform diagram of the three-phase output current of an inverter provided according to Embodiment 2 of the present invention;

[0028] Figure 7 It is a schematic structural diagram of a carrier synchronization device without an interconnection line provided according to Embodiment 3 of the present invention;

[0029] Figure 8 It is a schematic structural diagram of an electronic device provided according to Embodiment 4 of the present invention. Detailed implementation manners

[0030] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In the description of the present invention, unless otherwise stated, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In addition, the terms "include" and "have" and any of their deformations are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily need to be limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0032] Embodiment 1

[0033] Figure 1The figure below is a flowchart of a carrier synchronization method without interconnection lines provided by Embodiment 1 of the present invention. This embodiment is applicable to the situation of carrier synchronization. This method can be executed by a carrier synchronization device without interconnection lines, which can be implemented in the form of hardware and / or software. The carrier synchronization device without interconnection lines can be configured in an electronic device, which can be composed of two or more physical entities or one physical entity.

[0034] As Figure 1 shown, the carrier synchronization method without interconnection lines provided by Embodiment 1 of the present invention specifically includes the following steps:

[0035] S101. Obtain the voltage signal at the grid connection point, and use the logic state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal.

[0036] Specifically, the method described in this embodiment can be applied to various types of converters.

[0037] Exemplarily, Figure 2 is a circuit diagram of multiple inverters in parallel and connected to the grid. As Figure 2 shown, the AC output terminals of the inverters are connected in parallel to a step-up transformer and then connected to the grid. The parallel generation of switching frequency circulating current is caused by the asynchronous driving signals of the switching tubes of the inverters. Further analysis shows that it is caused by the deviation of the crystal oscillators of each inverter, resulting in a deviation of the carrier frequency. The voltage sensor built in the inverter and the sampling conditioning circuit on the control board can be used to obtain the voltage signal at the grid connection point. Then, the logic state capture unit can trigger an interrupt according to the state of the voltage signal, and the moment corresponding to this interrupt is the first interrupt trigger moment, denoted as teCAP. Among them, usually, there is a relatively fixed deviation, denoted as ΔteCAP, between teCAP and the actual occurrence moment corresponding to the state when the grid voltage actually triggers the interrupt. This deviation is affected by the differences in the hardware circuit parameters of different inverters, but the specific deviation range is uncertain.

[0038] S102. Use the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determine the optimal time interval according to the first interrupt trigger moment and the clock reference moment.

[0039] In this embodiment, the PLL software (i.e., phase-locked loop software) can be used to determine the voltage phase according to the digital signal corresponding to the voltage signal, and determine the moment corresponding to the phase pre-specified by the voltage phase (i.e., the target phase) as the clock reference moment. For example, the moment corresponding to the a-phase voltage reaching the trough or peak is determined as the clock reference moment, denoted as tPLL. The time difference between tPLL and the actual moment corresponding to the target phase of the grid voltage is theoretically π / 2. However, since the PLL is implemented by software and affected by the deviation of the chip crystal oscillator frequency, there are fluctuations, but the fluctuation range is clear, usually one switching period. Then, the time difference between the clock reference moment and the first interrupt trigger moment can be determined as the optimal time interval. Alternatively, a preset operation can be performed on this difference, and the operation result can be determined as the optimal time interval. For example, the sum of this difference and a preset margin value is determined as the optimal time interval.

[0040] S103. Determine the carrier synchronization reference moment as the moment after the second interrupt trigger moment passes through the optimal time interval, and perform carrier synchronization at the carrier synchronization reference moment, where the second interrupt trigger moment is the interrupt trigger moment determined by the logic state capture unit and later than the first interrupt trigger moment.

[0041] In this embodiment, after determining the optimal time interval, when the interrupt is triggered again (i.e., after the second interrupt is triggered), the optimal time interval can be assigned to the period register of the timer, and the timer interrupt is turned on. The moment when the timer interrupt occurs (i.e., the moment after the second interrupt trigger moment passes through the optimal time interval) is determined as the carrier synchronization reference moment, and then the timer interrupt is turned off. Finally, carrier synchronization is started at this carrier synchronization reference moment to suppress the parallel circulating current.

[0042] The technical solution of the embodiment of the present invention makes use of the characteristics that the PLL software determines the voltage phase relatively accurately and the fluctuation range is clear, compensates for the hardware deviation of the hardware logic state capture unit for capturing the interrupt trigger voltage and the specific deviation range is uncertain, makes up for the disadvantages of both by combining the advantages of both, realizes the accurate determination of the carrier synchronization reference moment, and is simple to implement, solves the problem that the reference time of the carrier synchronization without interconnection line is inaccurate, improves the carrier synchronization effect, and suppresses the parallel circulating current.

[0043] Optionally, the using the logic state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal includes: using the built-in eCAP capture unit to determine the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal, and determining the target moment as the first interrupt trigger moment.

[0044] Specifically, the eCAP capture unit in the embedded chip built into the converter, such as a DSP (Digital Signal Processing chip), can determine the voltage change direction of the (second) target phase in the grid voltage according to the state of the voltage signal, thereby triggering an interruption, and the moment corresponding to this interruption is the first interruption trigger moment. Among them, the voltage change direction of the first target phase can be the upward zero crossing and / or the downward zero crossing, and the first target phase can be at least one of phase a, phase b, and phase c.

[0045] Exemplarily, when the voltage change direction of the first target phase is the upward zero crossing and the downward zero crossing, and the first target phase is one of phase a, phase b, and phase c, two first interruption trigger moments can be determined within one power frequency cycle. When the voltage change direction of the first target phase is the upward zero crossing or the downward zero crossing, and the first target phase is phase a, phase b, and phase c, three first interruption trigger moments can be determined within one power frequency cycle. When the voltage change direction of the first target phase is the upward zero crossing and the downward zero crossing, and the first target phase is phase a, phase b, and phase c, six first interruption trigger moments can be determined within one power frequency cycle.

[0046] Among them, the PLL software is a phase-locked loop technology that is completely implemented in the software of a digital signal processor (DSP), a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC). A phase-locked loop is a circuit used to synchronize and stabilize clock signals. It compares the phase of a reference signal with the phase of a feedback signal to generate a control signal to adjust the input of a variable oscillator, thereby locking the output frequency and phase to the reference frequency and phase. The eCAP capture unit of the DSP is a powerful functional module mainly used to capture the logical state changes of external input pins, such as the high and low levels, rising edges, or falling edges.

[0047] Optionally, the carrier synchronization at the carrier synchronization reference moment includes: determining the maximum value of the time base counter value within the analog-to-digital conversion interruption period corresponding to the carrier synchronization reference moment as the original maximum value; according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, updating the maximum value of the time base counter value to a target value using a preset value, and updating the target value to the original maximum value after a preset period to complete the carrier synchronization.

[0048] Specifically, the ePWM (Enhanced Pulse Width Modulation) unit is an enhanced pulse width modulation module widely used in digital signal processors (DSPs) for controlling applications such as power conversion and motor drive. The maximum value of the time base counter value of the ePWM unit can be changed using a preset value according to the change trend of the time base counter value after the carrier synchronization reference time. For example, when the change trend is upward, the maximum value of the time base counter value is updated to the first preset value, and when the change trend is downward, the maximum value of the time base counter value is updated to the second preset value. At this time, the first preset value can be greater than the original maximum value, and the second preset value can be less than the original maximum value. After a preset period, the target value is restored to the original maximum value to complete carrier synchronization.

[0049] Further, the method of updating the maximum value of the time base counter value to a target value using a preset value according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference time and updating the target value to the original maximum value after a preset period to complete carrier synchronization includes: when the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference time, updating the maximum value of the time base counter value to the first target value in the next analog-to-digital conversion interrupt period and updating the maximum value of the time base counter value to the original maximum value after the first preset period, where the first target value is the difference between the original maximum value and the preset value, and the first preset period is the quotient of the original maximum value and the preset value multiplied by a preset multiple in terms of the number of analog-to-digital conversion interrupt periods; when the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference time, updating the maximum value of the time base counter value to the second target value in the next analog-to-digital conversion interrupt period and updating the maximum value of the time base counter value to the original maximum value after the first preset period, where the second target value is the sum of the original maximum value and the preset value.

[0050] Exemplarily, after determining the carrier synchronization reference time, the carrier can be synchronized in a manner of slow carrier change. Figure 3 As a schematic diagram of a slow carrier change method, as Figure 3 shown, at the carrier synchronization reference time (i.e., Figure 3At the timer interrupt moment in [ ], record the value of the time base count register (i.e., the time base counter value) TBCTR of the ePWM unit and the counting direction of the time base counter. When the counting direction is decreasing (i.e., the time base counter value shows a downward trend), in the next analog-to-digital conversion interrupt cycle, update the ePWM period register value TBPRD (i.e., the original maximum value) to the value obtained by subtracting Δ from the original value of TBPRD (Δ can be any positive integer less than the original value of TBPRD), and after [TBCTR / (2Δ)] interrupt cycles ([] represents the integer operation), change TBPRD back to the original value. This process is equivalent to increasing the carrier frequency to achieve the purpose of carrier synchronization. When the counting direction is increasing, in the next analog-to-digital conversion interrupt cycle, change TBPRD to the value obtained by adding Δ to the original value, and after [TBCTR / (2Δ)] interrupt cycles, change TBPRD back to the original value. This process is equivalent to decreasing the carrier frequency to achieve the purpose of carrier synchronization.

[0051] Embodiment 2

[0052] Figure 4 The flowchart of a carrier synchronization method without interconnection lines provided by Embodiment 2 of the present invention. The technical solution of the embodiment of the present invention is further optimized on the basis of the above optional technical solutions, and a specific method for carrier synchronization is given.

[0053] Optionally, the step of using the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase includes: using the phase-locked loop software to determine the voltage phase of the grid voltage according to the digital signal of the voltage signal; after the first interrupt trigger moment, screening out the target phase corresponding to the preset phase from the voltage signals of the first target phase of the grid voltage; and determining the moment corresponding to the target phase as the clock reference moment.

[0054] Optionally, before using the built-in eCAP capture unit to determine the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal, it further includes: converting the voltage signal into a square wave; wherein, the step of using the built-in eCAP capture unit to determine the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal includes: using the built-in eCAP capture unit to determine the falling edge or rising edge of the square wave of the first target phase, and determining the occurrence moment of the falling edge or rising edge as the target moment. Optionally, the step of determining the optimal time interval according to the first interrupt trigger moment and the clock reference moment includes: for each first interrupt trigger moment, determining the time interval between the target clock reference moment and the current first interrupt trigger moment as the initial time interval, where the target clock reference moment is the clock reference moment that appears after the current first interrupt trigger moment and before the next first interrupt trigger moment; and using the initial time interval to determine the optimal time interval.

[0055] As shown Figure 4 in the figure, a carrier synchronization method without interconnection lines provided in the second embodiment of the present invention specifically includes the following steps:

[0056] S201. Obtain the voltage signal at the grid connection point and convert the voltage signal into a square wave.

[0057] Specifically, Figure 5 it is a waveform schematic diagram. The sine voltage signal can be converted into a square wave by using the built-in filter circuit, and the corresponding waveform is as Figure 5 shown.

[0058] S202. Use the built-in eCAP capture unit to determine the falling edge or rising edge of the square wave of the first target phase, and determine the occurrence time of the falling edge or rising edge as the target time; determine the target time as the first interrupt trigger time.

[0059] Specifically, as Figure 5 shown, the falling edge of the square wave can generate an eCAP interrupt, and the time corresponding to this interrupt can be determined as the target time teCAP. ΔteCAP is a fixed deviation between teCAP and the occurrence time of the actual zero-crossing point of the grid voltage. Among them, the occurrence time of the falling edge or rising edge of the square wave is the target time when the voltage changes direction.

[0060] S203. Use the phase-locked loop software to determine the voltage phase of the grid voltage according to the digital signal of the voltage signal.

[0061] Specifically, after the voltage signal is processed by the analog-to-digital converter, the digital signal of the voltage signal can be obtained. The phase-locked loop software can output the voltage phase of the grid voltage according to the digital signal.

[0062] S204. After the first interrupt trigger time, screen out the target phase corresponding to the preset phase from the voltage signal of the first target phase of the grid voltage.

[0063] Specifically, the first target phase of the grid voltage can be one of the a-phase, b-phase, and c-phase. Exemplarily, if the preset phase is the phase at the wave trough, the phase when the voltage of the first target phase in the voltage signal reaches the wave trough is the target phase.

[0064] S205. Determine the time corresponding to the target phase as the clock reference time.

[0065] Exemplarily, as Figure 5 shown, the clock reference time when the voltage passes through the wave trough can be denoted as tPLL, and this time is also the time when the movie phase determined by the PLL software occurs.

[0066] S206. For each first interrupt trigger moment, determine the time interval between the target clock reference moment and the current first interrupt trigger moment as the initial time interval; determine the optimal time interval by using the initial time interval.

[0067] Wherein, the target clock reference moment is the clock reference moment that appears after the current first interrupt trigger moment and before the next first interrupt trigger moment.

[0068] Exemplarily, Figure 5 Δtd shown in is the initial time interval, and Δtstd is the optimal time interval. If it is preset to determine N first interrupt trigger moments, the process of determining the initial time interval can be as follows:

[0069] Whenever the eCAP capture unit captures the eCAP interrupt (teCAP moment) triggered by the falling edge of the grid voltage, the timer starts timing until the tPLL moment (i.e., the clock reference moment). Store the timer count result Δtd into an array, and repeat the above counting process N - 1 times in the next N - 1 power frequency cycles. Wherein, selecting an appropriate N value can reflect the frequency deviation of the chip crystal oscillator. For example, the count value result of the timer changes uniformly within one or more switching cycles.

[0070] Then, a preset operation can be performed on these N counter count results, such as finding the maximum value, finding the minimum value, finding the average value or other preset algorithms, to obtain the optimal time interval Δtstd. The above entire process can be defined as a self - learning process.

[0071] S207. Determine the moment after the second interrupt trigger moment passes through the optimal time interval as the carrier synchronization reference moment.

[0072] Exemplarily, the timer can be used to start counting at the second interrupt trigger moment and stop after passing through the optimal time interval. The stop moment is the carrier synchronization reference moment. Figure 5 The rising edge moment of the timer interrupt shown in is the timer interrupt stop moment, and this moment is also the carrier synchronization reference moment.

[0073] S208. Determine the maximum value of the time - base counter value within the analog - to - digital conversion interrupt period corresponding to the carrier synchronization reference moment as the original maximum value.

[0074] S209. When the time - base counter value of the built - in ePWM unit shows a downward trend at the carrier - synchronization reference moment, update the maximum value of the time - base counter value to the first target value in the next analog - to - digital conversion interrupt cycle, and update the maximum value of the time - base counter value to the original maximum value after the first preset period; when the time - base counter value of the built - in ePWM unit shows an upward trend at the carrier - synchronization reference moment, update the maximum value of the time - base counter value to the second target value in the next analog - to - digital conversion interrupt cycle, and update the maximum value of the time - base counter value to the original maximum value after the first preset period.

[0075] Wherein, the first target value is the difference between the original maximum value and the preset value, the first preset period is the quotient of the original maximum value divided by the preset value multiplied by the preset multiple in terms of the number of analog - to - digital conversion interrupt cycles, and the second target value is the sum of the original maximum value and the preset value.

[0076] Specifically, the above steps can be executed multiple times in a loop until the carrier synchronization is completed.

[0077] Exemplarily, take the parallel grid - connection of three energy storage converters as an example. The hardware topological relationship of the three inverters is as Figure 2 shown. The rated power of a single energy storage converter is 200 kW, the rated voltage is 800 V, the rated frequency is 50 Hz, and the short - circuit ratio of the power grid is 10. Figure 6 It is a waveform diagram of the three - phase output current of an inverter. Figure 6 Figure a in Figure 6 is the three - phase output current waveform after the inverter is fully loaded, Figure 6 Figure b in Figure 6 is the three - phase output current waveform before the carrier - synchronization algorithm cut - in moment (i.e., the application moment of the carrier - synchronization method without interconnection lines provided in the embodiment of the present invention),

[0078] The carrier synchronization method without interconnection lines provided by the embodiment of the present invention uses the built-in eCAP capture unit to capture the moment when the grid voltage passes through the zero point, calculates the reference moment by using PLL software, and obtains the optimal time interval based on these two moments. After the eCAP triggers an interruption again, the timer is used to trigger a timer interruption after the optimal time interval has elapsed. At the moment of this timer interruption, effective synchronization of the carrier without interconnection lines is achieved through a preset carrier slow change synchronization method. This method is applicable to various types of converters operating in parallel.

[0079] Embodiment III

[0080] Figure 7 It is a schematic structural diagram of a carrier synchronization device without interconnection lines provided by Embodiment III of the present invention. As Figure 7 shown, the device includes: an interruption moment determination module 301, an optimal interval module 302, and a carrier synchronization module 303, where:

[0081] The interruption moment determination module 301 is configured to obtain the voltage signal of the grid connection point and use the logic state capture unit to determine the first interruption trigger moment according to the state of the voltage signal;

[0082] The optimal interval module 302 is configured to use PLL software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determine the optimal time interval according to the first interruption trigger moment and the clock reference moment;

[0083] The carrier synchronization module 303 is configured to determine the moment after the second interruption trigger moment has passed through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, where the second interruption trigger moment is an interruption trigger moment determined by the logic state capture unit that is later than the first interruption trigger moment.

[0084] The carrier synchronization device without interconnection lines provided by the embodiment of the present invention makes use of the relatively accurate characteristic of determining the voltage phase by PLL software to make up for the time deviation of the interruption triggered by the hardware logic state capture unit for capturing key signals (such as the voltage passing through the zero point). Through the combination of software and hardware, the reference moment is determined with high precision, and the implementation is simple. It solves the problem of inaccurate reference time for carrier synchronization without interconnection lines, improves the carrier synchronization effect, and suppresses the parallel circulating current.

[0085] Optionally, the optimal interval module 302 includes:

[0086] The voltage phase determination unit is configured to use PLL software to determine the voltage phase of the grid voltage according to the digital signal of the voltage signal;

[0087] A target phase determination unit, configured to, after the first interruption trigger moment, screen out a target phase corresponding to a preset phase from the voltage signal of the first target phase of the grid voltage;

[0088] A clock reference moment determination unit, configured to determine the moment corresponding to the target phase as the clock reference moment.

[0089] Optionally, the interruption moment determination module 301 includes:

[0090] An interruption moment determination unit, configured to use a built-in eCAP capture unit to determine a target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal, and determine the target moment as the first interruption trigger moment.

[0091] Optionally, the device further includes:

[0092] A signal conversion module, configured to convert the voltage signal into a square wave before determining the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal by using the built-in eCAP capture unit.

[0093] Further, the determining the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal by using the built-in eCAP capture unit includes: using the built-in eCAP capture unit to determine a falling edge or a rising edge of the square wave of the first target phase, and determining the occurrence moment of the falling edge or the rising edge as the target moment.

[0094] Optionally, the optimal interval module 302 includes:

[0095] An initial interval determination unit, configured to, for each first interruption trigger moment, determine the time interval between the target clock reference moment and the current first interruption trigger moment as the initial time interval, where the target clock reference moment is the clock reference moment that appears after the current first interruption trigger moment and before the next first interruption trigger moment appears;

[0096] An optimal interval determination unit, configured to determine the optimal time interval by using the initial time interval.

[0097] Optionally, the carrier synchronization module 303 includes:

[0098] A raw maximum value determination unit, configured to determine the maximum value of the time base counter value within the analog-to-digital conversion interruption period corresponding to the carrier synchronization reference moment as the raw maximum value;

[0099] A carrier synchronization unit is configured to update the maximum value of the time base counter value of the built-in ePWM unit to a target value according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference time, using a preset value, and update the target value to the original maximum value after a preset period to complete carrier synchronization.

[0100] Further, the process of updating the maximum value of the time base counter value to a target value according to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference time, using a preset value, and updating the target value to the original maximum value after a preset period to complete carrier synchronization includes: when the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference time, updating the maximum value of the time base counter value to a first target value in the next analog-to-digital conversion interrupt period, and updating the maximum value of the time base counter value to the original maximum value after a first preset period, where the first target value is the difference between the original maximum value and the preset value, and the first preset period is the quotient of the original maximum value divided by a preset multiple of the preset value in terms of the number of analog-to-digital conversion interrupt periods; when the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference time, updating the maximum value of the time base counter value to a second target value in the next analog-to-digital conversion interrupt period, and updating the maximum value of the time base counter value to the original maximum value after the first preset period, where the second target value is the sum of the original maximum value and the preset value.

[0101] The carrier synchronization device without interconnection lines provided by the embodiments of the present invention can execute the carrier synchronization method without interconnection lines provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.

[0102] Embodiment 4

[0103] Figure 8 FIG. shows a schematic structural diagram of an electronic device 40 that can be used to implement the embodiments of the present invention. The electronic device can be various forms of digital computers, converters, etc. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0104] As Figure 8As shown, the electronic device 40 includes at least one processor 41 and a memory communicatively connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc. The memory stores a computer program executable by the at least one processor. The processor 41 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 into the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0105] Multiple components in the electronic device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disc, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the electronic device 40 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0106] The processor 41 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 41 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 executes the various methods and processes described above, such as the carrier synchronization method without interconnection lines.

[0107] In some embodiments, the carrier synchronization method without interconnection lines can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as the storage unit 48. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the carrier synchronization method without interconnection lines described above can be executed. Alternatively, in other embodiments, the processor 41 can be configured to execute the carrier synchronization method without interconnection lines in any other appropriate manner (e.g., by means of firmware).

[0108] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0109] Computer programs for implementing the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer programs can be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0110] The computer device provided above can be used to execute the carrier synchronization method without interconnection lines provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0111] Embodiment Five

[0112] In the context of the present invention, a computer-readable storage medium can be a tangible medium, and the computer-executable instructions are used to execute a carrier synchronization method without interconnection lines when executed by a computer processor. The method includes:

[0113] Obtaining a voltage signal at the grid connection point, and using a logic state capture unit to determine a first interrupt trigger time according to the state of the voltage signal;

[0114] Using a phase-locked loop software to determine a clock reference time corresponding to a target phase in the voltage phase, and determining an optimal time interval according to the first interrupt trigger time and the clock reference time;

[0115] Determining a carrier synchronization reference time as the time after the second interrupt trigger time passes through the optimal time interval, and performing carrier synchronization at the carrier synchronization reference time, where the second interrupt trigger time is an interrupt trigger time determined by the logic state capture unit and later than the first interrupt trigger time.

[0116] In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium may be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] The computer device provided above can be used to execute the carrier synchronization method without interconnection lines provided in any of the above embodiments, and has the corresponding functions and beneficial effects.

[0118] It should be noted that in the embodiments of the carrier synchronization device without interconnection lines described above, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of mutual distinction and do not limit the protection scope of the present invention.

[0119] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A carrier synchronization method without interconnection lines, characterized in that Including: Obtain the voltage signal of the grid connection point, and use the logic state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal; Use the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determine the optimal time interval according to the first interrupt trigger moment and the clock reference moment; Determine the carrier synchronization reference moment as the moment after the second interrupt trigger moment passes through the optimal time interval, and perform carrier synchronization at the carrier synchronization reference moment, where the second interrupt trigger moment is the interrupt trigger moment determined by the logic state capture unit and later than the first interrupt trigger moment; Among them, the determining the optimal time interval according to the first interrupt trigger moment and the clock reference moment includes: For each first interrupt trigger moment, determine the time interval between the target clock reference moment and the current first interrupt trigger moment as the initial time interval, where the target clock reference moment is the clock reference moment that appears after the current first interrupt trigger moment and before the next first interrupt trigger moment appears; Use the initial time interval to determine the optimal time interval.

2. The method according to claim 1, characterized in that The using the logic state capture unit to determine the first interrupt trigger moment according to the state of the voltage signal includes: Use the built-in eCAP capture unit to determine the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal, and determine the target moment as the first interrupt trigger moment.

3. The method according to claim 1, wherein The using the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase includes: Use the phase-locked loop software to determine the voltage phase of the grid voltage according to the digital signal of the voltage signal; After the first interrupt trigger moment, screen out the target phase corresponding to the preset phase from the voltage signal of the first target phase of the grid voltage; Determine the moment corresponding to the target phase as the clock reference moment.

4. The method according to claim 2, wherein Before the using the built-in eCAP capture unit to determine the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal, it further includes: Convert the voltage signal into a square wave; Among them, the using the built-in eCAP capture unit to determine the target moment when the voltage change direction of the first target phase is determined according to the state of the voltage signal includes: Use the built-in eCAP capture unit to determine the falling edge or rising edge of the square wave of the first target phase, and determine the occurrence moment of the falling edge or rising edge as the target moment.

5. The method according to claim 1, characterized in that The performing carrier synchronization at the carrier synchronization reference moment includes: Determine the maximum value of the time base counter value within the analog-to-digital conversion interrupt period corresponding to the carrier synchronization reference moment as the original maximum value; According to the change trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, use a preset value to update the maximum value of the time base counter value to a target value, and update the target value to the original maximum value after a preset period to complete carrier synchronization.

6. The method according to claim 5, characterized in that Updating the maximum value of the time base counter value to a target value according to the changing trend of the time base counter value of the built-in ePWM unit after the carrier synchronization reference moment, and updating the target value to the original maximum value after a preset period to complete carrier synchronization, includes: When the time base counter value of the built-in ePWM unit shows a downward trend at the carrier synchronization reference moment, updating the maximum value of the time base counter value to a first target value in the next analog-to-digital conversion interrupt period, and updating the maximum value of the time base counter value to the original maximum value after a first preset period, where the first target value is the difference between the original maximum value and a preset value, and the first preset period is the quotient of the original maximum value divided by the preset value multiplied by a preset multiple, in terms of the number of analog-to-digital conversion interrupt periods; When the time base counter value of the built-in ePWM unit shows an upward trend at the carrier synchronization reference moment, updating the maximum value of the time base counter value to a second target value in the next analog-to-digital conversion interrupt period, and updating the maximum value of the time base counter value to the original maximum value after the first preset period, where the second target value is the sum of the original maximum value and the preset value.

7. A carrier synchronization device without interconnection lines, characterized in that, Includes: An interruption moment determination module, configured to obtain the voltage signal at the grid connection point, and use the logic state capture unit to determine the first interruption trigger moment according to the state of the voltage signal; An optimal interval module, configured to use the phase-locked loop software to determine the clock reference moment corresponding to the target phase in the voltage phase, and determine the optimal time interval according to the first interruption trigger moment and the clock reference moment; A carrier synchronization module, configured to determine the moment after the second interruption trigger moment passes through the optimal time interval as the carrier synchronization reference moment, and perform carrier synchronization at the carrier synchronization reference moment, where the second interruption trigger moment is the interruption trigger moment determined by the logic state capture unit and later than the first interruption trigger moment; Among them, the optimal interval module includes: An initial interval determination unit, configured to, for each first interruption trigger moment, determine the time interval between the target clock reference moment and the current first interruption trigger moment as the initial time interval, where the target clock reference moment is the clock reference moment that appears after the current first interruption trigger moment and before the next first interruption trigger moment; An optimal interval determination unit, configured to determine the optimal time interval using the initial time interval.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; where The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the carrier synchronization method without interconnection line according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a processor to implement the carrier synchronization method without interconnection line according to any one of claims 1-6 when executed.

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