Semiconductor memory device

Abstract

The semiconductor memory device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a plurality of gate electrodes extending in a first direction in the substrate of the cell region; a plurality of bit lines extending in a second direction crossing the first direction on the substrate in the cell region and the boundary region; a plurality of buried contacts connected to the substrate of the cell region on the substrate of the cell region and located between the gate electrodes and between the bit lines; dummy buried contacts between the bit lines on the substrate in the boundary region; and a bit line contact connected to at least one of the bit lines on the substrate of the boundary region, where the dummy buried contact includes an insulating material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0154777 filed in the Korean Intellectual Property Office on November 9, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same. Background Art

[0004] As semiconductor elements are increasingly highly integrated, individual circuit patterns become finer in order to implement more semiconductor elements in the same area. That is, as the integration of semiconductor elements increases, the design rules of components of semiconductor elements have been reduced.

[0005] Meanwhile, in highly scaled semiconductor elements, processes for forming buried contacts in a boundary region between a cell region and a peripheral region and forming bit line contacts in the boundary region have gradually become complicated and difficult. Summary of the invention

[0006] Some example embodiments of the present disclosure provide a semiconductor memory device having improved reliability.

[0007] Some example embodiments of the present disclosure provide a method of manufacturing a semiconductor memory device having improved reliability.

[0008] However, exemplary embodiments of the present disclosure are not limited to those set forth herein. The above and other exemplary embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an example embodiment of the present disclosure, a semiconductor memory device includes: a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a plurality of gate electrodes extending along a first direction within the substrate of the cell region; a plurality of bit lines extending along a second direction intersecting the first direction on the substrate of the cell region and the boundary region; a plurality of buried contacts connected to the substrate of the cell region and between the gate electrodes and between the bit lines on the substrate of the cell region; a pseudo buried contact located between the bit lines on the substrate of the boundary region; and a bit line contact connected to at least one of the bit lines on the substrate of the boundary region, wherein the pseudo buried contact includes an insulating material.

[0010] According to an example embodiment of the present disclosure, a semiconductor memory device includes: a substrate, which includes a cell area, a peripheral area, and a boundary area between the cell area and the peripheral area, the cell area includes a capacitor, and the peripheral area includes a peripheral circuit element; a plurality of gate electrodes, the plurality of gate electrodes extending along a first direction within the substrate of the cell area; a plurality of first bit lines, the plurality of first bit lines extending along a second direction intersecting the first direction on the substrate of the cell area; a plurality of second bit lines, the plurality of second bit lines being respectively connected to the first bit lines on the substrate of the boundary area; a plurality of fences and a plurality of buried contacts alternately arranged along the second direction between the first bit lines; a pseudo buried contact, which is located between the second bit lines; and a bit line contact, which contacts at least some of the second bit lines on the substrate of the boundary area, wherein a width of a corresponding one of the first bit lines in the first direction is smaller than a width of a corresponding one of the second bit lines in the first direction, and the pseudo buried contact includes an insulating material.

[0011] According to an example embodiment of the present disclosure, a semiconductor memory device includes: a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a peripheral circuit element disposed on the substrate in the peripheral region; a plurality of gate electrodes extending along a first direction within the substrate in the cell region; a plurality of bit lines extending along a second direction intersecting the first direction on the substrate in the cell region and the boundary region; a plurality of buried contacts, the plurality of buried contacts being on the substrate in the cell region and spaced apart from each other along the second direction, the buried contacts being connected to the substrate in the cell region, the buried contacts being between the gate electrodes and between the bit lines; a plurality of capacitors, the plurality of capacitors being connected on the substrate in the cell region, respectively. to a buried contact; a plurality of fences, the plurality of fences being between the buried contacts and between the gate electrodes, the fences being spaced apart from each other along a second direction and being on a substrate in a cell region; a pseudo buried contact, which is located between the bit lines on a substrate in a boundary region; and a bit line contact, which is connected to at least one of the bit lines on a substrate in a boundary region, wherein a first distance from an upper surface of a corresponding one of the buried contacts to a bottom surface of a corresponding one of the buried contacts is less than a second distance from an upper surface of a corresponding one of the buried contacts to a bottom surface of a corresponding one of the fences, at least a portion of the pseudo buried contact is in contact with the substrate in the boundary region, and the pseudo buried contact and the fences comprise the same material.

[0012] According to an example embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes: providing a substrate including a cell area, a peripheral area, and a boundary area between the cell area and the peripheral area; forming a plurality of gate electrodes in the substrate of the cell area, the gate electrodes extending in a first direction; forming a plurality of bit lines on the substrate of the cell area and the boundary area, the bit lines extending in a second direction intersecting the first direction; forming embedded contacts between the bit lines on the substrate of a portion of the cell area and the boundary area; forming a mask film on the substrate of the cell area; removing the embedded contacts by using the mask film as an etching mask, forming a second trench on the cell area and forming a first trench on the boundary area; forming a fence in the second trench and forming a pseudo-buried contact in the first trench, wherein the fence and the pseudo-buried contact each include an insulating material.

[0013] According to an example embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes: providing a substrate including a cell area, a peripheral area, and a boundary area between the cell area and the peripheral area; forming a plurality of gate electrodes in the substrate of the cell area, the gate electrodes extending in a first direction; forming a plurality of bit lines on the substrate of the cell area and the boundary area, the bit lines extending in a second direction intersecting the first direction; forming embedded contacts between the bit lines on the substrate of the cell area and a portion of the boundary area; forming pseudo-embedded contacts by etching a portion of the embedded contacts on the substrate of the boundary area; forming a plurality of embedded contacts by etching the embedded contacts on the substrate of the cell area after forming the pseudo-embedded contacts; and forming fences between the embedded contacts, wherein the fences and the pseudo-embedded contacts each include an insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram of a semiconductor memory device according to an example embodiment of the present disclosure.

[0016] Figure 2 is a plan view of a semiconductor memory device according to an example embodiment of the present disclosure.

[0017] Figure 3 is along Figure 2 A cross-sectional view taken along line AA in FIG.

[0018] Figure 4 is along Figure 2 A cross-sectional view taken along line BB in FIG.

[0019] Figure 5 is along Figure 2 Cross-sectional view taken along line CC in FIG.

[0020] Figure 6 is along Figure 2 A cross-sectional view taken along line DD in FIG.

[0021] Figures 7 to 13 are diagrams for describing semiconductor memory devices according to some example embodiments of the present disclosure.

[0022] Fig.14 is a plan view of a semiconductor memory device according to an example embodiment of the present disclosure.

[0023] Fig.15 is along Fig.14 A cross-sectional view taken along line EE in FIG.

[0024] Figures 16 to 22 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure.

[0025] Figure 23 to Figure 28 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure.

[0026] Figure 29 to Figure 35 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As used herein, the terms "first", "second", etc. are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first element or component mentioned below may also be the second element or component within the inventive concept of the present disclosure.

[0028] Although the terms "same," "equal," or "equivalent" are used in the description of example embodiments, it should be understood that some imprecision may exist. Thus, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element or value within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0029] When the terms "about," "substantially," or "approximately" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about," "substantially," or "approximately" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the freedom of choice of shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially," it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0030] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0031] Hereinafter, some example embodiments of the inventive concepts according to the present disclosure will be described with reference to the accompanying drawings.

[0032] In the drawings of the semiconductor memory device according to some example embodiments, a dynamic random access memory (DRAM) has been illustrated by way of example, but the present disclosure is not limited thereto.

[0033] First, refer to Figures 1 to 6 A semiconductor memory device according to some example embodiments is described.

[0034] Figure 1 is a block diagram of a semiconductor memory device according to an example embodiment of the present disclosure. Figure 2 is a plan view of a semiconductor memory device according to an example embodiment of the present disclosure. Figure 3 is along Figure 2 A cross-sectional view taken along line AA in FIG. Figure 4 is along Figure 2 A cross-sectional view taken along line BB in FIG. Figure 5 is along Figure 2 Cross-sectional view taken along line CC in FIG. Figure 6 is along Figure 2 For reference, Figure 2 It can be corresponding to Figure 1 Floor plan of the P1 section.

[0035] First, refer to Figure 1, a semiconductor memory device may include a cell block CB and a peripheral block PB surrounding each of the cell blocks CB. Each of the cell blocks CB may include a cell circuit, such as a memory integrated circuit. The peripheral block PB may include various peripheral circuits required for the operation of the cell circuit. The peripheral circuit may be electrically connected to the cell circuit.

[0036] The peripheral block PB may include a sense amplifier circuit SA and a sub-word line driver circuit SMD. As an example, the sense amplifier circuits SA may face each other, and the cell block CB is interposed between the sense amplifier circuits SA. The sub-word line driver circuits SMD may face each other, and the cell block CB is interposed between the sub-word line driver circuits SMD. The peripheral block PB may also include a power supply for driving the sense amplifier and the ground driver circuit, but the inventive concept of the present disclosure is not limited thereto.

[0037] Reference Figures 2 to 6 , a substrate 100 may be provided. The substrate 100 may include a cell region CR, a boundary region BR, and a peripheral region PR.

[0038] The cell region CR may be a region where a plurality of memory cells are disposed. The boundary region BR may be disposed around the cell region CR. The peripheral region PR may be a region where a peripheral circuit for operating a plurality of memory cells in the cell region CR is disposed. For example, the boundary region BR may be disposed between the peripheral region PR and the cell region CR. The boundary region BR may be a region for connecting a structure disposed in the cell region CR and a structure in the peripheral region PR to each other.

[0039] For example, the substrate 100 may be a silicon single crystal substrate or a silicon on insulator (SOI) substrate. In some example embodiments, the substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0040] The cell element isolation film 103 may be disposed in the substrate 100 of the cell region CR. The cell element isolation film 103 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a combination thereof, but is not limited thereto.

[0041] The boundary element isolation film 105 may be disposed in the substrate 100 of the boundary region BR. In some example embodiments, the boundary element isolation film 105 may include a first liner film 105a, a second liner film 105b, and a buried insulating film 105c. The first liner film 105a may be conformally formed on the inner sidewall and bottom surface of the trench formed in the substrate 100 of the boundary region BR. The buried insulating film 105c may fill the trench. The second liner film 105b may be interposed between the first liner film 105a and the buried insulating film 105c.

[0042] The first liner film 105a may be formed as a silicon oxide film. The second liner film 105b may be formed as a silicon nitride film. The buried insulating film 105c may be formed as a silicon oxide film.

[0043] The cell region CR may include a plurality of active regions ACT. The plurality of active regions ACT may be defined by the cell element isolation film 103 and / or the boundary element isolation film 105. According to the reduction in the design rule of the semiconductor memory device, each of the plurality of active regions ACT may be as follows: Figure 2 For example, the active area ACT may extend in the fourth direction.

[0044] A plurality of active areas ACT may be arranged parallel to each other in a first direction D1. An end of one active area ACT may be arranged adjacent to a center of another active area ACT adjacent to the one active area ACT. In the present specification, the first direction D1, the second direction D2, the third direction D3, and the fourth direction may intersect with each other. The first direction D1, the second direction D2, and the third direction D3 may be substantially perpendicular to each other. The fourth direction may be located in the same plane as the first direction D1 and the second direction D2. That is, the fourth direction may be any direction between the first direction D1 and the second direction D2.

[0045] A semiconductor memory device according to some example embodiments may include various contact arrangements formed on an active area ACT. The various contact arrangements may include, for example, a direct contact DC, a buried contact BC, a landing pad LP, and the like.

[0046] Here, the direct contact DC may refer to a contact that electrically connects each of the plurality of active regions ACT to the bit line BL. The buried contact BC may refer to a contact that connects each of the plurality of active regions ACT to the capacitor lower electrode 191. Due to the arrangement structure, the contact area between the buried contact BC and the plurality of active regions ACT may be small. Therefore, a landing pad LP having conductivity may be introduced so as to increase the contact area with the plurality of active regions ACT and increase the contact area with the capacitor lower electrode 191.

[0047] The landing pad LP may be disposed between the plurality of active regions ACT and the buried contact BC, or between the buried contact BC and the capacitor lower electrode 191. According to some example embodiments, the landing pad LP may be disposed between the buried contact BC and the capacitor lower electrode 191. By increasing the contact area by introducing the landing pad LP, the contact resistance between the plurality of active regions ACT and the capacitor lower electrode 191 may be reduced.

[0048] The word lines WL may be buried in the substrate 100 of the cell region CR. The word lines WL may cross the plurality of active regions ACT. The word lines WL may extend in the first direction D1. The word lines WL may be spaced apart from each other in the second direction D2. The word lines WL may be buried in the substrate 100 and extend in the first direction D1. Although not shown, an impurity region may be formed in the substrate 100 between the word lines WL. The impurity region may be doped with N-type impurities.

[0049] According to some example embodiments, a semiconductor memory device may include a plurality of word line structures 110. Each of the plurality of word line structures 110 may be buried in a substrate 100 and extend in a first direction D1. The plurality of word line structures 110 may be spaced apart from each other in a second direction D2.

[0050] Each of the plurality of word line structures 110 may include a gate insulating film 111, a gate electrode 112, and gate capping films 113 and 114. The gate electrode 112 of the word line structure 110 may correspond to a word line WL of the semiconductor memory device. Each of the plurality of word line structures 110 may be disposed in a gate trench formed in the substrate 100.

[0051] The gate insulating film 111 may extend along the inner sidewall and the bottom surface of the gate trench. The gate insulating film 111 may extend along at least a portion of the outline of the gate trench.

[0052] The gate insulating film 111 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0053] The gate electrode 112 may be disposed on the gate insulating film 111. The gate electrode 112 may fill a portion of the gate trench.

[0054] The gate electrode 112 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, or a conductive metal oxide. The gate electrode 112 may include, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, NiPt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrO x 、RuO x Or at least one of a combination thereof, but is not limited thereto.

[0055] The gate capping films 113 and 114 may be disposed on the gate electrode 112. The gate capping films 113 and 114 may fill the gate trench remaining after the gate insulating film 111 and the gate electrode 112 are formed.

[0056] In some example embodiments, the gate capping films 113 and 114 may include a gate capping conductive film 113 and a gate capping insulating film 114. The gate capping conductive film 113 and the gate capping insulating film 114 may be sequentially stacked. That is, the gate capping insulating film 114 is disposed on the gate capping conductive film 113. The gate capping conductive film 113 may include, for example, polycrystalline silicon or polycrystalline silicon germanium, but is not limited thereto. The gate capping insulating film 114 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or at least one of a combination thereof.

[0057] A cell buffer film 120 may be provided on the substrate 100 of the cell region CR. Although not shown, the cell buffer film 120 may include a first insulating film to a third insulating film stacked sequentially. The second insulating film may include a material having an etching selectivity relative to the first insulating film and the third insulating film. For example, the second insulating film may include silicon nitride, and the first insulating film and the third insulating film may include silicon oxide.

[0058] A plurality of bit lines BL may be disposed on the substrate 100. The bit lines BL may be disposed on the cell buffer film 120. The bit lines BL may cross the word lines WL. The bit lines BL may extend in the second direction D2. In addition, the bit lines BL may be spaced apart from each other in the first direction D1. The bit lines BL may correspond to a bit line structure 130 to be described later.

[0059] The bit line structure 130 may include a bit line lower electrode 131, a bit line middle electrode 132, and a bit line lower electrode 133 stacked in sequence. The bit line lower electrode 131 may include polysilicon doped with impurities. The bit line middle electrode 132 may include TiSiN. The bit line upper electrode 133 may include tungsten (W). However, the inventive concept of the present disclosure is not limited thereto. The bit line capping pattern 140 may be disposed on the bit line structure 130. The bit line capping pattern 140 may include silicon nitride.

[0060] The bit line spacers SP may be disposed on the sidewalls of the bit line structure 130 and the sidewalls of the bit line capping pattern 140. Figure 4 In the portion where the direct contact DC is formed, the bit line spacer SP may be disposed on the substrate 100 and the cell element isolation film 103. However, in the portion where the direct contact DC is not formed, the bit line spacer SP may be disposed on the cell buffer film 120.

[0061] As shown in the figure, the bit line spacer SP may be a single layer, but the inventive concept of the present disclosure is not limited thereto. The bit line spacer SP may also be a multilayer. The bit line spacer SP may include, for example, one of a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon oxycarbonitride (SiOCN) film, air, or a combination thereof, but is not limited thereto.

[0062] The cell buffer film 120 may be interposed between the bit line structure 130 and the cell element isolation film 103 and between the bit line spacer SP and the substrate 100 .

[0063] The bit line BL may be electrically connected to the impurity region of the active area ACT through a direct contact DC. For example, the direct contact DC may be made of polysilicon doped with impurities.

[0064] The buried contact BC may be disposed between the paired bit lines BL adjacent to each other. The buried contacts BC may be spaced apart from each other. The buried contacts BC may include at least one of polysilicon doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal. The buried contacts BC may have an island shape in which the buried contacts BC are spaced apart from each other in a plan view. The buried contacts BC may penetrate the cell buffer film 120 to contact the impurity region of the active region ACT.

[0065] In some example embodiments, the embedded contact PBC (see Fig.16 ) may be formed to be elongated in the second direction D2, and the fence FC may be formed by removing the pre-buried contact PBC. Therefore, although not shown, a seam elongated in the second direction D2 may be disposed within the buried contact BC. However, the inventive concept of the present disclosure is not limited thereto.

[0066] The landing pad LP may be formed on the buried contact BC. The landing pad LP may be electrically connected to the buried contact BC. The landing pad LP may overlap a portion of the upper surface of the bit line BL. The landing pad LP may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, or a metal alloy.

[0067] The fence FC may be disposed on the substrate 100 and the cell element isolation film 103. The fence FC may be disposed on the word line structure 110. The fence FC may overlap the word line structure 110 formed in the substrate 100. The fence FC may be disposed between the pair of bit lines BL extending along the second direction D2. The fence FC may be disposed between the pair of bit line structures 130 extending along the second direction D2.

[0068] The fence FC may also be inserted between the buried contacts BC. That is, the fence FC and the buried contacts BC may be alternately arranged in the second direction D2. The fence FC may include an insulating material. The fence FC may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As an example, the fence FC may be formed as a silicon nitride film.

[0069] The pad isolation insulating film 180 may be formed on the landing pad LP and the bit line structure 130. For example, the pad isolation insulating film 180 may be disposed on the bit line capping pattern 140. The pad isolation insulating film 180 may define an isolation region in which the landing pad LP is to be disposed. In addition, the pad isolation insulating film 180 may not cover the upper surface of the landing pad LP.

[0070] The pad isolation insulating film 180 may include an insulating material and may electrically isolate the plurality of landing pads LP from each other. For example, the pad isolation insulating film 180 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbon nitride film, or a silicon carbon nitride film.

[0071] The etch stop film 185 may be disposed on the pad isolation insulating film 180 and the landing pad LP. The etch stop film 185 may include at least one of a silicon nitride film, a silicon carbonitride film, a silicon boron nitride (SiBN) film, a silicon oxynitride film, or a silicon oxycarbide film.

[0072] The capacitor 190 may be disposed on the landing pad LP. The capacitor 190 may be electrically connected to the landing pad LP. A portion of the capacitor 190 may be disposed within the etch stop film 185. The capacitor 190 includes a capacitor lower electrode 191, a capacitor dielectric film 192, and a capacitor upper electrode 193.

[0073] The capacitor lower electrode 191 may be disposed on the landing pad LP. It has been shown that the capacitor lower electrode 191 has a columnar shape, but example embodiments of the present disclosure are not limited thereto. In some example embodiments, the capacitor lower electrode 191 may have a cylindrical shape. The capacitor dielectric film 192 is formed on the capacitor lower electrode 191. The capacitor dielectric film 192 may be formed along the contour of the capacitor lower electrode 191. The capacitor upper electrode 193 is formed on the capacitor dielectric film 192. The capacitor upper electrode 193 may surround the outer side wall of the capacitor lower electrode 191.

[0074] As an example, the capacitor dielectric film 192 may be provided in a portion vertically overlapping with the capacitor upper electrode 193. As another example, unlike what is shown, the capacitor dielectric film 192 may include a portion vertically overlapping with the capacitor upper electrode 193 and a portion not vertically overlapping with the capacitor upper electrode 193. That is, the portion of the capacitor dielectric film 192 not vertically overlapping with the capacitor upper electrode 193 is a portion of the capacitor dielectric film 192 that is not covered by the capacitor upper electrode 193.

[0075] The capacitor lower electrode 191 and the capacitor upper electrode 193 may each include, for example, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), metals (e.g., ruthenium, iridium, titanium, tantalum, etc.) and conductive metal oxides (e.g., iridium oxide, niobium oxide, etc.), etc., but are not limited thereto.

[0076] The capacitor dielectric film 192 may include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof, but is not limited thereto. According to some example embodiments, the capacitor dielectric film 192 may have a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. According to some example embodiments, the capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). According to some example embodiments, the capacitor dielectric film 192 may have a stacked film structure of a ferroelectric material film and a paraelectric material film.

[0077] In some example embodiments, a pseudo buried contact DBC may be provided. The pseudo buried contact DBC may be provided on the substrate 100 of the boundary region BR. The pseudo buried contact DBC may be provided on the boundary element isolation film 105 within the substrate 100 of the boundary region BR. At least a portion of the pseudo buried contact DBC may overlap with a bit line contact BLCT to be described later in the first direction D1. The pseudo buried contact DBC may be interposed between adjacent bit line contacts BLCT.

[0078] The pseudo buried contact DBC may be made of an insulating material. For example, the pseudo buried contact DBC may include a silicon nitride film, a silicon oxide film, a silicon oxynitride film, and / or a combination thereof. Since the pseudo buried contact DBC is made of an insulating material, even if the bit line contact BLCT and the pseudo buried contact DBC contact each other, a short circuit does not occur. Therefore, a semiconductor memory device with improved reliability can be manufactured.

[0079] In some example embodiments, the pseudo buried contact DBC and the fence FC may be formed by the same process. That is, the pseudo buried contact DBC and the fence FC may include the same material. As an example, the pseudo buried contact DBC and the fence FC may each be formed as a silicon nitride film, but the inventive concept of the present disclosure is not limited thereto.

[0080] In some example embodiments, the buried contact BC includes an upper surface BC_US and a bottom surface BC_BS. The upper surface BC_US of the buried contact BC may face the capacitor 190. The bottom surface BC_BS of the buried contact BC may face away from the capacitor 190.

[0081] In some example embodiments, a first distance d1 from the upper surface BC_US of the buried contact BC to the bottom surface BC_BS of the buried contact BC along the third direction D3 is smaller than a second distance d2 from the upper surface BC_US of the buried contact BC to the bottom surface FC_BS of the fence FC along the third direction D3.

[0082] This may be because the fence FC is formed by etching the embedded contact PBC (see Fig.16 ) is formed by a portion of the grating FC. The bottom surface FC_BS of the grating FC may face away from the capacitor 190. It has been illustrated that the bottom surface FC_BS of the grating FC is convex relative to the capacitor 190, but the inventive concept of the present disclosure is not limited thereto.

[0083] In some example embodiments, a first distance d1 from the upper surface BC_US of the buried contact BC to the bottom surface BC_BS of the buried contact BC along the third direction D3 is smaller than a third distance d3 from the upper surface BC_US of the buried contact BC to the bottom surface DBC_BS of the dummy buried contact DBC along the third direction D3.

[0084] This may be because the PBC is embedded by etching (see Fig.16 ) forms a dummy buried contact DBC. A bottom surface DBC_BS of the dummy buried contact DBC may face away from the capacitor 190. It has been illustrated that the bottom surface DBC_BS of the dummy buried contact DBC is convex relative to the capacitor 190, but the inventive concept of the present disclosure is not limited thereto.

[0085] In other words, the level of the bottom surface BC_BS of the buried contact BC is different from the level of the bottom surface FC_BS of the fence FC. In addition, the level of the bottom surface BC_BS of the buried contact BC is different from the level of the bottom surface DBC_BS of the pseudo buried contact DBC. In addition, the level of the bottom surface FC_BS of the fence FC is different from the level of the bottom surface DBC_BS of the pseudo buried contact DBC.

[0086] In some example embodiments, the second distance d2 may be smaller than the third distance d3. This may be because the width of the fence FC in the second direction D2 is smaller than the width of the dummy buried contact DBC in the second direction D2. However, the inventive concepts of the present disclosure are not limited thereto.

[0087] According to some example embodiments, the semiconductor memory device may further include a bit line contact BLCT and a bit line pad BP.

[0088] The bit line contact BLCT may be disposed on the substrate 100 in the boundary region BR. The bit line contact BLCT may penetrate the bit line capping pattern 140 to be electrically connected to the bit line structure 130 or the bit line BL. Figure 4 It has been illustrated that the bit line contact BLCT penetrates the bit line capping pattern 140 , the bit line upper electrode 133 , and the bit line intermediate electrode 132 , but the inventive concept of the present disclosure is not limited thereto.

[0089] The bit line pad BP may be disposed on the bit line contact BLCT. The bit line pad BP may be formed by the same process as the above-mentioned landing pad LP. The level of the upper surface of the bit line pad BP may be the same as the level of the upper surface of the landing pad LP, but is not limited thereto. Similarly, the level of the upper surface of the bit line pad BP may be the same as the level of the upper surface of the pad isolation insulating film 180.

[0090] exist Figure 6 In the embodiment of the present invention, the bit line contact BLCT may not be in contact with the pseudo buried contact DBC. However, at least a portion of the bit line pad BP may be in contact with the pseudo buried contact DBC. Since the pseudo buried contact DBC is made of an insulating material, even if the bit line pad BP and the pseudo buried contact DBC are in contact with each other, a short circuit does not occur.

[0091] exist Figure 2 In the embodiment of the present invention, the bit line contact BLCT may not be formed on one of the paired bit lines BL that are most adjacent to each other along the first direction D1. For example, the bit line contact BLCT may include a first contact connected to one of the plurality of bit lines BL and a second contact connected to another of the plurality of bit lines BL. One or more bit lines BL may be disposed between the first contact and the second contact. However, the inventive concept of the present disclosure is not limited thereto.

[0092] The bit line contact BLCT and the bit line pad BP may each include a conductive material, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, or a metal alloy.

[0093] According to some example embodiments, the semiconductor memory device may further include a first interlayer insulating film 260 , a second interlayer insulating film 270 , and a third interlayer insulating film 195 .

[0094] The first interlayer insulating film 260 may be disposed on the bit line spacer SP. The first interlayer insulating film 260 may be disposed on a portion of the boundary element isolation film 105 and the substrate 100 of the peripheral region PR. The first interlayer insulating film 260 may include an insulating material. For example, the first interlayer insulating film 260 may be formed as a silicon oxide film.

[0095] The second interlayer insulating film 270 may be disposed on the bit line structure 130. The second interlayer insulating film 270 may also be disposed on the first interlayer insulating film 260. The second interlayer insulating film 270 may surround at least a portion of the bit line contact BLCT and may surround at least a portion of the bit line pad BP. The second interlayer insulating film 270 may include an insulating material. For example, the second interlayer insulating film 270 may be formed as a silicon nitride film.

[0096] The third interlayer insulating film 195 may be disposed on the etch stop film 185. The third interlayer insulating film 195 may cover the sidewall of the capacitor upper electrode 193. The third interlayer insulating film 195 may include an insulating material. For example, the third interlayer insulating film 195 may be formed as a silicon oxide film.

[0097] In some example embodiments, the peripheral circuit element PT may be disposed on the substrate 100 in the peripheral region PR.

[0098] Although not shown, a peripheral element isolation film may be provided in the substrate 100 of the peripheral region PR. The peripheral element isolation film may define a peripheral active region. The peripheral circuit element PT may be provided on the peripheral active region.

[0099] The peripheral circuit element PT may include a peripheral gate insulating film 220, a peripheral gate structure 230, a peripheral gate capping pattern 240, and a peripheral gate spacer 250. Components of the peripheral gate structure 230 may be respectively disposed at substantially the same level as components of the bit line structure 130. The peripheral gate insulating film 220 may be disposed at substantially the same level as the cell buffer film 120. The peripheral gate capping pattern 240 may be disposed at substantially the same level as the bit line capping pattern 140.

[0100] The peripheral gate insulating film 220 may extend along the substrate 100 of the peripheral region PR. The peripheral gate insulating film 220 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide.

[0101] The peripheral gate structure 230 may include first to third conductive films 231, 232, and 233 stacked in sequence. The first conductive film 231 may be disposed on the peripheral gate insulating film 220. The second conductive film 232 may be disposed on the first conductive film 231. The third conductive film 233 may be disposed on the second conductive film 232. The first conductive film 231 may be formed by the same process as the bit line lower electrode 131. The second conductive film 232 may be formed by the same process as the bit line middle electrode 132. The third conductive film 233 may be formed by the same process as the bit line upper electrode 133. Therefore, the thickness of the first conductive film 231 in the third direction D3 may be substantially the same as the thickness of the bit line lower electrode 131 in the third direction D3. Similarly, the thickness of the second conductive film 232 in the third direction D3 may be substantially the same as the thickness of the bit line middle electrode 132 in the third direction D3. The thickness of the third conductive film 233 in the third direction D3 may be substantially the same as the thickness of the bit line upper electrode 133 in the third direction D3.

[0102] The first conductive film 231 may include polysilicon doped with impurities. The second conductive film 232 may include TiSiN. The third conductive film 233 may include tungsten (W). However, the inventive concept of the present disclosure is not limited thereto.

[0103] The peripheral gate capping pattern 240 is disposed on the peripheral gate structure 230. The peripheral gate capping pattern 240 may be formed by substantially the same process as the bit line capping pattern 140. Therefore, the thickness of the peripheral gate capping pattern 240 in the third direction D3 may be substantially the same as the thickness of the bit line capping pattern 140 in the third direction D3. The peripheral gate capping pattern 240 may include, for example, silicon nitride.

[0104] The peripheral gate spacer 250 may be disposed on the sidewalls of the peripheral gate structure 230 and the sidewalls of the peripheral gate capping pattern 240. The peripheral gate spacer 250 may include, for example, one of a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon oxycarbon nitride (SiOCN) film, air, or a combination thereof, but is not limited thereto.

[0105] In the following, reference will be made to Figures 7 to 13 A semiconductor memory device according to some example embodiments of the present disclosure is described. Figures 1 to 6 The contents described overlap, or their description will be omitted.

[0106] Figures 7 to 13 are diagrams for describing semiconductor memory devices according to some other example embodiments of the present disclosure.

[0107] First, refer to Figure 7 , a second distance d2 from the upper surface BC_US of the buried contact BC to the bottom surface FC_BS of the fence FC in the third direction D3 may be equal to a third distance d3 from the upper surface BC_US of the buried contact BC to the bottom surface DBC_BS of the dummy buried contact DBC in the third direction D3.

[0108] That is, the level of the bottom surface FC_BS of the fence FC may be the same as the level of the bottom surface DBC_BS of the dummy buried contact DBC. This may be because the fence FC and the dummy buried contact DBC are formed by the same process.

[0109] In this case, the first distance d1 from the upper surface BC_US of the buried contact BC to the bottom surface BC_BS of the buried contact BC in the third direction D3 may be smaller than the second distance d2 and the third distance d3. In addition, the level of the bottom surface BC_BS of the buried contact BC may be higher than the level of the bottom surface FC_BS of the fence FC and the level of the bottom surface DBC_BS of the dummy buried contact DBC.

[0110] Reference Figure 8 , a first distance d1 from the upper surface BC_US of the buried contact BC to the bottom surface BC_BS of the buried contact BC in the third direction D3 may be equal to a third distance d3 from the upper surface BC_US of the buried contact BC to the bottom surface DBC_BS of the dummy buried contact DBC in the third direction D3.

[0111] That is, the level of the bottom surface BC_BS of the buried contact BC may be the same as the level of the bottom surface DBC_BS of the dummy buried contact DBC. In this case, the second distance d2 from the upper surface BC_US of the buried contact BC to the bottom surface FC_BS of the fence FC in the third direction D3 may be greater than the first distance d1 and the third distance d3.

[0112] Reference Fig. 9 , the cell buffer film 120 may be interposed between the substrate 100 and the pseudo buried contact DBC in the boundary region BR. In the process of forming the pseudo buried contact DBC, the cell buffer film 120 on the substrate 100 in the boundary region BR may not be removed. Therefore, on the substrate 100 in the boundary region BR, the pseudo buried contact DBC may be formed on the cell buffer film 120.

[0113] In this case, a third distance d3 from the upper surface BC_US of the buried contact BC to the bottom surface DBC_BS of the pseudo buried contact DBC in the third direction D3 is smaller than a first distance d1 from the upper surface BC_US of the buried contact BC to the bottom surface BC_BS of the buried contact BC in the third direction D3. In this case, the third distance d3 may be smaller than a second distance d2 from the upper surface BC_US of the buried contact BC to the bottom surface FC_BS of the fence FC in the third direction D3.

[0114] Reference Fig.10 , the cell buffer film 120 may be interposed between a portion of the substrate 100 and the dummy buried contact DBC in the boundary region BR. The cell buffer film 120 may not be interposed between the substrate 100 and the other portion of the dummy buried contact DBC in the boundary region BR.

[0115] For example, the cell buffer film 120 is not interposed under the pseudo buried contact DBC adjacent to the cell region CR. The cell buffer film 120 is interposed under the pseudo buried contact DBC adjacent to the peripheral region PR. When the pseudo buried contact DBC is formed, only a portion of the cell buffer film 120 may be removed. Therefore, the cell buffer film 120 may be interposed between a portion of the pseudo buried contact DBC and the substrate 100 of the boundary region BR.

[0116] Reference Fig.11 , the dummy buried contact DBC may include a first portion DBC_1 and a second portion DBC_2.

[0117] The second portion DBC_2 of the dummy buried contact DBC may be disposed on the first portion DBC_1 of the dummy buried contact DBC. That is, the first portion DBC_1 of the dummy buried contact DBC may contact a portion of the substrate 100 of the boundary region BR, and the second portion DBC_2 of the dummy buried contact DBC may contact the etch stop film 185.

[0118] The boundary between the first portion DBC_1 and the second portion DBC_2 of the dummy buried contact DBC may be an uneven curved surface. This may be because a portion of the first portion DBC_1 of the dummy buried contact DBC is removed in the process of forming the fence FC, and then the second portion DBC_2 of the dummy buried contact DBC is formed.

[0119] The first portion DBC_1 of the pseudo buried contact DBC and the second portion DBC_2 of the pseudo buried contact DBC may be made of the same material. As an example, the first portion DBC_1 of the pseudo buried contact DBC and the second portion DBC_2 of the pseudo buried contact DBC may each be formed as a silicon nitride film. As another example, the first portion DBC_1 of the pseudo buried contact DBC and the second portion DBC_2 of the pseudo buried contact DBC may be made of different materials.

[0120] Reference Fig.12 , the second interlayer insulating film 270 may include a first portion 271 and a second portion 272 .

[0121] The second portion 272 of the second interlayer insulating film 270 may be disposed on the first portion 271 of the second interlayer insulating film 270. That is, the first portion 271 of the second interlayer insulating film 270 may contact the bit line capping pattern 140, and the second portion 272 of the second interlayer insulating film 270 may contact the etch stop film 185.

[0122] In the process of forming fence FC, a portion of first portion 271 of second interlayer insulating film 270 may be removed. Then, second portion 272 of second interlayer insulating film 270 may be formed. First portion 271 of second interlayer insulating film 270 and second portion 272 of second interlayer insulating film 270 may be made of the same material. As an example, first portion 271 of second interlayer insulating film 270 and second portion 272 of second interlayer insulating film 270 may each be formed as a silicon nitride film. As another example, first portion 271 of second interlayer insulating film 270 and second portion 272 of second interlayer insulating film 270 may be made of different materials.

[0123] Reference Fig.13 , at least a portion of the bit line contact BLCT may be in contact with the pseudo buried contact DBC. The width of the bit line contact BLCT may be greater than the distance between the outer sidewalls of the bit line spacer SP disposed on both sides (e.g., two opposite sidewalls) of the bit line structure 130. Therefore, the bit line contact BLCT may be electrically connected to the bit line structure 130, and at the same time, at least a portion of the bit line contact BLCT may be in contact with the pseudo buried contact DBC.

[0124] As described above, since the dummy buried contact DBC is made of an insulating material, even if the bit line contact BLCT and the dummy buried contact DBC contact each other, a short circuit does not occur.

[0125] In the following, reference will be made to Fig.14 and Fig.15 A semiconductor memory device according to an exemplary embodiment of the present disclosure is described. Figures 1 to 6 The contents described overlap with the contents described above, or their description will be omitted.

[0126] Fig.14 is a plan view of a semiconductor memory device according to some example embodiments of the present disclosure. Fig.15 is along Fig.14 For reference, Fig.14 It can be corresponding to Figure 1 Floor plan of the P1 section.

[0127] Reference Fig.14 and Fig.15 , each of the plurality of bit lines BL may include a first bit line BL1 and a second bit line BL2 .

[0128] The first bit line BL1 may extend to be elongated in the second direction D2. The second bit line BL2 may be connected to the first bit line BL1. The first bit line BL1 and the second bit line BL2 may be arranged side by side in the second direction D2.

[0129] In some example embodiments, the first bit line BL1 has a first width W1 in the first direction D1. The second bit line BL2 has a second width W2 in the first direction D1. The first width W1 may be smaller than the second width W2. That is, the bit line BL may have a width that is constant in the first direction D1 and then increases from the cell region CR toward the peripheral region PR. The point at which the width of the bit line BL in the first direction D1 changes may be a boundary between the first bit line BL1 and the second bit line BL2.

[0130] In some example embodiments, the second bit line BL2 may be disposed at an end of one of the paired first bit lines BL1 that are most adjacent to each other, but may not be disposed at an end of the other of the paired first bit lines BL1 that are most adjacent to each other. The phrase “paired bit lines that are most adjacent to each other” may mean that no other bit line is disposed between the paired bit lines.

[0131] That is, one first bit line BL1 may be disposed between the pairs of second bit lines BL2 that are most adjacent to each other. In this case, the first bit line BL1 does not overlap the pairs of second bit lines BL2 that are most adjacent to each other in the first direction D1. However, the first bit line BL1 may overlap at least some portions of the pairs of second bit lines BL2 that are most adjacent to each other in the second direction D2.

[0132] In other words, a spacing distance between pairs of second bit lines BL2 that are most adjacent to each other in the first direction D1 may be smaller than a first width W1 of the first bit line BL1 in the first direction D1. However, the inventive concepts of the present disclosure are not limited thereto.

[0133] In some example embodiments, the bit line spacers SP may include a first bit line spacer SP1 and a second bit line spacer SP2 .

[0134] A first bit line spacer SP1 may be disposed on a sidewall of the first bit line BL1. A second bit line spacer SP2 may be disposed on a sidewall of the second bit line BL2. The first bit line spacer SP1 and the second bit line spacer SP2 may be connected to each other.

[0135] A spacing distance between the paired first bit line spacers SP1 may be a first width W1 , and a spacing distance between the paired second bit line spacers SP2 may be a second width W2 .

[0136] The dummy buried contact DBC may be interposed between the first bit lines BL1 and between the second bit lines BL2. The dummy buried contact DBC may include an insulating material. Fig.15 In the embodiment, each of the bit line contact BLCT and the bit line pad BP may not be in contact with the dummy buried contact DBC. However, the inventive concept of the present disclosure is not limited thereto.

[0137] In the process of forming the bit line contact BLCT, the bit line contact BLCT may be misaligned. Therefore, the bit line contact BLCT may contact the second bit line spacer SP2 and the pseudo buried contact DBC. However, since the second bit line spacer SP2 and the pseudo buried contact DBC are made of insulating materials, a short circuit does not occur.

[0138] In the following, reference will be made to Figures 16 to 22 A method of manufacturing a semiconductor memory device according to an example embodiment of the present disclosure is described. Figures 16 to 22 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure.

[0139] Reference Fig.16 , a substrate 100 is provided. The substrate 100 includes a cell region CR, a boundary region BR, and a peripheral region PR.

[0140] A cell element isolation film 103 and a boundary element isolation film 105 may be formed in the substrate 100. The cell element isolation film 103 may be formed in the substrate 100 in the cell region CR, and the boundary element isolation film 105 may be formed in the substrate 100 in the boundary region BR.

[0141] Subsequently, the word line structure 110 may be formed. First, a gate trench may be formed in the substrate 100 of the cell region CR. The gate trench may extend to be elongated in the first direction D1. Some portions of the gate trench may be formed in the cell element isolation film 103. Other portions of the gate trench may be formed in the substrate 100.

[0142] The word line structure 110 may be formed in the gate trench. First, a gate insulating film 111 may be formed along the outline of the gate trench. Subsequently, a gate electrode 112 may be formed on the gate insulating film 111. Subsequently, gate capping films 113 and 114 may be formed on the gate electrode 112.

[0143] A peripheral circuit element PT may be formed on the substrate 100 of the peripheral region PR. In addition, although not shown, a bit line and a direct contact may be formed on the substrate 100 of the cell region CR. The peripheral circuit element PT, the bit line, and the direct contact may be formed by the same process. The peripheral circuit element PT may include a peripheral gate insulating film 220, a peripheral gate structure 230, a peripheral gate capping pattern 240, and a peripheral gate spacer 250. The components of the peripheral gate structure 230 may be respectively disposed at substantially the same level as the components of the bit line structure.

[0144] A second interlayer insulating film 270 covering the peripheral circuit element PT may be formed. In addition, a pre-buried contact PBC may be formed on the cell region CR and a portion of the boundary region BR. The pre-buried contact PBC may be formed between the paired bit lines BL. The pre-buried contact PBC may be elongated in the second direction D2. The pre-buried contact PBC may include at least one of polysilicon doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0145] Reference Fig.17 , a first mask film MASK1 may be formed on the buried contact PBC and the second interlayer insulating film 270. The first mask film MASK1 may have an opening that substantially defines the position of the fence FC. The first mask film MASK1 may be formed as at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC) film, or a silicon nitride film.

[0146] Reference Fig.18 , a second mask film MASK2 may be formed on the substrate 100 of the cell region CR. The second mask film MASK2 may be made of a material having an etching selectivity relative to the first mask film MASK1. The second mask film MASK2 may substantially hide or cover a position where the fence FC is to be formed. The second mask film MASK2 may hide a portion of the first mask film MASK1 and expose other portions of the first mask film MASK1.

[0147] Reference Fig.19 , a portion of the first mask film MASK1 may be removed. For example, the first mask film MASK1 exposed by the second mask film MASK2 may be removed.

[0148] Reference Fig. 20 , the first mask film MASK1 may be exposed by removing the second mask film MASK2.

[0149] Reference Fig.21 , the buried contact PBC may be etched using the first mask film MASK1 as an etching mask. The buried contact BC may be formed by etching the buried contact PBC. In addition, the first trench t1 and the second trench t2 may be formed by etching the buried contact PBC. The first trench t1 and the second trench t2 may be formed by the same etching process.

[0150] The first trench t1 may be a trench for forming a pseudo buried contact DBC described later. The first trench t1 may be formed on the substrate 100 of the boundary region BR. In the process of forming the first trench t1, a portion of the substrate 100 of the boundary region BR and a portion of the boundary element isolation film 105 may be removed. That is, the bottom surface of the first trench t1 may be a curved surface convex downward.

[0151] The second trench t2 may be a trench for forming a fence FC described later. The second trench t2 may be formed on the substrate 100 of the cell region CR. For example, the second trench t2 may be formed on the word line structure 110. In the process of forming the second trench t2, a portion of the word line structure 110 may be removed. That is, the bottom surface of the second trench t2 may be a curved surface convex downward.

[0152] In some example embodiments, the depth of the first trench t1 may be greater than the depth of the second trench t2. This may be because the width of the first trench t1 is greater than the width of the second trench t2. However, the inventive concept of the present disclosure is not limited thereto. The depth of the first trench t1 may also be less than the depth of the second trench t2.

[0153] In some example embodiments, a portion of the second interlayer insulating film 270 may also be removed. The second interlayer insulating film 270 and the embedded contact PBC have an etching selectivity with respect to each other, but a portion of the second interlayer insulating film 270 may also be removed in the process of removing the embedded contact PBC. In this case, Fig.12 As shown, the second interlayer insulating film 270 may be divided into a first portion 271 and a second portion 272 .

[0154] Reference Fig. 22 , a fence FC and a pseudo buried contact DBC may be formed. The pseudo buried contact DBC may fill the first trench t1. The fence FC may fill the second trench t2. The fence FC and the pseudo buried contact DBC may be formed by the same process. Therefore, the fence FC and the pseudo buried contact DBC may include the same material. As an example, the fence FC and the pseudo buried contact DBC may each be formed as a silicon nitride film.

[0155] In the following, reference will be made to Figure 23 to Figure 28A method of manufacturing a semiconductor memory device according to an example embodiment of the present disclosure is described. Figure 23 to Figure 28 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure.

[0156] Reference Fig.23 , a substrate 100 is provided. The substrate 100 includes a cell region CR, a boundary region BR, and a peripheral region PR.

[0157] A cell element isolation film 103 and a boundary element isolation film 105 may be formed within the substrate 100. Subsequently, a word line structure 110 may be formed. A peripheral circuit element PT may be formed on the substrate 100 in the peripheral region PR.

[0158] The embedded contact PBC may be formed on the cell region CR and a portion of the boundary region BR. The embedded contact PBC may be formed between the paired bit lines BL. The embedded contact PBC may be elongated in the second direction D2. The embedded contact PBC may include at least one of polysilicon doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0159] Reference Fig.24 , a first trench t1 may be formed. The first trench t1 may be formed at a location where a dummy buried contact DBC is to be disposed. Fig.24 Although not shown in the figure, the cell buffer film 120 may be disposed on the substrate 100 in the boundary region BR. Fig.24 As shown, the cell buffer film 120 may be removed in the process of forming the first trench t1. However, the inventive concepts of the present disclosure are not limited thereto. According to some example embodiments, the cell buffer film 120 may be retained in the process of forming the first trench t1.

[0160] Reference Fig.25 , a dummy buried contact DBC may be formed. The dummy buried contact DBC may fill the first trench t1. The dummy buried contact DBC may be formed as a silicon nitride film, but the inventive concept of the present disclosure is not limited thereto.

[0161] Reference Fig.26 , a third mask film MASK3 may be formed on the pre-buried contact PBC, the dummy buried contact DBC, and the second interlayer insulating film 270. The third mask film MASK3 may have an opening that substantially defines the position of the fence FC. The third mask film MASK3 may be formed as at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC) film, or a silicon nitride film.

[0162] Reference Fig. 27, the buried contact PBC may be etched using the third mask film MASK3 as an etching mask. The buried contact BC may be formed by etching the buried contact PBC. In addition, the second trench t2 may be formed by etching the buried contact PBC. The second trench t2 may be formed on the word line structure 110.

[0163] Reference Fig.28 , a fence FC may be formed. The fence FC may fill the second trench t2. The fence FC may not be formed by the same process as the pseudo buried contact DBC. Therefore, the fence FC and the pseudo buried contact DBC may include different materials. However, the inventive concept of the present disclosure is not limited thereto. Even if the fence FC and the pseudo buried contact DBC are formed by different processes, the fence FC and the pseudo buried contact DBC may be made of the same material.

[0164] In the following, reference will be made to Figure 29 to Figure 35 A method of manufacturing a semiconductor memory device according to an example embodiment of the present disclosure is described. Figure 29 to Figure 35 are diagrams for describing intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure.

[0165] Reference Fig.29 , a substrate 100 is provided. The substrate 100 includes a cell region CR, a boundary region BR, and a peripheral region PR.

[0166] A cell element isolation film 103 and a boundary element isolation film 105 may be formed in the substrate 100. The cell element isolation film 103 may be formed in the substrate 100 in the cell region CR, and the boundary element isolation film 105 may be formed in the substrate 100 in the boundary region BR.

[0167] Subsequently, the word line structure 110 may be formed. First, a gate trench may be formed in the substrate 100 of the cell region CR. The gate trench may extend to be elongated in the first direction D1. Some portions of the gate trench may be formed in the cell element isolation film 103. Other portions of the gate trench may be formed in the substrate 100.

[0168] The word line structure 110 may be formed in the gate trench. First, a gate insulating film 111 may be formed along the outline of the gate trench. Subsequently, a gate electrode 112 may be formed on the gate insulating film 111. Subsequently, gate capping films 113 and 114 may be formed on the gate electrode 112.

[0169] A peripheral circuit element PT may be formed on the substrate 100 of the peripheral region PR. In addition, although not shown, a bit line and a direct contact may be formed on the substrate 100 of the cell region CR. The peripheral circuit element PT, the bit line, and the direct contact may be formed by the same process. The peripheral circuit element PT may include a peripheral gate insulating film 220, a peripheral gate structure 230, a peripheral gate capping pattern 240, and a peripheral gate spacer 250. The components of the peripheral gate structure 230 may be respectively disposed at substantially the same level as the components of the bit line structure.

[0170] The cell buffer film 120 formed on the substrate 100 of the cell region CR and the boundary region BR may be exposed. A mold film ML may be formed on the cell buffer film 120. The mold film ML may be made of, for example, an oxide-based insulating material. As an example, the mold film ML may be formed as a silicon oxide film.

[0171] Reference Fig.30 , a fourth mask film MASK4 may be formed on the mold film ML. The fourth mask film MASK4 may have an opening that substantially defines the position of the dummy buried contact DBC. The fourth mask film MASK4 may be formed as at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC) film, or a silicon nitride film.

[0172] Subsequently, a portion of the mold film ML may be removed using the fourth mask film MASK4 as an etching mask. A first trench t1 may be formed by removing a portion of the mold film ML. The first trench t1 may expose the cell buffer film 120.

[0173] Reference Fig.31 , a dummy buried contact DBC may be formed. The dummy buried contact DBC may fill the first trench t1. The dummy buried contact DBC may be formed as a silicon nitride film.

[0174] Reference Fig.32 , the fourth mask film MASK4 may be removed. Subsequently, the third trench t3 may be formed. The third trench t3 may be formed by removing the mold film ML. That is, the third trench t3 may be a space in which the mold film ML is removed. When the third trench t3 is formed, the cell buffer film 120 (see Fig.33 ). That is, the third trench t3 may expose some portions of the substrate 100 of the cell region CR and the upper surface of the word line structure 110 , and the upper surface of the cell element isolation film 103 .

[0175] Reference Fig.33, a pre-buried contact PBC may be formed. A pre-buried contact PBC may be formed in the third trench t3. The pre-buried contact PBC may include at least one of polysilicon doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal.

[0176] Reference Fig.34 , a fifth mask film MASK5 may be formed on the pre-buried contact PBC, the dummy buried contact DBC, and the second interlayer insulating film 270. The fifth mask film MASK5 may have an opening that substantially defines the position of the fence FC. The fifth mask film MASK5 may be formed as at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC) film, or a silicon nitride film.

[0177] Reference Fig.35 , the buried contact PBC may be etched using the fifth mask film MASK5 as an etching mask. The buried contact BC may be formed by etching the buried contact PBC. In addition, a second trench may be formed by etching the buried contact PBC. The second trench may be formed on the word line structure 110.

[0178] A fence FC may be formed in the second groove. The fence FC may not be formed by the same process as the pseudo buried contact DBC. Therefore, the fence FC and the pseudo buried contact DBC may include different materials. However, the inventive concept of the present disclosure is not limited thereto. Even if the fence FC and the pseudo buried contact DBC are formed by different processes, the fence FC and the pseudo buried contact DBC may be made of the same material.

[0179] Some example embodiments of the present disclosure have been described above with reference to the accompanying drawings, but the present disclosure is not limited to the above example embodiments and can be implemented in various different forms. A person skilled in the art in the art to which the present disclosure belongs can understand that the present disclosure can be implemented in other specific forms without changing the technical spirit, inventive concept or basic features of the present disclosure. Therefore, it should be understood that the above example embodiments are illustrative and not restrictive in all aspects.

Claims

1. A semiconductor memory device, comprising: a substrate comprising a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; A plurality of gate electrodes extending along a first direction within the substrate of the cell region; a plurality of bit lines extending on the substrate in the cell region and the boundary region along a second direction intersecting the first direction; a plurality of buried contacts connected to a substrate of the cell region on the substrate of the cell region and between the gate electrodes and between the bit lines; a dummy buried contact located between the bit lines on the substrate in the boundary region; as well as a bit line contact connected to at least one of the bit lines on the substrate in the boundary region, Wherein, the pseudo buried contact comprises insulating material.

2. The semiconductor memory device according to claim 1, further comprising: a fence between corresponding pairs of the bit lines and between corresponding pairs of the buried contacts, Wherein, the fence comprises the same material as the dummy buried contact.

3. The semiconductor memory device according to claim 2, wherein: A first distance from an upper surface of a corresponding one of the buried contacts to a bottom surface of the corresponding one of the buried contacts is smaller than a second distance from an upper surface of the corresponding one of the buried contacts to a bottom surface of the fence.

4. The semiconductor memory device according to claim 3, wherein: A third distance from an upper surface of the corresponding one of the buried contacts to a bottom surface of the dummy buried contact is equal to the second distance.

5. The semiconductor memory device according to claim 3, wherein: A third distance from the upper surface of the corresponding one of the buried contacts to the bottom surface of the dummy buried contact is different from the second distance.

6. The semiconductor memory device according to claim 1, further comprising: A cell buffer film is located between the dummy buried contact and the substrate in the boundary region.

7. The semiconductor memory device according to claim 1, wherein: A level of a bottom surface of a corresponding one of the buried contacts is different from a level of a bottom surface of the dummy buried contact.

8. The semiconductor memory device according to claim 1, wherein: A level of a bottom surface of a corresponding one of the buried contacts is the same as a level of a bottom surface of the dummy buried contact.

9. The semiconductor memory device according to claim 1, wherein: At least a portion of the bit line contact is in contact with the dummy buried contact.

10. The semiconductor memory device according to claim 1, wherein The bit line contact includes a first contact connected to one of the bit lines and a second contact connected to another of the bit lines, and At least one of the bit lines is located between the first contact and the second contact.

11. A semiconductor memory device comprising: a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, the cell region including a capacitor, and the peripheral region including a peripheral circuit element; A plurality of gate electrodes extending along a first direction within the substrate of the cell region; a plurality of first bit lines extending on the substrate of the cell region along a second direction intersecting the first direction; a plurality of second bit lines, the plurality of second bit lines being respectively connected to the first bit lines on the substrate in the boundary region; a plurality of fences and a plurality of buried contacts alternately arranged along the second direction between the first bit lines; a dummy buried contact located between the second bit lines; as well as bit line contacts contacting at least some of the second bit lines on the substrate in the boundary region, wherein a width of a corresponding one of the first bit lines in the first direction is smaller than a width of a corresponding one of the second bit lines in the first direction, and The dummy buried contact includes an insulating material.

12. The semiconductor memory device according to claim 11, further comprising: a pair of second bit line spacers respectively located on two opposite side walls of each of the second bit lines, Wherein, at least one of the second bit line spacers is in contact with the dummy buried contact.

13. The semiconductor memory device according to claim 12, further comprising: a pair of first bit line spacers respectively located on two opposite side walls of each of the first bit lines, The paired first bit line spacers are respectively connected to the paired second bit line spacers.

14. The semiconductor memory device according to claim 11, wherein: A bottom surface of a corresponding one of the fences has the same level as a bottom surface of the dummy buried contact.

15. The semiconductor memory device according to claim 11, wherein A material included in the fence is the same as a material included in the dummy buried contact.

16. The semiconductor memory device according to claim 15, wherein: A first distance from an upper surface of a corresponding one of the buried contacts to a bottom surface of the corresponding one of the buried contacts is smaller than a second distance from an upper surface of the corresponding one of the buried contacts to a bottom surface of the corresponding one of the fences.

17. The semiconductor memory device according to claim 11, further comprising: A cell buffer film is located between the dummy buried contact and the substrate in the boundary region.

18. The semiconductor memory device according to claim 11, wherein At least a portion of the bit line contact is in contact with the dummy buried contact.

19. The semiconductor memory device according to claim 11, wherein: The substrate of the cell region includes an impurity region located between the gate electrodes, and The buried contacts are connected to the impurity regions, respectively.

20. A semiconductor memory device comprising: a substrate comprising a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; Peripheral circuit elements, which are on the substrate in the peripheral region; A plurality of gate electrodes extending along a first direction within the substrate of the cell region; a plurality of bit lines extending on the substrate in the cell region and the boundary region along a second direction intersecting the first direction; a plurality of buried contacts, the plurality of buried contacts being on the substrate of the cell region and spaced apart in the second direction, the buried contacts being connected to the substrate of the cell region, the buried contacts being located between the gate electrodes and between the bit lines; a plurality of capacitors, the plurality of capacitors being respectively connected to the buried contacts on the substrate of the cell region; a plurality of fences, the plurality of fences being between the buried contacts and between the gate electrodes, the fences being spaced apart from each other in the second direction and on the substrate of the cell region; a dummy buried contact located between the bit lines on the substrate in the boundary region; as well as a bit line contact connected to at least one of the bit lines on the substrate in the boundary region, wherein a first distance from an upper surface of a corresponding one of the buried contacts to a bottom surface of the corresponding one of the buried contacts is less than a second distance from the upper surface of the corresponding one of the buried contacts to a bottom surface of the corresponding one of the fences, At least a portion of the dummy buried contact contacts the substrate of the boundary region, and The dummy buried contact and the fence include the same material.

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