Memory device and manufacturing method thereof

Abstract

A method of manufacturing a memory device includes forming a bit line structure over a substrate; conformally forming a first spacer layer over the bit line structure; carrying out surface treatment on the upper part of the first spacing layer, and after the surface treatment, the oxygen concentration of the upper part of the first spacing layer is higher than that of the lower part of the first spacing layer; removing an upper portion of the first spacer layer; forming a contact structure adjacent to the bit line structure; and forming a landing pad over the contact structure and the bit line structure. The method can be used for reducing the depth-to-width ratio of the grooves between the bit line structures so as to reduce the difficulty of filling the grooves between the bit line structures.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for manufacturing the same. Background Art

[0002] A typical dynamic random access memory (DRAM) cell combines a capacitor and a transistor, where the capacitor temporarily stores data based on the charge state of the capacitor. The bit line is electrically connected to one of the source / drain regions of the transistor, and the word line is electrically connected to the gate region of the transistor. As semiconductor dimensions shrink and density increases, the aspect ratio of semiconductor structures increases, which leads to difficulties in deposition gap fill performance. Summary of the invention

[0003] Some embodiments of the present invention provide a method for manufacturing a memory device, comprising the following steps: forming a bit line structure above a substrate; conformally forming a first spacer layer above the bit line structure; performing surface treatment on an upper portion of the first spacer layer, wherein after the surface treatment, an oxygen concentration in the upper portion of the first spacer layer is higher than an oxygen concentration in a lower portion of the first spacer layer; removing an upper portion of the first spacer layer; forming a contact structure adjacent to the bit line structure; and forming a landing pad above the contact structure and the bit line structure.

[0004] In some embodiments, the step of performing the surface treatment includes the step of performing an oxygen-containing plasma treatment or a hydrogen-containing plasma treatment on the upper portion of the first spacer layer.

[0005] In some embodiments, after the surface treatment, a silicon concentration in an upper portion of the first spacer layer is lower than a silicon concentration in a lower portion of the first spacer layer.

[0006] In some embodiments, the surface treatment is performed at an oblique angle.

[0007] In some embodiments, the manufacturing method further includes the following steps: after performing surface treatment, conformally forming a second spacer layer above the first spacer layer; forming a photoresist layer covering a lower portion of the second spacer layer, wherein an upper portion of the second spacer layer is exposed by the photoresist layer; and removing the upper portion of the second spacer layer.

[0008] In some embodiments, an upper portion of the second spacer layer is removed simultaneously with an upper portion of the first spacer layer.

[0009] In some embodiments, the manufacturing method further includes the following steps: after removing the upper portion of the first spacer layer and the upper portion of the second spacer layer, conformally forming a third spacer layer over the bit line structure and the second spacer layer, wherein the upper portion of the third spacer layer contacts the bit line structure.

[0010] In some embodiments, the second spacer layer is sandwiched by a lower portion of the third spacer layer and the first spacer layer.

[0011] In some embodiments, the landing pad is spaced apart from the first spacer layer.

[0012] In some embodiments, the bottom of the landing pad is higher than the top of the first spacer layer.

[0013] Some embodiments of the present invention provide a memory device, including a bit line structure, a bit line spacer, and a landing pad. The bit line spacer is arranged along the side wall of the bit line structure, and includes a first spacer, a second spacer, and a third spacer, the first spacer is in contact with the lower part of the side wall of the bit line structure, the second spacer is arranged along the side wall of the first spacer, and the third spacer is arranged along the side wall of the second spacer, wherein the third spacer extends to the upper part of the side wall of the bit line structure. The landing pad is located above the bit line structure.

[0014] In some embodiments, the third spacer layer contacts a top end of the first spacer layer.

[0015] In some embodiments, an interface between the first spacer layer and the bit line structure is aligned with an interface between the third spacer layer and the bit line structure.

[0016] In some embodiments, a top end of the first spacer layer is substantially flush with a top end of the second spacer layer.

[0017] In some embodiments, the landing pad is spaced apart from the first spacer layer.

[0018] In some embodiments, the bottom surface of the landing pad is higher than the top of the first spacer layer.

[0019] In some embodiments, a top end of the first spacer layer is lower than a top surface of the bit line structure.

[0020] In some embodiments, the third spacer layer vertically overlaps the first spacer layer.

[0021] In some embodiments, the third spacer layer has a portion vertically located between the landing pad and the first spacer layer.

[0022] In some embodiments, the first spacer layer and the third spacer layer are made of different materials.

[0023] It is to be understood that both the foregoing general description and the following detailed description are exemplary descriptions, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The content of the present invention may be more fully understood by reading the detailed description of the following embodiments in conjunction with the accompanying drawings:

[0025] Figure 1 A circuit diagram illustrating a memory device.

[0026] Figure 2 A top view illustrating a method of manufacturing a memory device in some embodiments of the present disclosure.

[0027] Figures 3 to 11 Description Figure 2 A cross-sectional view of the memory device taken along line AA' in FIG.

[0028] Fig.12 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated.

[0029] Fig.13 and Fig.14 Separate description Fig.12 sectional views of the memory device taken along lines AA' and BB'.

[0030] Fig.15 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated.

[0031] Fig.16 and Fig.17 Separate description Fig.15 sectional views of the memory device taken along lines AA' and BB'.

[0032] Fig.18 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated.

[0033] Fig.19 illustrate Fig.18 A cross-sectional view of the memory device taken along line AA' in FIG.

[0034] Fig. 20 Description Fig.18 A cross-sectional view of a memory device taken along line BB′ in FIG.

[0035] Fig.21 illustrate Fig.18 A cross-sectional view of the memory device taken along line AA' in FIG.

[0036] Fig. 22 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated.

[0037] Fig.23 Description Fig. 22 A cross-sectional view of a memory device taken along line AA′ in FIG. DETAILED DESCRIPTION

[0038] Figure 1 A circuit diagram illustrating a memory device. Figure 1, a memory device (e.g., a dynamic random access memory (DRAM)) may include a plurality of memory cells MC. A typical DRAM memory cell combines a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on the charge state of the capacitor CA. The capacitor CA is electrically connected to a source / drain region of the transistor TR, a bit line BL is electrically connected to another source / drain region of the transistor TR, and a word line WL is electrically connected to a gate region of the transistor TR. In the present invention, we focus on the manufacturing process of the bit line and the capacitor. The manufacturing process of the word line and the transistor will not be mentioned in the present invention.

[0039] Figure 2 A top view of a method for manufacturing a memory device in some embodiments of the present invention is illustrated. The memory device includes an active area AA, a word line WL, and a bit line structure 110. The word line WL is located above the active area AA, and the bit line structure 110 is located above the word line WL. The word line WL and the bit line structure 110 are along different directions. For example, the longitudinal direction of the word line WL is perpendicular to the longitudinal direction of the bit line structure 110. The word line WL divides each active area AA into three regions. The regions at both ends of the active area AA will be connected to the capacitor, and the middle region will be connected to the bit line structure 110.

[0040] Figures 3 to 11 Description Figure 2 A cross-sectional view of the memory device taken along line AA' in FIG. Figures 3 to 11 The word line WL is not shown in FIG. Figure 3 , providing a substrate 100. An isolation structure 102 is formed in the substrate 100 and defines Figure 2 The active area AA in the dielectric layer 106 is formed on the substrate 100 and the isolation structure 102. A recess R1 may be formed in the substrate 100 and the isolation structure 102 that are not covered by the dielectric layer 106. The substrate 100 may be made of a semiconductor, such as silicon. The isolation structure 102 may be made of silicon oxide, silicon nitride, etc. The dielectric layer 106 may be made of silicon oxide, silicon nitride, etc.

[0041] Subsequently, a bit line contact 108 and a bit line structure 110 are formed over the substrate 100 and the dielectric layer 106. The bit line structure 110 is located over the bit line contact 108, and each bit line structure 110 includes a conductive layer 112, a conductive layer 114 located over the conductive layer 112, and a cap layer 116 located over the conductive layer 114. The bit line contact 108 and the bit line structure 110 can be formed by, for example, sequentially forming a conductive material layer and a cap material layer over the substrate 100. Subsequently, the conductive material layer and the cap material layer are patterned into the bit line contact 108 and the bit line structure 110 including the conductive layer 112, the conductive layer 114, and the cap layer 116. Adjacent bit line structures 110 define a trench T1. In some embodiments, the width of the trench T1 is between 30 nanometers and 50 nanometers. In some embodiments, the width of the bit line structure 110 is between 8 nanometers and 12 nanometers. In some embodiments, the bit line contact 108 may be made of polysilicon. The conductive layer 112 may be made of a metal nitride, such as titanium nitride. The conductive layer 114 may be made of a metal, such as tungsten. The cap layer 116 may be made of a dielectric material, such as silicon nitride. In some embodiments, a portion of the bit line structure 110 may be formed in the recess R1.

[0042] See also Figure 4 , a spacer layer 122, an etch stop layer 124, and a filling layer 126 are sequentially formed over the substrate 100, the isolation structure 102, the dielectric layer 106, and the bit line structure 110. Specifically, the spacer layer 122 may be conformally formed over the bit line structure 110 and lined with the recess R1. Subsequently, the spacer layer 122 is surface treated so that the outer portion of the spacer layer 122 is converted into the etch stop layer 124. Subsequently, a filling layer 126 is conformally formed over the etch stop layer 124. The filling layer 126 is thicker than the spacer layer 122 and the etch stop layer 124, and the filling layer 126 fills the recess R1. The spacer layer 122, the etch stop layer 124, and the filling layer 126 are all made of dielectric materials. In some embodiments, the spacer layer 122 and the filling layer 126 are made of silicon nitride, and the etch stop layer 124 is made of silicon oxide. In some other embodiments, the spacer layer 122 is made of a low-k material, such as SiC, SiCO, SiCN, and the etch stop layer 124 may be omitted. In some embodiments, the thickness of the spacer layer 122 is between 4 nanometers and 6 nanometers.

[0043] See also Figure 5, an etching process is performed to remove a portion of the etching stop layer 124 and the filling layer 126 above the dielectric layer 106. After the etching process is completed, a portion of the etching stop layer 124 and the filling layer 126 in the groove R1 still remain. The etching stop layer 124 can protect the spacer layer 122 from being etched by the etching process, so the spacer layer 122 still remains after the etching process is completed. In some embodiments, the etching process can be a wet etching process using hot phosphoric acid as an etchant.

[0044] See also Figure 6 and Figure 7 , the upper portion of the spacer layer 122 is subjected to surface treatment to change the properties of the spacer layer 122. Specifically, the surface treatment may be an oxygen-containing plasma treatment, a hydrogen-containing plasma treatment, an oxygen-containing implantation process, or a hydrogen-containing implantation process, and the surface treatment is performed at an inclined angle. That is, the incident direction of the implant or plasma may be inclined to the normal of the substrate 100. In some embodiments, the inclination angle may be about 25° to 45°. In some embodiments, the surface treatment may be performed at an angle of about 10° to about 15°. Figure 6 The surface is treated in the first direction D1, and then Figure 7 Surface treatment is performed in the second direction D2 of the spacer layer 122. Since the depth-width ratio of the trench T1 between the bit line structures 110 is relatively large, the surface treatment has little effect on the properties of the lower portion of the spacer layer 122. After the surface treatment is completed, the oxygen concentration of the upper portion of the spacer layer 122 is higher than the oxygen concentration of the lower portion of the spacer layer 122, and the silicon concentration of the upper portion of the spacer layer 122 is lower than the silicon concentration of the lower portion of the spacer layer 122. In some other embodiments, when the spacer layer 122 is a carbon-containing layer, after the surface treatment is completed, the carbon concentration of the upper portion of the spacer layer 122 is lower than the carbon concentration of the lower portion of the spacer layer 122. Therefore, after the surface treatment is completed, the properties of the upper portion of the spacer layer 122 and the lower portion of the spacer layer 122 are different.

[0045] See also Figure 8 After surface treatment, a spacer layer 128 is conformally formed on the spacer layer 122. The spacer layer 128 is made of a dielectric material that is different from the material of the spacer layer 122. In some embodiments, the spacer layer 128 is made of silicon oxide. In some embodiments, the thickness of the spacer layer 128 is between 4 nanometers and 6 nanometers.

[0046] See also Fig. 9 A photoresist layer PR is formed on the spacer layer 128 and overfills the trench T1 between the bit line structures 110, and then the photoresist layer PR is etched back so that the photoresist layer PR covers the lower portion of the spacer layer 128. The upper portion of the spacer layer 128 is exposed by the photoresist layer PR.

[0047] See also Fig.10, an etching process is performed to remove the upper portion of the spacer layer 128 and the upper portion of the spacer layer 122. The photoresist layer PR does not cover the upper portion of the spacer layer 128 and the upper portion of the spacer layer 122, and thus can be etched by a suitable etching process. The etching process has an etching selectivity between the oxide-based material and other materials. In some embodiments, Fig.10 The etching process in the etching process etches silicon oxide faster than other materials (such as silicon nitride). In some embodiments, the higher the oxygen concentration of the spacer layer 122, the faster the etching process removes the spacer layer 122; the lower the silicon concentration of the spacer layer 122, the faster the etching process removes the spacer layer 122; and the lower the carbon concentration of the spacer layer 122, the faster the etching process removes the spacer layer 122. Since the upper portion of the spacer layer 122 has been processed and has a higher oxygen concentration, the properties of the upper portion of the spacer layer 122 are similar to silicon oxide. Therefore, when removing the upper portion of the spacer layer 128, it is also easy to remove the upper portion of the spacer layer 122. Since the upper portion of the spacer layer 122 is removed, the opening of the trench T1 becomes wider, so the aspect ratio of the trench T1 becomes smaller. After the etching process is completed, the top of the spacer layer 122 is lower than the top surface of the bit line structure 110. After the etching process is completed, the top of the spacer layer 122 is substantially flush with the top of the spacer layer 128. After removing the upper portion of the spacer layer 122 and the upper portion of the spacer layer 128 , the photoresist layer PR is stripped off.

[0048] See also Fig.11 , after removing the upper portion of the spacer layer 122 and the upper portion of the spacer layer 128, a spacer layer 129 is conformally formed over the bit line structure 110 and the spacer layer 128. The upper portion of the spacer layer 129 contacts the capping layer 116 of the bit line structure 110. The spacer layer 128 is sandwiched by the lower portion of the spacer layer 129 and the spacer layer 122. The interface between the spacer layer 122 and the bit line structure 110 is aligned with the interface between the spacer layer 129 and the bit line structure 110. The spacer layer 129 is made of a dielectric material, such as silicon nitride. In some embodiments, the spacer layer 122 and the spacer layer 129 are made of the same material; for example, the spacer layer 122 and the spacer layer 129 are both made of silicon nitride. In some other embodiments, the spacer layer 122 and the spacer layer 129 are made of different materials, for example, the spacer layer 122 is made of a high-k dielectric material, and the spacer layer 129 is made of silicon nitride. The spacer layer 122 is completely covered and protected by the spacer layer 129. In the embodiment where the spacer layer 122 is made of a low-k material, the spacer layer 122 is easily oxidized and easily removed in a subsequent process, which will result in a connection between the conductive layer 114 and the components formed in the subsequent process. Therefore, in the context of the present invention, the spacer layer 122 covered by the spacer layer 129 will not be removed in a subsequent process. In some embodiments, the thickness of the spacer layer 122 is between 4 nanometers and 6 nanometers. In some embodiments, the spacer layers 122, 128, and 129 can be collectively referred to as bit line spacers.

[0049] Fig.12 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated. Fig.13 and Fig.14 Describe along Fig.12 A cross-sectional view of the memory device taken along lines AA' and BB' in FIG. Fig.12 Only the bit line structure 110 and the sacrificial layer 130 are illustrated. Fig.12 Other components are omitted. Fig.12 , Fig.13 and Fig.14 , a sacrificial layer 130 is formed over the substrate 100 and the bit line structure 110 and overfills the trench T1. In some embodiments, the sacrificial layer 130 may be formed by spin-on dielectric coating. As the upper portion of the spacer layer 122 is removed, the opening of the trench T1 becomes wider, resulting in a better gap filling performance of the sacrificial layer 130.

[0050] Subsequently, a planarization process is performed to remove the excess portion of the sacrificial layer 130 until the top of the bit line structure 110 is exposed. Subsequently, the sacrificial layer 130 is patterned so that the sacrificial layer 130 covers a portion of the substrate 100 (eg, Fig.13 ), while the sacrificial layer 130 does not cover another portion of the substrate 100 (as shown Fig.14 ). The spacer layer 129 completely covers the spacer layer 122. Therefore, even if the spacer layer 122 is oxidized in the previous stage, the spacer layer 129 prevents the process of patterning the sacrificial layer 130 from removing the spacer layer 122. Materials formed in subsequent processes will not contact the bit line structure 110. After patterning the sacrificial layer 130, the top of the bit line structure 110 is partially etched, and the top of the bit line structure 110 that is not adjacent to the sacrificial layer 130 becomes a curve. The top of the bit line structure 110 that is not adjacent to the sacrificial layer 130 is lower than the top of the bit line structure 110 that is adjacent to the sacrificial layer 130. Partially removing the bit line structure 110 can reduce the aspect ratio of the trench T1 between the bit line structures 110, thereby reducing the difficulty of filling the material in the subsequent process. The sacrificial layer 130 is made of a dielectric material that is different from the material of the spacer layer 129. In some embodiments, the sacrificial layer 130 can be made of silicon oxide.

[0051] Fig.15 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated. Fig.16 and Fig.17 Describe along Fig.15 A cross-sectional view of the memory device taken along lines AA' and BB' in FIG. Fig.15 Only the bit line structure 110, the sacrificial layer 130 and the isolation layer 140 are illustrated. Fig.15Other components are omitted. Fig.15 , Fig.16 and Fig.17 , the isolation layer 140 overfills the trench T1 and is formed above the bit line structure 110. In some embodiments, the isolation layer 140 may be formed by low pressure chemical vapor deposition (LPCVD). As the upper portion of the spacer layer 122 is removed, the opening of the trench T1 becomes wider, resulting in better gap filling performance of the isolation layer 140.

[0052] Subsequently, a planarization process is performed to remove the excess portion of the isolation layer 140 until the top of the bit line structure 110 is exposed. Since the top of the bit line structure 110 not adjacent to the sacrificial layer 130 is lower than the top of the bit line structure 110 adjacent to the sacrificial layer 130, the top of the bit line structure 110 not adjacent to the sacrificial layer 130 is still covered by the isolation layer 140. The isolation layer 140 is made of a dielectric material that is different from the material of the sacrificial layer 130. In some embodiments, the isolation layer 140 may be made of silicon nitride.

[0053] Fig.18 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated. Fig.19 and Fig.21 Description Fig.18 A cross-sectional view of the memory device taken along line AA' in FIG. Fig. 20 Description Fig.18 A cross-sectional view of the memory device taken along line BB' in FIG. Fig.18 Only the bit line structure 110 and the isolation layer 140 are illustrated. Fig.18 Other components are omitted. Fig.18 , Fig.19 and Fig. 20 , an etching process may be performed to remove the sacrificial layer 130. Since the material of the sacrificial layer 130 is different from that of the spacer layer 129 and the isolation layer 140, a suitable etching process may be selected to remove the sacrificial layer 130 without substantially removing the spacer layer 129 and the isolation layer 140. The adjacent isolation layer 140 defines a trench T2.

[0054] See also Fig.21 , an etching process is performed to etch away a portion of the spacer layer 128 and the spacer layer 129 in the trench T2, thereby forming a recess R2 exposing the substrate 100. The recess R1 (see Figure 3 ) are also partially etched. The remaining portions of the spacer layer 128 and the spacer layer 129 covered by the isolation layer 140 are not etched.

[0055] Fig. 22 A top view of a memory device in accordance with some embodiments of the present disclosure is illustrated. Fig.23 Description Fig. 22 A cross-sectional view of the memory device taken along line AA' in FIG. Fig. 22 Only the bit line structure 110, the isolation layer 140 and the contact structure 150 are illustrated. Fig. 22 Other components are omitted. Fig. 22 and Fig.23 , the contact structure 150 is formed near the bit line structure 110 and in the trench T2. Specifically, the contact structure 150 is formed by sequentially forming a conductive layer 152, a conductive layer 154, and a conductive layer 156 in the trench T2. In some embodiments, the conductive layer 152 may be made of doped polysilicon, the conductive layer 154 may be made of a metal silicide (such as CoSi), and the conductive layer 156 may be made of a metal (such as tungsten). Subsequently, a landing pad 160 is formed over and in contact with the bit line structure 110 and the contact structure 150, and the landing pad 160 is spaced apart from the spacer layer 122 and the spacer layer 128. The bottom surface of the landing pad 160 is higher than the top of the spacer layer 122. In some embodiments, the landing pad 160 may be made of a metal (such as tungsten). The conductive layer 152 of the contact structure 150 contacts the substrate 100 , and the contact structure 150 and the landing pad 160 provide a connection between the substrate 100 and a capacitor to be formed subsequently.

[0056] Subsequently, a groove is formed through the landing pad 160, and an isolation structure 170 is formed in the groove. The bottom of the isolation structure 170 contacts the cap layer 116, the spacer layers 122, 128, 129 and the contact structure 150 of the bit line structure 110. The isolation structure 170 is used to isolate adjacent landing pads 160. After the isolation structure 170 is formed, a capacitor (not shown) is formed above the landing pad 160.

[0057] The resulting memory device is Fig.23 The memory device includes a bit line structure 110, a bit line spacer, and a landing pad 160. The bit line spacer is disposed along the sidewall of the bit line structure 110, and includes a spacer 122, a spacer 128, and a spacer 129. The spacer 122 is in contact with the lower portion of the sidewall of the bit line structure 110. The spacer 128 is disposed along the sidewall of the spacer 122. The spacer 129 is disposed along the sidewall of the spacer 128, and the spacer 129 extends to the upper portion of the sidewall of the bit line structure 110. The spacer 129 is in contact with the top of the spacer 122. The landing pad 160 is located above the bit line structure 110. The spacer 129 vertically overlaps the spacer 122, and the spacer 129 has a portion vertically located between the landing pad 160 and the spacer 122.

[0058] As described above, the present invention is used to reduce the aspect ratio of the trenches between the bit line structures 110. Therefore, it is easier to fill materials in the trenches between the bit line structures 110. Specifically, the aspect ratio of the trenches between the bit line structures 110 can be reduced by surface treating the spacer layer 122 composed of silicon nitride or low-k material along the sidewalls of the bit line structures 110. Therefore, the upper portion of the spacer layer 122 has a higher oxygen concentration. The upper portion of the spacer layer 122 can be removed by an etching process for removing the spacer layer 128 composed of silicon oxide, and the width of the trenches between the bit line structures 110 can be widened to reduce the aspect ratio.

[0059] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0060] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In summary, the present invention is intended to cover modifications and variations of the present invention as long as such modifications and variations fall within the scope of the claims.

[0061]

Explanation of symbols

[0062] 100:Substrate

[0063] 102, 170: Isolation structure

[0064] 106: Dielectric layer

[0065] 108: Bit line contact

[0066] 110: Bit line structure

[0067] 112, 114, 152, 154, 156: conductive layer

[0068] 116: Covering layer

[0069] 122, 128, 129: spacer layer

[0070] 124: Etching stop layer

[0071] 126: Filling layer

[0072] 130: Sacrificial layer

[0073] 140: Isolation layer

[0074] 150: Contact structure

[0075] 160: Landing Pad

[0076] AA: Active Area

[0077] A-A', B-B': line

[0078] BL: Bit Line

[0079] CA:Capacitor

[0080] D1: First direction

[0081] D2: Second direction

[0082] MC:Memory Cell

[0083] PR: Photoresist layer

[0084] R1, R2: Groove

[0085] T1, T2: Groove

[0086] TR: Transistor

[0087] WL: character line.

Claims

1. A method for manufacturing a memory device, characterized in that: The following steps are involved: forming a bit line structure over the substrate; conformally forming a first spacer layer over the bit line structure; Performing a surface treatment on the upper portion of the first spacer layer, wherein after the surface treatment, the oxygen concentration of the upper portion of the first spacer layer is higher than the oxygen concentration of the lower portion of the first spacer layer; removing the upper portion of the first spacer layer; forming a contact structure adjacent to the bit line structure; and A landing pad is formed over the contact structure and the bit line structure.

2. The manufacturing method according to claim 1, characterized in that: The surface treatment step comprises the following steps: The upper portion of the first spacer layer is subjected to an oxygen-containing plasma treatment or a hydrogen-containing plasma treatment.

3. The manufacturing method according to claim 1, characterized in that: After the surface treatment, the silicon concentration of the upper portion of the first spacer layer is lower than the silicon concentration of the lower portion of the first spacer layer.

4. The manufacturing method according to claim 1, characterized in that: The surface treatment is performed at an oblique angle.

5. The manufacturing method according to claim 1, characterized in that: Further comprising the following steps: After performing the surface treatment, conformally forming a second spacer layer on the first spacer layer; forming a photoresist layer covering a lower portion of the second spacer layer, wherein the upper portion of the second spacer layer is exposed by the photoresist layer; and The upper portion of the second spacer layer is removed.

6. The manufacturing method according to claim 5, characterized in that: The upper portion of the second spacing layer and the upper portion of the first spacing layer are removed simultaneously.

7. The manufacturing method according to claim 5, characterized in that: Further comprising the following steps: After removing the upper portion of the first spacer layer and the upper portion of the second spacer layer, a third spacer layer is conformally formed over the bit line structure and the second spacer layer, wherein an upper portion of the third spacer layer contacts the bit line structure.

8. The manufacturing method according to claim 7, characterized in that: The second spacing layer is sandwiched by the lower part of the third spacing layer and the first spacing layer.

9. The manufacturing method according to claim 1, characterized in that: The landing pad is separated from the first spacing layer.

10. The manufacturing method according to claim 1, characterized in that: The bottom of the landing pad is higher than the top of the first spacing layer.

11. A memory device, characterized in that: Include: bit line structure; A bit line spacer is disposed along a sidewall of the bit line structure and comprises: a first spacer layer in contact with a lower portion of the sidewall of the bit line structure; A second spacer layer is disposed along a side wall of the first spacer layer; and A third spacer layer is disposed along the sidewall of the second spacer layer, wherein the third spacer layer extends to an upper portion of the sidewall of the bit line structure; and A landing pad is located above the bit line structure.

12. The memory device according to claim 11, wherein: The third spacer layer contacts the top of the first spacer layer.

13. The memory device according to claim 11, wherein: The interface between the first spacer layer and the bit line structure is aligned with the interface between the third spacer layer and the bit line structure.

14. The memory device according to claim 11, wherein: The top of the first spacer layer is substantially flush with the top of the second spacer layer.

15. The memory device according to claim 11, wherein: The landing pad is separated from the first spacing layer.

16. The memory device according to claim 11, wherein: The bottom surface of the landing pad is higher than the top of the first spacing layer.

17. The memory device according to claim 11, wherein: The top of the first spacer layer is lower than the top surface of the bit line structure.

18. The memory device according to claim 11, wherein: The third spacer layer overlaps the first spacer layer vertically.

19. The memory device according to claim 11, wherein: The third spacer layer has a portion vertically located between the landing pad and the first spacer layer.

20. The memory device according to claim 11, wherein: The first spacing layer and the third spacing layer are made of different materials.

Images