Chip packaging structure and device

Abstract

The invention provides a chip packaging structure and equipment, the chip packaging structure comprises a circuit board, a chip and a central processing unit, the circuit board comprises at least two packaging areas, the packaging areas comprise a first packaging area and a second packaging area which are sequentially arranged along a first direction, and the chip is at least packaged in the first packaging area and the second packaging area. The central processing unit is packaged on the circuit board and arranged on the same side of the chip, the central processing unit and the chip can be connected through wires in the circuit board, and the first packaging area and the second packaging area are provided with signal point positions close to the central processing unit. The chip packaging structure provided by the invention is convenient in wiring, and / or high in signal transmission rate consistency, and less in electromagnetic interference and signal crosstalk.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and equipment. Background Art

[0002] LPDDR (Low Power Double Data Rate SDRAM) chip is a communication standard developed by the American JEDEC (Joint Electron Device Engineering Council) Association for low-power memory. It is known for its low power consumption and small size and is specifically used in mobile devices.

[0003] In the process of conceiving and implementing the present application, the inventors found that there are at least the following problems: some multi-channel (for example, 4-channel) LPDDR chip packaging solutions all stack the LPDDR chip on the central processing unit (Central Processing Unit / Processor, referred to as CPU). The LPDDR chip is directly packaged on the central processing unit using the package on package (POP) process. However, when the chip adopts the stacking packaging process, the distance between different chips and the central processing unit is different, and the signal of the upper chip needs to pass through more layers to reach the bottom central processing unit, resulting in a longer signal path, increased delay, and affected transmission rate. In turn, the signal transmission rate of different chips may be inconsistent. And / or, when signal transmission is performed, especially when high-speed signal transmission is required, the electromagnetic interference and signal crosstalk of the chip packaging structure using the stacking packaging process will also increase significantly.

[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the invention

[0005] In response to the above technical problems, the present application provides a chip packaging structure and device, the chip packaging structure has convenient routing, and / or high consistency of signal transmission rate, and less electromagnetic interference and signal crosstalk.

[0006] The present application provides a chip packaging structure, including: a circuit board, including at least two packaging areas, the packaging areas including a first packaging area and a second packaging area arranged in sequence along a first direction; a chip, at least packaged in the first packaging area and the second packaging area; a central processing unit, packaged in the circuit board and located on the same side of the chip; the central processing unit and the chip are connected through wiring in the circuit board.

[0007] Optionally, both the first packaging area and the second packaging area are provided with signal points close to the central processing unit.

[0008] Optionally, at least one data input / output point and / or at least one blank point are arranged in the signal points of the first packaging area and the second packaging area close to the central processing unit.

[0009] Optionally, in a row of signal points near the central processing unit in the first packaging area, two data input and output points are provided, and there is a blank point between the two data input and output points; and / or, in a row of signal points near the central processing unit in the second packaging area, two data input and output points are provided, and there is a blank point between the two data input and output points.

[0010] Optionally, in a row of signal points in the first packaging area away from the second packaging area, power input and output points and blank points are arranged.

[0011] Optionally, in a row of signal points in the first packaging area away from the second packaging area, there is a blank point between two adjacent power input and output points.

[0012] Optionally, the packaging area further includes a third packaging area and a fourth packaging area sequentially arranged along the first direction, the third packaging area is symmetrically arranged with the second packaging area, and the fourth packaging area is symmetrically arranged with the first packaging area.

[0013] Optionally, there is at least one row of blank spots between the second packaging area and the third packaging area.

[0014] Optionally, there are no blank spots in a row of signal spots where the second packaging area and the third packaging area are close to each other.

[0015] Optionally, the diameter of the electrical contact ball used to form the signal point is 0.20-0.35 mm.

[0016] Optionally, along the first direction, the ball spacing between adjacent electrical balls is 0.35-0.65 mm.

[0017] Optionally, along the second direction, the ball spacing between adjacent electrical balls is 0.35-0.65 mm.

[0018] Another aspect of the present application provides a device, comprising any chip packaging structure as described above.

[0019] The device may be a chip (such as a memory chip or a SOC chip set, etc.), or may be an electronic device (such as a smart terminal).

[0020] The chip packaging structure and device provided in the present application include a circuit board, a chip and a central processing unit. The circuit board includes at least two packaging areas, and the packaging areas include a first packaging area and a second packaging area sequentially arranged along a first direction. The chip can be packaged in at least the first packaging area and the second packaging area. The central processing unit is packaged on the circuit board and arranged on the same side of the chip. The central processing unit and the chip can be connected through wiring in the circuit board. Among them, the first packaging area and the second packaging area are both provided with signal points near the central processing unit.

[0021] Since the first package area and the second package area are both arranged on the same side of the central processing unit, and the first package area and the second package area are both arranged with signal points close to the central processing unit, when the first package area and the central processing unit are connected, and the second package area and the central processing unit are connected through wiring in the circuit board, the length of the signal transmission path between the first package area and the second package area and the central processing unit can be relatively consistent, which helps to ensure that the delay and loss of signal transmission are similar, thereby improving the consistency of signal transmission rate between each package area.

[0022] And / or, setting the signal point close to the central processor can also significantly shorten the distance of signal transmission, which is not only beneficial to wiring design and reduces complex cross wiring, but also reduces the delay of signal transmission. And / or, a shorter signal transmission path can also reduce the energy loss during the transmission process, thereby reducing the overall power.

[0023] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the chip packaging structure and equipment provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0025] Figure 1 A cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the external connection between the chip packaging structure and the central processing unit provided in the embodiment of the present application;

[0027] Figure 3 A schematic diagram of a layout of signal points on a circuit board provided in an embodiment of the present application;

[0028] Figure 4 Another schematic diagram of the layout of signal points on a circuit board provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of a connection between a chip packaging structure and a central processing unit provided in an embodiment of the present application;

[0030] Figure 6 Another schematic diagram of the connection between the chip packaging structure and the central processing unit provided in the embodiment of the present application;

[0031] Figure 7 A schematic diagram of the hardware structure of a mobile terminal for implementing various embodiments of the present application.

[0032] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0033] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. Optionally, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment.

[0035] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following" etc. used in this application can be interpreted as inclusive, or mean any one or any combination. For example, “comprising at least one of the following: A, B, C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”, and for another example, “A, B or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A and B and C”. An exception to this definition will only occur when a combination of elements, functions, steps or operations are inherently mutually exclusive in some manner.

[0036] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0037] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0039] LPDDR chip is a kind of volatile memory product, which is characterized by low power consumption and small size, and is specially used in mobile devices. In some schemes, multi-channel (for example, 4-channel) LPDDR chip packaging schemes are to stack LPDDR chips on the central processing unit (CPU). The package on package (POP) process is used to directly package the LPDDR chip on the central processing unit.

[0040] When the chip adopts the stacking packaging process, the distance between different chips and the central processor is different. The signal of the upper chip needs to pass through more layers to reach the bottom central processor, which makes the signal path longer, increases the delay, and affects the transmission rate. In turn, it may cause the signal transmission rate of different chips to be inconsistent. And / or, when signal transmission is performed, especially when high-speed signal transmission is required, the electromagnetic interference and signal crosstalk of the chip packaging structure using the stacking packaging process will also increase significantly.

[0041] Take smartphones as an example. If the signal transmission rates of internal memory chips are inconsistent, the chips with lower signal transmission rates will limit the overall motherboard data processing speed. This may lead to longer application loading time, slower data processing, and / or unstable phone performance due to electromagnetic interference and signal crosstalk inside the motherboard, such as application crashes, system restarts, or freezes.

[0042] In view of this, an embodiment of the present application provides a chip packaging structure and a device, wherein the chip packaging structure includes a circuit board, a chip and a central processing unit, wherein the circuit board includes at least two packaging areas, wherein the packaging areas include a first packaging area and a second packaging area sequentially arranged along a first direction, and the chip can be packaged in at least the first packaging area and the second packaging area. The central processing unit is packaged on the circuit board and arranged on the same side of the chip. The central processing unit and the chip can be connected through wiring in the circuit board. Optionally, the first packaging area and the second packaging area are both provided with signal points near the central processing unit.

[0043] Since the first package area and the second package area are both arranged on the same side of the central processing unit, and the first package area and the second package area are both arranged with signal points close to the central processing unit, when the first package area and the central processing unit are connected, and the second package area and the central processing unit are connected through wiring in the circuit board, the length of the signal transmission path between the first package area and the second package area and the central processing unit can be relatively consistent, which helps to ensure that the delay and loss of signal transmission are similar, thereby improving the consistency of signal transmission rate between each package area.

[0044] Optionally, setting the signal point close to the central processor can also significantly shorten the distance of signal transmission, which is not only beneficial to wiring design and reduces complex cross wiring, but also reduces the delay of signal transmission. And / or, a shorter signal transmission path can also reduce the energy loss during the transmission process, thereby reducing the overall power consumption.

[0045] The chip packaging structure and the device equipped with the chip packaging structure provided in the embodiments of the present application are described in detail below.

[0046] The chip packaging structure provided in the embodiment of the present application can be applied to large equipment or small equipment. The equipment can be a terminal device, which can also be called a terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), etc.

[0047] The devices include, but are not limited to, mobile phones, smart TVs, wearable devices, tablet computers, computers with wireless transceiver functions, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0048] Figure 1 A cross-sectional view of a chip packaging structure provided in an embodiment of the present application. Figure 1 As shown, the chip packaging structure in this embodiment includes a circuit board 100 and a chip 200. The circuit board 100 is provided with at least two packaging areas 110 (not shown in the figure), and correspondingly, the chip 200 is packaged in at least two packaging areas 110.

[0049] Optionally, the chip 200 referred to here may be a memory, or the chip 200 is a storage chip, for example, the chip 200 is the aforementioned LPDDR chip. In addition to the chip 200, other devices may be provided on the circuit board 100. Optionally, other devices such as a processor and a power manager may be provided on the circuit board 100. The circuit board 100 serves to carry these devices and realize communication connection between these devices.

[0050] Optionally, a package area 110 can form a separate storage channel in the memory chip, which makes it easier for designers to select and configure different storage channels as needed to meet different performance and capacity requirements. By packaging the storage channels separately, faults can be isolated and the impact of single point failures can be reduced. When multiple package areas 110 architectures are used, the memory chip controller can communicate with multiple storage channels at the same time. Optionally, each channel can transmit data independently, thereby improving overall data throughput and system performance. Optionally, the memory chip controller can be a central processor 400 (such as Figure 2 shown).

[0051] Optionally, the circuit board 100 may be a main board in the device, and the circuit board 100 includes but is not limited to a printed circuit board (PCB), a flexible printed circuit (FPC), and a hard-soft combined circuit board.

[0052] Optionally, at least one chip 200 is disposed in one package area 110, and the specific number of chips 200 is not limited. Optionally, only one chip 200 is disposed in one package area 110, thereby reducing the difficulty of design and manufacturing and reducing the communication delay between chips 200.

[0053] Optionally, a package area 110 may be provided with multiple chips 200 (such as 2, 3, or 4), so that the chips packaged in a single package area can be flexibly designed, the chip size is smaller, and the layout is more flexible. The following is an example of a package area 110 consisting of a chip 200.

[0054] Optionally, when the circuit board 100 is provided with two packaging areas 110, the two packaging areas 110 may be arranged side by side up and down or side by side left and right, which is not limited here. In this way, the arrangement of the packaging areas 110 can be flexibly adjusted according to specific needs or the positions of other devices on the circuit board 100, thereby effectively utilizing the space of the circuit board 100.

[0055] Optionally, the number of package areas 110 on the circuit board 100 may be an even number greater than or equal to 2. Optionally, the number of chips 200 may also be an even number greater than or equal to 2. Taking the number of package areas 110 on the circuit board 100 as 4 as an example, every two package areas 110 may form a group of package areas 110, and may be symmetrically distributed with another group of package areas 110, and the chips 200 contained in each package area 110 may be symmetrically arranged in pairs. This may simplify subsequent connection and wiring.

[0056] Optionally, refer to Figure 1 As shown, a plurality of electrical balls 300 are arranged between the chip 200 and the circuit board 100, and the electrical balls 300 are used to electrically connect the chip 200 to the circuit board 100. The plurality of electrical balls 300 can be arranged in an array as a whole. Optionally, the electrical balls 300 generally refer to solder balls or conductive bumps. Optionally, the electrical balls 300 can be tin balls or copper balls.

[0057] Optionally, the edge region of the chip 200 may be provided with pins, and the pins of the chip 200 are connected to the circuits arranged inside the chip 200, so that the internal circuit of the chip 200 is led out through the pins and connected to the external circuit. These electrical balls 300 may be electrically connected to the pins of the chip 200 through the circuits inside the chip 200, so that the circuit board 100 can transmit signals to the external circuit through the chip 200 to realize the electrical connection between the chip 200 and the external circuit.

[0058] Optionally, each pin of the chip 200 has a specific function for transmitting signals of different functions. Optionally, each pin transmits data transmission signals, power signals, control signals, ground signals and other signals between the chip 200 and the external circuit. When the chip 200 is packaged on the circuit board 100, the pins of the chip 200 are electrically connected to the corresponding electrical balls 300 through the internal circuits of the chip 200. This connection method can ensure that the signals on the pins can be accurately transmitted to the electrical balls 300, thereby realizing signal transmission between the chip 200 and the external circuit.

[0059] Optionally, the plurality of electrical balls 300 disposed between the chip 200 and the circuit board 100 may be considered as a plurality of signal points disposed in the packaging area 110 of the circuit board 100, and the plurality of signal points are led out by the pins of the chip 200. Optionally, each signal point is used to transmit a different signal.

[0060] Figure 2 This is a schematic diagram of the external connection of the chip packaging structure provided in the embodiment of the present application. Figure 2 As shown, the chip packaging structure also includes a central processing unit 400, and the central processing unit 400 is packaged on the circuit board 100. Optionally, the central processing unit 400 can be connected to the circuit board 100 through the electrical ball 300 to reduce the length of the signal path and improve the electrical performance. And / or, the central processing unit 400 can be electrically connected to each chip 200 through the wiring in the circuit board 100, so that the central processing unit 400 can adjust and control the working state of each chip 200.

[0061] Optionally, the CPU 400 is disposed on the same side of each package area 110. In this way, the circuits arranged in each package area 110 on the circuit board 100 can be led out from one side of the chip 200, thereby simplifying the wiring between the chip package structure and the CPU 400 and reducing the wiring difficulty of the circuit board 100. Figure 2 Taking the paper direction shown in as an example, the central processing unit 400 is arranged on the left side of each chip 200, and the lines arranged in the packaging area 110 on the circuit board 100 can be led out from the left side of the chip 200.

[0062] Figure 3 A schematic diagram of the layout of signal points on a circuit board provided in an embodiment of the present application. Figure 3 As shown, the package area 110 on the circuit board 100 may include a first package area 111 and a second package area 112. Correspondingly, the chip 200 may be packaged in the first package area 111 and the second package area 112. The first package area 111 and the second package area 112 are both provided with signal points close to the central processor 400 to facilitate wiring connection between the first package area 111, the second package area 112 and the central processor 400. Optionally, the first package area 111 and the second package area 112 may be arranged in sequence along a first direction. The first direction may be Figure 3 and Figure 4 The Y direction shown in Figure 3 and Figure 4 The X direction perpendicular to the Y direction may be defined as the second direction. The first encapsulation area 111 and the second encapsulation area 112 may both be rectangular, and the adjacent two sides of the rectangle extend along the X direction and the Y direction respectively.

[0063] Optionally, the arrangement of the first encapsulation area 111 and the second encapsulation area 112 in the first direction can be flexibly set. Optionally, the first encapsulation area 111 and the second encapsulation area 112 can be arranged adjacent to each other along the first direction, or the first encapsulation area 111 and the second encapsulation area 112 can be arranged alternately in the first direction.

[0064] Optionally, the first packaging area 111 and the second packaging area 112 constitute a basic packaging unit as a whole, and at least one basic packaging unit is provided on the circuit board 100. On this basis, other packaging units may be provided on the circuit board, and the other packaging units may be symmetrically provided with the basic packaging unit.

[0065] Optionally, since each packaging area 110 is electrically connected to the circuit board 100 through a plurality of electrical balls 300, the area occupied by an electrical ball 300 can be defined as a signal point. Here, the interval arrangement between the first packaging area 111 and the second packaging area 112 means that the first packaging area 111 and the second packaging area 112 are completely separated in the first direction. Optionally, the adjacent areas of the first packaging area 111 and the second packaging area 112 in the first direction are separated by blank points. In other words, there are signal points where the electrical balls 300 are not set in the adjacent areas of the first packaging area 111 and the second packaging area 112.

[0066] Optionally, the first packaging area 111 and the second packaging area 112 are arranged adjacent to each other, which means that the first packaging area 111 and the second packaging area 112 are not completely separated in the first direction. Optionally, there is at least one blank point in the adjacent area of ​​the first packaging area 111 and the second packaging area 112 in the first direction. That is to say, in the first direction, there is at least one signal point of the electrical contact ball 300 in the adjacent area of ​​the first packaging area 111 and the second packaging area 112.

[0067] Optionally, the first packaging area 111 and the second packaging area 112 can be designed to be narrow and long, the first direction is the width direction of the first packaging area 111 and the second packaging area 112, and the second direction is the length direction of the first packaging area 111 and the second packaging area 112. In this way, the packaging unit formed by the first packaging area 111 and the second packaging area 112 as a whole has a closer length and width and is roughly square. The layout of the packaging unit is more reasonable, and the signal point distribution is more uniform, which is convenient for chip design and packaging. And / or, on the basis of the packaging unit, other packaging units are added symmetrically, and the overall layout design is more regular.

[0068] The following description is made by taking the first packaging area 111 and the second packaging area 112 as an example of being arranged adjacent to each other along the first direction. Figure 3 As shown, each signal point position can be arranged in an array along the X direction and the Y direction. A group of signal points located at the same position in the X direction and arranged in sequence along the Y direction is defined as a column of signal points. A group of signal points located at the same position in the Y direction and arranged in sequence along the X direction is defined as a row of signal points. Optionally, the first packaging area 111 and the second packaging area 112 can have signal points in different rows or columns. Optionally, each packaging area 110 can be divided into three sub-areas, and the three sub-areas in this embodiment are defined as a first functional area 121, a second functional area 122 and a third functional area 123 respectively. The first functional area 121, the second functional area 122 and the third functional area 123 can all be arranged in sequence along the second direction.

[0069] Optionally, within the packaging area 110, all signal points (or all electrical balls 300) are distributed within the first functional area 121, the second functional area 122 and the third functional area 123, and there are no signal points (or electrical balls 300) outside the first functional area 121, the second functional area 122 and the third functional area 123.

[0070] Optionally, the arrangement of the first functional area 121, the second functional area 122 and the third functional area 123 in the second direction can be flexibly set. Optionally, the first functional area 121, the second functional area 122 and the third functional area 123 can be arranged adjacent to each other along the second direction, and the first functional area 121, the second functional area 122 and the third functional area 123 can also be arranged at intervals in the second direction. Optionally, the first functional area 121 and the second functional area 122 are arranged adjacent to each other, and the second functional area 122 and the third functional area 123 are arranged at intervals. Optionally, the first functional area 121 and the second functional area 122 are arranged at intervals, and the second functional area 122 and the third functional area 123 are arranged adjacent to each other.

[0071] Optionally, the interval arrangement here refers to that the adjacent functional areas in the second direction are completely separated, and the adjacent functional areas in the second direction are separated by blank points. The adjacent arrangement means that the adjacent functional areas in the second direction are not completely separated, and there is no blank point in at least one of the adjacent areas in the second direction between the adjacent functional areas. By arranging the first functional area 121, the second functional area 122 and the third functional area 123 in close proximity, the space occupied by the packaging area 110 on the circuit board 100 can be reduced, thereby reducing the overall volume of the packaging area 110, which is convenient for the arrangement of other devices on the circuit board 100. And / or, it can also shorten the routing length, increase the transmission speed, and reduce signal delay and signal attenuation.

[0072] Optionally, the following description is made by taking the first functional area 121, the second functional area 122 and the third functional area 123 as an example of being arranged adjacent to each other along the second direction. Figure 3 As shown, along the first direction, the first packaging area 111 may be provided with 6 rows of signal points, and the second packaging area 112 may be provided with 5 rows of signal points. Figure 3 The six rows of signal points from row A to row F are the encapsulation range of the first encapsulation area 111. The five rows of signal points from row G to row L are the encapsulation range of the second encapsulation area 112. And / or, the first encapsulation area 111 and the second encapsulation area 112 may each include 17 columns of signal points.

[0073] Optionally, the first functional area 121, the second functional area 122, and the third functional area 123 arranged in sequence along the second direction together constitute 17 columns of signal points contained in each packaging area 110. Optionally, the first functional area 121 includes 6 columns of signal points, the second functional area 122 includes 4 columns of signal points, and the third functional area 123 includes 7 columns of signal points. That is, the first to sixth columns are the first functional area 121. The seventh to tenth columns are the second functional area 122. The eleventh to seventeenth columns are the third functional area 123.

[0074] Optionally, the first functional area 121 of the first packaging area 111 may be an overlapping area enclosed by the 1st to 6th columns and the Ath to Fth rows. The second functional area 122 of the first packaging area 111 may be an overlapping area enclosed by the 7th to 10th columns and the Ath to Fth rows. The third functional area 123 of the first packaging area 111 may be an overlapping area enclosed by the 11th to 17th columns and the Ath to Fth rows.

[0075] Optionally, the first functional area 121 of the second packaging area 112 may be an overlapping area enclosed by the 1st to 6th columns and the Gth to Lth rows. The second functional area 122 of the second packaging area 112 may be an overlapping area enclosed by the 7th to 10th columns and the Gth to Lth rows. The third functional area 123 of the second packaging area 112 may be an overlapping area enclosed by the 11th to 17th columns and the Gth to Lth rows.

[0076] Optionally, all signal points within the packaging area 110 may include data input and output points (DQ), power input and output points (VDD), ground points (VSS), chip select points (CS), address points (CA), clock points (WCK), differential clock signal points (CK), differential synchronization signal points (RDQS), and input data mask points (DMI).

[0077] Optionally, at least one data input / output point (DQ) may be arranged in the signal points near the central processing unit 400 in the first packaging area 111 and the second packaging area 112, or at least one blank point may be arranged, or at least one data input / output point (DQ) and at least one blank point may be arranged.

[0078] Optionally, when at least one data input / output point (DQ) is arranged in a row of signal points close to the central processor 400 in the first packaging area 111 and the second packaging area 112, the signal transmission distance will be significantly shortened, thereby reducing the delay of data transmission. And / or, a shorter transmission path can support a higher frequency and a faster data transmission rate to achieve rapid processing of large amounts of data.

[0079] Optionally, when a plurality of blank points are arranged in a row of signal points near the central processor 400 in the first packaging area 111 and the second packaging area 112, it can facilitate the wiring connection between the chip 200 and the circuit board 100 to reduce possible electromagnetic interference and crosstalk between signal lines.

[0080] Optionally, the following describes in detail the distribution design of each signal point in the first packaging area 111 and the second packaging area 112. Optionally, when the circuit board 100 is provided with two packaging areas 110, the first packaging area 111 and the second packaging area 112, the electrical contact ball 300 arranged in each packaging area 110 can be used as a separate chip 200 signal transmission channel. Figure 3 As shown, the first packaging area 111 may form a separate chip 200 signal transmission channel A. The second packaging area 112 may form a separate chip 200 signal transmission channel C.

[0081] Optionally, the data input and output points (DQ) for transmitting data can be distributed entirely in the first functional area 121 and the third functional area 123. By clearly dividing the area where the data input and output points (DQ) are located, a flexible arrangement of multiple data input and output points (DQ) can be achieved. It is also convenient for the layout design of other signal points. And / or, the distribution of the data input and output points (DQ) on both sides can also provide an independent wiring area for each packaging area 110 to reduce signal crossing. Thus, the chip 200 can be connected to the circuit board 100 by directly outputting a line from one side of the packaging area 110, thereby realizing the parallel connection of the chip 200 and the central processing unit 400 on the circuit board 100.

[0082] Optionally, since the central processing unit 400 is disposed on one side of the chip 200, data input and output points (DQ) are distributed on the side close to the central processing unit, which can also reduce signal delays in data transmission and facilitate wiring.

[0083] Optionally, the number of data input / output points (DQ) arranged in the first functional area 121 may be the same as the number of data input / output points (DQ) arranged in the third functional area 123. By evenly distributing all data input / output points (DQ), it is possible to avoid the phenomenon that one of the first functional area 121 and the third functional area 123 has too many data input / output points (DQ). And / or, the first functional area 121 and the third functional area 123 may reserve more space for arranging other signal points.

[0084] Optionally, in this embodiment, all data input / output points (DQs) arranged in one of the first functional area 121 and the third functional area 123 in a single package area 110 are defined as a first group of data input / output points, and all data input / output points (DQs) arranged in the other of the first functional area 121 and the third functional area 123 in a single package area 110 are defined as a second group of data input / output points. Both the first group of data input / output points and the second group of data input / output points include the same number of data input / output points (DQs).

[0085] Optionally, on the basis that the number of data input and output points (DQ) in the first group of data input and output points and the number of data input and output points (DQ) in the second group of data input and output points are the same, this embodiment does not limit the layout position of each data input and output point (DQ) in the first group of data input and output points and the layout position of each data input and output point (DQ) in the second group of data input and output points.

[0086] Optionally, refer to Figure 3 As shown, the number of data input and output points (DQ) in each package area 110 is the same, and the number of data input and output points (DQ) in a single package area 110 can be 16. That is, the first package area 111 and the second package area 112 are both provided with 16 data input and output points (DQ), and are respectively set to DQ0-DQ15. Among them, the number of the first group of data input and output points is 8, respectively DQ0-DQ7. The number of the second group of data input and output points is also 8, respectively DQ8-DQ15.

[0087] Optionally, taking the chip 200 as channel A as an example, the 16 data input and output points (DQ) in channel A are respectively DQ0 A-DQ15 A. Optionally, taking the first group of data input and output points arranged in the first functional area 121 and the second group of data input and output points arranged in the third functional area 123 as an example, the 8 data input and output points (DQ) arranged in the first functional area 121 are respectively DQ0A-DQ7 A, and the 8 data input and output points (DQ) arranged in the third functional area 123 are respectively DQ8A-DQ15A. The 8 data input and output points (DQ) DQ0A-DQ7A arranged in the first functional area 121 are distributed in rows B-F, columns 1-2, and columns 4-6. The eight data input and output points (DQ) DQ8A-DQ15A arranged in the second functional area 122 are distributed in the Bth row to the Fth row and the 11th column to the 16th column.

[0088] Optionally, taking the chip 200 as a C channel as an example, the 16 data input and output points (DQ) in the C channel are also DQ0 A-DQ15 A. Optionally, taking the first group of data input and output points arranged in the first functional area 121 and the second group of data input and output points arranged in the third functional area 123 as an example, the 8 data input and output points (DQ) arranged in the first functional area 121 are DQ0C-DQ7C respectively, and the 8 data input and output points (DQ) arranged in the third functional area 123 are DQ8C-DQ15C respectively. The 8 data input and output points (DQ) DQ0C-DQ7C arranged in the first functional area 121 are distributed in the Gth row-Lth row, the 1st column-the 2nd column, and the 5th column-the 6th column. The eight data input and output points (DQ) DQ8C-DQ15C arranged in the third functional area 123 are distributed in the Gth row to the Hth row, the Kth row to the Lth row, the 11th column to the 13th column, and the 15th column to the 16th column. In this way, the data input and output points are arranged preferentially in a limited space, which improves the data throughput, thereby significantly improving the data transmission capability and parallel processing capability of the chip 200.

[0089] Optionally, at least one data input / output point (DQ) and at least one blank point may be arranged in a row of signal points closest to the central processor 400 in the first packaging area 111 (A channel) and the second packaging area 112 (C channel), that is, in the first column of signal points.

[0090] Optionally, the data input and output points (DQ) are preferably set close to the central processing unit 400, which not only facilitates the wiring of the data input and output signal lines, but also shortens the signal transmission path, reduces signal delay and attenuation, and improves signal integrity. Optionally, the setting of multiple blank points facilitates the wiring connection with the central processing unit 400, can ensure that there is sufficient spacing between adjacent lines, and the risk of short circuit of the lines arranged in the circuit board 100 and the chip 200 is small, thereby improving the reliability of the chip packaging structure.

[0091] Optionally, in the first column of signal points in the first packaging area 111 and the second packaging area 112 , blank points may be arranged at least on one side of the data input / output point (DQ) for easy wiring.

[0092] Optionally, two data input / output points (DQ) may be provided in the first column of signal points in the first packaging area 111, and a blank point may be provided between the two data input / output points (DQ). Alternatively, two data input / output points (DQ) may be provided in the first column of signal points in the second packaging area 112, and a blank point may be provided between the two data input / output points (DQ).

[0093] Optionally, two data input / output points (DQ) may be provided in the first column of signal points in the first packaging area 111 and the second packaging area 112, and a blank point may be provided between the two data input / output points (DQ).

[0094] By leaving a blank point between two data input and output points, the wiring arrangement of the data input and output signal lines can be facilitated, and / or, physical isolation of different data input and output points can be achieved, electromagnetic interference between adjacent signal lines can be reduced, and signal integrity and transmission quality can be improved. And / or, a thermal buffer can also be established to help dissipate heat and prevent the performance of the data input and output points from being affected by overheating.

[0095] Optionally, a set of clock points (WCK) may be provided in the first functional area 121 and the third functional area 123 of each packaging area 110. The clock points (WCK) may achieve precise timing alignment. Optionally, each set of clock points (WCK) may include a write clock point (WCK T) and a read clock point (WCK C).

[0096] Optionally, the write clock point (WCK T) and the read clock point (WCK C) are arranged diagonally adjacent to each other. That is, the write clock point (WCK T) and the read clock point (WCK C) are located at the diagonal ends of adjacent rows and adjacent columns (e.g. Figure 3 As shown). Optionally, the write clock point (WCK T) and the read clock point (WCK C) are arranged adjacent to each other in rows and columns. Optionally, the write clock point (WCK T) and the read clock point (WCK C) can be arranged at adjacent positions in the same row, and the write clock point (WCKT) and the read clock point (WCK C) can also be arranged at adjacent positions in the same column.

[0097] Such a configuration can more easily achieve clock signal synchronization, help ensure that the clock signals for write and read operations remain consistent, and improve the reliability of data transmission. It can also reduce crosstalk and interference between signals and improve signal integrity. And / or, it can also provide more flexible wiring path selection, reduce wiring complexity and crossover, simplify wiring design, and reduce manufacturing costs.

[0098] In this embodiment, two groups of clock points (WCK) are arranged in a single package area 110, and the two groups of clock points can be defined as a first clock point (WCK0) and a second clock point (WCK1), respectively. One of the first clock point (WCK0) and the second clock point (WCK1) can be arranged in the first functional area 121, and the other can be arranged in the third functional area 123. The first clock point (WCK0) includes a first write clock point (WCK0 T) and a first read clock point (WCK0C) arranged adjacently, and the second clock point (WCK1) can include a second write clock point (WCK1 T) and a second read clock point (WCK1 C) arranged adjacently.

[0099] Alternatively, if Figure 3 As shown, taking the chip 200 as channel A as an example, the first clock point (WCK0) may be located in the first functional area 121, the first write clock point (WCK0 TA) may be located in the Dth row and the 4th column in the first functional area 121, and the first read clock point (WCK0 CA) may be located in the Eth row and the 3rd column in the first functional area 121. The second clock point (WCK1) may be located in the third functional area 123, the second write clock point (WCK1 TA) may be located in the Dth row and the 12th column in the third functional area 123, and the second read clock point (WCK1 CA) may be located in the Eth row and the 13th column in the third functional area 123.

[0100] Optionally, taking the chip 200 as a C channel as an example, the first clock point (WCK0) may be located in the first functional area 121, the first write clock point (WCK0 TC) may be located in the Kth row and the 4th column in the first functional area 121, and the first read clock point (WCK0 CC) may be located in the Jth row and the 3rd column in the first functional area 121. The second clock point (WCK1) may be located in the third functional area 123, the second write clock point (WCK1 TC) may be located in the Jth row and the 13th column in the third functional area 123, and the second read clock point (WCK1 CC) may be located in the Kth row and the 12th column in the third functional area 123.

[0101] Optionally, a set of differential synchronization signal points (RDQS) may be provided in the first functional area 121 and the third functional area 123 of each packaging area 110. The differential synchronization signal points (RDQS) may implement a synchronous data reading operation.

[0102] Optionally, each group of differential synchronization signal points (RDQS) may include a differential write synchronization signal point (RDQS T) and a differential read synchronization signal point (RDQS C). The differential write synchronization signal point (RDQS T) and the differential read synchronization signal point (RDQS C) may be arranged diagonally adjacent to each other or in rows and columns adjacent to each other. This facilitates the positioning of the differential synchronization signal points (RDQS) and the layout of the differential synchronization lines (for transmitting differential synchronization signals) in the circuit board 100 and the chip 200.

[0103] In this embodiment, two groups of differential synchronization signal points (RDQS) may be arranged in a single package area 110, and in this embodiment, the two groups of differential synchronization signal points (RDQS) are defined as a first differential synchronization signal point (RDQS0) and a second differential synchronization signal point (RDQS1). One of the first differential synchronization signal point (RDQS0) and the second differential synchronization signal point (RDQS1) may be arranged in the first functional area 121, and the other may be arranged in the third functional area 123. The first differential synchronization signal point includes a first differential read synchronization signal point (RDQS0 C) and a first differential write synchronization signal point (RDQS0 T) that are adjacently arranged, and the second differential synchronization signal point may include a second differential read synchronization signal point (RDQS1C) and a second differential write synchronization signal point (RDQS1 T) that are adjacently arranged.

[0104] Optionally, one of the first differential synchronization signal point (RDQS0) and the second differential synchronization signal point (RDQS1) arranged in the first functional area 121, the differential read synchronization signal point (RDQSC) and the differential write synchronization signal point (RDQS T) in the group of differential synchronization signal points (RDQS) can be adjacently arranged along the first direction, can be adjacently arranged along the second direction, and can also be diagonally adjacently arranged.

[0105] Alternatively, if Figure 3 As shown, taking the chip 200 as channel A as an example, the first differential synchronization signal point (RDQS0 A) can be located in the first functional area 121, the first differential read synchronization signal point (RDQS0C A) can be located in the Cth row and the 3rd column in the first functional area, and the first differential write synchronization signal point (RDQS0T A) can be located in the Bth row and the 4th column in the third functional area 123. The second differential synchronization signal point (RDQS1 A) can be located in the third functional area 123, the second differential read synchronization signal point (RDQS1C A) can be located in the Dth row and the 14th column in the third functional area 123, and the second differential write synchronization signal point (RDQS1T A) can be located in the Cth row and the 15th column in the third functional area 123.

[0106] Optionally, taking the chip 200 as the C channel as an example, the first differential synchronization signal point (RDQS0 C) can be located in the first functional area 121, the first differential read synchronization signal point (RDQS0 CC) can be located in the Hth row and the 4th column in the first functional area, and the first differential write synchronization signal point (RDQS0 TC) can be located in the Gth row and the 3rd column in the third functional area 123. The second differential synchronization signal point (RDQS1 C) can be located in the third functional area 123, the second differential read synchronization signal point (RDQS1CC) can be located in the Hth row and the 14th column in the third functional area 123, and the second differential write synchronization signal point (RDQS1 TC) can be located in the Jth row and the 15th column in the third functional area 123.

[0107] Optionally, an input data mask point (DMI) may be evenly distributed in the first functional area 121 and the third functional area 123 in the single package area 110. In this embodiment, two input data mask points (DMI) are defined as a first input data mask point (DMI0) and a second input data mask point (DMI1). One of the first input data mask point (DMI0) and the second input data mask point (DMI1) may be located in the first functional area 121, and the other may be located in the third functional area 123.

[0108] Alternatively, if Figure 3 As shown, taking the chip 200 as channel A as an example, the first input data mask point (DMI0 A) is arranged at the Fth row and the third column in the first functional area 121, and the second input data mask point (DMI1 A) is arranged at the Fth row and the fourteenth column in the third functional area 123.

[0109] Optionally, taking chip 200 as C channel as an example, the first input data mask point (DMI0 C) is arranged in the Lth row and the third column in the first functional area 121, and the second input data mask point (DMI1 C) is arranged in the Kth row and the fourteenth column in the third functional area 123.

[0110] Optionally, the main signal points of the second functional area 122 are introduced below. Figure 3 As shown, differential clock signal points (CK) are distributed in the second functional area 122. Optionally, a group of differential clock signal points (CK) are provided in the second functional area 122. Optionally, each group of differential clock signal points (CK) may include a write differential clock signal point (CK T) and a read differential clock signal point (CK C).

[0111] Optionally, the write differential clock signal point (CK T) and the read differential clock signal point (CK C) are arranged diagonally adjacent to each other, that is, the write differential clock signal point (CK T) and the read differential clock signal point (CK C) are located at the diagonal ends of adjacent rows and adjacent columns.

[0112] Such an arrangement facilitates the positioning of the differential clock signal point (CK) and also facilitates the layout of the differential clock lines (for transmitting differential clock signals) in the circuit board 100 and the chip 200 .

[0113] In this embodiment, a group of differential clock signal points (CK) are arranged in a single package area 110, and the group of differential clock signal points (CK) are arranged in the second functional area 122. In other words, the write differential clock signal point (CK T) and the read differential clock signal point (CK C) are both arranged in the second functional area 122.

[0114] Alternatively, if Figure 3 As shown, taking chip 200 as channel A as an example, the write differential clock signal point (CK TA) can be located at the Dth row and the 8th column in the second functional area 122, and the read differential clock signal point (CK CA) can be located at the Eth row and the 9th column in the second functional area 122.

[0115] Optionally, taking chip 200 as a C channel as an example, the write differential clock signal point (CK TC) can be located at the Hth row and the 8th column in the second functional area 122, and the read differential clock signal point (CK CC) can be located at the Jth row and the 9th column in the second functional area 122.

[0116] Optionally, chip selection points (CS) are further distributed in the second functional area 122. Optionally, the chip selection points (CS) may include a first chip selection point (CS 0) and a second chip selection point (CS 1). And / or, the first chip selection point (CS 0) and the second chip selection point (CS 1) are adjacently arranged along a diagonal.

[0117] Such an arrangement facilitates the positioning of the chip select point (CS) and also facilitates the layout of the chip select signal lines (for transmitting chip select signals) in the circuit board 100 and the chip 200 .

[0118] In this embodiment, a group of chip select points (CS) are arranged in a single package area 110, and the group of chip select points (CS) are arranged in the second functional area 122. In other words, the first chip select point (CS0) and the second chip select point (CS1) are arranged in the second functional area 122.

[0119] Alternatively, if Figure 3As shown, taking the chip 200 as channel A as an example, the first chip selection point (CS 0A) and the second chip selection point (CS1A) can be located at the Cth row and the 7th column and the Bth row and the 8th column in the second functional area 122, respectively.

[0120] Optionally, taking the chip 200 as a C channel as an example, the first chip selection point (CS 0C) and the second chip selection point (CS1C) can be located at the Kth row and the 8th column and the Lth row and the 9th column in the second functional area 122, respectively.

[0121] Optionally, the second functional area 122 is also provided with some address points (CA). Multiple address points (CA) may be provided, and are preferentially provided in unoccupied signal points in the second functional area 122. And the remaining address points (CA) may be provided adjacent to the second functional area 122. For example, the remaining address points (CA) may be provided in the signal points in an adjacent column of the first functional area 121 close to the second functional area 122. The remaining address points (CA) may also be provided in the signal points in an adjacent column of the third functional area 123 close to the second functional area 122. Of course, the remaining address points (CA) may also be provided in the signal points in an adjacent column of the first functional area 121 close to the second functional area 122 and in the signal points in an adjacent column of the third functional area 123 close to the second functional area 122. In this embodiment, a single packaging area 110 is provided with a plurality of address points (CA), and the plurality of address points (CA) include a first address point (CA0), a second address point (CA1), a third address point (CA2), a fourth address point (CA3), a fifth address point (CA4), a sixth address point (CA5), and a seventh address point (CA6).

[0122] Alternatively, if Figure 3 As shown, taking the chip 200 as channel A as an example, the first address point (CA0 A) can be located at the Dth row and the 6th column in the first functional area 121, and the second address point (CA1 A) can be located at the Eth row and the 7th column in the second functional area 122. The third address point (CA2 A) can be located at the Fth row and the 8th column in the second functional area 122. The fourth address point (CA4 A) can be located at the Cth row and the 9th column in the second functional area 122. The fifth address point (CA5 A) can be located at the Fth row and the 10th column in the second functional area 122. The sixth address point (CA6 A) can be located at the Dth row and the 10th column in the second functional area 122. The seventh address point (CA7 A) can be located at the Bth row and the 10th column in the second functional area 122.

[0123] Optionally, taking the chip 200 as the C channel as an example, the first address point (CA0 C) can be located at the Hth row and the 6th column in the first functional area 121, and the second address point (CA1 A) can be located at the Gth row and the 7th column in the second functional area 122. The third address point (CA2 A) can be located at the Jth row and the 7th column in the second functional area 122. The fourth address point (CA3 A) can be located at the Kth row and the 10th column in the second functional area 122. The fifth address point (CA4 A) can be located at the Hth row and the 10th column in the second functional area 122. The sixth address point (CA5 A) can be located at the Lth row and the 11th column in the third functional area 123. The seventh address point (CA6 A) can be located at the Jth row and the 11th column in the third functional area 123.

[0124] Optionally, continue to refer to Figure 3 , a single package area 110 includes multiple power input and output points (VDD) and ground points (VSS). The power input and output points (VDD) and ground points (VSS) can be distributed in the first functional area 121, the second functional area 122 and the third functional area 123. In this way, the power input and output points (VDD) and the ground points (VSS) can be distributed more evenly in the entire package area 110110, which is convenient for arranging the power lines (for transmitting power signals) and the ground lines (for transmitting ground signals) in the circuit board 100 and the chip 200. And / or, more scattered space can be reserved to facilitate the layout of other signal points.

[0125] Optionally, except for a row of signal points in the first package area 111 away from the second package area 112 and a column of signal points close to the central processor 400, the ground points (VSS) may be arranged alternately in the remaining rows and columns. And / or, the ground points (VSS) between adjacent rows or adjacent columns are arranged diagonally.

[0126] Optionally, the power input and output points (VDD) may be preferentially arranged in a row of signal points in the first packaging area 111 away from the second packaging area 112 (eg Figure 3 The A row in FIG. 1 is used to facilitate the wiring connection with the circuit board 100. The remaining power input and output points (VDD) can be arranged according to the unoccupied points in each functional area.

[0127] Optionally, a row of signal points in the first packaging area 111 away from the second packaging area 112 may be provided with power input and output points (VDD) and blank points. In this way, the power lines (for transmitting power signals) in the circuit board 100 and the chip 200 may be centrally arranged. And / or, the retention of blank points further facilitates routing.

[0128] On this basis, in a row of signal points in the first packaging area 111 far from the second packaging area 112, there is a blank point between two adjacent power input and output points (VDD). This ensures that each power line can be routed separately and is not prone to crossover, resulting in electromagnetic interference between adjacent signal lines.

[0129] Optionally, the following Figure 3 For example, the layout structure of all signal points in the chip 200 packaged in the first packaging area 111 and the chip 200 packaged in the second packaging area 112 is described.

[0130] Optionally, the following is a description of the A channel layout structure of the chip 200.

[0131] Optionally, the signal point in the Cth row of the first column is the first data input / output point of the A channel of the chip 200 , and the signal point in the Eth row of the first column is the second data input / output point of the A channel of the chip 200 .

[0132] Optionally, the signal point position of the second column, row B is the third data input and output point position of channel A of chip 200, the signal point position of the second column, row D is the fourth data input and output point position of channel A of chip 200, and the signal point position of the second column, row C and the signal point position of the second column, row E are the ground points of channel A of chip 200.

[0133] Optionally, the signal point position of the third column, row C is the first differential read synchronization signal point position of channel A of chip 200, the signal point position of the third column, row E is the first readout clock point position of channel A of chip 200, the signal point position of the third column, row A is the power input and output point position of channel A of chip 200, and the signal point position of the third column, row B, the signal point position of the third column, the signal point position of the third row D, and the signal point position of the third row F are the ground points of channel A of chip 200.

[0134] Optionally, the signal point position of the fourth column, row F is the fifth data input and output point position of channel A of chip 200, the signal point position of the fourth column, row B is the first differential write synchronization signal point position of channel A of chip 200, the signal point position of the fourth column, row D is the first write clock point position of channel A of chip 200, and the signal point position of the fourth column, row C and the signal point position of the fourth row E are the grounding points of channel A of chip 200.

[0135] Optionally, the signal point position of the fifth column, row C is the eighth data input and output point position of channel A of chip 200, the signal point position of the fifth column, row E is the sixth data input and output point position of channel A of chip 200, the signal point position of the fifth column, row A is the power input and output point position of channel A of chip 200, the signal point position of the fifth column, row B, the signal point position of the fifth column, row D and the signal point position of the fifth column, row F are the grounding point position of channel A of chip 200.

[0136] Optionally, the signal point position of the sixth column, row B is the seventh data input and output point position of channel A of chip 200, the signal point position of the sixth column, row D is the first address point position of channel A of chip 200, the signal point position of the sixth column, row C and the signal point position of the sixth column, row E are the grounding points of channel A of chip 200, and the signal point position of the sixth column, row F is the power input and output point position of channel A of chip 200.

[0137] Optionally, the signal point of the seventh column, row C is the first chip select point of channel A of chip 200, the signal point of the seventh column, row E is the second address point of channel A of chip 200, the signal point of the seventh column, row A is the power input and output point of channel A of chip 200, and the signal point of the seventh column, row B, the signal point of the seventh column, the signal point of the seventh row D and the signal point of the seventh row F are the ground points of channel A of chip 200.

[0138] Optionally, the signal point position in the eighth column, row B is the second chip select point position of channel A of chip 200, the signal point position in the eighth column, row D is the write differential clock signal point position of channel A of chip 200, and the signal point position in the eighth column, row F is the third address point position of channel A of chip 200. The signal point positions in the eighth column, rows C and E are the ground points of channel A of chip 200.

[0139] Optionally, the signal point position of the ninth column, row C is the fourth address point position of channel A of chip 200, the signal point position of the ninth column, row E is the read differential clock signal point position of channel A of chip 200, the signal point position of the ninth column, row A is the power input and output point position of channel A of chip 200, the signal point position of the ninth column, row B, the signal point position of the ninth column, row D and the signal point position of the ninth column, row F are the ground point position of channel A of chip 200.

[0140] Optionally, the signal point position of the tenth column, row B is the seventh address point position of channel A of chip 200, the signal point position of the tenth column, row D is the sixth address point position of channel A of chip 200, the signal point position of the tenth column, row F is the fifth address point position of channel A of chip 200, the signal point position of the tenth column, row C and the signal point position of the tenth column, row E are the ground points of channel A of chip 200.

[0141] Optionally, the signal point in the eleventh column, row C is the sixteenth data input and output point of channel A of chip 200, the signal point in the eleventh column, row E is the fifteenth data input and output point of channel A of chip 200, the signal point in the eleventh column, row A is the power input and output point of channel A of chip 200, and the signal point in the eleventh column, row B, row D and row F are ground points of channel A of chip 200.

[0142] Optionally, the signal point position of the twelfth column, row B is the fourteenth data input and output point position of channel A of chip 200, the signal point position of the twelfth column, row E is the second write clock point position of channel A of chip 200, the signal point position of the twelfth column, row C and the signal point position of the E are the grounding points of channel A of chip 200, and the signal point position of the twelfth column, row F is the power input and output point position of channel A of chip 200.

[0143] Optionally, the signal point position of the thirteenth column, row C is the thirteenth data input and output point position of channel A of chip 200, the signal point position of the thirteenth column, row E is the second readout clock point position of channel A of chip 200, the signal point position of the thirteenth column, row A is the power input and output point position of channel A of chip 200, the signal point position of the thirteenth column, row B, the signal point position of the D row and the signal point position of the F row are the ground points of channel A of chip 200.

[0144] Optionally, the signal point position of the fourteenth column, row B is the twelfth data input and output point position of channel A of chip 200, the signal point position of the fourteenth column, row D is the second differential read synchronization signal point position of channel A of chip 200, the signal point position of the fourteenth column, row F is the second input data mask point position of channel A of chip 200, and the signal point positions of the fourteenth column, rows C and E are the grounding points of channel A of chip 200.

[0145] Optionally, the signal point position of the fifteenth column, row E is the eleventh data input and output point position of channel A of chip 200, the signal point position of the fifteenth column, row C is the second differential write synchronization signal point position of channel A of chip 200, the signal point position of the fifteenth column, row A is the power input and output point position of channel A of chip 200, and the signal point positions of the fifteenth column, row B, row D, and row F are the ground points of channel A of chip 200.

[0146] Optionally, the signal point position of the sixteenth column, row D is the ninth data input and output point position of channel A of chip 200, the signal point position of the sixteenth column, row F is the tenth data input and output point position of channel A of chip 200, the signal point position of the sixteenth column, row B is the unassigned point position of channel A of chip 200, and the signal point positions of the sixteenth column, row C and row E are the ground points of channel A of chip 200.

[0147] Optionally, the signal point position of the seventeenth column, row E is the drive strength calibration signal point position of channel A of chip 200, the signal point position of the seventeenth column, row C is the power input and output point position of channel A of chip 200, and the signal point position of the seventeenth column, row D and row F is the grounding point position of channel A of chip 200.

[0148] The following is a description of the C channel layout structure of chip 200.

[0149] Optionally, the signal point in the first column and the Jth row is the first data input and output point of the C channel of the chip 200, and the signal point in the first column and the Lth row is the second data input and output point of the C channel of the chip 200. The signal point in the first column and the Gth row is the power input and output point of the C channel of the chip 200.

[0150] Optionally, the signal point position of the Hth row in the second column is the third data input and output point position of the C channel of chip 200, the signal point position of the Kth row in the second column is the fourth data input and output point position of the C channel of chip 200, and the signal point positions of the Gth row, the Jth row and the Lth row in the second column are the ground points of the C channel of chip 200.

[0151] Optionally, the signal point position of the third column, row G is the first differential write synchronization signal point position of the C channel of chip 200, the signal point position of the third column, row J is the first read clock point position of the C channel of chip 200, the signal point position of the third column, row L is the first input data mask point position of the C channel of chip 200, and the signal point positions of the third column, row H and row K are the ground points of the C channel of chip 200.

[0152] Optionally, the signal point position of the fourth column and the Hth row is the first differential read synchronization signal point position of the C channel of chip 200, the signal point position of the fourth column and the Kth row is the first write clock point position of the C channel of chip 200, the signal point position of the fourth column and the Gth row, the signal point position of the fourth column and the Jth row and the signal point position of the Lth row are the grounding points of the C channel of chip 200.

[0153] Optionally, the signal point position of the fifth column and row G is the fifth data input and output point position of the C channel of chip 200, the signal point position of the fifth column and row J is the sixth data input and output point position of the C channel of chip 200, the signal point position of the fifth column and row L is the seventh data input and output point position of the C channel of chip 200, the signal point position of the fifth column and row H and the signal point position of the fifth column and row K are the grounding points of the C channel of chip 200.

[0154] Optionally, the signal point position of the sixth column and the Kth row is the eighth data input and output point position of the C channel of chip 200, the signal point position of the sixth column and the Hth row is the first address point position of the C channel of chip 200, and the signal point position of the sixth column and the Gth row, the signal point position of the Jth row and the signal point position of the Lth row are the grounding point position of the C channel of chip 200.

[0155] Optionally, the signal point position of the seventh column, row G is the second address point position of the C channel of chip 200, the signal point position of the seventh column, row J is the third address point position of the C channel of chip 200, the signal point position of the seventh column, row L is the power input and output point position of the C channel of chip 200, and the signal point position of the seventh column, row H and the signal point position of the K are the grounding point position of the C channel of chip 200.

[0156] Optionally, the signal point position of the eighth column and the Hth row is the differential clock signal point position for writing the C channel of chip 200, the signal point position of the eighth column and the Kth row is the first chip select point position of the C channel of chip 200, and the signal point positions of the eighth column and the Gth row, the Jth row and the Lth row are the ground points of the C channel of chip 200.

[0157] Optionally, the signal point position of the ninth column, row J is the C channel read differential clock signal point position of chip 200, the signal point position of the ninth column, row L is the C channel second chip select point position of chip 200, the signal point position of the ninth column, row G is the C channel power input and output point position of chip 200, the signal point position of the ninth column, row H and the signal point position of the ninth column, row K are the C channel grounding point position of chip 200.

[0158] Optionally, the signal point position of the tenth column and row H is the fifth address point position of the C channel of chip 200, the signal point position of the tenth column and row K is the fourth address point position of the C channel of chip 200, and the signal point positions of the tenth column and row G, row J and row L are the ground points of the C channel of chip 200.

[0159] Optionally, the signal point position in the eleventh column, row G is the sixteenth data input and output point position of the C channel of chip 200, the signal point position in the eleventh column, row J is the seventh address point position of the C channel of chip 200, the signal point position in the eleventh column, row L is the sixth address point position of the C channel of chip 200, the signal point position in the eleventh column, row H and the signal point position in the K are the ground points of the C channel of chip 200.

[0160] Optionally, the signal point position of the twelfth column, row H is the fifteenth data input and output point position of the C channel of chip 200, the signal point position of the twelfth column, row K is the second readout clock point position of the C channel of chip 200, and the signal point position of the twelfth column, row G, the signal point position of the J row and the signal point position of the L row are the grounding points of the C channel of chip 200.

[0161] Optionally, the signal point position of the thirteenth column, row G is the fourteenth data input and output point position of the C channel of chip 200, the signal point position of the thirteenth column, row L is the thirteenth data input and output point position of the C channel of chip 200, the signal point position of the thirteenth column, row J is the second write clock point position of the C channel of chip 200, the signal point position of the thirteenth column, row H and the signal point position of the K are ground points of the C channel of chip 200.

[0162] Optionally, the signal point position of the fourteenth column, row H is the second differential read synchronization signal point position of the C channel of chip 200, the signal point position of the fourteenth column, row K is the second input data mask point position of the C channel of chip 200, and the signal point positions of the fourteenth column, row G, row J and row L are the grounding points of the C channel of chip 200.

[0163] Optionally, the signal point position of the fifteenth column, row G is the twelfth data input and output point position of the C channel of chip 200, the signal point position of the fifteenth column, row L is the eleventh data input and output point position of the C channel of chip 200, the signal point position of the fifteenth column, row J is the second differential write synchronization signal point position of the C channel of chip 200, and the signal point positions of the fifteenth column, row H and row K are the ground points of the C channel of chip 200.

[0164] Optionally, the signal point position of the sixteenth column, row H is the tenth data input and output point position of the C channel of chip 200, the signal point position of the sixteenth column, row K is the ninth data input and output point position of the C channel of chip 200, and the signal point positions of the sixteenth column, row G, row J and row L are the ground points of the C channel of chip 200.

[0165] Optionally, the signal points in the seventeenth column, row G and row L are power input and output points of the C channel of chip 200 , and the signal points in the seventeenth column, row H and row K are ground points of the A channel of chip 200 .

[0166] Figure 4 Another schematic diagram of the layout of signal points on a circuit board provided in an embodiment of the present application. Figure 4 As shown, four packaging areas 110 are arranged on the circuit board 100. In addition to the first packaging area 111 and the second packaging area 112, the circuit board 100 is also provided with a third packaging area 113 and a fourth packaging area 114. Among them, the first packaging area 111, the second packaging area 112, the third packaging area 113 and the fourth packaging area 114 are arranged in sequence along the first direction. And / or, the chip 200 is also packaged in the third packaging area 113 and the fourth packaging area 114. Correspondingly, the third packaging area 113 can form a separate chip 200 signal transmission channel D. The fourth packaging area 114 can form a separate chip 200 signal transmission channel B.

[0167] Optionally, when the circuit board 100 is packaged with a first packaging area 111, a second packaging area 112, a third packaging area 113 and a fourth packaging area, the chip 200 signal transmission channel A, the chip 200 signal transmission channel B, the chip 200 signal transmission channel C and the chip 200 signal transmission channel D may all work at the same time, or any two or any three of the chip 200 signal transmission channel A, the chip 200 signal transmission channel B, the chip 200 signal transmission channel C and the chip 200 signal transmission channel D may work at the same time, or any one of the chip 200 signal transmission channel A, the chip 200 signal transmission channel B, the chip 200 signal transmission channel C and the chip 200 signal transmission channel D may work alone.

[0168] Optionally, the third packaging area 113 is symmetrically arranged with the second packaging area 112, and the fourth packaging area 114 is symmetrically arranged with the first packaging area 111. That is, the electrical connection balls 300 of the third packaging area 113 and the second packaging area 112 are symmetrically distributed, and the electrical connection balls 300 of the fourth packaging area 114 and the first packaging area 111 are symmetrically arranged. Correspondingly, the chips 200 packaged in the third packaging area 113 and the fourth packaging area 114 are also symmetrically arranged with the chips 200 packaged in the second packaging area 112 and the first packaging area 111. That is, the signal transmission channel A and the signal transmission channel B, and the signal transmission channel C and the signal transmission channel D are all symmetrically arranged along the second direction.

[0169] Optionally, at least one row of blank spots may be spaced between the second packaging area 112 and the third packaging area 113 to facilitate the arrangement of the outgoing wires at the junction of the second packaging area 112 and the third packaging area 113. Figure 4 As shown, two complete rows of blank points (such as the Mth row and the Nth row in the figure) are provided between the second packaging area 112 and the third packaging area 113. In this way, not only can the outlet space be provided for the electrical connection ball 300 on the side of the second packaging area 112 close to the third packaging area 113, but also the outlet of the electrical connection ball 300 on the side of the third packaging area 113 close to the second packaging area 112 is convenient. In this way, when laying out a row of signal points close to the second packaging area 112 and the third packaging area 113, there is no need to consider leaving a separate wiring space.

[0170] Optionally, no blank spots are provided in a row of signal spots close to each other in the second packaging area 112 and the third packaging area 113. This can increase the compactness of the signal spot layout, thereby reducing the size of the chip 200.

[0171] Optionally, through the above layout and design, the total number of electrical balls 300 (signal points) for transmitting various signals in the first packaging area 111, the second packaging area 112, the third packaging area 113 and the fourth packaging area 114 in this embodiment can be 352.

[0172] Optionally, the diameter of the electrical contact ball 300 used to form the signal point in this embodiment may be 0.20 mm-0.35 mm. For example, the diameter of the electrical contact ball 300 is in the range of 0.20 mm, 0.25 mm, 0.30 mm, 0.35 mm, or any two thereof.

[0173] Optionally, along the first direction, the ball spacing between adjacent electrical balls 300 may be 0.35 mm-0.65 mm. For example, along the first direction, the ball spacing between adjacent electrical balls 300 may be 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm, or a range consisting of any two of them.

[0174] Optionally, along the second direction, the ball spacing between adjacent electrical balls 300 may be 0.35-0.65 mm. For example, along the second direction, the ball spacing between adjacent electrical balls 300 is 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm, or a range consisting of any two thereof.

[0175] In this way, while ensuring reasonable wiring and / or increasing the point density, the chip 200 can be more integrated, thereby achieving miniaturization of the chip 200.

[0176] On this basis, in this embodiment, the diameter of the electrical balls 300 can be 0.25 mm, the ball spacing between two adjacent rows of electrical balls 300 can be 0.5 mm, and the ball spacing between two adjacent columns of electrical balls 300 can be 0.45 mm. Such a configuration can ensure that the gap between adjacent electrical balls 300 is reasonable, which is convenient for routing and less prone to signal interference. And / or, since the number of columns of each packaging area 110 is greater than the number of rows, and the ball spacing between two adjacent rows of electrical balls 300 is greater than the ball spacing between two adjacent columns of electrical balls 300, the length and width of the packaging unit formed by the first packaging area 111 and the second packaging area 112 as a whole can be closer, which is beneficial to the layout of the packaging unit.

[0177] Optionally, the size of the chip packaging structure provided in this embodiment can be reduced to 8.2 mm*12.4 mm. Optionally, 12.4 mm is the size of the chip 200 extending along the first direction, and 8.2 mm is the size of the chip 200 extending along the second direction.

[0178] Compared with the related art, in which the POP packaging process is used for the chip 200 with a large ball diameter and a high point density, this embodiment chooses to place the central processing unit 400 and the chip 200 side by side for packaging, and realizes reasonable wiring between the chip 200 and the circuit board 100 through the above signal point layout. And / or, the diameter of the electrical connection ball 300 is reduced and the ball spacing between adjacent electrical connection balls 300 is reduced, and the overall area of ​​a single chip 200 is reduced on the basis of ensuring reasonable wiring, so that the overall size of the chip 200 can be reduced. In addition, the space of the circuit board 100 can be saved, which is convenient for the layout design of other devices on the circuit board 100.

[0179] Based on the above embodiments, the embodiments of the present application further provide a device, in which the processor can adopt the above chip packaging structure. Figure 5 A schematic diagram of a connection between the chip packaging structure provided in an embodiment of the present application and the central processing unit 400. Figure 6 Another schematic diagram of the connection between the chip packaging structure and the central processing unit 400 provided in the embodiment of the present application. Figure 5 and Figure 6 As shown, at least one central processor 400 is also provided on one side of the chip package structure, and the central processor 400 is connected to the electrical contact ball 300 in the chip package structure by routing across the target edge of the chip 200. The target edge is a completely blank area in the package area 110 extending to one side edge, such as Figure 5 and Figure 6 The left edge of the packaging area 110 is shown in FIG.

[0180] Optionally, the central processor 400 may be a SOC chip. The SOC chip is disposed on the circuit board 100 and is electrically connected to the aforementioned chip 200. The SOC chip may include a first channel, a second channel, a third channel, and a fourth channel. The first channel is electrically connected to the A channel of the chip 200, the second channel is electrically connected to the B channel of the chip 200, the third channel is electrically connected to the C channel of the chip 200, and the fourth channel is electrically connected to the D channel of the chip 200.

[0181] Optionally, the device can be implemented in various forms. For example, the smart terminal described in this application may include smart terminals such as mobile phones, tablet computers, laptop computers, PDAs, portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., as well as fixed terminals such as digital TVs and desktop computers.

[0182] The following description will be made by taking a mobile terminal as an example, and those skilled in the art will understand that, in addition to components specifically used for mobile purposes, the construction according to the embodiments of the present application can also be applied to fixed-type terminals.

[0183] Figure 7 A schematic diagram of the hardware structure of a smart terminal implementing each embodiment of the present application. Figure 7, which is a schematic diagram of the hardware structure of a mobile terminal for implementing various embodiments of the present application, the mobile terminal 500 may include: RF (Radio Frequency) unit 501, WiFi module 502, audio output unit 503, A / V (audio / video) input unit 504, sensor 505, display unit 506, user input unit 507, interface unit 508, memory 509, processor 510, and power supply 511 and other components. Those skilled in the art can understand that Figure 7 The structure of the mobile terminal shown in the figure does not constitute a limitation on the mobile terminal. The mobile terminal may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0184] Combine the following Figure 7 The following is a detailed introduction to the various components of the mobile terminal:

[0185] The radio frequency unit 501 can be used for receiving and sending signals during information transmission or communication. Specifically, after receiving the downlink information of the base station, it is sent to the processor 510 for processing; in addition, the uplink data is sent to the base station. Generally, the radio frequency unit 501 includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, etc. And / or, the radio frequency unit 501 can also communicate with the network and other devices through wireless communication. The above-mentioned wireless communications can use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution), TDD-LTE (Time Division Duplexing-Long Term Evolution) and 5G, etc.

[0186] WiFi is a short-range wireless transmission technology. The mobile terminal can help users send and receive emails, browse web pages, and access streaming media through the WiFi module 502. It provides users with wireless broadband Internet access. Figure 7 A WiFi module 502 is shown, but it is understandable that it is not an essential component of the mobile terminal and can be omitted as required without changing the essence of the invention.

[0187] The audio output unit 503 can convert the audio data received by the RF unit 501 or the WiFi module 502 or stored in the memory 509 into an audio signal and output it as sound when the mobile terminal 500 is in a call signal reception mode, a talk mode, a recording mode, a voice recognition mode, a broadcast reception mode, etc. Moreover, the audio output unit 503 can also provide audio output related to a specific function performed by the mobile terminal 500 (for example, a call signal reception sound, a message reception sound, etc.). The audio output unit 503 may include a speaker, a buzzer, etc.

[0188] The A / V input unit 504 is used to receive audio or video signals. The A / V input unit 504 may include a graphics processor (GPU) 5041 and a microphone 5042, and the graphics processor 5041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The processed image frame can be displayed on the display unit 506. The image frame processed by the graphics processor 5041 can be stored in the memory 509 (or other storage medium) or sent via the radio frequency unit 501 or the WiFi module 502. The microphone 5042 can receive sound (audio data) via the microphone 5042 in a telephone call mode, a recording mode, a voice recognition mode, and other operating modes, and can process such sound into audio data. The processed audio (voice) data can be converted into a format output that can be sent to a mobile communication base station via the radio frequency unit 501 in the case of a telephone call mode. The microphone 5042 can implement various types of noise elimination (or suppression) algorithms to eliminate (or suppress) noise or interference generated in the process of receiving and sending audio signals.

[0189] The mobile terminal 500 also includes at least one sensor 505, such as a light sensor, a motion sensor, and other sensors. Optionally, the light sensor includes an ambient light sensor and a proximity sensor. Optionally, the ambient light sensor can adjust the brightness of the display panel 5061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 5061 and / or the backlight when the mobile terminal 500 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in all directions (generally three axes), and can detect the magnitude and direction of gravity when stationary. It can be used for applications that identify the posture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; as for other sensors that can also be configured on the mobile phone, such as fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc., they will not be repeated here.

[0190] The display unit 506 is used to display information input by the user or information provided to the user. The display unit 506 may include a display panel 5061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0191] The user input unit 507 can be used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the mobile terminal. Optionally, the user input unit 507 may include a touch panel 5071 and other input devices 5072. The touch panel 5071, also known as a touch screen, can collect the user's touch operation on or near it (such as the user's operation on the touch panel 5071 or near the touch panel 5071 using any suitable object or accessory such as a finger, stylus, etc.), and drive the corresponding connection device according to a pre-set program. The touch panel 5071 may include two parts: a touch detection device and a touch controller. Optionally, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the touch point coordinates, and then sends it to the processor 510, and can receive and execute the command sent by the processor 510. In addition, the touch panel 5071 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves. In addition to the touch panel 5071, the user input unit 507 may also include other input devices 5072. Optionally, the other input devices 5072 may include, but are not limited to, one or more of a physical keyboard, a function key (such as a volume control key, a switch key, etc.), a trackball, a mouse, a joystick, etc., which are not specifically limited here.

[0192] Optionally, the touch panel 5071 may cover the display panel 5061. When the touch panel 5071 detects a touch operation on or near it, it transmits the information to the processor 510 to determine the type of the touch event. Then, the processor 510 provides a corresponding visual output on the display panel 5061 according to the type of the touch event. Figure 7 In the figure, the touch panel 5071 and the display panel 5061 are used as two independent components to realize the input and output functions of the mobile terminal. However, in some embodiments, the touch panel 5071 and the display panel 5061 can be integrated to realize the input and output functions of the mobile terminal, which is not limited here.

[0193] The interface unit 508 serves as an interface through which at least one external device can be connected to the mobile terminal 500. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, etc. The interface unit 508 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the mobile terminal 500 or may be used to transmit data between the mobile terminal 500 and an external device.

[0194] The memory 509 can be used to store software programs and various data. The memory 509 can mainly include a program storage area and a data storage area. Optionally, the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory 509 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0195] The processor 510 is the control center of the mobile terminal. It uses various interfaces and lines to connect various parts of the entire mobile terminal. It executes various functions of the mobile terminal and processes data by running or executing software programs and / or modules stored in the memory 509, and calling data stored in the memory 509, so as to monitor the mobile terminal as a whole. The processor 510 may include one or more processing units; preferably, the processor 510 may integrate an application processor and a modem processor. Optionally, the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 510.

[0196] The mobile terminal 500 may also include a power supply 511 (such as a battery) for supplying power to various components. Preferably, the power supply 511 may be logically connected to the processor 510 via a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system.

[0197] although Figure 7 Not shown, the mobile terminal 500 may also include a Bluetooth module, etc., which will not be described in detail here.

[0198] It is understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0199] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0200] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A circuit board, comprising at least two packaging areas, wherein the packaging areas include a first packaging area and a second packaging area sequentially arranged along a first direction; A chip, packaged at least in the first packaging area and the second packaging area; A central processing unit is packaged on the circuit board and is located on the same side as the chip; the central processing unit and the chip are connected via wiring in the circuit board; The first packaging area and the second packaging area are both provided with signal points close to the central processing unit.

2. The chip packaging structure according to claim 1, characterized in that: At least one data input / output point and / or at least one blank point are arranged in the signal points of the first packaging area and the second packaging area close to the central processing unit.

3. The chip packaging structure according to claim 2, characterized in that: In a row of signal points in the first packaging area close to the central processing unit, two data input and output points are provided, and there is a blank point between the two data input and output points; and / or, In a row of signal points in the second packaging area close to the central processing unit, two data input and output points are arranged, and the blank point is arranged between the two data input and output points.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: In a row of signal points in the first packaging area away from the second packaging area, power input and output points and blank points are arranged.

5. The chip packaging structure according to claim 4, characterized in that: In a row of signal points in the first packaging area far away from the second packaging area, there is a blank point between two adjacent power input and output points.

6. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The packaging area further includes a third packaging area and a fourth packaging area sequentially arranged along the first direction, the third packaging area is symmetrically arranged with the second packaging area, and the fourth packaging area is symmetrically arranged with the first packaging area.

7. The chip packaging structure according to claim 6, characterized in that: There is at least one row of blank spots between the second packaging area and the third packaging area.

8. The chip packaging structure according to claim 6, characterized in that: There are no blank spots in a row of signal spots where the second packaging area and the third packaging area are close to each other.

9. The chip packaging structure according to any one of claims 1 to 3, characterized in that: Include at least one of the following: The diameter of the electric ball used to form the signal point is 0.20-0.35mm; Along the first direction, the ball spacing between adjacent electrical contact balls is 0.35-0.65 mm; Along the second direction, the ball spacing between adjacent electrical balls is 0.35-0.65 mm.

10. A device, characterized in that: A chip packaging structure comprising any one of claims 1 to 9.

Images