GaN thin film power device and preparation method thereof

Abstract

The invention relates to the field of transistors, and particularly discloses a GaN thin film power device and a preparation method thereof. The GaN thin film power device comprises a composite adjusting layer, a buffer layer, a channel layer, a barrier layer, a passivation layer, a gate electrode, a source electrode and a drain electrode, and the composite adjusting layer, the buffer layer, the channel layer, the barrier layer, the passivation layer and the gate electrode are stacked in sequence; the source electrode and the drain electrode are arranged on the two sides of the gate electrode, penetrate through the passivation layer and extend into the barrier layer; the composite adjusting layer comprises an HfO2 layer, an AlON layer, a BGaN layer and an SiN layer which are stacked in sequence. By implementing the invention, the loss of various properties in the substrate stripping process can be reduced, and the pressure resistance can be improved.

Description

Technical Field

[0001] The present invention relates to the field of transistors, and in particular to a GaN thin film power device and a preparation method thereof. Background Art

[0002] Flexible electronic devices are bendable and stretchable, and have great application potential in various fields. Currently, most flexible electronic devices are based on organic semiconductor materials, but the low mobility and thermal conductivity of organic electronic materials make it difficult to increase their operating frequency, limiting their application. Flexible devices based on inorganic materials (such as GaN, GaAs, etc.) can meet the needs of high-frequency and high-power use, and are the dominant development direction in the future. At present, the preparation method of flexible HEMT devices is to first grow a thin film on a rigid substrate, then laser peel the original substrate, and transfer it to a flexible substrate such as PET and PI, but laser peeling causes high damage to the film, resulting in a large loss of the maximum saturation current, which weakens various performances. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a GaN thin film power device with high withstand voltage and low performance loss.

[0004] Another technical problem to be solved by the present invention is to provide a method for preparing a GaN thin film power device.

[0005] In order to solve the above technical problems, the present invention provides a GaN thin film power device, which includes a composite adjustment layer, a buffer layer, a channel layer, a barrier layer, a passivation layer, a gate electrode, a source electrode and a drain electrode, wherein the composite adjustment layer, the buffer layer, the channel layer, the barrier layer, the passivation layer and the gate electrode are stacked in sequence; the source electrode and the drain electrode are arranged on both sides of the gate electrode, and extend through the passivation layer to the barrier layer;

[0006] The composite adjustment layer includes a HfO2 layer, an AlON layer, a BGaN layer and a SiN layer stacked in sequence.

[0007] As an improvement of the above technical solution, the thickness of the HfO2 layer is 10 to 50 nm;

[0008] The thickness of the AlON layer is 5 to 20 nm;

[0009] The thickness of the BGaN layer is 10-30 nm, and the B component accounts for 0.05-0.1;

[0010] The thickness of the SiN layer is 10-30 nm.

[0011] As an improvement of the above technical solution, the composite adjustment layer is provided with a F ion implantation region, and the projection of the F ion implantation region on the barrier layer is located between the gate electrode and the drain electrode;

[0012] The implantation depth D of the F ions in the F ion implantation area and the thickness T of the composite adjustment layer meet the following relationship: TD ≥ 30 nm.

[0013] As an improvement of the above technical solution, the buffer layer is an unintentionally doped GaN layer, and its thickness is 100-500 nm.

[0014] As an improvement of the above technical solution, the channel layer is a GaN channel layer, and its thickness is 100-200nm;

[0015] The barrier layer is an AlGaN barrier layer, the thickness of which is 10 to 30 nm, and the Al component ratio thereof is 0.2 to 0.3;

[0016] The passivation layer is a SiON layer, a SiO2 layer or an Al2O3 layer, and its thickness is 50 to 500 nm;

[0017] The source electrode and the drain electrode are both a stacked structure consisting of one or at least two of a Ti layer, an Al layer, a Ni layer, an Au layer, and a Cr layer;

[0018] The gate electrode is a stacked structure consisting of at least two of a Ni layer, an Au layer, a Pt layer, and a Ti layer.

[0019] As an improvement of the above technical solution, a space layer is further provided between the channel layer and the barrier layer, which is an AlN layer with a thickness of 1 to 2 nm;

[0020] A P-type GaN cap layer is provided below the gate electrode, penetrating the passivation layer and contacting the barrier layer. The thickness of the P-type GaN cap layer is 20-40 nm.

[0021] Correspondingly, the present invention also discloses a method for preparing a GaN thin film power device, which is used for the above-mentioned GaN thin film power device, and comprises:

[0022] sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a passivation layer on a temporary substrate;

[0023] forming a source window and a drain window on the passivation layer;

[0024] forming a source electrode in the source window and forming a drain electrode in the drain window;

[0025] forming a gate electrode on the passivation layer to obtain a first intermediate;

[0026] forming a protective adhesive layer on a side of the first intermediate body where the gate electrode is located, and bonding the first intermediate body to a hard substrate through the protective adhesive layer;

[0027] peeling off the temporary substrate, removing the nucleation layer at the same time, and exposing the buffer layer;

[0028] Sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a composite regulating layer;

[0029] The protective adhesive layer and the hard substrate are removed.

[0030] As an improvement of the above technical solution, the step of peeling off the temporary substrate, removing the nucleation layer and exposing the buffer layer comprises:

[0031] peeling off the temporary substrate by a laser lift-off process, while removing the nucleation layer;

[0032] Etching to thin the buffer layer;

[0033] Wherein, the temporary substrate is a sapphire substrate, and the nucleation layer is an AlN layer;

[0034] The buffer layer is an unintentionally doped GaN layer, and the buffer layer is thinned by ICP etching, and the etching conditions include:

[0035] BCl3 and Cl2 are used as etching gas sources, the flow rate of BCl3 is 15-25sccm, the flow rate of Cl2 is 60-90sccm, the ICP power is 200-300W, and the RF power is 100-150W.

[0036] As an improvement of the above technical solution, the SiN layer is grown by PECVD, and its growth parameters include: growth temperature of 250-350°C, growth pressure of 100-200mtorr, RF power of 200-300W, flow rate of SiH4 of 100-200sccm, flow rate of NH3 of 300-500sccm, and flow rate of Ar of 100-300sccm;

[0037] The AlON layer is grown by ALD, and its growth parameters include: deposition temperature of 200-350° C., annealing temperature of 300-500° C., pressure of 1-10 torr, flow rate of TMA of 10-50 sccm, flow rate of NH3 of 10-50 sccm, and flow rate of O2 of 10-50 sccm;

[0038] The BGaN layer is grown by MOCVD, and its growth parameters include: growth temperature of 900-1100° C., and growth pressure of 100-400 torr;

[0039] The HfO2 layer is grown by ALD, and its growth parameters include: a deposition temperature of 150-350°C, an annealing temperature of 300-500°C, a pressure of 1-10 torr, a flow rate of HfCl4 of 10-50 sccm, and a flow rate of O2 of 10-50 sccm.

[0040] As an improvement of the above technical solution, the step of sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a composite adjustment layer includes:

[0041] Sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a second intermediate;

[0042] F ion implantation is performed on the side of the HfO2 layer of the second intermediate body corresponding to the position between the gate electrode and the drain electrode through RIE process; the implantation time is 20 to 50 seconds, CF4 is used to generate plasma, and the power is 120 to 150W.

[0043] The implementation of the present invention has the following beneficial effects:

[0044] In the GaN thin film power device in one embodiment of the present invention, after removing the temporary substrate, a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer are sequentially formed on the buffer layer. Among them, the interface state density of the SiN layer is low, which can repair the damage of the buffer layer, reduce dangling bonds, passivate interface defects, and reduce various performance losses caused by the peeling of the temporary substrate. Moreover, the SiN layer is mainly amorphous, which can avoid excessive strain between the composite adjustment layer and the buffer layer during the growth process of the composite adjustment layer, improve the crystal quality of the composite adjustment layer and the buffer layer, and reduce leakage current. The BGaN layer has a high barrier and a large resistance, which can reduce leakage current. At the same time, the BGaN layer has a high density, can fill surface defects, and block the defects caused by stress from continuing to extend upward to the AlON layer and the HfO2 layer. The AlON layer has a low interface state density and good insulation performance, which can reduce peeling loss and leakage current. In addition, the AlON layer has a large lattice constant due to the introduction of O, which can serve as a good transition between the HfO2 layer and the BGaN layer, and improve the overall crystal quality of the composite adjustment layer. The HfO2 layer has a high dielectric constant and high capacitance density, which can block carrier propagation, further reduce leakage current, increase breakdown voltage, and improve the performance of GaN thin-film power devices.

[0045] Therefore, the GaN thin film power device based on this embodiment can reduce the performance loss caused by temporary substrate peeling, increase the breakdown voltage, and improve various performances of the GaN thin film power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A schematic diagram of the structure of a GaN thin film power device in one embodiment of the present invention;

[0047] Figure 2 A schematic diagram of the structure of a GaN thin film power device in another embodiment of the present invention;

[0048] Figure 3 A schematic diagram of the structure of a GaN thin film power device in another embodiment of the present invention;

[0049] Figure 4 A schematic diagram of the structure of a GaN thin film power device in another embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of the first intermediate after step S4 in one embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the structure of the first intermediate after step S5 in one embodiment of the present invention;

[0052] Figure 7 This is a schematic structural diagram of the first intermediate after step S7 in one embodiment of the present invention;

[0053] In the figure, 1 is a temporary substrate, 2 is a nucleation layer, 31 is a buffer layer, 32 is a channel layer, 33 is a barrier layer, 34 is a space layer, 35 is a P-type GaN cap layer, 36 is a passivation layer, 4 is a gate electrode, 5 is a source electrode, 6 is a drain electrode, 7 is a hard substrate, 8 is a protective glue layer, 9 is a composite adjustment layer, 91 is a HfO2 layer, 92 is an AlON layer, 93 is a BGaN layer, 94 is a SiN layer, and 95 is a F ion implantation area. DETAILED DESCRIPTION

[0054] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific implementation methods or embodiments and are not intended to limit the present invention.

[0056] Those skilled in the art will appreciate that the materials, reagents, etc. used in the following examples, unless otherwise specified, can be obtained from commercial sources.

[0057] In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features.

[0058] The temperature parameters in the present invention, if not specifically limited, allow for both constant temperature treatment and treatment within a certain temperature range. The constant temperature treatment allows the temperature to fluctuate within the precision range controlled by the instrument.

[0059] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0061] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use scenarios of other materials.

[0062] See also Figure 1The present invention discloses a GaN thin film power device, which includes a composite adjustment layer 9, a buffer layer 31, a channel layer 32, a barrier layer 33, a passivation layer 36, a gate electrode 4, a source electrode 5 and a drain electrode 6. The composite adjustment layer 9, the buffer layer 31, the channel layer 32, the barrier layer 33, the passivation layer 36 and the gate electrode 4 are stacked in sequence. The source electrode 5 and the drain electrode 6 are arranged on both sides of the gate electrode 4, and the source electrode 5 and the drain electrode 6 extend through the passivation layer 36 to the barrier layer 33. Specifically, in some embodiments, the source electrode 5 and the drain electrode 6 may be partially located on the passivation layer 36, and partially pass through the openings on the passivation layer 36 to contact the barrier layer 33; in other embodiments, the source electrode 5 and the drain electrode 6 are located in the openings of the passivation layer 36 as a whole, and directly contact the barrier layer 33, but are not limited thereto.

[0063] Among them, the composite adjustment layer 9 includes a HfO2 layer 91, an AlON layer 92, a BGaN layer 93 and a SiN layer 94 stacked in sequence from away from the buffer layer 31 to close to the buffer layer 31. In this embodiment, after removing the temporary substrate 1, a SiN layer 94, a BGaN layer 93, an AlON layer 92 and a HfO2 layer 91 are formed on the buffer layer 31 in sequence. Among them, the interface state density of the SiN layer 94 is low, which can repair the damage of the buffer layer 31, reduce hanging bonds, passivate interface defects, and reduce various performance losses caused by substrate peeling. Moreover, the SiN layer 94 is mainly amorphous, which can avoid excessive strain with the buffer layer 31 during the growth of the composite adjustment layer 9, improve the crystal quality of the composite adjustment layer 9 and the buffer layer 31, and reduce leakage current. The BGaN layer 93 has a high barrier and a large resistance, which can reduce leakage current. At the same time, the BGaN layer 93 has a high density, can fill surface defects, and block the defects caused by stress from continuing to extend upward to the AlON layer 92 and the HfO2 layer 91. The AlON layer 92 has low interface state density and good insulation performance, which can reduce stripping loss and leakage current. In addition, the AlON layer 92 has a larger lattice constant due to the introduction of O, which can serve as a good transition between the HfO2 layer 91 and the BGaN layer 93, thereby improving the overall crystal quality of the composite adjustment layer 9. The HfO2 layer 91 has a high dielectric constant and high capacitance density, which can block carrier propagation, further reduce leakage current, increase breakdown voltage, and improve the performance of GaN thin film power devices.

[0064] Specifically, in some embodiments, the thickness of the HfO2 layer 91 is 5 to 60 nm, exemplarily 8 nm, 15 nm, 24 nm, 38 nm, 47 nm or 56 nm, but not limited thereto, and preferably 10 to 50 nm.

[0065] Specifically, in some embodiments, the thickness of the AlON layer 92 is 2-20 nm, exemplarily 5 nm, 8 nm, 11 nm, 14 nm or 17 nm, but not limited thereto, preferably 5-20 nm.

[0066] Specifically, in some embodiments, the thickness of the BGaN layer 93 is 5 to 50 nm, exemplarily 8 nm, 16 nm, 24 nm, 32 nm, 40 nm or 48 nm, but not limited thereto, and preferably 10 to 30 nm.

[0067] Specifically, in some embodiments, the proportion of the B component in the BGaN layer 93 is 0.02-0.1, exemplarily 0.03, 0.04, 0.06 or 0.08, but not limited thereto, preferably 0.05-0.1.

[0068] Specifically, in some embodiments, the thickness of the SiN layer 94 is 5 to 50 nm, exemplarily 8 nm, 15 nm, 25 nm, 35 nm or 45 nm, but not limited thereto, and preferably 10 to 30 nm.

[0069] Specifically, in some embodiments, the buffer layer 31 is an AlGaN layer, an undoped GaN layer, a C-doped GaN layer or a Fe-doped GaN layer, but is not limited thereto. The buffer layer 31 has a thickness of 0.1 to 2.5 μm.

[0070] Specifically, in some embodiments, the channel layer 32 is a GaN channel layer, and the thickness thereof is 100-300 nm, but not limited thereto. Preferably, the thickness of the channel layer 32 is 100-200 nm.

[0071] Specifically, in some embodiments, the barrier layer 33 is an AlGaN barrier layer, the Al component ratio of which is 0.2-0.3 and the thickness is 10-30 nm, but it is not limited thereto.

[0072] Specifically, in some embodiments, the passivation layer 36 is a SiON layer, a SiO2 layer or an Al2O3 layer, and its thickness is 50-500 nm, but not limited thereto, preferably a SiO2 layer, and its thickness is 50-300 nm.

[0073] Specifically, in some embodiments, the source electrode 5 and the drain electrode 6 are both a stacked structure composed of one or at least two of a Ti layer, an Al layer, a Ni layer, an Au layer, and a Cr layer, but are not limited thereto. Exemplarily, the source electrode 5 and the drain electrode 6 are composed of a Ti layer, an Al layer, a Ni layer, and an Au layer stacked in sequence, and the thickness of each layer is 10 to 30 nm, 100 to 150 nm, 30 to 80 nm, and 50 to 150 nm, respectively.

[0074] Specifically, in some embodiments, the gate electrode 4 is a stacked structure composed of at least two of a Ni layer, an Au layer, a Pt layer, and a Ti layer, but is not limited thereto. Exemplarily, the gate electrode 4 is composed of a Ni layer and an Au layer stacked in sequence, and the thickness of each layer is 30 to 80 nm and 150 to 200 nm, respectively.

[0075] Preferably, in some embodiments, the buffer layer 31 is an unintentionally doped GaN layer. It should be noted that in order to prevent DC leakage and AC coupling, the buffer layer 31 below the channel layer 32 often needs to have a higher resistivity. Unintentionally doped GaN layers are generally weakly N-type, have a low resistivity, and are prone to leakage. Therefore, C-doped GaN layers or Fe-doped GaN layers are often used as buffer layers 31. However, C doping requires a lower temperature, resulting in poor lattice quality of the buffer layer 31 itself, which in turn results in poor lattice quality of the channel layer 32, low two-dimensional electron gas concentration, and weakened various performances of the HEMT device. Studies have shown that C doping is closely related to current collapse and dynamic characteristic degradation of HEMT devices. Fe doping can easily form high-resistance GaN materials at a lower doping concentration, but Fe doping has a memory effect, and it is not easy to obtain a sudden interface, which will also cause a certain amount of decrease in the density of the two-dimensional electron gas. In the present technical solution, by sequentially forming a SiN layer 94, a BGaN layer 93, an AlON layer 92 and a HfO2 layer 91 on the buffer layer 31 after removing the temporary substrate 1, the resistance can be greatly increased and the leakage current can be greatly reduced, so that the present technical solution can use an unintentionally doped GaN layer as the buffer layer 31, thereby also improving the crystal quality of the channel layer 32, increasing the density of the two-dimensional electron gas, and optimizing the device performance.

[0076] Specifically, based on this embodiment, the thickness of the buffer layer 31 is 0.1 to 2.5 μm, exemplarily 0.4 μm, 0.7 μm, 0.8 μm, 1.2 μm, 1.6 μm, 2.1 μm or 2.3 μm, but not limited thereto. Preferably, in some embodiments, the thickness of the buffer layer 31 is ≤ 800 nm, which is the thickness after the temporary substrate 1 is peeled off and the buffer layer 31 is thinned. It should be noted that when the temporary substrate 1 is peeled off by laser, the buffer layer 31 will be damaged and a leakage channel will be formed. Therefore, in this technical solution, the buffer layer 31 is etched and thinned to remove the damaged part, thereby reducing the thickness of the buffer layer 31 in the finished GaN thin film power device. At the same time, by introducing the SiN layer 94 as a transition after thinning, it is also possible to prevent the buffer layer 31 and the channel layer 32 from forming a large strain due to excessive changes in the stress distribution after the buffer layer 31 is thinned, ensuring that a high two-dimensional electron gas concentration is still maintained after the buffer layer 31 is thinned, and optimizing the various performances of the device. More preferably, the thickness of the buffer layer 31 is 100-500 nm.

[0077] Preferably, in some embodiments, see Figure 2 , the composite adjustment layer 9 is provided with an F ion implantation region 95, and the projection of the F ion implantation region 95 on the barrier layer 33 is located between the gate electrode 4 and the drain electrode 6. The introduction of F ions will induce vacancies in the composite adjustment layer 9, thereby adjusting the distribution of the electric field. It should be noted that in conventional enhanced HEMT devices, F ions are often implanted in the barrier layer 33 or the buffer layer 31. Although it can play a role in adjusting the electric field, it will also spread to the channel region, causing additional defects in the channel layer 32, resulting in a decrease in the concentration and mobility of the two-dimensional electron gas, thereby affecting the saturation current and switching frequency of the device. However, the present technical solution injects F ions into the composite adjustment layer 9, which will not affect the concentration and mobility of the two-dimensional electron gas. Furthermore, the implantation depth D of the F ions in the F ion implantation region 95 and the thickness T of the composite adjustment layer 9 meet the following relationship: TD≥30nm. Based on this control, F ions can be better prevented from entering the buffer layer 31. Furthermore, TD=30~45nm.

[0078] Preferably, see Figure 3 In some embodiments, the GaN thin film power device further includes a space layer 34, which is disposed between the channel layer 32 and the barrier layer 33. The space layer 34 can reduce the scattering effect of the barrier layer 33 on the two-dimensional electron gas and improve the mobility of the two-dimensional electron gas. Specifically, the space layer 34 is an AlN layer with a thickness of 1 to 2 nm. If the thickness is too large, the mobility of the two-dimensional electron gas will be reduced.

[0079] Preferably, see Figure 4 In some embodiments, a P-type GaN cap layer 35 is provided below the gate electrode 4, penetrating the passivation layer 36 and contacting the barrier layer 33. The thickness of the P-type GaN cap layer 35 is 20 to 40 nm, which can improve the reliability and performance of the device.

[0080] Accordingly, an embodiment of the present invention further discloses a method for preparing a GaN thin film power device, which is used to prepare the above-mentioned GaN thin film power device, and comprises the following steps:

[0081] S1: growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a passivation layer in sequence on a temporary substrate;

[0082] Specifically, the temporary substrate 1 is a silicon substrate or a sapphire substrate, but is not limited thereto.

[0083] The nucleation layer 2 is an AlN layer with a thickness of 2-3 nm, which can be grown by PVD or MOCVD, but is not limited thereto. Preferably, in some embodiments, the nucleation layer 2 is grown by MOCVD at a growth temperature of 700-900°C.

[0084] Specifically, in some embodiments, the buffer layer 31 is grown by MOCVD at a growth temperature of 800-1000°C.

[0085] Specifically, in some embodiments, the channel layer 32 is grown by MOCVD at a growth temperature of 900-1100°C.

[0086] Specifically, in some embodiments, the barrier layer 33 is grown by MOCVD at a growth temperature of 950-1100°C.

[0087] Preferably, in some embodiments, an AlN layer is grown by MOCVD or PVD to serve as the space layer 34. Preferably, an AlN layer is grown by MOCVD to serve as the space layer 34, and the growth temperature thereof is 900-1000°C.

[0088] Preferably, in some embodiments, before growing the passivation layer 36, a P-type GaN cap layer 35 is grown on the barrier layer 33 and patterned. The P-type GaN cap layer 35 can be grown by MOCVD or MBE, but is not limited thereto. Preferably, the P-type GaN cap layer 35 is grown by MOCVD at a growth temperature of 900 to 1100°C.

[0089] Specifically, in some embodiments, the passivation layer 36 is grown by MOCVD, PECVD, or ALD, but is not limited thereto. Preferably, in some embodiments, a SiO2 layer is grown by PECVD as the passivation layer 36, and the growth temperature is 300-350° C., the chamber pressure is 0.5-5 torr, and the RF power is 50-300W.

[0090] S2: forming a source window and a drain window on the passivation layer;

[0091] Specifically, the passivation layer 36 in a specific area may be removed by wet etching or dry etching to expose the source window and the drain window, but the present invention is not limited thereto.

[0092] S3: forming a source electrode in the source window and forming a drain electrode in the drain window;

[0093] Specifically, the source electrode 5 and the drain electrode 6 can be formed by electron beam evaporation, physical sputtering and other processes, but are not limited thereto. Preferably, in some embodiments, the source electrode 5 and the drain electrode 6 can be obtained by forming a metal layer by electron beam evaporation and then annealing.

[0094] S4: forming a gate electrode on the passivation layer to obtain a first intermediate;

[0095] Specifically, the gate electrode 4 may be formed by electron beam evaporation, physical sputtering, etc., but is not limited thereto. Preferably, in some embodiments, the gate electrode 4 may be obtained by forming a metal layer by electron beam evaporation and then annealing.

[0096] S5: forming a protective adhesive layer on a side of the first intermediate body where the gate electrode is located, and bonding the first intermediate body to the hard substrate through the protective adhesive layer;

[0097] Specifically, in some embodiments, the hard substrate 7 may be a silicon substrate or a glass substrate, but is not limited thereto. The protective glue may be organic silicon, epoxy resin, polyurethane glue or photoresist, but is not limited thereto. Preferably, in some embodiments, the protective glue is photoresist, more specifically, a photoresist of model Y100 produced by Shandong Yunsheng New Materials Co., Ltd.

[0098] Specifically, in some embodiments, the protective glue layer 8 is formed on the first intermediate by spin coating, spray coating, screen printing and other processes, but is not limited thereto. Preferably, the protective glue layer 8 is formed on the first intermediate by spin coating. The thickness of the protective glue layer 8 should be greater than the thickness of the gate electrode 4, the drain electrode 6, and the source electrode 5, so that the protective glue layer 8 completely wraps the gate electrode 4, the drain electrode 6, and the source electrode 5 to protect them. More preferably, the protective glue layer 8 also wraps the sidewalls of the first intermediate with a preset thickness. More specifically, see Figure 6 , the protective adhesive layer 8 should cover at least 10-20% of the thickness of the barrier layer 33 .

[0099] The thickness of the protective adhesive layer 8 is 0.8-1.5 μm.

[0100] Preferably, in some embodiments, a protective adhesive layer is also formed on the surface of the hard substrate 7, and then the hard substrate 7 with the protective adhesive layer is bonded to the first intermediate with the protective adhesive layer 8. The bonding pressure is 300-400N, and the bonding temperature is 180-300°C.

[0101] S6: peeling off the temporary substrate, removing the nucleation layer at the same time, and exposing the buffer layer;

[0102] Specifically, the temporary substrate 1 can be peeled off by laser peeling, chemical etching peeling, etc., but is not limited thereto. Preferably, in some embodiments, the temporary substrate 1 is peeled off by laser peeling, and the nucleation layer 2 is removed at the same time.

[0103] Preferably, in some embodiments, step S6 comprises:

[0104] S61: peeling off the temporary substrate by a laser lift-off process, while removing the nucleation layer;

[0105] S62: etching and thinning the buffer layer;

[0106] Specifically, the buffer layer 31 can be thinned by dry etching or wet etching, but is not limited thereto. Preferably, in some embodiments, the buffer layer 31 is thinned by ICP etching, and the etching conditions include: using BCl3 and Cl2 as etching gas sources, the flow rate of BCl3 is 15-25sccm, the flow rate of Cl2 is 60-90sccm, the ICP power is 200-300W, and the RF power is 100-150W. This process can reduce the etching damage to the buffer layer 31 and improve the various performances of the power device.

[0107] S7: sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a composite adjustment layer;

[0108] Specifically, the SiN layer 94 can be grown by MOCVD or PECVD, but is not limited thereto. Preferably, in some embodiments, the SiN layer 94 is grown by PECVD, and its growth parameters include: a growth temperature of 250-350° C., a growth pressure of 100-200 mtorr, an RF power of 200-300 W, a flow rate of SiH4 of 100-200 sccm, a flow rate of NH3 of 300-500 sccm, and a flow rate of Ar of 100-300 sccm.

[0109] Specifically, the AlON layer 92 can be grown by PVD or ALD, but is not limited thereto. Preferably, in some embodiments, the AlON layer 92 is grown by ALD, and its growth parameters include: a deposition temperature of 200 to 350° C., an annealing temperature of 300 to 500° C., a pressure of 1 to 10 torr, a TMA flow rate of 10 to 50 sccm, a NH3 flow rate of 10 to 50 sccm, and an O2 flow rate of 10 to 50 sccm;

[0110] Specifically, the BGaN layer 93 can be grown by MOCVD or MBE, but is not limited thereto. Preferably, in some embodiments, the BGaN layer 93 is grown by MOCVD, and its growth parameters include: a growth temperature of 900 to 1100° C., a growth pressure of 100 to 400 torr;

[0111] Specifically, the HfO2 layer 91 can be grown by PVD or ALD, but is not limited thereto. Preferably, in some embodiments, the HfO2 layer 91 is grown by ALD, and its growth parameters include: a deposition temperature of 150 to 350° C., an annealing temperature of 300 to 500° C., a pressure of 1 to 10 torr, a flow rate of HfCl4 of 10 to 50 sccm, and a flow rate of O2 of 10 to 50 sccm.

[0112] Preferably, in some embodiments, step S7 includes:

[0113] S71: sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a second intermediate;

[0114] S72: performing F ion implantation on the side of the HfO2 layer of the second intermediate body corresponding to the position between the gate electrode and the drain electrode by RIE process;

[0115] Specifically, the injection time is 20 to 50 seconds, CF4 is used to generate plasma, and the power is 120 to 150W.

[0116] S8: removing the protective adhesive layer and the hard substrate.

[0117] Specifically, the protective glue layer 8 can be dissociated by organic solvent cleaning, plasma cleaning, etc., and then the hard substrate 7 can be removed, but it is not limited thereto. Preferably, in some embodiments, acetone, isopropanol, and water are used for cleaning in sequence to remove the protective glue layer 8.

[0118] The present invention is further described below with specific embodiments:

[0119] Example 1

[0120] This embodiment provides a GaN thin film power device, which includes a composite adjustment layer, a buffer layer, a channel layer, a space layer, a barrier layer, a passivation layer, a gate electrode, a source electrode and a drain electrode stacked in sequence; the composite adjustment layer, the buffer layer, the channel layer, the space layer, the barrier layer, the passivation layer and the gate electrode are stacked in sequence. The source electrode and the drain electrode are located on both sides of the gate electrode and extend through the passivation layer into the barrier layer;

[0121] The composite adjustment layer includes a HfO2 layer, an AlON layer, a BGaN layer and a SiN layer stacked in sequence. The thickness of the HfO2 layer is 30nm, the thickness of the AlON layer is 10nm, the thickness of the BGaN layer is 15nm, and the B component accounts for 0.08; the thickness of the SiN layer is 20nm.

[0122] The buffer layer is a C-doped GaN layer with a C doping concentration of 5.5×10 18 cm -3 , its thickness after thinning is 350nm; due to the poor quality of the crystal during its growth, the retained thickness after thinning is larger.

[0123] The channel layer is a GaN channel layer with a thickness of 120nm. The space layer is an AlN layer with a thickness of 1.5nm. The barrier layer is an AlGaN barrier layer with a thickness of 20nm and an Al component ratio of 0.22. The passivation layer is a SiO2 layer with a thickness of 150nm.

[0124] The structure of the source electrode and the drain electrode is: Ti / Al / Ni / Au (20nm / 130nm / 50nm / 100nm), and the structure of the gate electrode is: Ni / Au (50nm / 180nm).

[0125] The method for preparing the GaN thin film power device in this embodiment includes the following steps:

[0126] (1) A nucleation layer, a buffer layer, a channel layer, a space layer, a barrier layer and a passivation layer are sequentially grown on a temporary substrate (sapphire substrate);

[0127] Specifically, a 2.5 nm AlN layer was grown by MOCVD as a nucleation layer, and its growth temperature was 720°C.

[0128] Specifically, the buffer layer, the channel layer, the space layer, and the barrier layer are all grown by MOCVD, the growth temperature of the buffer layer is 810° C., the growth temperature of the channel layer is 980° C., the growth temperature of the space layer is 920° C., and the growth temperature of the barrier layer is 1080° C. It should be noted that the thickness of the buffer layer during the growth process is 2 μm.

[0129] Specifically, the passivation layer is grown by PECVD, and its growth parameters include: growth temperature of 320° C., chamber pressure of 1 torr, and RF power of 210W.

[0130] (2) forming a source window and a drain window on the passivation layer;

[0131] Specifically, a source window and a drain window are formed by ICP etching.

[0132] (3) forming a source electrode in the source window and forming a drain electrode in the drain window;

[0133] Specifically, a Ti layer, an Al layer, a Ni layer and an Au layer were deposited by electron beam evaporation, and then annealed at 850° C. for 30 seconds in a nitrogen atmosphere.

[0134] (4) forming a gate electrode on the passivation layer to obtain a first intermediate;

[0135] Specifically, a Ni layer and an Au layer were deposited by electron beam evaporation to form the gate electrode.

[0136] (5) forming a protective adhesive layer on the side where the gate electrode of the first intermediate is located, and bonding the first intermediate to the hard substrate through the protective adhesive layer;

[0137] Specifically, a protective glue layer (photoresist layer) with a thickness of 500 nm is first spin-coated on the Si substrate, and then a protective glue layer (photoresist layer) with a thickness of 1000 nm is spin-coated on the first intermediate, and then bonded, with a bonding pressure of 320N and a bonding temperature of 220°C.

[0138] (6) using laser lift-off to peel off the temporary substrate, remove the nucleation layer, and expose the buffer layer;

[0139] (7) etching and thinning the buffer layer;

[0140] Specifically, the buffer layer is thinned by ICP etching, and the etching conditions include: using BCl3 and Cl2 as etching gas sources, the flow rate of BCl3 is 18 sccm, the flow rate of Cl2 is 70 sccm, the ICP power is 240W, and the RF power is 130W.

[0141] (8) forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer in sequence on the buffer layer to obtain a composite adjustment layer;

[0142] Specifically, the SiN layer is grown by PECVD, and its growth parameters include: growth temperature of 310° C., growth pressure of 120 mtorr, RF power of 210 W, flow rate of SiH 4 of 140 sccm, flow rate of NH 3 of 440 sccm, and flow rate of Ar of 150 sccm.

[0143] Specifically, the AlON layer is grown by ALD, and its growth parameters include: deposition temperature of 240° C., annealing temperature of 340° C., pressure of 4 torr, flow rate of TMA of 22 sccm, flow rate of NH3 of 18 sccm, and flow rate of O2 of 30 sccm;

[0144] Specifically, the BGaN layer is grown by MOCVD, and its growth parameters include: growth temperature of 1050° C., growth pressure of 200 torr;

[0145] Specifically, the HfO2 layer is grown by ALD, and its growth parameters include: a deposition temperature of 270°C, an annealing temperature of 310°C, a pressure of 5 torr, a flow rate of HfCl4 of 42 sccm, and a flow rate of O2 of 35 sccm.

[0146] (9) Remove the protective adhesive layer and hard substrate.

[0147] Specifically, acetone, isopropyl alcohol and water are used for cleaning in sequence to dissociate the protective adhesive layer, thereby removing the hard substrate.

[0148] Example 2

[0149] This embodiment provides a GaN thin film power device, which is different from Embodiment 1 in that:

[0150] The buffer layer is a non-doped GaN layer, the growth thickness is 1.5 μm, the growth temperature is 910° C., and the thickness after thinning is 150 nm. The rest is the same as in Example 1.

[0151] Example 3

[0152] This embodiment provides a GaN thin film power device, which differs from Embodiment 2 in that:

[0153] The composite regulating layer is provided with a F ion implantation region, the projection of the F ion implantation region on the barrier layer is located between the gate electrode and the drain electrode, and the implantation depth of the F ions in the F ion implantation region is 35-42 nm.

[0154] Accordingly, in the preparation method, after preparing the composite adjustment layer, F ion implantation is performed on the side where the HfO2 layer is located and corresponding to the position between the gate electrode and the drain electrode through the RIE process; specifically, the injection time is 34s, CF4 is used to generate plasma, and the power is 135W.

[0155] The rest are the same as in Example 2.

[0156] Example 4

[0157] This embodiment provides a GaN thin film power device, which is different from Embodiment 3 in that:

[0158] A P-type GaN cap layer is provided below the gate electrode, penetrating the passivation layer and contacting the barrier layer, and has a thickness of 30 nm.

[0159] Accordingly, in the preparation method, in step (1), after forming the barrier layer, a P-type GaN cap layer is grown by MOCVD at a growth temperature of 960° C. and patterned by dry etching.

[0160] The rest is the same as Example 3.

[0161] Comparative Example 1

[0162] This comparative example provides a GaN-based power device, which differs from Example 1 in that:

[0163] The temporary substrate is not peeled off, that is, the preparation method does not include steps (5) to (8).

[0164] Accordingly, the composite regulating layer is not included in its structure, and the buffer layer is not thinned.

[0165] The rest are the same as in Example 1.

[0166] Comparative Example 2

[0167] This comparative example provides a GaN thin film power device, which differs from Example 1 in that:

[0168] The composite adjustment layer is not included, and the rest is the same as in Example 1.

[0169] The power devices obtained in Examples 1 to 4 and Comparative Examples 1 to 2 were tested, and the specific results are shown in the following table:

[0170] Saturation current (mA / mm) Breakdown voltage / V Example 1 464 1015 Example 2 458 1042 Example 3 472 1085 Example 4 475 1095 Comparative Example 1 487 954 Comparative Example 2 288 805

[0171] By comparing Example 1 with Comparative Examples 1 and 2, it can be seen that the GaN thin film power device based on the present invention can reduce the peeling loss to below 5% and effectively improve the breakdown voltage.

[0172] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A GaN thin film power device, characterized in that: The invention comprises a composite adjustment layer, a buffer layer, a channel layer, a barrier layer, a passivation layer, a gate electrode, a source electrode and a drain electrode, wherein the composite adjustment layer, the buffer layer, the channel layer, the barrier layer, the passivation layer and the gate electrode are stacked in sequence; the source electrode and the drain electrode are arranged on both sides of the gate electrode and extend through the passivation layer to the barrier layer; The composite adjustment layer includes a HfO2 layer, an AlON layer, a BGaN layer and a SiN layer stacked in sequence.

2. The GaN thin film power device according to claim 1, characterized in that: The thickness of the HfO2 layer is 10 to 50 nm; The thickness of the AlON layer is 5 to 20 nm; The thickness of the BGaN layer is 10-30 nm, and the B component accounts for 0.05-0.1; The thickness of the SiN layer is 10-30 nm.

3. The GaN thin film power device according to claim 1, characterized in that: The composite adjustment layer is provided with a F ion implantation region, and the projection of the F ion implantation region on the barrier layer is located between the gate electrode and the drain electrode; The implantation depth D of the F ions in the F ion implantation area and the thickness T of the composite adjustment layer meet the following relationship: TD ≥ 30 nm.

4. The GaN thin film power device according to any one of claims 1 to 3, characterized in that: The buffer layer is an unintentionally doped GaN layer, and its thickness is 100-500nm.

5. The GaN thin film power device according to claim 1, characterized in that: The channel layer is a GaN channel layer, and its thickness is 100-200 nm; The barrier layer is an AlGaN barrier layer, the thickness of which is 10 to 30 nm, and the Al component ratio thereof is 0.2 to 0.3; The passivation layer is a SiON layer, a SiO2 layer or an Al2O3 layer, and its thickness is 50 to 500 nm; The source electrode and the drain electrode are both a stacked structure consisting of one or at least two of a Ti layer, an Al layer, a Ni layer, an Au layer, and a Cr layer; The gate electrode is a stacked structure consisting of at least two of a Ni layer, an Au layer, a Pt layer, and a Ti layer.

6. The GaN thin film power device according to claim 1, characterized in that: A space layer is also provided between the channel layer and the barrier layer, which is an AlN layer with a thickness of 1 to 2 nm; A P-type GaN cap layer is provided below the gate electrode, penetrating the passivation layer and contacting the barrier layer. The thickness of the P-type GaN cap layer is 20-40 nm.

7. A method for preparing a GaN thin film power device, for preparing the GaN thin film power device according to any one of claims 1 to 6, characterized in that: include: sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a passivation layer on a temporary substrate; forming a source window and a drain window on the passivation layer; forming a source electrode in the source window and forming a drain electrode in the drain window; forming a gate electrode on the passivation layer to obtain a first intermediate; forming a protective adhesive layer on a side of the first intermediate body where the gate electrode is located, and bonding the first intermediate body to a hard substrate through the protective adhesive layer; peeling off the temporary substrate, removing the nucleation layer at the same time, and exposing the buffer layer; Sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a composite regulating layer; The protective adhesive layer and the hard substrate are removed.

8. The method for preparing a GaN thin film power device according to claim 7, characterized in that: The step of peeling off the temporary substrate, removing the nucleation layer and exposing the buffer layer comprises: peeling off the temporary substrate by a laser lift-off process, while removing the nucleation layer; Etching to thin the buffer layer; Wherein, the temporary substrate is a sapphire substrate, and the nucleation layer is an AlN layer; The buffer layer is an unintentionally doped GaN layer, and the buffer layer is thinned by ICP etching, and the etching conditions include: BCl3 and Cl2 are used as etching gas sources, the flow rate of BCl3 is 15-25sccm, the flow rate of Cl2 is 60-90sccm, the ICP power is 200-300W, and the RF power is 100-150W.

9. The method for preparing a GaN thin film power device according to claim 7, characterized in that: The SiN layer is grown by PECVD, and its growth parameters include: growth temperature of 250-350° C., growth pressure of 100-200 mtorr, RF power of 200-300 W, flow rate of SiH4 of 100-200 sccm, flow rate of NH3 of 300-500 sccm, and flow rate of Ar of 100-300 sccm; The AlON layer is grown by ALD, and its growth parameters include: deposition temperature of 200-350° C., annealing temperature of 300-500° C., pressure of 1-10 torr, flow rate of TMA of 10-50 sccm, flow rate of NH3 of 10-50 sccm, and flow rate of O2 of 10-50 sccm; The BGaN layer is grown by MOCVD, and its growth parameters include: growth temperature of 900-1100° C., and growth pressure of 100-400 torr; The HfO2 layer is grown by ALD, and its growth parameters include: a deposition temperature of 150-350°C, an annealing temperature of 300-500°C, a pressure of 1-10 torr, a flow rate of HfCl4 of 10-50 sccm, and a flow rate of O2 of 10-50 sccm.

10. The method for preparing a GaN thin film power device according to claim 7, characterized in that: The step of sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a composite adjustment layer comprises: Sequentially forming a SiN layer, a BGaN layer, an AlON layer and a HfO2 layer on the buffer layer to obtain a second intermediate; F ion implantation is performed on the side of the HfO2 layer of the second intermediate body corresponding to the position between the gate electrode and the drain electrode through RIE process; the implantation time is 20 to 50 seconds, CF4 is used to generate plasma, and the power is 120 to 150W.

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