Semiconductor device based on two-dimensional semimetal interface optimized contact and preparation method thereof

Abstract

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

Description

Technical Field

[0001] The present invention relates to a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which is applied to devices containing a gold-semiconductor contact structure based on a two-dimensional semiconductor, such as thin film transistors, Schottky junction diodes / transistors, etc., to eliminate the Fermi level pinning effect, controllably adjust / eliminate the Schottky barrier and contact resistance, and improve device performance. Background Art

[0002] Silicon-based technology has long been the core foundation of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices and has driven the rapid development of information technology. However, as Moore's Law drives the continued reduction of device dimensions, silicon-based CMOS technology faces limitations caused by quantum effects, such as short channel effects and heat dissipation issues, which pose a huge challenge to further advancement of process nodes. In this context, two-dimensional materials (2D materials) such as graphene, boron nitride, and transition metal dichalcogenides (TMDCs) have become the focus of research on next-generation electronic devices due to their atomically thin, dangling bond-free surface properties, and excellent optical and electrical properties.

[0003] However, existing research has found that although two-dimensional materials ideally have no dangling bonds, various defects always exist in two-dimensional materials prepared by various preparation methods, which leads to a large number of defect energy levels in the band gap. In addition, during the preparation of metal electrodes, the interaction between metal atoms and two-dimensional materials will introduce defect energy levels. In addition, chemical adsorption on the surface of two-dimensional materials will also cause additional energy levels. These effects lead to the Fermi pinning phenomenon in two-dimensional materials. Therefore, when realizing high-performance two-dimensional semiconductor gold-semiconductor contact structure devices, such as thin-film transistors (TFTs) and Schottky barrier diodes / transistors (SDBs), the Fermi level pinning effect and the intrinsic surface properties between metals and two-dimensional materials pose serious challenges: (1) Strong interface hybridization at the interface between metal electrodes and two-dimensional materials leads to the Fermi level pinning effect, which limits the improvement of contact performance. (2) There is a high Schottky barrier between the metal and the two-dimensional material, which inhibits the effective injection of electrons.

[0004] However, in the research and application of gold-semiconductor contact devices with two-dimensional semiconductors, regulating the Schottky barrier is crucial to contact resistance and device performance. In thin-film transistors based on two-dimensional semiconductors, the degree of alignment between the work function of the metal electrode and the energy band of the two-dimensional semiconductor determines the ohmic or Schottky nature of the contact. By selecting the appropriate metal material, the contact resistance and Schottky barrier can be adjusted to optimize device performance. In Schottky diodes / transistors based on two-dimensional semiconductors, adjusting the height of the contact barrier between the metal and semiconductor is key to controlling device performance. By adjusting the metal's work function, the contact barrier height can be precisely controlled, thereby optimizing the rectification and switching characteristics of the Schottky diode / transistor.

[0005] Therefore, the manufacturing process of two-dimensional electronic devices with direct contact between metal electrodes and two-dimensional materials needs to be improved urgently. Currently, there are four main methods to optimize the contact between metal electrodes and two-dimensional materials:

[0006] (1) Graphene-assisted electrode transfer method: Graphene is used as an electrode. Through the weak van der Waals (vdWs) interaction between graphene and the two-dimensional material, the Fermi pinning effect is weakened, the barrier height is reduced, and a quasi-ohmic contact is achieved. However, due to the weak interaction between graphene and the two-dimensional semiconductor material, this method has the problems of material damage during the transfer process and high graphene resistance.

[0007] (2) Direct transfer method: Transferring semiconductor 2D materials directly onto electrodes can also reduce the interaction between the metal electrode and the 2D material, thereby reducing the Fermi pinning effect. However, during the transfer process, due to the dependence on the contact quality between the 2D material and the electrode, some unavoidable defects and damage may occur. These defects and damage may degrade the performance of the material, especially at high current density.

[0008] (3) Introducing an interface layer: Using an interface layer to reduce the interaction between the metal and the two-dimensional material or to achieve heavy doping, thereby weakening the Fermi pinning effect and achieving a quasi-ohmic contact. For example, In is used as a buffer layer between the metal and the two-dimensional material to reduce Fermi pinning. In addition, the temperature required for preparing In is low, and its impact on the two-dimensional material is minimal. However, the selection and preparation of the interface layer face technical challenges such as material lattice matching and interface energy control.

[0009] (4) Doping and denaturation: Contact resistance can be directly reduced by doping, or performance can be effectively improved by converting the two-dimensional material in the contact area into a metallic phase. However, the doping process may introduce additional impurities or defects, affecting the lattice structure and electronic properties of the material, leading to increased electron scattering and loss.

[0010] While these methods have improved the contact performance between metal electrodes and two-dimensional materials to a certain extent, and have made some progress in regulating contact resistance and Schottky barriers, achieving controllable contact properties in gold-contact devices with two-dimensional semiconductors remains a challenge in practical applications. Furthermore, achieving CMOS-compatible large-scale process stability and performance consistency remains a key bottleneck. Summary of the Invention

[0011] The purpose of the present invention is to provide a semiconductor device based on two-dimensional semi-metal interface optimized contact and its preparation method, by introducing a non-transferred two-dimensional semi-metal as an interface layer between the metal electrode (source-drain electrode) and the two-dimensional material (conductive channel) through PVD deposition and CVD processes, bringing new opportunities for the device integration technology of the gold-semiconductor contact structure of two-dimensional semiconductors with advanced process technology.

[0012] To achieve the above object, the technical solution adopted by the present invention is:

[0013] A semiconductor device based on two-dimensional semi-metal interface optimized contact, comprising:

[0014] Substrate; preferably, the substrate is a silicon-based substrate;

[0015] a bottom electrode, located on the top surface of the substrate;

[0016] a dielectric layer, located on the top surface of the bottom electrode; preferably, the material of the dielectric layer is HfO2, Al2O3, SiO2, ZrO2, TiO2 or La2O3;

[0017] The two-dimensional semimetal interface layer comprises two symmetrical semimetal interface layers I and II, respectively, located on either side of the top surface of the dielectric layer. Preferably, the two-dimensional semimetal behaves as a semiconductor when in a single layer and becomes metallic when in multiple layers. Considering device miniaturization, the thickness is preferably 5 to 10 nm. The two-dimensional semimetal is made of layered van der Waals crystals such as PtSe2, PtS2, NbSe2, NbS2, or 2H-TaS2. These materials are composed of layered structures interacting with weak van der Waals forces, resulting in weak interlayer bonding and enabling the realization of ultrathin structures at the atomic level. Their semimetal / metallic state, acting as an interfacial intermediate layer, can reduce contact resistance or modulate the band structure, thereby optimizing interfacial electron transport properties.

[0018] Source-drain electrodes, located on top of the two-dimensional semi-metal interface layer, the source-drain electrodes include a source electrode and a drain electrode; preferably, the source-drain electrodes are made of Ni / Au, Cr / Au or Ti / Au;

[0019] A conductive channel is located in the middle of the top surface of the dielectric layer and is in direct contact with the two-dimensional semi-metal interface layer I and the two-dimensional semi-metal interface layer II. The conductive channel does not contact the source and drain electrodes, but is connected to the source and drain electrodes through the two-dimensional semi-metal interface layer. Preferably, the conductive channel is made of a two-dimensional material such as a transition metal disulfide.

[0020] The present invention also provides a method for preparing a semiconductor device based on the above-mentioned two-dimensional semi-metal interface optimized contact, comprising the following steps:

[0021] depositing a bottom electrode and a dielectric layer in sequence on the substrate;

[0022] A two-dimensional semi-metal interface layer I and a two-dimensional semi-metal interface layer II are respectively formed on both sides of the top surface of the dielectric layer by PVD deposition and CVD process to obtain a two-dimensional semi-metal interface layer;

[0023] Transferring the channel material to the middle of the top surface of the dielectric layer, and forming a conductive channel through photolithography, development and etching processes;

[0024] The target product is obtained by preparing source and drain electrodes on the top surface of the two-dimensional semi-metal interface layer.

[0025] The present invention has the following beneficial effects:

[0026] The present invention introduces a two-dimensional semi-metallic interface layer between the source and drain electrodes and the conductive channel through PVD deposition and CVD processes, avoiding the pollution and defects caused by the additional transfer step, and can achieve the preparation of a large-area, highly uniform and thickness-controllable interface layer to meet industrial needs.

[0027] The semiconductor device provided by the present invention significantly optimizes the contact resistance between the source and drain electrodes and the conductive channel by introducing a two-dimensional semimetal as an interface layer, eliminates Fermi level pinning, and achieves adjustable Schottky barrier height. This provides a new solution for the development and industrial application of high-performance two-dimensional semiconductor gold-semiconductor contact structure devices. Its advantages are as follows:

[0028] (1) Forming van der Waals contact to reduce interfacial chemical reactions

[0029] Unlike traditional metal-semiconductor contacts, this approach uses van der Waals interactions, rather than covalent bonds, between the two-dimensional material forming the conductive channel and the two-dimensional semimetal interface layer in semiconductor devices. Because van der Waals contacts do not form dangling bonds or introduce additional interface states, they reduce the pinning effect of interface states on the Fermi level.

[0030] (2) Screened Metal Induced Gap States (MIGS)

[0031] When a two-dimensional semimetal (such as NbSe2, TaSe2) is introduced as an intermediate layer, it can shield the wave function penetration of the metal, forming a better potential barrier control between the metal and the semiconductor, thereby reducing the FLP phenomenon.

[0032] (3) Regulate the contact work function to achieve adjustable Schottky barrier

[0033] The work function of the two-dimensional semimetal itself is adjustable. By selecting suitable two-dimensional semimetal materials, its work function can be matched with the target semiconductor and the electron or hole injection characteristics can be optimized, thereby further reducing the FLP effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic structural diagram of a semiconductor device based on two-dimensional semi-metal interface optimized contact provided by the present invention;

[0035] Figure 2 A process flow chart for a method for preparing a semiconductor device with optimized contact based on a two-dimensional semi-metal interface;

[0036] Figure numerals: 1 - substrate, 2 - bottom electrode, 3 - dielectric layer, 401 - two-dimensional semi-metal interface layer I, 402 - two-dimensional semi-metal interface layer II, 501 - source electrode, 502 - drain electrode, 6 - conductive channel. DETAILED DESCRIPTION

[0037] The present invention will be further described below with reference to the embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0038] In addition, unless otherwise specified, the preparation processes in the following embodiments are all conventional means in the prior art in the field, and therefore, they are not described in detail; the raw materials used in the following embodiments are all commercially available products and can be purchased commercially.

[0039] refer to Figure 1A semiconductor device based on two-dimensional semi-metal interface optimized contact includes a substrate 1, a bottom electrode 2 located on the top surface of the substrate, a dielectric layer 3 located on the top surface of the bottom electrode, and a two-dimensional semi-metal interface layer located on the top surface of the dielectric layer, the two-dimensional semi-metal interface layer including a two-dimensional semi-metal interface layer I401 and a two-dimensional semi-metal interface layer II402, which are symmetrically located on both sides of the top surface of the dielectric layer; the top of the two-dimensional semi-metal interface layer has a source-drain electrode, the source-drain electrode includes a source electrode 501 and a drain electrode 502, specifically, the source electrode 501 is located on the top of the two-dimensional semi-metal interface layer I401, and the drain electrode 502 is located on the top of the two-dimensional semi-metal interface layer II402; the device also includes a conductive channel 6, which is located in the middle of the top surface of the dielectric layer 3 and is in direct contact with the two-dimensional semi-metal interface layer I and the two-dimensional semi-metal interface layer II; the conductive channel does not contact the source-drain electrode, and the conductive channel is connected to the source-drain electrode through the two-dimensional semi-metal interface layer.

[0040] In a specific embodiment, the dielectric layer can be made of HfO2, Al2O3, SiO2, ZrO2, TiO2, or La2O3; the thickness of the two-dimensional semimetal interface layer is 5-10 nm, and the two-dimensional semimetal material is a layered van der Waals crystal such as PtSe2, PtS2, NbSe2, NbS2, or 2H-TaS2; the source and drain electrodes can be made of Ni / Au, Cr / Au, or Ti / Au; and the conductive channel can be made of a two-dimensional material such as transition metal disulfide. Those skilled in the art can select the desired materials based on actual needs.

[0041] The present invention also provides a method for preparing a semiconductor device based on the above-mentioned two-dimensional semi-metal interface optimized contact, and its process flow chart is as follows: Figure 2 , as follows:

[0042] In this embodiment, HfO2 is used as the dielectric layer material, a single layer of MoS2 is used as the channel material, and PtSe2 is used as the two-dimensional semi-metal interface layer material. The method for preparing a back-gate field-effect transistor with optimized interface contact comprises the following steps:

[0043] Step 1: The SiO2 / Si substrate was ultrasonically cleaned with acetone and isopropyl alcohol for 15 minutes, and then dried in an oven at 70°C. In the embodiment, a p-type heavily doped Si wafer was used, and the SiO2 oxide layer was about 300 nm thick.

[0044] Step 2: Define the shape of the back gate electrode through photolithography exposure and development, deposit 10nm Ni / 30nm Au through electron beam, and form the bottom electrode after lift-off and de-resist.

[0045] Step 3: A 15 nm HfO2 film was deposited as the dielectric layer by atomic layer deposition (ALD).

[0046] Step 4: Define the source and drain patterns by photolithography exposure and development, and deposit 6nm Pt by magnetron sputtering at a deposition rate of After degumming, it serves as the metal interface layer.

[0047] Step 5: Place the sample and selenium powder in step 4 into the same temperature zone of CVD, with selenium powder as the Se source, the distance between the sample and the selenium powder is 10 cm, the flow rate of the carrier gas (5% hydrogen / 95% argon) is 20 sccm, the selenization temperature is 400°C, and the selenization time is 1 hour to obtain a two-dimensional semi-metallic interface layer PtSe2 with a thickness of about 10 nm.

[0048] Step 6: Use wet transfer to transfer the 2D MoS2 grown on the sapphire substrate to the top of the sample obtained in step 5.

[0049] Step 7: After photolithography, exposure and development, the channel pattern is defined, and the channel material MoS2 not protected by the photoresist is etched using reactive ion etching (RIE) and soaked in acetone at 80°C for 2 hours to remove the resist.

[0050] Step 8: Define the source and drain patterns through photolithography exposure and development, deposit 10nm Ni / 30nm Au by electron beam, lift off and remove the glue, and form the source and drain electrodes on the top of the two-dimensional semi-metal interface layer PtSe2 to complete the device preparation.

[0051] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

Claims

1. A semiconductor device based on two-dimensional semi-metal interface optimized contact, characterized by: include: substrate; a bottom electrode, located on the top surface of the substrate; a dielectric layer, located on a top surface of the bottom electrode; A two-dimensional semi-metal interface layer, comprising a two-dimensional semi-metal interface layer I and a two-dimensional semi-metal interface layer II respectively and symmetrically located on both sides of the top surface of the dielectric layer; a source-drain electrode, located on top of the two-dimensional semi-metal interface layer; A conductive channel, wherein the conductive channel is located in the middle of the top surface of the dielectric layer and is in direct contact with the two-dimensional semi-metal interface layer I and the two-dimensional semi-metal interface layer II; the conductive channel is not in contact with the source and drain electrodes, and the conductive channel is connected to the source and drain electrodes through the two-dimensional semi-metal interface layer.

2. The semiconductor device based on two-dimensional semi-metal interface optimized contact according to claim 1, characterized in that: The material of the two-dimensional semi-metal interface layer is PtSe2, PtS2, NbSe2, NbS2 or 2H-TaS2.

3. The semiconductor device based on two-dimensional semi-metal interface optimized contact according to claim 1, characterized in that: The thickness of the two-dimensional semi-metal interface layer is 5 to 10 nm.

4. The semiconductor device based on two-dimensional semi-metal interface optimized contact according to claim 1, characterized in that: The substrate is a silicon-based substrate.

5. The semiconductor device based on two-dimensional semi-metal interface optimized contact according to claim 1, characterized in that: The material of the dielectric layer is HfO2, Al2O3, SiO2, ZrO2, TiO2 or La2O3.

6. The semiconductor device based on two-dimensional semi-metal interface optimized contact according to claim 1, characterized in that: The conductive channel is made of a two-dimensional material, which is transition metal disulfide.

7. The semiconductor device based on two-dimensional semi-metal interface optimized contact according to claim 1, characterized in that: The source and drain electrodes are made of Ni / Au, Cr / Au or Ti / Au.

8. A method for preparing a semiconductor device, characterized in that: The semiconductor device is a semiconductor device based on two-dimensional semi-metal interface optimized contact according to any one of claims 1 to 7, comprising the following steps: depositing a bottom electrode and a dielectric layer in sequence on the substrate; Forming a two-dimensional semi-metal interface layer I and a two-dimensional semi-metal interface layer II on both sides of the top surface of the dielectric layer by PVD deposition and CVD processes, respectively, to obtain a two-dimensional semi-metal interface layer; Transferring the channel material to the middle of the top surface of the dielectric layer, and forming a conductive channel through photolithography, development and etching processes; The target product is obtained by preparing source and drain electrodes on the top surface of the two-dimensional semi-metal interface layer.

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