Semiconductor structure, memory and method of manufacturing the same, electronic device

Abstract

Embodiments of the present application provide a semiconductor structure, a memory and a manufacturing method thereof, and an electronic device. The semiconductor structure comprises an isolation column, a first semiconductor layer, a first gate insulating layer and a first gate electrode. The isolation column extends along a first direction perpendicular to the substrate, the first semiconductor layer is arranged at the outer periphery of the isolation column, the first semiconductor layer comprises a first drain region, a first channel region and a first source region in sequence away from the substrate, and the first gate insulating layer and the first gate electrode are arranged in sequence at the outer periphery of the first channel region. Embodiments of the present application ensure the integrity of the first semiconductor layer, avoid the problem of electric leakage caused by consumption of the first semiconductor layer, and are beneficial to improving the performance of the first transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a memory and its manufacturing method, and an electronic device. Background Technology

[0002] Currently, semiconductor memory technology is developing towards increasing integration density and reducing device size. To minimize product costs, the goal is to fabricate as many device cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0003] This application addresses at least one drawback of existing methods by proposing a semiconductor structure, a memory, a method for manufacturing the same, and an electronic device.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure, including: a first transistor disposed on one side of a substrate, the first transistor comprising:

[0005] An isolation pillar extending along a first direction perpendicular to the substrate;

[0006] A first semiconductor layer is disposed on the outer periphery of the isolation pillar, and the first semiconductor layer includes a first drain region, a first channel region, and a first source region that are sequentially located away from the substrate.

[0007] A first gate insulating layer and a first gate electrode are sequentially disposed around the outer periphery of the first channel region.

[0008] Secondly, embodiments of this application provide a memory, including: a plurality of semiconductor structures provided in the first aspect;

[0009] Along a second direction parallel to the substrate, the memory includes multiple rows of first transistors, with the first gate electrode of each first transistor in each row connected to form a write word line.

[0010] Thirdly, embodiments of this application provide an electronic device, including: a memory as provided in the second aspect.

[0011] Fourthly, embodiments of this application provide a method for manufacturing a memory, comprising:

[0012] An array of first sacrificial semiconductor pillars is fabricated on one side of a substrate, such that a first trench extending in a second direction is formed between two adjacent columns of the first sacrificial semiconductor pillars arranged along a third direction, and a first dielectric layer is disposed between two adjacent rows of the first sacrificial semiconductor pillars arranged along the second direction, wherein the third direction has a design angle with the second direction and is parallel to the substrate.

[0013] A second dielectric layer is manufactured along the sidewall of the first trench; a third dielectric layer is manufactured within the first trench;

[0014] Remove the first dielectric layer and the second dielectric layer from the outer periphery of the first sacrificial drain and the first sacrificial channel region of the first sacrificial semiconductor pillar; sequentially fabricate a first gate insulating layer and a first gate electrode on the outer periphery of the first sacrificial channel region, such that each of the first gate electrodes located in the same row along the second direction is connected to form a word line; fabricate a fourth dielectric layer on the outer periphery of the first sacrificial drain.

[0015] Remove the first sacrificial semiconductor pillar to form an array of first grooves; fabricate a first semiconductor layer and isolation pillars sequentially along the first groove to form an array of first transistors, such that the isolation pillars fill the first groove.

[0016] The beneficial technical effects of the technical solutions provided in this application include:

[0017] The first semiconductor layer is disposed on the outer periphery of the isolation pillar, and the first semiconductor layer can be manufactured after the first gate electrode is manufactured. This ensures the integrity of the first semiconductor layer, avoids leakage problems caused by the consumption of the first semiconductor layer, and helps to improve the performance of the first transistor.

[0018] Moreover, the first transistor adopts the Gate-All-Around FET mode, which can increase the control capability of the first gate electrode, reduce the operating voltage, and improve the energy efficiency ratio.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0023] Figure 3 This is another schematic diagram of a semiconductor structure provided in the embodiments of this application;

[0024] Figure 4 A top view schematic diagram of a memory provided in an embodiment of this application;

[0025] Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure at point AA of a type of memory.

[0026] Figure 6 for Figure 4 A schematic diagram of the cross-sectional structure at the BB point of a type of memory.

[0027] Figure 7 for Figure 4 A schematic diagram of the cross-sectional structure at the CC position of a type of memory.

[0028] Figure 8 for Figure 4 A schematic diagram of the cross-sectional structure at the DD position of a type of memory.

[0029] Figure 9 A schematic cross-sectional view of another memory at point AA provided in an embodiment of this application;

[0030] Figure 10 A schematic cross-sectional view of the BB section of another memory provided in an embodiment of this application;

[0031] Figure 11 A schematic diagram of the cross-sectional structure at the CC position of another memory provided in an embodiment of this application;

[0032] Figure 12 A schematic diagram of the cross-sectional structure at the DD position of another memory provided in an embodiment of this application;

[0033] Figure 13 A schematic cross-sectional view of a memory at point AA provided in an embodiment of this application;

[0034] Figure 14 A schematic cross-sectional view of the BB section of another memory provided in an embodiment of this application;

[0035] Figure 15 A schematic cross-sectional view of the CC section of another memory provided in an embodiment of this application;

[0036] Figure 16 A schematic cross-sectional structure diagram of the DD section of another memory provided in an embodiment of this application;

[0037] Figure 17A schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of this application;

[0038] Figures 18 to 47 The flowchart of a method for manufacturing a memory provided in this application is shown in the diagrams of the various structures obtained in the method.

[0039] Figure 48 The flowchart of a method for manufacturing a memory provided in this application is expanded to show the process of manufacturing a second transistor.

[0040] Figures 49 to 74 The flowchart of a method for manufacturing a memory provided in this application is expanded to show various structural schematic diagrams obtained during the manufacturing of a second transistor in the process of the method.

[0041] Figure 75 The flowchart of a method for manufacturing a memory provided in this application is expanded to show the flowchart of manufacturing another second transistor in the process.

[0042] Figures 76 to 92 The flowchart of a method for manufacturing a memory provided in this application is expanded to show various structural schematic diagrams obtained during the manufacturing of another second transistor in the process of the method.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1-Substrate;

[0045] 2-First transistor; 21-Isolation pillar; 22-First semiconductor layer; 221-First drain region; 222-First channel region; 223-First source region; 23-First gate insulating layer; 24-First gate electrode;

[0046] 3-Second transistor; 31-Vertical pillar; 311-Second gate electrode; 312-Second gate insulating layer; 313-Second semiconductor layer; 32-Second source region; 33-Second drain region; 34-Back gate electrode; 35-Back gate insulating layer;

[0047] 4-First isolation layer;

[0048] 51-Write line; 52-Write bit line; 53-Read bit line; 54-Read line / Source line; 55-Source layer;

[0049] 61-First sacrificial semiconductor pillar; 611-First sacrificial drain; 612-First sacrificial channel region; 62-First trench; 63-First dielectric layer; 631-Initial first dielectric layer; 64-Second dielectric layer; 65-Third dielectric layer; 66-Fourth dielectric layer; 67-First recess;

[0050] 71 - Initial first isolation layer; 72 - Second sacrificial semiconductor layer; 73 - Second trench; 74 - Third trench; 75 - Fourth trench; 76 - Fifth trench; 77 - Sixth trench;

[0051] 81-Second sacrificial semiconductor pillar; 811-Second sacrificial source; 812-Second sacrificial channel region; 82-Second groove; 83-Initial read bit line; 84-Second isolation layer; 85-Third isolation layer; 86-Read word line layer / source line layer; 87-Fourth isolation layer; 88-Write bit line layer; 89-First sacrificial semiconductor layer;

[0052] 91 - Fifth isolation layer; 92 - Sixth isolation layer. Detailed Implementation

[0053] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0054] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0056] The research and development approach of this application includes: In related technologies, when the semiconductor pillar material is silicon, there are problems such as excessive semiconductor pillar consumption and source-gate leakage during word line manufacturing. Additionally, the small drain contact area leads to voids during metal filling, resulting in unstable contact and interconnect resistance in the bit lines. Furthermore, in a 1T1C (1 transistor 1 capacitor) structure, the capacitor volume is large, and the high aspect ratio increases the manufacturing difficulty.

[0057] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0058] This application provides a semiconductor structure, the schematic diagram of which is shown below. Figure 1 As shown, it includes a first transistor 2 disposed on one side of the substrate 1. The first transistor 2 includes an isolation pillar 21, a first semiconductor layer 22, a first gate insulating layer 23, and a first gate electrode 24.

[0059] The isolation pillar 21 extends along a first direction perpendicular to the substrate 1.

[0060] The first semiconductor layer 22 is disposed on the outer periphery of the isolation pillar 21. The first semiconductor layer 22 includes a first drain region 221, a first channel region 222 and a first source region 223 that are sequentially located away from the substrate 1.

[0061] The first gate insulating layer 23 and the first gate electrode 24 are sequentially disposed around the outer periphery of the first channel region 222.

[0062] In related technologies, after manufacturing the silicon pillars, excessive silicon pillars are easily consumed during the manufacturing of the gate electrode, leading to severe leakage.

[0063] In this embodiment, the first semiconductor layer 22 is disposed on the outer periphery of the isolation pillar 21, and the first semiconductor layer 22 can be manufactured after the first gate electrode 24 is manufactured, which can ensure the integrity of the first semiconductor layer 22, avoid leakage problems caused by consuming the first semiconductor layer 22, and help improve the performance of the first transistor 2.

[0064] Moreover, the first transistor 2 adopts the Gate-All-Around FET mode, which can increase the control capability of the first gate electrode 24, reduce the operating voltage, improve the energy efficiency ratio, and enhance the performance of the memory by increasing the drive current.

[0065] Optionally, the material of the first channel region 222 can be indium gallium zinc oxide (InGaZnO), which reduces the leakage current of the first transistor 2 and thereby improves the operating performance of the memory.

[0066] In some embodiments, the material of the first channel region 222 may further comprise one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (InGaSiO), indium tungsten oxide (InWO, IWO), and titanium oxide (InGaSiO). Materials such as TiO, zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made according to the actual situation.

[0067] The material in the first channel region 222 mentioned above only emphasizes the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0068] Optionally, refer to Figure 2 The semiconductor structure further includes a second transistor 3 disposed on the side of the first transistor 2 away from the substrate 1. The second transistor 3 includes a vertical pillar 31.

[0069] The vertical post 31 extends in a direction perpendicular to the substrate 1. The vertical post 31 includes a second gate electrode 311, a second gate insulating layer 312 and a second semiconductor layer 313 that surround the outer periphery of the second gate electrode 311 in sequence, and the second gate electrode 311 is connected to the first source region 223.

[0070] In this embodiment, a second transistor 3 is stacked on top of the first transistor 2, that is, a 2TOC (2 transistors and 0 capacitors) structure is adopted, which eliminates the need for a large capacitor structure, thereby increasing the integration density and reducing the size and cost of the memory.

[0071] Moreover, the second transistor 3 adopts a vertical channel-all-around (CAA) transistor mode, which has good thermal stability and reliability.

[0072] In one embodiment, reference Figure 2 The second transistor 3 also includes a second source region 32 and a second drain region 33.

[0073] The second drain region 33 surrounds the outer periphery of the second semiconductor layer 313 near the substrate 1, and the second source region 32 surrounds the outer periphery of the second semiconductor layer 313 away from the substrate 1.

[0074] In this embodiment, the second semiconductor layer 313 between the second drain region 33 and the second source region 32 is an effective second semiconductor layer 313 (channel region). During the operation of the second transistor 3, the second drain region 33 and the second source region 32 are turned on through the effective second semiconductor layer 313.

[0075] In another embodiment, the second transistor 3 of this application may also be a transistor controlled by a dual-gate structure, see reference. Figure 3 The second transistor 3 also includes a second source region 32, a second drain region 33, a back gate electrode 34, and a back gate insulating layer 35.

[0076] The second source region 32 surrounds the outer periphery of the second semiconductor layer 313 near the substrate 1, and the second source region 32 is used for grounding; the second drain region 33 surrounds the outer periphery of the second semiconductor layer 313 away from the substrate 1.

[0077] The back gate insulating layer 35 and the back gate electrode 34 are sequentially disposed on the outer periphery of the second semiconductor layer 313, and the back gate insulating layer 35 and the back gate electrode 34 are disposed between the second source region 32 and the second drain region 33.

[0078] In this embodiment, the second transistor 3 can be a dual-gate controlled transistor, which can enhance the control capability of the second transistor 3.

[0079] Optionally, refer to Figure 2 and Figure 3 The semiconductor structure also includes a first isolation layer 4 disposed between the first transistor 2 and the second transistor 3.

[0080] In this embodiment, the material of the first isolation layer 4 can be a material with a high dielectric constant, which can isolate the first transistor 2 and the second transistor 3, and also increase the charge storage capacity.

[0081] Based on the same inventive concept, this application provides a memory, the structural schematic diagram of which is shown below. Figures 4 to 8 As shown, a semiconductor structure as provided in the above embodiments includes multiple arrays.

[0082] Along a second direction parallel to the substrate 1, the memory includes multiple rows of first transistors 2, with the first gate electrode 24 of each first transistor 2 in each row connected to form a write word line 51.

[0083] In this embodiment, the first semiconductor layer 22 in the first transistor 2 is disposed on the outer periphery of the isolation pillar 21, and the first semiconductor layer 22 can be manufactured after the first gate electrode 24 is manufactured, which can ensure the integrity of the first semiconductor layer 22, avoid consuming the first semiconductor layer 22, and help improve the performance of the first transistor 2.

[0084] Optionally, refer to Figure 5 Along the third direction, the memory includes multiple rows of first transistors 2, and the first drain region 221 of each row of first transistors 2 is connected to a write bit line 52. The third direction is parallel to the substrate 1 and has a design angle with the second direction.

[0085] In this embodiment, the integration density of the memory can be improved by sharing a single write bit line 52.

[0086] In one possible embodiment, such as Figures 9 to 12 Along the second direction, the memory also includes multiple rows of second transistors 3 disposed on the side of the first transistor 2 away from the substrate 1, and the second drain region 33 of each row of second transistors 3 is connected to the same read bit line 53.

[0087] Along the third direction, the memory also includes multiple rows of second transistors 3, with the second source region 32 of each row of second transistors 3 connected to the same source line 54.

[0088] In this embodiment, a second transistor 3 is stacked on top of the first transistor 2, eliminating the need for a large capacitor structure, which increases integration density and reduces the size and cost of the memory.

[0089] Another possible embodiment, such as Figures 13 to 16 The memory also includes a source layer 55 for connecting to a reference power supply (e.g., ground), the source layer 55 being connected to the second source region 32 of the second transistor 3 of each semiconductor structure.

[0090] Along the second direction, the memory also includes multiple rows of second transistors 3, with the back gate electrode 35 of each row of second transistors 3 connected to form a read word line 54.

[0091] Along the third direction, the memory also includes multiple rows of second transistors 3, and the second drain region 33 of each row of second transistors 3 is connected to the same read bit line 53.

[0092] In this embodiment, the second transistor 3 can be a dual-gate controlled transistor, which can enhance the control capability of the second transistor 3.

[0093] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes any of the memories provided in the above embodiments.

[0094] In this embodiment, since the electronic device uses any of the memory provided in the foregoing embodiments, its principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0095] Optionally, the electronic device may include a smartphone, computer, tablet, artificial intelligence, wearable device, or smart mobile terminal.

[0096] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the memory provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0097] Based on the same inventive concept, embodiments of this application provide a method for manufacturing a memory, the flowchart of which is shown below. Figure 17 As shown, the method includes steps S1 to S4:

[0098] S1: First sacrificial semiconductor pillars 61 arranged in an array are fabricated on one side of substrate 1, such that a first trench 62 extending in a second direction is formed between two adjacent columns of first sacrificial semiconductor pillars 61 arranged in a third direction, and a first dielectric layer 63 is disposed between two adjacent rows of first sacrificial semiconductor pillars 61 arranged in the second direction, wherein the third direction has a design angle with the second direction and is parallel to substrate 1.

[0099] After step S1, the resulting structural diagram is as follows: Figures 28 to 31 As shown.

[0100] In this embodiment, the material of the first sacrificial semiconductor pillar 61 can be polycrystalline silicon. As a sacrificial structure, the first sacrificial semiconductor pillar 61 has high etching selectivity and is easy to remove subsequently. The material of the first dielectric layer 63 can be silicon dioxide.

[0101] S2: Fabricate a second dielectric layer 64 along the sidewall of the first trench 62; fabricate a third dielectric layer 65 within the first trench 62.

[0102] After step S2, the resulting structural diagram is as follows: Figures 32 to 35 As shown.

[0103] In this embodiment, the material of the second dielectric layer 64 can be silicon dioxide, and the material of the third dielectric layer 65 can be silicon nitride. The second dielectric layer 64 and the third dielectric layer 65 have a significant etching ratio. Subsequently, the writing line 51 is manufactured by removing the second dielectric layer 64, and the third dielectric layer 65 can isolate the writing line 51.

[0104] Optionally, a deposition process such as ALD (Atomic Layer Deposition) can be used to obtain the second dielectric layer 64 and the third dielectric layer 65.

[0105] S3: Remove the first sacrificial drain 611 and the first dielectric layer 63 and the second dielectric layer 64 around the first sacrificial channel region 612 of the first sacrificial semiconductor pillar 61; sequentially fabricate a first gate insulating layer 23 and a first gate electrode 24 around the first sacrificial channel region 612, such that each first gate electrode 24 located in the same row along the second direction is connected to form a word line 51; fabricate a fourth dielectric layer 66 around the first sacrificial drain 611.

[0106] After removing the first sacrificial drain 611 of the first sacrificial semiconductor pillar 61 and the first dielectric layer 63 and the second dielectric layer 64 around the first sacrificial channel region 612 in step S3, the resulting structural schematic diagram is as follows: Figures 36 to 38 As shown.

[0107] In step S3, a first gate insulating layer 23 and a first gate electrode 24 are sequentially fabricated on the outer periphery of the first sacrificial channel region 612, such that the first gate electrodes 24 located in the same row along the second direction are connected to form a write line 51. The resulting structural schematic diagram is shown below. Figures 39 to 41 .

[0108] After step S3, where a fourth dielectric layer 66 is fabricated around the first sacrificial drain 611, the resulting structural schematic is shown below. Figures 42 to 44 As shown.

[0109] S4: Remove the first sacrificial semiconductor pillar 61 to form an array of first grooves 67; fabricate the first semiconductor layer 22 and isolation pillars 21 sequentially along the first groove 67 to form an array of first transistors 2, such that the isolation pillars 21 fill the first groove 67.

[0110] After removing the first sacrificial semiconductor pillar 61 in step S4 to form the arrayed first grooves 67, the resulting structural schematic diagram is as follows. Figures 45 to 47 As shown.

[0111] In step S4, the first semiconductor layer 22 and the isolation pillars 21 are sequentially fabricated along the first groove 67 to form the arrayed first transistors 2. After the isolation pillars 21 fill the first groove 67, the resulting structural schematic diagram is shown below. Figures 5 to 8 As shown.

[0112] In this embodiment, by first setting the first sacrificial semiconductor pillar 61, the first semiconductor layer 22 can be manufactured first; then, after removing the first sacrificial semiconductor pillar 61, the first semiconductor layer 22 can be manufactured. This can ensure the integrity of the first semiconductor layer 22, avoid consuming the first semiconductor layer 22, and help avoid serious leakage due to excessive consumption of the first semiconductor layer 22, thereby improving the performance of the memory.

[0113] Optionally, in step S1, before fabricating the arrayed first sacrificial semiconductor pillars 61 on one side of the substrate 1, the manufacturing method further includes:

[0114] A write bit line layer 88 and a first sacrificial semiconductor layer 89 are sequentially fabricated on one side of substrate 1. The resulting structure is shown in the schematic diagram below. Figures 18 to 21 As shown.

[0115] The write bit line layer 88 and the first sacrificial semiconductor layer 89 are patterned to obtain write bit lines 52 and a sixth trench 77, such that both write bit lines 52 and the sixth trench 77 extend along a third direction and are spaced apart along a second direction. The schematic diagram of the structure obtained in this step is shown below. Figures 22 to 24 As shown.

[0116] An initial first dielectric layer 631 is fabricated within the sixth trench 77. A schematic diagram of the structure obtained in this step is shown below. Figures 25 to 27 As shown.

[0117] Optionally, a write bit line layer 88 and a first sacrificial semiconductor layer 89 can be deposited on one side of the substrate 1 using deposition processes such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or ALD (Atomic Layer Deposition).

[0118] Optionally, after fabricating the initial first dielectric layer 631 within the sixth trench 77 and before fabricating the arrayed first sacrificial semiconductor pillars 61 on one side of the substrate 1, the fabrication method further includes:

[0119] Patterning is performed on the first sacrificial semiconductor layer 89 and the initial first dielectric layer 631 to obtain the first sacrificial semiconductor pillar 61 and the first dielectric layer 63.

[0120] In this embodiment, the first sacrificial semiconductor layer 89 and the initial first dielectric layer 631 are patterned, specifically by: trenching the first sacrificial semiconductor layer 89 along the second direction to obtain the first trench 62, forming the array of first sacrificial semiconductor pillars 61, and forming the first dielectric layer 63 between two adjacent rows of first sacrificial semiconductor pillars 61 arranged along the second direction.

[0121] In one feasible embodiment, after the first semiconductor layer 22 and the isolation pillar 21 are sequentially fabricated along the first groove 67 in step S4, the manufacturing method further includes steps S101 to S106, the flowchart of which is shown below. Figure 48 As shown.

[0122] S101: An initial first isolation layer 71 is fabricated on the side of the first transistor 2 away from the substrate 1; and an array of second sacrificial semiconductor pillars 81 are fabricated on the initial first isolation layer 71.

[0123] Optionally, in step S101, fabricating an array of second sacrificial semiconductor pillars 81 on the initial first isolation layer 71 includes:

[0124] A second sacrificial semiconductor layer 72 is fabricated on the initial first isolation layer 71. A schematic diagram of the structure after this step is shown below. Figure 49 and Figure 50 As shown.

[0125] The second sacrificial semiconductor layer 72 is patterned to obtain an array of second sacrificial semiconductor pillars 81, and second trenches 73 extending along a third direction and spaced apart along a second direction, and third trenches 74 spaced apart along a third direction and extending along a second direction. A schematic diagram of the structure after this step is shown below. Figure 51 and Figure 52 As shown.

[0126] S102: Fabricate multiple read lines 53 such that the read lines 53 are disposed on the outer periphery of each second sacrificial semiconductor pillar 81 located in the same row along the second direction near one end of the substrate 1, and the multiple read lines 53 are spaced apart along the third direction and extend along the second direction.

[0127] Optionally, in step S102, manufacturing the read bit line 53 includes:

[0128] Initial read lines 83 are fabricated at the bottom of the second trench 73 and the third trench 74. A structural diagram after this step is shown below. Figure 53 and Figure 54 As shown.

[0129] A second isolation layer 84 is manufactured within the second trench 73 and the third trench 74. A structural schematic diagram after this step is shown below. Figure 55 and Figure 56 As shown.

[0130] The second isolation layer 84 and the initial read line 83 are patterned to obtain the read line 53 and the fourth trench 75, such that the read line 53 and the fourth trench 75 are both spaced apart along the third direction and extend along the second direction. A schematic diagram of the structure after this step is shown below. Figure 57 and Figure 58 As shown.

[0131] A third isolation layer 85 is manufactured within the fourth trench 75. A structural diagram illustrating this step is shown below. Figure 59 and Figure 60 As shown.

[0132] S103: Fabricate multiple source lines 54 such that the source lines 54 are disposed on the outer periphery of the second sacrificial channel regions 812 of each second sacrificial semiconductor pillar 81 located in the same column along the third direction, and the source lines 54 extend along the third direction and are spaced apart along the second direction.

[0133] Optionally, in step S103, manufacturing the source line 54 includes:

[0134] The dielectric material corresponding to the second sacrificial source 811 of the second sacrificial semiconductor pillar 81 is removed. A schematic diagram of the structure after this step is shown below. Figure 61 and Figure 62 As shown.

[0135] A source line layer 86 is fabricated such that it surrounds the outer periphery of the second sacrificial source 811 of the second sacrificial semiconductor pillar 81. A schematic diagram of the structure after this step is shown below. Figure 63 and Figure 64 As shown.

[0136] The source line layer 86 is patterned to obtain the source line 54 and the fifth trench 76, such that both the source line 54 and the fifth trench 76 extend along a third direction and are spaced apart along a second direction. A schematic diagram of the structure after this step is shown below. Figure 65 and Figure 66 As shown.

[0137] A fourth isolation layer 87 is manufactured within the fifth trench 76. A structural diagram illustrating this step is shown below. Figure 67 and Figure 68 As shown.

[0138] S104: Remove the second sacrificial semiconductor pillar 81 to form an array of second grooves 82; sequentially fabricate the second semiconductor layer 313 and the second gate insulating layer 312 along the sidewall of the second groove 82.

[0139] After removing the second sacrificial semiconductor pillar 81 in step S104 to form the arrayed second grooves 82, the resulting structural schematic diagram is as follows. Figure 69 and Figure 70 As shown.

[0140] After fabricating the second semiconductor layer 313 and the second gate insulating layer 312 sequentially along the sidewall of the second groove 82 in step S104, the resulting structural schematic diagram is shown below. Figure 71 and Figure 72 As shown.

[0141] S105: Remove the initial first isolation layer 71 above the isolation pillar 21 and the isolation pillar 21 corresponding to the first source region 223 to expose the sidewall of the first source region 223, and obtain the first isolation layer 4 formed by the initial first isolation layer 71.

[0142] After step S105, the resulting structural diagram is as follows: Figure 73 and Figure 74 As shown.

[0143] S106: A second gate electrode 311 is manufactured in the second groove 82, such that the second gate electrode 311 is connected to the first source region 223.

[0144] After step S106, the resulting structural diagram is as follows: Figures 9 to 12 As shown.

[0145] In another feasible embodiment, after the first semiconductor layer 22 and the isolation pillar 21 are sequentially fabricated along the first groove 67 in step S4, the manufacturing method further includes steps S201 to S207, the flowchart of which is shown below. Figure 75 As shown.

[0146] S201: An initial first isolation layer 71 is fabricated on the side of the first transistor 2 away from the substrate 1; and an array of second sacrificial semiconductor pillars 81 are fabricated on the initial first isolation layer 71.

[0147] S202: Fabricate a source layer 55 such that the source layer 55 surrounds the outer periphery of each second sacrificial semiconductor pillar 81 near the end of the substrate 1, and the source layer 55 is used for grounding.

[0148] After steps S201 and S202, the resulting structural diagram is as follows: Figures 76 to 77 As shown.

[0149] After step S202 and before step S203, the manufacturing method further includes:

[0150] Remove the second isolation layer 84 around the second sacrificial source 811 and the second sacrificial channel region 812. The resulting structural schematic is shown below. Figure 78 and Figure 79 As shown.

[0151] S203: Fabricate a back gate insulating layer 35 and a back gate electrode 34, such that the back gate insulating layer 35 and the back gate electrode 34 are sequentially located on the outer periphery of the second sacrificial channel region 812 of the second sacrificial semiconductor pillar 81, and the back gate electrodes 34 located in the same row are connected to form a read word line 54, and the read word lines 54 are arranged at intervals along the third direction.

[0152] After step S203, the resulting structural diagram is as follows: Figures 83 to 84 As shown.

[0153] In this embodiment, adjacent columns of reading lines 54 are isolated by a medium along a third direction.

[0154] Optionally, in step S203, manufacturing the back gate electrode 34 includes:

[0155] A back gate insulating layer 35 and a read line layer 86 are sequentially fabricated on the outer periphery of the second sacrificial channel region 812.

[0156] A fifth isolation layer 91 is fabricated above the gate insulating layer 35 and the read word line layer 86. The resulting structural schematic is shown below. Figures 80 to 82 As shown.

[0157] Patterning is performed on the reading line layer 86 and the fifth isolation layer 91 to obtain the reading line 54 and the groove (not labeled), such that the groove is arranged at intervals along the third direction and extends along the second direction.

[0158] A sixth isolation layer 92 is manufactured within the trench. This step yields... Figure 83 and Figure 84 .

[0159] S204: Manufacturing read bit lines 53 such that read bit lines 53 are disposed on the outer periphery of the second sacrificial source 811 of each second sacrificial semiconductor pillar 81 located in the same column along the third direction, and the read bit lines 53 extend along the third direction and are spaced apart along the second direction.

[0160] After step S204, the resulting structural diagram is as follows: Figures 85 to 86 As shown.

[0161] S205: Remove the second sacrificial semiconductor pillar 81 to form an array of second grooves 82; sequentially fabricate a second semiconductor layer 313 and a second gate insulating layer 312 along the sidewall of the second groove 82.

[0162] After removing the second sacrificial semiconductor pillar 81 in step S205 to form the arrayed second grooves 82, the resulting structural schematic diagram is as follows. Figure 87 and Figure 88 As shown.

[0163] After the second semiconductor layer 313 and the second gate insulating layer 312 are sequentially fabricated along the sidewall of the second groove 82 in step S205, the resulting structural schematic diagram is as follows: Figure 89 and Figure 90 As shown.

[0164] S206: Remove the initial first isolation layer 71 above the isolation pillar 21 and the isolation pillar 21 corresponding to the first source region 223 to expose the sidewall of the first source region 223, and obtain the first isolation layer 4 formed by the initial first isolation layer 71.

[0165] After step S201, the resulting structural diagram is as follows: Figures 91 to 92 As shown.

[0166] S207: A second gate electrode 311 is manufactured in the second groove 82, such that the second gate electrode 311 is connected to the first source region 223.

[0167] After step S207, the resulting structural diagram is as follows: Figures 13 to 16 As shown.

[0168] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0169] In this embodiment, the first semiconductor layer is disposed on the outer periphery of the isolation pillar, and the first semiconductor layer can be manufactured after the first gate electrode is manufactured, which can ensure the integrity of the first semiconductor layer, avoid leakage problems caused by the consumption of the first semiconductor layer, and improve the performance of the first transistor.

[0170] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0171] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0172] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0173] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0174] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0175] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0176] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A semiconductor structure, characterized by, Comprising: a first transistor disposed on one side of a substrate and a second transistor disposed on a side of the first transistor away from the substrate; the first transistor comprising: a spacer column extending along a first direction perpendicular to the substrate; a first semiconductor layer disposed on an outer periphery of the spacer column, the first semiconductor layer comprising a first drain region, a first channel region, and a first source region in order away from the substrate; a first gate insulating layer and a first gate electrode disposed in order around an outer periphery of the first channel region; the second transistor comprising: a vertical column extending along a direction perpendicular to the substrate, the vertical column comprising a second gate electrode, a second gate insulating layer disposed in order around an outer periphery of the second gate electrode, and a second semiconductor layer, the second gate electrode connected to the first source region.

2. The semiconductor structure of claim 1, wherein, the second transistor further comprising: a second source region and a second drain region; 3. The semiconductor structure of claim 1, wherein, the second drain region disposed around an outer periphery of an end of the second semiconductor layer close to the substrate, and the second source region disposed around an outer periphery of an end of the second semiconductor layer away from the substrate. the second transistor further comprising: a second source region and a second drain region, the second source region disposed around an outer periphery of an end of the second semiconductor layer close to the substrate, and the second source region connected to ground; and the second drain region disposed around an outer periphery of an end of the second semiconductor layer away from the substrate; 4. The semiconductor structure according to claim 2 or 3, characterized in that a back gate electrode and a back gate insulating layer disposed in order around an outer periphery of the second semiconductor layer, the back gate insulating layer and the back gate electrode disposed between the second source region and the second drain region.

5. A memory, comprising: Further comprising a first isolation layer disposed between the first transistor and the second transistor. Comprising a plurality of arrayed semiconductor structures as claimed in any one of claims 1 to 4; 6. The memory of claim 5, wherein, along a second direction parallel to the substrate, the memory comprising a plurality of rows of the first transistors, the first gate electrodes of the first transistors in each row connected to form a write word line.

7. The memory of claim 6, wherein, along a third direction, the memory comprising a plurality of columns of the first transistors, the first drain regions of the first transistors in each column connected to a write bit line, the third direction parallel to the substrate and having a design angle with the second direction. along the second direction, the memory further comprising a plurality of rows of the second transistors disposed on a side of the first transistors away from the substrate, the second drain regions of the second transistors in each row connected to a same read bit line; 8. The memory of claim 6, wherein, along the third direction, the memory further comprising a plurality of columns of the second transistors, the second source regions of the second transistors in each column connected to a same source line. the memory further comprising a source layer for connecting to a reference power supply, the source layer connected to the second source regions of the second transistors of the semiconductor structures; along the second direction, the memory further comprising a plurality of rows of the second transistors, the back gate electrodes of the second transistors in each row connected to form a read word line; In the third direction, the memory further comprises a plurality of columns of second transistors, each column of the second transistors having a second drain region connected to a same read bit line.

9. An electronic device, comprising: The memory comprises: The memory of any one of claims 5 to 8.

10. A method of manufacturing a memory, characterized by, The memory comprises: Fabricating an array of first sacrificial semiconductor pillars on one side of a substrate, such that first trenches extending in a second direction are formed between adjacent two columns of the first sacrificial semiconductor pillars arranged in a third direction, and such that a first dielectric layer is provided between adjacent two rows of the first sacrificial semiconductor pillars arranged in the second direction, the third direction and the second direction having a design angle and both being parallel to the substrate; Fabricating a second dielectric layer along sidewalls of the first trenches; and fabricating a third dielectric layer in the first trenches; Removing the first dielectric layer and the second dielectric layer from a periphery of a first sacrificial drain region and a first sacrificial channel region of the first sacrificial semiconductor pillar; fabricating a first gate insulating layer and a first gate electrode in sequence on a periphery of the first sacrificial channel region, such that each of the first gate electrodes in a same row in the second direction is connected to form a write word line; and fabricating a fourth dielectric layer on a periphery of the first sacrificial drain region; Removing the first sacrificial semiconductor pillar to form an array of first recesses; and fabricating a first semiconductor layer and a spacer in sequence along the first recesses to form an array of first transistors, such that the spacer fills the first recesses.

11. The method of manufacturing a memory according to claim 10, wherein, After fabricating the first semiconductor layer and the spacer in sequence along the recesses, the method further comprises: Fabricating an initial first spacer layer on a side of the first transistors away from the substrate; and fabricating an array of second sacrificial semiconductor pillars on the initial first spacer layer; Fabricating a plurality of read bit lines, such that the read bit lines are provided on a periphery of each of the second sacrificial semiconductor pillars in a same row in the second direction close to the substrate, and the read bit lines are arranged in the third direction and extend in the second direction; Fabricating a plurality of source lines, such that the source lines are provided on a periphery of a second sacrificial channel region of each of the second sacrificial semiconductor pillars in a same column in the third direction, and the source lines extend in the third direction and are arranged in the second direction; Removing the second sacrificial semiconductor pillar to form an array of second recesses; and fabricating a second semiconductor layer and a second gate insulating layer in sequence along sidewalls of the second recesses; Removing the initial first spacer layer above the spacer and the first semiconductor layer corresponding to a first source region of the spacer to expose sidewalls of the first source region, to obtain a first spacer layer formed by the initial first spacer layer; Fabricating a second gate electrode in the second recess, such that the second gate electrode is connected to the first source region.

12. The manufacturing method according to claim 11, wherein Fabricating an array of second sacrificial semiconductor pillars on the initial first spacer layer comprises: Fabricating a second sacrificial semiconductor layer on the initial first spacer layer; Patterning the second sacrificial semiconductor layer to obtain an array of second sacrificial semiconductor pillars, and to obtain second trenches extending in the third direction and arranged in the second direction, and third trenches arranged in the third direction and extending in the second direction.

13. The manufacturing method according to claim 12, wherein Fabricating a read bit line comprises: Manufacturing an initial read bit line at the bottom of the second trench and the third trench; Manufacturing a second isolation layer in the second trench and the third trench; Patterning the second isolation layer and the initial read bit line to obtain a read bit line and a fourth trench, so that the read bit line and the fourth trench are arranged in the third direction and extend in the second direction; Manufacturing a third isolation layer in the fourth trench.

14. The manufacturing method according to claim 13, wherein Manufacturing a source line, comprising: Removing the second sacrificial source electrode corresponding medium of the second sacrificial semiconductor column; Manufacturing a source line layer, so that the source line layer surrounds the outer periphery of the second sacrificial source electrode of the second sacrificial semiconductor column; Patterning the source line layer to obtain a source line and a fifth trench, so that the source line and the fifth trench extend in the third direction and are arranged in the second direction; Manufacturing a fourth isolation layer in the fifth trench.

15. The manufacturing method according to claim 10, wherein Before manufacturing the arrayed first sacrificial semiconductor column on one side of the substrate, further comprising: Manufacturing a write bit line layer and a first sacrificial semiconductor layer on one side of the substrate in sequence; Patterning the write bit line layer and the first sacrificial semiconductor layer to obtain a write bit line and a sixth trench, so that the write bit line and the sixth trench extend in the third direction and are arranged in the second direction; Manufacturing an initial first dielectric layer in the sixth trench.

16. The manufacturing method according to claim 10, wherein After conformally manufacturing a first semiconductor layer and an isolation column in the first groove in sequence, further comprising: Manufacturing an initial first isolation layer on the side of the first transistor away from the substrate; manufacturing an arrayed second sacrificial semiconductor column on the initial first isolation layer; Manufacturing a source electrode layer, so that the source electrode layer surrounds the outer periphery of each second sacrificial semiconductor column close to the substrate, and the source electrode layer is used for connecting a reference power supply; Manufacturing a back gate insulating layer and a back gate electrode, so that the back gate insulating layer and the back gate electrode are located in sequence at the outer periphery of the second sacrificial channel region of the second sacrificial semiconductor column, and the back gate electrodes in the same row are connected to form a read word line, and the read word line is arranged in the third direction; Manufacturing a read bit line, so that the read bit line is arranged at the outer periphery of the second sacrificial source electrode of each second sacrificial semiconductor column in the same column in the third direction, and the read bit line extends in the third direction and is arranged in the second direction; Removing the second sacrificial semiconductor column to form an arrayed second groove; and sequentially manufacturing a second semiconductor layer and a second gate insulating layer along the sidewall of the second groove; Removing the initial first isolation layer above the isolation column and the isolation column corresponding to the first source region of the first semiconductor layer, to expose the sidewall of the first source region to obtain a first isolation layer formed by the initial first isolation layer; Manufacturing a second gate electrode in the second groove, so that the second gate electrode is connected with the first source region.

Images