High dielectric constant gate dielectric material of in-situ oxidation of two-dimensional semiconductor material and preparation method and application thereof

Abstract

The disclosure provides a preparation method of a high dielectric constant gate dielectric material of in-situ oxidation of a two-dimensional semiconductor material, comprising: irradiating the two-dimensional semiconductor material by ultraviolet light, the ultraviolet light decomposes oxygen in air and oxidizes the two-dimensional semiconductor material, to grow the high dielectric constant gate dielectric material on the surface of the two-dimensional semiconductor material in-situ; and then rapidly heat annealing the high dielectric constant gate dielectric material, to obtain a dense high dielectric constant gate dielectric material. Wherein the two-dimensional semiconductor material is two-dimensional tantalum sulfide, the surface flatness of the two-dimensional tantalum sulfide is ± 0.5 nm, the high dielectric constant gate dielectric material is tantalum oxide, the dielectric constant of the tantalum oxide is 18-22, and the surface flatness of the tantalum oxide is ± 0.7 nm. The disclosure also provides the high dielectric constant gate dielectric material obtained by the foregoing preparation method, and a transistor and a complementary metal-oxide-semiconductor inverter using the high dielectric constant gate dielectric material as a gate dielectric material.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor chip technology, specifically relating to a high dielectric constant gate dielectric material of two-dimensional semiconductor material in situ oxidation, its preparation method, and its application. Background Technology

[0002] With the development of semiconductor technology, increasing the transistor density in chips and shrinking the transistor size are inevitable trends in achieving Moore's Law. However, since chip size has shrunk to the sub-10nm level, miniaturizing transistor size is becoming increasingly difficult, and Moore's Law is becoming unsustainable due to the physical limitations of bulk materials.

[0003] Due to the physical limitations of silicon, its process technology can only accommodate a feature size of 5 nanometers (nm), while the lattice constant of silicon atoms is 0.54nm. This means that in nanoscale chips, only 10 silicon atoms can be placed side-by-side within the feature size of a transistor. As the feature size decreases further, the number of silicon atoms will decrease even further, making problems such as heat dissipation, increased leakage current, and slower clock frequency growth difficult to solve. Simultaneously, the short-channel effect is exacerbated by the continuously shrinking transistor channel length, leading to various adverse effects such as reduced threshold voltage, carrier velocity saturation, and degradation of subthreshold characteristics. All of these factors result in a significant increase in leakage current and energy dissipation in silicon transistors, posing a tremendous challenge to the development of the silicon-based integrated circuit industry.

[0004] Two-dimensional (2D) semiconductor materials possess advantages such as high carrier mobility and suppression of short-channel effects, making them ideal channel materials for next-generation integrated circuit chips. Developing 2D semiconductor channel materials can overcome the limitations of traditional silicon-based integrated circuit processes and drive advancements in semiconductor technology. Developing ultra-thin gate dielectric layer integration processes tailored to the characteristics of 2D semiconductor materials and meeting future device requirements to realize low-power 2D transistors is fundamental to the development of 2D semiconductor devices in microelectronics. For example, in the semiconductor channel or dielectric gate stack of a field-effect transistor (FET), the dangling-bond-free surface of most 2D semiconductor materials provides compatibility with any substrate or channel semiconductor, contributing to performance improvement, structural diversity, and simplified manufacturing. However, traditional semiconductor methods employ deposition nucleation to prepare oxide gate dielectric materials. Due to the lack of dangling bonds on the surface of 2D semiconductor materials, it is difficult to integrate high-interface-quality, uniform, and ultra-thin high-dielectric-constant (κ) gate dielectric layers using standard atomic layer deposition processes. This results in challenges for the development of 2D semiconductor transistors, including high operating voltage, high power consumption, and low yield.

[0005] Therefore, designing a gate dielectric material with a high dielectric constant is of great significance in order to ensure the excellent device performance of two-dimensional semiconductor transistors. Summary of the Invention

[0006] In view of this, to solve at least one technical problem in related technologies and other aspects, this disclosure proposes a method for preparing a high-dielectric-constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material, comprising: firstly, irradiating the two-dimensional semiconductor material with ultraviolet light, wherein the ultraviolet light decomposes oxygen in the air and oxidizes the two-dimensional semiconductor material, thereby obtaining a high-dielectric-constant gate dielectric material in situ on the surface of the two-dimensional semiconductor material; and then rapidly thermally annealing the high-dielectric-constant gate dielectric material to obtain a dense high-dielectric-constant gate dielectric material. Wherein, the two-dimensional semiconductor material is two-dimensional tantalum sulfide, the surface flatness of the two-dimensional tantalum sulfide is ±0.5 nm, and the high-dielectric-constant gate dielectric material is tantalum oxide, the dielectric constant of tantalum oxide is 18-22, and the surface flatness of tantalum oxide is ±0.7 nm.

[0007] According to embodiments of this disclosure, in irradiating a two-dimensional semiconductor material with ultraviolet light, the wavelength of the ultraviolet light is 185 nm, the irradiation temperature is room temperature, and the irradiation time is 1-30 min.

[0008] According to embodiments of this disclosure, in the rapid thermal annealing of high dielectric constant gate dielectric materials, the high dielectric constant gate dielectric material is heated to 250-300°C, held at that temperature for 10-30 minutes, and then cooled in an environment of -10-5°C.

[0009] In another aspect of this disclosure, a high-dielectric-constant gate dielectric material obtained according to the aforementioned preparation method is also proposed. The high-dielectric-constant gate dielectric material is tantalum oxide, and the dielectric constant of tantalum oxide is 18-22.

[0010] According to embodiments of this disclosure, tantalum oxide is in an amorphous state.

[0011] In another aspect of this disclosure, a transistor having a high-dielectric-constant gate dielectric is also proposed. The gate dielectric layer of the transistor is the aforementioned high-dielectric-constant gate dielectric material, or is obtained by the aforementioned fabrication method.

[0012] According to embodiments of this disclosure, the gate of the transistor is graphene, and the channel layer of the transistor is molybdenum disulfide.

[0013] According to embodiments of this disclosure, the substrate of the transistor is a rigid substrate or a flexible substrate; wherein, the rigid substrate is a composite material of silicon and silicon dioxide; the flexible substrate includes a polyester polymer material, and the bending radius of the flexible substrate is 5-20 mm.

[0014] In another aspect of this disclosure, a complementary metal-oxide-semiconductor inverter is also proposed. The gate dielectric layer of the complementary metal-oxide-semiconductor inverter is the aforementioned high-dielectric-constant gate dielectric material, or is obtained by the aforementioned fabrication method.

[0015] According to embodiments of this disclosure, the N-type channel material of the complementary metal-oxide-semiconductor inverter is molybdenum disulfide, and the P-type channel material of the complementary metal-oxide-semiconductor inverter is tungsten diselenide.

[0016] According to embodiments of this disclosure, the method proposed here directly oxidizes a high-dielectric-constant gate dielectric material (tantalum oxide) onto the surface of two-dimensional tantalum sulfide using ultraviolet light irradiation. This avoids the deposition difficulties of traditional methods, reduces interface contamination and defect generation, and helps maintain the high performance and stability of two-dimensional semiconductor materials. Rapid thermal annealing further improves the density and crystallinity of the tantalum oxide gate dielectric layer, reduces porosity and defects, and enhances dielectric properties and reliability. This high-quality gate dielectric layer with a dense, smooth surface and high dielectric constant is crucial for improving the electrical performance and long-term stability of devices. This method not only simplifies the fabrication process of the gate dielectric layer for two-dimensional semiconductor devices and improves material quality and device performance, but also offers cost-effectiveness and environmental friendliness, providing a new approach for the development of high-performance, highly integrated two-dimensional semiconductor devices. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the preparation method of a high-dielectric-constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material in this embodiment of the present disclosure;

[0018] Figure 2 This is a graph showing the relationship between height and time during the ultraviolet oxidation process of tantalum sulfide in Example 1 of this disclosure;

[0019] Figure 3 This is a transmission electron microscope (TEM) image of the high dielectric constant gate dielectric material in situ oxidized from the two-dimensional semiconductor material in Embodiment 1 of this disclosure, wherein a is a TEM image of the overall structure and b is a magnified view of the interface between tantalum sulfide and tantalum oxide.

[0020] Figure 4 These are atomic force microscopy comparison images of tantalum sulfide sheet before and after oxidation in Embodiment 1 of this disclosure, where a is an atomic force microscopy image of the two-dimensional tantalum sulfide sheet before oxidation, and b is an atomic force microscopy image of tantalum oxide after oxidation.

[0021] Figure 5 This is a schematic diagram of the structure of the transistor fabricated on a rigid substrate in Embodiment 3 of this disclosure;

[0022] Figure 6 This is a transfer curve performance diagram of the transistor prepared in Embodiment 3 of this disclosure;

[0023] Figure 7 This is a schematic diagram of the structure of the transistor fabricated on a flexible substrate in Embodiment 4 of this disclosure;

[0024] Figure 8 This is a transfer curve performance diagram of the transistor prepared in Embodiment 4 of this disclosure;

[0025] Figure 9 This is a graph showing the transfer curve performance of the transistor prepared in Embodiment 4 of this disclosure at different bending radii;

[0026] Figure 10 This is a schematic diagram of the structure of the complementary metal-oxide-semiconductor (CMOS transistor) prepared in Embodiment 5 of this disclosure;

[0027] Figure 11 This is a voltage transfer performance curve diagram of the complementary metal-oxide-semiconductor inverter prepared in Embodiment 5 of this disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0029] The endpoints and any values ​​of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and such ranges or values ​​should be understood to include values ​​close to such ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be regarded as specifically disclosed in this disclosure.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0032] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person with ordinary skill in the art to which this disclosure pertains. Where the terms "first," "second," etc., are used throughout, they are used only to distinguish similar objects and should not be construed as indicating or implying their relative importance, order of precedence, or implicitly specifying the number of technical features indicated. It should be understood that the data described by "first," "second," etc., can be interchanged where appropriate.

[0033] Throughout the accompanying drawings, identical elements are represented by the same or similar reference numerals. Conventional structures or configurations have been omitted where they may cause confusion in understanding this disclosure. Furthermore, the shapes, dimensions, and positional relationships of the components in the drawings do not reflect their actual size, scale, or actual positional relationships. Additionally, any reference symbols enclosed in parentheses should not be construed as limiting this disclosure.

[0034] Similarly, to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0035] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this disclosure.

[0036] Controllable self-oxidation of some two-dimensional semiconductor materials can produce high-quality native oxide dielectric layers, potentially overcoming the bottleneck of depositing ultrathin, high-quality oxides in current common processes. This could drive the development of two-dimensional semiconductor materials in large-scale device arrays and integrated circuits. Compared to relatively inert semiconductors such as MoS2, MoSe2, and WSe2, metals like TaS2 are prone to surface oxidation in the environment. Tantalum oxide (Ta2O5) has a high dielectric constant (κ), which is a significant advantage for its use as a high-quality gate dielectric.

[0037] In the process of implementing this disclosure, it was discovered that the dielectric constant of Ta2O5, formed after the oxidation of two-dimensional tantalum sulfide, can effectively modulate the electric field and enhance the capacitance effect, thereby optimizing transistor performance. In contrast, other two-dimensional sulfide materials may not achieve sufficiently high dielectric constants after oxidation. For example, the products of some sulfide oxidation have low dielectric constants, and under the influence of the gate electric field, they cannot effectively control the carrier concentration in the channel, leading to a decrease in the switching performance and current control capability of the transistor. The band structure of tantalum oxide (Ta2O5) is beneficial for achieving good electrical performance. It can form suitable band alignment when in contact with semiconductor channel materials, reducing the interface state density. This means that during transistor operation, charge transport at the gate-channel interface is smoother, reducing adverse phenomena such as charge scattering at the interface. At the same time, tantalum oxide (Ta2O5) exhibits good chemical stability and oxidation resistance. In the complex operating environment of semiconductor devices and during long-term use, it can resist the corrosion of chemical substances and further redox reactions.

[0038] Figure 1 This is a flowchart illustrating the preparation method of a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material in this embodiment.

[0039] This disclosure proposes a method for preparing a high-dielectric-constant gate dielectric material through in-situ oxidation of a two-dimensional semiconductor material, such as... Figure 1 As shown, the process includes: firstly, irradiating a two-dimensional semiconductor material with ultraviolet light, which decomposes oxygen in the air and oxidizes the two-dimensional semiconductor material, thereby growing a high-dielectric-constant gate dielectric material in situ on the surface of the two-dimensional semiconductor material; further, rapidly thermally annealing the high-dielectric-constant gate dielectric material to obtain a dense high-dielectric-constant gate dielectric material. The two-dimensional semiconductor material is two-dimensional tantalum sulfide, with a surface flatness of ±0.5 nm; the high-dielectric-constant gate dielectric material is tantalum oxide, with a dielectric constant of 18-22 and a surface flatness of ±0.7 nm.

[0040] According to embodiments of this disclosure, the method proposed here directly oxidizes a high-dielectric-constant gate dielectric material (tantalum oxide) onto the surface of two-dimensional tantalum sulfide using ultraviolet light irradiation. This avoids the deposition difficulties of traditional methods, reduces interface contamination and defect generation, and helps maintain the high performance and stability of two-dimensional semiconductor materials. Rapid thermal annealing further improves the density and crystallinity of the tantalum oxide gate dielectric layer, reduces porosity and defects, and enhances dielectric properties and reliability. This high-quality gate dielectric layer with a dense, smooth surface and high dielectric constant is crucial for improving the electrical performance and long-term stability of devices. This method not only simplifies the fabrication process of the gate dielectric layer for two-dimensional semiconductor devices and improves material quality and device performance, but also offers cost-effectiveness and environmental friendliness, providing a new approach for the development of high-performance, highly integrated two-dimensional semiconductor devices.

[0041] Specifically, the method proposed in this disclosure requires the initial surface flatness of the two-dimensional tantalum sulfide to reach ±0.5 nm, which provides a good growth foundation. After oxidation and annealing, the surface flatness of the tantalum oxide gate dielectric layer can still be maintained at ±0.7 nm, ensuring the compactness and flatness of the tantalum oxide gate dielectric layer material. This is crucial for ensuring the uniformity of subsequent processes such as gate metal deposition and the consistency of device performance.

[0042] Specifically, the tantalum oxide gate dielectric material obtained according to the preparation method proposed in this disclosure has a dielectric constant of 18-22, which is higher than that of conventional gate dielectric materials (e.g., the dielectric constant of conventional tantalum oxide is around 15, and the dielectric constant of conventional silicon dioxide is about 3.9). This helps to reduce the physical size of the gate capacitor, improve the integration density, and at the same time reduce the gate leakage current and improve the device energy efficiency.

[0043] In some specific embodiments, after rapid thermal annealing, a nitrogen gun can be used to dry the moisture condensed on the tantalum oxide surface to obtain dry tantalum oxide material for subsequent testing and processing.

[0044] According to embodiments of this disclosure, in irradiating a two-dimensional semiconductor material with ultraviolet light, the wavelength of the ultraviolet light is 185nm, the irradiation temperature is room temperature, and the irradiation time is 1-30min, for example, 1min, 5min, 10min, 15min, 20min, 25min, 30min, etc.

[0045] According to embodiments of this disclosure, ultraviolet light has high energy, effectively decomposing oxygen in the air to generate reactive oxygen atoms, oxygen free radicals, and ozone. These reactive oxygen species can react with two-dimensional semiconductor materials (two-dimensional tantalum sulfide) to achieve in-situ oxidation. Simultaneously, the 185nm wavelength of ultraviolet light provides sufficient energy to drive the oxidation reaction while avoiding material damage that may result from excessively high energy. The irradiation time of the ultraviolet light can be adjusted according to actual needs to control the thickness and properties of the generated tantalum oxide. This flexibility makes the preparation process more controllable and adaptable to different application requirements. Specifically, short irradiation times (e.g., less than 10 minutes) can quickly form a thin oxide film, suitable for scenarios requiring a smaller oxide layer thickness, while longer irradiation times can form a thicker oxide layer or control the degree of ultraviolet oxidation, suitable for scenarios requiring a higher dielectric constant or devices with higher requirements for oxide layer thickness. The room-temperature ultraviolet oxidation operation eliminates the need for heating, avoiding material damage that may be caused by ultraviolet light at high temperatures, improving the quality of the oxide layer and the performance of the device, saving energy, and increasing production efficiency.

[0046] According to embodiments of this disclosure, in the rapid thermal annealing of a high dielectric constant gate dielectric material, the high dielectric constant gate dielectric material is heated to 250-300°C, for example, 250°C, 260°C, 270°C, 280°C, 290°C, 300°C, etc., and held at that temperature for 10-30 minutes, for example, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, etc., and then cooled in an environment of -10-5°C, for example, -10°C, -5°C, 0°C, 5°C, etc.

[0047] According to embodiments of this disclosure, rapid thermal annealing helps eliminate porosity and defects in in-situ generated tantalum oxide material, resulting in a denser high-dielectric-constant gate dielectric material (tantalum oxide). The denser structure reduces charge trapping, improves the electrical properties of tantalum oxide, and optimizes its dielectric constant and leakage characteristics, making it more suitable for gate dielectric applications. Specifically, within this temperature range, atomic migration and structural reorganization in tantalum oxide can be effectively promoted without being too high, leading to decomposition or damage. Holding at high temperatures for a sufficient time allows stress within the tantalum oxide to be released and defects to be repaired. Rapid cooling can fix the lattice structure formed during annealing, reduce grain growth, and maintain the fine grain structure of the material. The rapid thermal annealing process increases the density of tantalum oxide, reduces the interface state density, and optimizes dielectric properties.

[0048] In another aspect of this disclosure, a high-dielectric-constant gate dielectric material obtained according to the aforementioned preparation method is also proposed. The high-dielectric-constant gate dielectric material is tantalum oxide, and the dielectric constant of tantalum oxide is 18-22.

[0049] According to embodiments of this disclosure, high-k transistor devices prepared based on the aforementioned method exhibit excellent electrical performance, such as lower off-state current, lower gate leakage current, higher on / off ratio, subthreshold swing close to the room temperature limit, effective immunity to short-channel effects, and improved transistor performance stability and reliability.

[0050] According to embodiments of this disclosure, tantalum oxide is in an amorphous state.

[0051] According to embodiments of this disclosure, amorphous tantalum oxide lacks a long-range ordered structure and is therefore uniform at the microscopic level. This means that the electrical properties of the tantalum oxide gate dielectric layer are uniform at the macroscopic scale, helping to reduce fluctuations in device performance. Compared to polycrystalline materials, amorphous tantalum oxide lacks grain boundaries, which can lead to charge trapping and increased leakage current. Therefore, amorphous tantalum oxide can reduce these defects, improving device reliability, stability, and carrier mobility.

[0052] In another aspect of this disclosure, a transistor having a high-dielectric-constant gate dielectric is also proposed. The gate dielectric layer of the transistor is the aforementioned high-dielectric-constant gate dielectric material, or is obtained by the aforementioned fabrication method.

[0053] According to embodiments of this disclosure, transistor devices based on high-dielectric-constant gate dielectric materials prepared by the aforementioned method exhibit excellent electrical performance, such as lower off-state current, lower gate leakage current, higher on / off ratio, subthreshold swing close to the room temperature limit, effective immunity to short-channel effects, and improved transistor performance stability and reliability.

[0054] According to embodiments of this disclosure, the gate of the transistor is graphene, and the channel layer of the transistor is molybdenum disulfide.

[0055] According to embodiments of this disclosure, the high-dielectric-constant tantalum oxide gate dielectric layer can effectively reduce transistor leakage current, increase the on / off ratio, and thus improve transistor energy efficiency. Furthermore, due to the high dielectric constant of tantalum oxide, a thinner physical gate dielectric layer can be achieved while maintaining the same capacitance, contributing to improved transistor operating speed and integration density. The high conductivity of graphene, when used as an electrode, can reduce gate resistance and improve the overall performance of the transistor. The atomically thin molybdenum disulfide layer facilitates the realization of ultra-thin transistors, reducing device power consumption. Such transistors have broad application prospects in future electronic device fields, particularly in flexible electronics and high-speed, low-power applications.

[0056] According to embodiments of this disclosure, the substrate of the transistor is a rigid substrate or a flexible substrate; wherein, the rigid substrate is a composite material of silicon and silicon dioxide; the flexible substrate includes a polyester polymer material, and the bending radius of the flexible substrate is 5-20 mm.

[0057] According to embodiments of this disclosure, the transistor structure proposed in this disclosure has broad application prospects in the field of future electronic devices, especially in high-speed and low-power applications. Specifically, the rigid substrate provides good mechanical support, ensuring the stability of the transistor during operation and use; the flexible substrate allows the transistor to be bent, making it suitable for applications such as wearable devices, flexible electronic skin, and flexible displays; and the gate dielectric material obtained by the ultraviolet oxidation method can adapt to complex curved surface environments, allowing the device to operate under different bending conditions within a bending radius range of 5-20 mm, adapting to different application scenarios and design requirements.

[0058] In another aspect of this disclosure, a complementary metal-oxide-semiconductor (CMOS) inverter is also proposed. The gate dielectric layer of the complementary metal-oxide-semiconductor inverter is the aforementioned high-dielectric-constant gate dielectric material, or is obtained by the aforementioned fabrication method.

[0059] According to embodiments of this disclosure, the N-type channel material of the complementary metal-oxide-semiconductor inverter is molybdenum disulfide, and the P-type channel material of the complementary metal-oxide-semiconductor inverter is tungsten diselenide.

[0060] According to embodiments of this disclosure, the high-k gate dielectric layer can reduce the subthreshold oscillation of the transistor, thereby improving the switching characteristics of the inverter and reducing power loss. It can also provide a stronger electric field, thereby improving the driving capability of the transistor and enhancing the performance of the inverter. Molybdenum disulfide, as a two-dimensional semiconductor material, has high mobility and good electrical properties. Meanwhile, tungsten diselenide and molybdenum disulfide have good complementarity, which can form a highly efficient CMOS structure. Tungsten diselenide, as a P-type channel material, provides stable electrical properties, which helps improve the reliability of the inverter. Furthermore, although the CMOS transistor proposed in this disclosure uses a novel high-k material, the overall process is compatible with traditional CMOS processes, facilitating integration and large-scale production. The atomic-level thickness of the two-dimensional semiconductor material provides the possibility for further miniaturization of the device, helping to achieve higher levels of integration.

[0061] It should be noted that the described embodiments are merely some, not all, of the embodiments disclosed herein. Other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are all within the scope of protection of this disclosure.

[0062] In the preparation and testing of the following specific embodiments, images of the height changes of the two-dimensional tantalum disulfide samples due to oxidation time were measured using a Bruker Dimension ICON atomic force microscope (AFM) in tapping mode. High-resolution images of the tantalum disulfide surface before and after oxidation were acquired using a Thermo Fisher Scientific aberration-corrected field emission transmission electron microscope (Themis Z). Optical images of the devices were acquired using an RX50M microscope. All electrical measurements were performed within 10... -3 The parameters were measured under vacuum conditions using a Keithley 4200A-SCS semiconductor parameter analyzer.

[0063] Example 1

[0064] TaS2 wafers were selected and mechanically peeled off on a clean SiO2 / Si substrate to obtain two-dimensional TaS2 wafers, ensuring the integrity and uniformity of the two-dimensional TaS2 wafers.

[0065] The peeled two-dimensional TaS2 sheet was placed in an ultraviolet ozone (UV–O3) cleaner, which was then turned on to emit 185nm ultraviolet light from its low-pressure mercury lamp. During the ultraviolet irradiation, the ultraviolet light decomposed atmospheric O2 to produce atomic oxygen and ozone, which oxidized the two-dimensional TaS2 sheet. The ambient temperature was kept constant at 25℃ during the oxidation process.

[0066] Samples were removed every 5 minutes, and the thickness change was measured using an atomic force microscope (AFM). The data were recorded and an error graph of thickness change over oxidation time was plotted.

[0067] Figure 2 This is a graph showing the relationship between height and time during the ultraviolet oxidation process of tantalum sulfide in Example 1 of this disclosure.

[0068] like Figure 2 As shown, the thickness of the TaS2 sheet changes with ultraviolet light irradiation. This change is due to the electrons in the two-dimensional TaS2 sheet transforming into higher energy states under ultraviolet light excitation. These high-energy electrons can interact with sulfur atoms or tantalum atoms in tantalum sulfide, leading to the breaking of chemical bonds. Besides exciting electrons in the two-dimensional TaS2 sheet, ultraviolet light can also decompose oxygen molecules (O2) in the air to generate oxygen atoms (O), oxygen radicals (·O), or ozone (O3). These highly reactive oxygen species act as strong oxidants, reacting with tantalum sulfide to form tantalum oxide. With the continuous adsorption of oxygen atoms and the release of sulfur atoms, the structure of tantalum sulfide gradually transforms into that of tantalum oxide. During this process, the coordination number and oxidation state of the tantalum atoms change, thus forming a stable tantalum oxide layer.

[0069] More specifically, based on the fact that the oxidation rate is almost constant in the first 20 minutes and decreases with increasing oxide thickness thereafter, the oxidation time can be controlled to obtain Ta2O5 material with the target thickness and quality.

[0070] After oxidation, after UV oxidation for 30 minutes, place the material on a hot plate heated to 300°C and heat for 15-30 minutes. Then quickly place it on a prepared iron plate at -10°C for heat annealing.

[0071] The material was characterized by transmission electron microscopy to confirm the completion of the chemical transformation.

[0072] Figure 3 This is a transmission electron microscope (TEM) image of the high dielectric constant gate dielectric material in situ oxidized from the two-dimensional semiconductor material in Embodiment 1 of this disclosure, wherein a is a TEM image of the overall structure and b is a magnified view of the interface between tantalum sulfide and tantalum oxide.

[0073] like Figure 3 As shown in Figure a, the two-dimensional semiconductor material exhibits a distinct layered structure, labeled from top to bottom as Ta₂O₅, TaS₂, and SiO₂, verifying the presence of tantalum oxide and confirming the chemical transformation from TaS₂ to Ta₂O₅. The entire structure is approximately 100 nanometers thick. Figure 3 As shown in b, in a detailed view at a smaller scale (10 nm), the fine structure and uniformity of the interface between the Ta2O5 and TaS2 layers are evident. It can also be seen that Ta2O5 has a relatively low density and an amorphous structure.

[0074] Figure 4 These are atomic force microscopy comparison images of tantalum sulfide sheet before and after oxidation in Embodiment 1 of this disclosure, where a is an atomic force microscopy image of the two-dimensional tantalum sulfide sheet before oxidation, and b is an atomic force microscopy image of tantalum oxide after oxidation.

[0075] like Figure 4 As shown, the root mean square roughness of the TaS2 sample before oxidation was 0.20 nm, and the root mean square roughness of the Ta2O5 surface after 30 min of oxidation was 0.55 nm, showing good smoothness and uniformity.

[0076] Example 2

[0077] In this Example 2, tantalum oxide prepared in Example 1 is used as the gate dielectric material of the transistor, and a transistor with a high dielectric constant gate dielectric is fabricated based on a rigid substrate. The specific fabrication method is as follows.

[0078] On a Si / SiO2 substrate, a 5-nanometer chromium (Gr) adhesion layer and a 20-nanometer gold (Au) layer are sequentially deposited using processes such as electron beam evaporation to form the bottom electrode.

[0079] Using dry transfer technology, a pre-prepared two-dimensional TaS2 sheet is precisely placed on the bottom electrode, and then placed in a UV-O3 cleaner for oxidation reaction, so that the two-dimensional TaS2 sheet is converted into Ta2O5, forming a Ta2O5 gate dielectric layer.

[0080] Multiple top electrodes are fabricated by depositing 10 nm of Gr and 20 nm of Au on top of the Ta2O5 gate dielectric layer using processes such as electron beam evaporation, thereby completing the fabrication of the parallel plate capacitor device.

[0081] Using a capacitance-voltage (CV) measurement system, different frequencies of 1 MHz and 0.5 MHz, as well as DC bias voltages from -5.0 V to 5.0 V, were applied to the capacitor. The functional relationship between capacitance and the applied DC bias voltage (CV) was measured. Background capacitance interference was eliminated by plotting the functional relationship between total capacitance and area. The relative permittivity of Ta2O5 was calculated and its stability was verified.

[0082] After testing and calculation, the dielectric constant of tantalum oxide material obtained by the in-situ oxidation method of two-dimensional semiconductor material proposed in this disclosure is 15-22. Specifically, the oxidation time can be adjusted to reach 18-22, which is much higher than that of traditional dielectric materials.

[0083] Example 3

[0084] In this embodiment 3, high dielectric constant (HKMG) field-effect transistors (FETs) are fabricated using Ta2O5 with a high dielectric constant as the dielectric layer, multilayer graphene as the gate, and molybdenum disulfide (MoS2) as the channel.

[0085] Figure 5 This is a schematic diagram of the structure of the transistor fabricated on a rigid substrate in Embodiment 3 of this disclosure.

[0086] After completing the Ta2O5 preparation steps as described in Example 1, multilayer graphene was transferred onto the Ta2O5 layer as a gate electrode. Then, a MoS2 channel was fabricated, with a channel length controlled to approximately 8.8 μm. Finally, the electrodes were connected via metal leads to complete the process. Figure 5 The transistor device shown was fabricated. Using a semiconductor parameter analyzer and other equipment, the electrical performance parameters of the device, including its transfer characteristics and output curve, were measured at room temperature with a drain-source voltage (Vds) of 500 mV.

[0087] Figure 6 This is a transfer curve performance diagram of the transistor prepared in Embodiment 3 of this disclosure.

[0088] like Figure 6As shown, the device exhibits typical n-type characteristics, with a channel current on / off ratio as high as 1.2 × 10⁻⁶. 8 Gate leakage current (Ig) as low as 10 -15 The A-level transistor exhibits remarkably low gate leakage current and minimal hysteresis, indicating high uniformity of the generated Ta₂O₅. Furthermore, the subthreshold swing is close to the room temperature limit (61.2 mV / dec). Additionally, when Vg exceeds the threshold voltage, Id increases rapidly and then plateaus in the saturation region, demonstrating excellent switching characteristics.

[0089] Example 4

[0090] Figure 7 This is a schematic diagram of the structure of the transistor fabricated based on a flexible substrate in Embodiment 4 of this disclosure.

[0091] Using a 130-micrometer-thick polyester (PET) substrate as a flexible substrate, a bottom electrode, a Ta2O5 gate dielectric layer, a top electrode, and a MoS2 channel structure were fabricated on its surface using a process similar to that in Example 3, resulting in the following structure: Figure 7 The flexible HKMG field-effect transistor with the structure shown.

[0092] Using equipment such as a semiconductor parameter analyzer, the electrical characteristics of flexible HKMG field-effect transistors, including parameters such as transfer characteristics and gate leakage current, were measured under different bending radii. The data were recorded and analyzed to study their stability under static tensile strain.

[0093] Figure 8 This is a transfer curve performance diagram of the transistor prepared in Embodiment 4 of this disclosure.

[0094] like Figure 8 As shown, the HKMG field-effect transistor located on the flexible substrate exhibits good electrical performance under different source-drain voltages (Vds), with an on / off ratio close to 10. 6 It has a counterclockwise hysteresis loop and a gate leakage current of less than 1pA.

[0095] Furthermore, in this embodiment 4, the transfer characteristics of the flexible HKMG field-effect transistor under different bending radii were also verified.

[0096] Figure 9 This is a transfer curve performance diagram of the transistor prepared in Embodiment 4 of this disclosure under different bending radii.

[0097] like Figure 9As shown, its bending radius (Rb) varies from 14.8 mm to 6.1 mm, maintaining good performance even at a bending radius as low as 6.1 mm, with a small change in subthreshold swing. Specifically, the curve is relatively flat at a bending radius of 14.8 mm, with a slightly higher turn-on voltage; the curve is steep at a bending radius of 10.5 mm, with a lower turn-on voltage; and the curve is steepest at a bending radius of 6.1 mm, with the lowest turn-on voltage.

[0098] The transistor based on a flexible substrate fabricated in Example 4 demonstrates its flexibility and adjustability under different bending radii, making it an important component in the field of electronic engineering. By adjusting the bending radius, the transistor's performance can be optimized to adapt to different application scenarios.

[0099] Example 5

[0100] FET devices were fabricated using molybdenum disulfide as the N-type channel and tungsten diselenide as the P-type channel, respectively, with the gate dielectric being Ta2O5 generated by ultraviolet oxidation. The specific fabrication process was similar to that of the corresponding channel transistor in the HKMG transistor device in Example 3.

[0101] Figure 10 This is a schematic diagram of the structure of the complementary metal-oxide-semiconductor (CMOS transistor) prepared in Embodiment 5 of this disclosure.

[0102] The prepared molybdenum disulfide transistor and tungsten diselenide transistor were connected in series to construct a structure as follows: Figure 10 The CMOS inverter shown is analyzed. Using a semiconductor parameter analyzer and other equipment, the corresponding transfer characteristic curves are measured under drain-source voltage (Vds) conditions of 0.5V, 1.0V, and 2.0V to determine the transistor polarity range and measure the output characteristics. Then, the voltage transfer curve of the inverter is measured at different supply voltages (Vdd), i.e., the relationship between input voltage (Vin) and output voltage (Vout), to obtain the inverter's voltage gain and other performance parameters.

[0103] Figure 11 This is a voltage transfer performance curve diagram of the complementary metal-oxide-semiconductor inverter prepared in Embodiment 5 of this disclosure.

[0104] like Figure 11 As shown, this inverter has good performance and a steep voltage transition region. Even with a power supply voltage as low as 0.75V, signal inversion can still be clearly observed at low input voltage and high output voltage. It can achieve a voltage gain of up to 26.15V / V at 2.0V Vdd.

[0105] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for preparing a high-dielectric-constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material, characterized in that, The preparation method includes: Two-dimensional semiconductor materials are irradiated with ultraviolet light, which decomposes oxygen in the air and oxidizes the two-dimensional semiconductor materials, so as to grow a high dielectric constant gate dielectric material in situ on the surface of the two-dimensional semiconductor materials. The high dielectric constant gate dielectric material is subjected to rapid thermal annealing to obtain a dense high dielectric constant gate dielectric material; The two-dimensional semiconductor material is two-dimensional tantalum sulfide, and the surface flatness of the two-dimensional tantalum sulfide is ±0.5nm. The high dielectric constant gate dielectric material is tantalum oxide, and the dielectric constant of the tantalum oxide is 18-22, and the surface flatness of the tantalum oxide is ±0.7nm.

2. The preparation method according to claim 1, wherein, In the process of irradiating the two-dimensional semiconductor material with ultraviolet light, the wavelength of the ultraviolet light is 185nm, the irradiation temperature is room temperature, and the irradiation time is 1-30min.

3. The preparation method according to claim 1, wherein, In the rapid thermal annealing of the high dielectric constant gate dielectric material, the high dielectric constant gate dielectric material is heated to 250-300℃, held at that temperature for 10-30 minutes, and then cooled in an environment of -10-5℃.

4. A high dielectric constant gate dielectric material obtained by the preparation method according to any one of claims 1-3, characterized in that, The high dielectric constant gate dielectric material is tantalum oxide, and the dielectric constant of the tantalum oxide is 18-22.

5. The high dielectric constant gate dielectric material according to claim 4, wherein, The tantalum oxide is in an amorphous state.

6. A transistor having a high dielectric constant gate dielectric, characterized in that, The gate dielectric layer of the transistor is a high dielectric constant gate dielectric material as described in claim 4 or 5, or is obtained by the preparation method described in any one of claims 1-3.

7. The transistor according to claim 6, wherein, The gate of the transistor is graphene, and the channel layer of the transistor is molybdenum disulfide.

8. The transistor according to claim 6, wherein, The substrate of the transistor is either a rigid substrate or a flexible substrate; wherein, The rigid substrate is a composite material of silicon and silicon dioxide; The flexible substrate comprises a polyester polymer material, and the bending radius of the flexible substrate is 5-20 mm.

9. A complementary metal-oxide-semiconductor inverter, characterized in that, The gate dielectric layer of the complementary metal-oxide-semiconductor inverter is a high dielectric constant gate dielectric material as described in claim 4 or 5, or is obtained by the preparation method described in any one of claims 1-3.

10. The complementary metal-oxide-semiconductor inverter according to claim 9, wherein, The N-type channel material of the complementary metal-oxide-semiconductor inverter is molybdenum disulfide, and the P-type channel material of the complementary metal-oxide-semiconductor inverter is tungsten diselenide.

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