Display panel, manufacturing method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a manufacturing method of the display panel and electronic equipment, and relates to the technical field of display. In the display panel, the etching resistance of at least part of the isolation structures is larger than that of the sub-pixel devices, and in the process of manufacturing the sub-pixel devices with different colors in sequence, the film layers in the sub-pixel devices with different colors are manufactured on the whole face, and then the sub-pixel devices with different colors are manufactured on the whole face. The film layer covering the area position where the sub-pixel device with the color manufactured later is located needs to be etched, and the etching substance does not affect the isolation structure at the area position, so that it is ensured that when the sub-pixel device with the corresponding color is manufactured at the area position subsequently, the color of the sub-pixel device with the color manufactured later is not influenced. The dark spot defect that the sub-pixel device cannot normally display due to the fact that the isolation structure is etched is avoided, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to a display panel, a method for manufacturing a display panel, and an electronic device. Background Art

[0002] With the development of display technology, consumers have higher and higher requirements for displays, and their tolerance for dark spots that affect display effects is also getting lower and lower. How to reduce dark spot defects in display panels has become a technical problem that technical personnel in this field urgently need technology for. Summary of the invention

[0003] In order to overcome the technical problems mentioned in the above technical background, embodiments of the present application provide a display panel, a method for manufacturing a display panel, and an electronic device.

[0004] In a first aspect of the present application, a display panel is provided, the display panel comprising:

[0005] An array substrate;

[0006] An isolation structure, the isolation structure is located on the array substrate and encloses a plurality of isolation openings;

[0007] a sub-pixel device, the sub-pixel device being located within the isolation opening;

[0008] Wherein, the etching resistance of at least part of the isolation structure is greater than the etching resistance of the sub-pixel device.

[0009] In the above design, at least part of the isolation structure has a higher etching resistance than the sub-pixel device. In the process of manufacturing sub-pixel devices of different colors in sequence, the film layer in the sub-pixel device of the first color will be manufactured on the entire surface, and it is necessary to etch the film layer covering the area where the sub-pixel device of the later color is located. The etching material will not affect the isolation structure at the area, thereby ensuring that when the corresponding color sub-pixel device is manufactured at the area subsequently, there will be no dark spots caused by the etching of the isolation structure that will cause the sub-pixel device to fail to display normally, thereby improving the display effect of the display panel.

[0010] In a possible implementation manner of the present application, the isolation structure includes an isolation portion and a blocking portion that are stacked;

[0011] The orthographic projection of the isolation portion on the array substrate is located within the orthographic projection of the blocking portion on the array substrate;

[0012] Preferably, the etching resistance of the isolation portion is greater than the etching resistance of the sub-pixel device;

[0013] Preferably, the display panel further comprises a first encapsulation layer, wherein the first encapsulation layer is arranged on a side of the sub-pixel device away from the array substrate and extends to a side of the isolation structure away from the array substrate;

[0014] Preferably, the first encapsulation layer comprises a plurality of encapsulation units, each encapsulation unit is used to encapsulate a sub-pixel device in a corresponding isolation opening, and two adjacent encapsulation units are disconnected at a side of the blocking portion away from the array substrate;

[0015] Preferably, the etching resistance of at least a portion of the isolation structure is greater than the etching resistance of the first encapsulation layer.

[0016] Preferably, the etching resistance of the isolation portion is greater than the etching resistance of the first encapsulation layer.

[0017] Preferably, the material of the isolation portion is an etching-resistant conductive material.

[0018] In a possible implementation manner of the present application, the isolation structure further includes an isolation substrate, and the isolation portion and the blocking portion are stacked on a side of the isolation substrate away from the array substrate;

[0019] The orthographic projection of the isolation portion on the array substrate is located within the orthographic projection of the isolation base on the array substrate;

[0020] Preferably, the orthographic projection of the isolation substrate on the array substrate is located within the orthographic projection of the blocking portion on the array substrate;

[0021] Preferably, in the direction toward the isolation opening, the extension dimension of the isolation substrate relative to the isolation portion is a first extension length, and the isolation structures corresponding to the isolation openings where the sub-pixel devices of different colors are located have the same first extension length.

[0022] Preferably, the extension dimension of the blocking portion relative to the isolation portion is a second extension length, and the isolation structures corresponding to the isolation openings where the sub-pixel devices of different colors are located have the same second extension length;

[0023] Preferably, in the isolation structures corresponding to the isolation openings where the sub-pixel devices of different colors are located, the blocking portions have the same extension length relative to the isolation substrate in the direction toward the corresponding isolation openings;

[0024] Preferably, the material of the isolation substrate is an etching-resistant conductive material;

[0025] Preferably, the isolation substrate and the isolation portion are made of the same material.

[0026] In a possible implementation manner of the present application, the display panel further includes a pixel defining layer, the pixel defining layer is located on one side of the array substrate, and the isolation structure is located on a side of the pixel defining layer away from the array substrate;

[0027] The pixel defining layer comprises a pixel opening, wherein the pixel opening is connected to the isolation opening, and the sub-pixel device is arranged in the pixel opening;

[0028] The sub-pixel device comprises a first electrode, a light-emitting material layer and a second electrode which are stacked, wherein the light-emitting material layer extends from the pixel opening to a side of the pixel defining layer away from the array substrate, and the second electrode extends from the pixel opening to a side of the pixel defining layer away from the array substrate and overlaps the isolation structure;

[0029] Preferably, the second electrode extends from the pixel opening to a side of the pixel defining layer away from the array substrate and overlaps the isolation portion and / or the isolation base.

[0030] In a possible implementation manner of the present application, the material of the isolation substrate and the isolation portion includes indium tin oxide, and the material of the barrier portion includes titanium.

[0031] In a possible implementation manner of the present application, the isolation substrate and the isolation portion are an integrated structure; or,

[0032] The isolation base and the isolation part are separate structures.

[0033] A second aspect of the present application provides a method for manufacturing a display panel, the method comprising:

[0034] Providing an array substrate;

[0035] Manufacturing an isolation structure on one side of the array substrate, wherein the isolation structure isolates and forms a plurality of isolation openings on the array substrate;

[0036] A sub-pixel device having an etching resistance lower than that of at least a portion of the isolation structure is fabricated in the isolation opening.

[0037] In a possible implementation manner of the present application, the isolation structure includes an isolation portion and a blocking portion stacked together, and the step of manufacturing the isolation structure on one side of the array substrate includes:

[0038] Sequentially forming an isolation layer and a barrier layer on one side of the array substrate;

[0039] Performing patterning on the barrier layer, removing the barrier layer at a position corresponding to the isolation opening, and obtaining the barrier portion;

[0040] The isolation layer is patterned to remove the isolation layer between the blocking parts and part of the isolation layer below the blocking parts to obtain the isolation parts, so that the orthographic projection of the isolation parts on the array substrate is located within the orthographic projection of the blocking parts on the array substrate.

[0041] In a possible implementation manner of the present application, the isolation structure includes an isolation substrate, an isolation portion, and a blocking portion that are stacked, and the step of manufacturing the isolation structure on one side of the array substrate includes:

[0042] Sequentially manufacturing an isolation base layer, an isolation layer, and a barrier layer on one side of the array substrate;

[0043] Performing patterning on the barrier layer, removing the barrier layer at a position corresponding to the isolation opening, and obtaining the barrier portion;

[0044] Performing patterning on the isolation layer, removing the isolation layer between the blocking parts and a portion of the isolation layer below the blocking parts to expose the isolation base layer, and obtaining the isolation parts, so that the orthographic projection of the isolation parts on the array substrate is located within the orthographic projection of the blocking parts on the array substrate;

[0045] Performing patterning on the exposed isolation base layer to obtain the isolation base extending relative to the isolation portion, so that the orthographic projection of the isolation base on the array substrate is located within the orthographic projection of the blocking portion on the array substrate;

[0046] Preferably, the isolation structure comprises an isolation substrate, an isolation portion and a blocking portion which are stacked, and the step of manufacturing the isolation structure on one side of the array substrate comprises:

[0047] Sequentially forming an isolation layer and a barrier layer on one side of the array substrate;

[0048] Performing patterning on the barrier layer, removing the barrier layer at a position corresponding to the isolation opening, and obtaining the barrier portion;

[0049] Performing patterned thinning on the isolation layer, thinning the isolation layer between the blocking parts and a portion of the isolation layer below the blocking parts, to obtain an isolation part that is raised relative to the thinned isolation layer, so that the orthographic projection of the isolation part on the array substrate is located within the orthographic projection of the blocking part on the array substrate;

[0050] The thinned isolation layer is patterned to obtain an isolation base extending relative to the isolation portion, so that the orthographic projection of the isolation base on the array substrate is within the orthographic projection of the blocking portion on the array substrate.

[0051] According to a third aspect of the present application, an electronic device is provided, wherein the electronic device comprises a display panel according to any possible implementation manner of the first aspect.

[0052] The embodiments of the present application provide a display panel, a method for manufacturing a display panel, and an electronic device. In the display panel, the etching resistance of at least part of the isolation structure is greater than the etching resistance of the sub-pixel device. In the process of manufacturing sub-pixel devices of different colors in sequence, the film layer in the sub-pixel device of the color manufactured first will be manufactured on the entire surface, and it is necessary to etch the film layer covering the area where the sub-pixel device of the color manufactured later is located. The etching material will not affect the isolation structure at the area, thereby ensuring that when the corresponding color sub-pixel device is subsequently manufactured at the area, there will be no dark spots caused by the etching of the isolation structure that cause the sub-pixel device to fail to display normally, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 This is a schematic diagram of a film layer structure of a display panel provided in this embodiment;

[0055] Figure 2 for Figure 1 A diagram showing the positional relationship between the isolation structure and the sub-pixel device;

[0056] Figure 3 The second schematic diagram of the film layer structure of the display panel provided in this embodiment;

[0057] Figure 4 The third schematic diagram of the film layer structure of the display panel provided in this embodiment;

[0058] Figure 5 The fourth schematic diagram of the film layer structure of the display panel provided in this embodiment;

[0059] Figure 6 The fifth schematic diagram of the film layer structure of the display panel provided in this embodiment;

[0060] Figure 7 A schematic diagram of a process for manufacturing a display panel provided in this embodiment;

[0061] Figure 8 for Figure 7 The corresponding process diagram;

[0062] Fig. 9 for Figure 7 A process flow chart of step S12;

[0063] Fig.10 for Figure 7 Another process flow chart of step S12; Fig.11 for Figure 7 Another process flow chart of step S12.

[0064] Icons: 1-display panel; 11-array substrate; 12-isolation structure; 121-isolation opening; 122-isolation base; 123-isolation part; 124-blocking part; 13-sub-pixel device; 131-first electrode; 132-light-emitting material layer; 133-second electrode; 141-first encapsulation layer; 1411-encapsulation unit; 142-second encapsulation layer; 143-third encapsulation layer; 16-pixel defining layer; 161-pixel opening; 20-isolation base layer; 30-isolation layer; 40-blocking layer. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0066] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0067] The inventors analyzed the causes of the dark spot defect and found that the main causes of the dark spot defect include corrosion of the light-emitting material layer in the sub-pixel device and poor electrical connection of the sub-pixel device.

[0068] After further research on the main reasons for the poor dark spots, the inventor found that in the process of making sub-pixel devices of different colors in sequence, the film layer and the first encapsulation layer in the sub-pixel device of the first color will be made on the whole surface, and it is necessary to etch the film layer covering the area where the sub-pixel device of the color to be made later is located. During the etching process, it is difficult to ensure that only the excess film layer is etched away, and the etching liquid may etch the isolation structure in the area where the sub-pixel device of the color to be made later is located, thereby causing the isolation structure to change, and an etching cavity appears in a layer of the isolation structure facing the sub-pixel device, or the extension length of the isolation structure away from the array substrate is longer than that of the side close to the array substrate. The etching cavity will cause the first encapsulation layer to be unable to be in close contact with the surface of the isolation structure, so that the etching liquid can corrode the light-emitting material layer through the invasion path; and the extension length of the isolation structure away from the array substrate relative to the side close to the array substrate will be longer, which will cause the electrode of the sub-pixel device to be unable to effectively overlap with the isolation structure, thereby causing poor electrical connection.

[0069] In order to solve the above problems, the inventor innovatively designed the following technical solution, and the specific implementation scheme of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the above solutions in the prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above technical problems and the solutions proposed in this embodiment below for the above problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0070] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of a film layer structure of a display panel provided in this embodiment is illustrated. Figure 2 The positional relationship diagram between the isolation structure and the sub-pixel device in this embodiment is illustrated. In this embodiment, the display panel 1 includes an array substrate 11, an isolation structure 12 and a sub-pixel device 13. The isolation structure 12 is located on one side of the array substrate 11, and the isolation structure 12 is isolated on the array substrate 11 to form a plurality of isolation openings 121, and the sub-pixel device 13 is located in the isolation opening 121. In this embodiment, at least one sub-pixel device 13 can be arranged in the isolation opening 121, and the pixel driving circuit in the array substrate 11 is connected to the sub-pixel device 13 to drive the sub-pixel device 13 to emit light. Preferably, at least one sub-pixel device 13 is arranged in one isolation opening 121.

[0071] The etching resistance of at least part of the isolation structure 12 is greater than that of the sub-pixel device 13, that is, the material of the isolation structure 12 has a stronger etching resistance to the etching material used to etch the film layer in the sub-pixel device 13, wherein the etching material for etching the film layer in the sub-pixel device 13 may be a liquid etching material, that is, the etching resistance may be wet etching resistance, specifically, it may be acid etching liquid resistance or alkaline etching liquid resistance. In this embodiment, the stronger the etching resistance, the less likely it is to be corroded by the corresponding etching material.

[0072] In the above structure, at least part of the isolation structure 12 has a greater etching resistance than the sub-pixel device 13. In the process of manufacturing sub-pixel devices of different colors in sequence, since part of the film layer in the sub-pixel device is formed on the entire surface, when the film layer in the unnecessary area is etched, the etching material will not affect the isolation structure 12 at the position of the unnecessary area, thereby ensuring that when other color sub-pixel devices are subsequently manufactured at the position of the area, the isolation structure 12 will not be etched, causing the sub-pixel device at that position to have dark spots, thereby improving the display effect of the display panel.

[0073] For further information, please refer to Figure 3 In this embodiment, the display panel 1 further includes a first encapsulation layer 141, which is located on a side of the sub-pixel device 13 away from the array substrate 11, and extends along the surface of the isolation structure 12 facing the sub-pixel device 13 to a side of the isolation structure 12 away from the array substrate 11. The first encapsulation layer 141 includes a plurality of encapsulation units 1411, and adjacent encapsulation units 1411 are disconnected on a side of the isolation structure 12 away from the array substrate 11, wherein the material of the encapsulation unit 1411 is an inorganic material, and the encapsulation unit 1411 can be made by chemical vapor deposition. Each encapsulation unit 1411 is used to independently encapsulate the sub-pixel device 13 in an isolation opening 121, specifically, the encapsulation unit 1411 extends from a side of the sub-pixel device 13 away from the array substrate 11 along the surface of the isolation structure 12 to a side of the isolation structure 12 away from the array substrate 11.

[0074] Please refer again Figure 3 The display panel 1 further includes a second encapsulation layer 142 and a third encapsulation layer 143. The second encapsulation layer 142 at least covers the encapsulation unit 141. The material of the second encapsulation layer 142 is an organic material. The second encapsulation layer 142 can be made by inkjet printing. The second encapsulation layer 142 can fill the isolation opening 121 and form a flat surface on the side away from the array substrate 11 to facilitate subsequent film layer production. The third encapsulation layer 143 is located on the side of the second encapsulation layer 142 away from the array substrate 11. The material of the third encapsulation layer 143 is an inorganic material. The third encapsulation layer 143 can be made by chemical vapor deposition.

[0075] Since the first encapsulation layer 141 is also formed on the entire surface, when etching the first encapsulation layer 141 in unnecessary areas, the isolation structure 12 in the etching area needs to be protected from being etched. For this reason, in the present embodiment, at least part of the isolation structure 12 has an etching resistance greater than that of the first encapsulation layer 141. Preferably, the etching resistance of the isolation structure 12 is greater than that of the first encapsulation layer 141, that is, the material of the isolation structure 12 has a stronger etching resistance to the etching material used to etch the first encapsulation layer 141, wherein the etching material for etching the first encapsulation layer 141 may be a gaseous etching material, that is, the etching resistance may be dry etching resistance.

[0076] For further information, please refer to Figure 4 The isolation structure 12 includes an isolation portion 123 and a blocking portion 124 which are stacked. The orthographic projection of the isolation portion 123 on the array substrate 11 is located within the orthographic projection of the blocking portion 124 on the array substrate 11. In this embodiment, the material of the isolation portion 123 is an etching-resistant conductive material.

[0077] Please refer to Figure 5 In this embodiment, the isolation structure 12 further includes an isolation substrate 122, and the isolation portion 123 and the blocking portion 124 are stacked and arranged on a side of the isolation substrate 122 away from the array substrate 11. The orthographic projection of the isolation portion 12 on the array substrate 11 is located within the orthographic projection of the isolation substrate 122 on the array substrate 11, and the orthographic projection of the isolation substrate 122 on the array substrate 11 is located within the orthographic projection of the blocking portion 124 on the array substrate 11.

[0078] In the direction toward the isolation opening 121, the extension dimension of the isolation substrate 122 relative to the isolation portion 123 is a first extension length S1, and the extension dimension of the blocking portion 124 relative to the isolation portion 123 is a second extension length S2. The isolation structures 12 corresponding to the isolation openings 121 where the sub-pixel devices 13 of different colors are located have the same first extension length S1, and the isolation structures 12 corresponding to the isolation openings 121 where the sub-pixel devices 13 of different colors are located have the same second extension length S2. Preferably, in the isolation structures 12 corresponding to the isolation openings 121 where the sub-pixel devices 13 of different colors are located, in the direction toward the corresponding isolation openings 121, the extension lengths S3 of the blocking portion 124 relative to the isolation substrate 122 are the same.

[0079] The above design can ensure that in the isolation structure 12 corresponding to the isolation opening 121 where the sub-pixel devices 13 of different colors are located, in the direction toward the isolation opening 121, the length of the orthographic projection of the blocking portion 124 on the array substrate 11 relative to the orthographic projection of the isolation base 122 on the array substrate 11 is the same. In this way, in the process of successively manufacturing sub-pixel devices of different colors, it is possible to achieve the same overlapping effect between the sub-pixel devices of different colors and the isolation structure without adjusting the evaporation angle.

[0080] Please refer to Figure 6 Furthermore, the display panel 1 further includes a pixel defining layer 16, the pixel defining layer 16 is located on one side of the array substrate 11, and the isolation structure 12 is located on the side of the pixel defining layer 16 away from the array substrate 11. The pixel defining layer 16 includes a pixel opening 161, the pixel opening 161 is connected to the isolation opening 121, and the sub-pixel device 13 is disposed in the pixel opening 161. It should be noted that the isolation structure 12 can also be as follows Figure 3 and Figure 4 As shown, it is directly disposed on one side of the array substrate 11, and this is not limited.

[0081] The sub-pixel device 13 includes a first electrode 131, a light-emitting material layer 132 and a second electrode 133 which are stacked. The first electrodes 131 are distributed at intervals on one side of the array substrate 11. For example, the first electrodes 131 are distributed at the position of the array substrate 11 corresponding to the isolation opening 121, and the pixel opening 161 exposes the first electrode 131. The light-emitting material layer 132 extends from the pixel opening 161 to the side of the pixel defining layer 16 away from the array substrate 11, and the second electrode 133 extends from the pixel opening 161 to the side of the pixel defining layer 16 away from the array substrate and overlaps the isolation structure 12. For example, the second electrode 133 extends from the pixel opening 161 to the side of the pixel defining layer 16 away from the array substrate and overlaps the isolation portion 123 and / or the isolation substrate. The first encapsulation layer 141 extends from the pixel opening along the surface of the isolation substrate 122 and the isolation portion 123 to the side of the blocking portion 123 away from the array substrate 11. In this way, a first encapsulation layer 15 covering the entire isolation opening can be formed. In this embodiment, the first electrode 131 may be an anode of the sub-pixel device 13 , and the second electrode 133 may be a cathode of the sub-pixel device 13 .

[0082] Further, in this embodiment, the material of the isolation substrate 122 and the isolation portion 123 is an etching-resistant conductive material. Exemplarily, when the second electrode 133 overlaps the isolation substrate 122, the second electrodes 133 in adjacent isolation openings 121 can be connected together through the isolation substrate 122 to form an electrode layer with equal potential. Preferably, in this embodiment, in order to enhance the connection stability between the isolation substrate 122 and the isolation portion 123, the isolation substrate 122 and the isolation portion 123 can be made of the same material.

[0083] In this embodiment, the materials of the isolation substrate 122 and the isolation portion 123 include indium tin oxide (ITO for short), and the material of the barrier portion 124 includes titanium (Ti).

[0084] In this embodiment, the isolation base 122 and the isolation part 123 can be an integrated structure or a split structure, wherein the integrated structure means that the isolation base 122 and the isolation part 123 are made of the same film layer, and the split structure means that the isolation base 122 and the isolation part 123 are made of different film layers, wherein the materials of different film layers can be the same or different.

[0085] Based on the same inventive concept, this embodiment also provides a method for manufacturing a display panel, please refer to Figure 7 and Figure 8 ,in Figure 7 A schematic diagram illustrating a method for manufacturing a display panel is provided. Figure 8 Example Figure 7 The corresponding process diagram is combined with the following Figure 7 and Figure 8 The manufacturing method of the display panel provided in this embodiment is described in detail.

[0086] Step S11, providing an array substrate 11.

[0087] The array substrate 11 includes a plurality of metal film layers and a plurality of non-metal film layers. A pixel driving circuit for driving sub-pixel devices to emit light can be formed in the array substrate through the wiring design of the metal film layers.

[0088] Step S12 , manufacturing an isolation structure 12 on one side of the array substrate 11 .

[0089] In this embodiment, the isolation structure 12 is isolated on the array substrate 11 to form a plurality of isolation openings 121 .

[0090] Step S13 , manufacturing a sub-pixel device 13 in the isolation opening 121 , the sub-pixel device 13 having an etching resistance lower than that of at least a portion of the isolation structure 12 .

[0091] In this step, sub-pixel devices 13 of different colors are manufactured in different isolation openings in sequence. In this embodiment, each film layer in the sub-pixel device 13 can be manufactured in sequence in the isolation opening 121. It can be understood that each film layer in the sub-pixel device 13 can be manufactured in sequence in the isolation opening 121 after all the isolation openings 121 are formed, or some of the film layers in the sub-pixel device 13 can be manufactured in sequence in the isolation opening 121 after the isolation opening 121 is formed. For example, the first electrode in the sub-pixel device 13 can be manufactured first, and then the isolation opening 121 is formed on the array substrate 11. Then, in the isolation opening 121, the light-emitting material layer and the second electrode are manufactured in sequence in the first electrode away from the array substrate 11.

[0092] In this embodiment, since the etching resistance of the isolation structure 12 is greater than that of the sub-pixel device 13, in the process of manufacturing sub-pixel devices of different colors in a sequential order, the isolation structures 12 corresponding to the isolation openings 121 where the sub-pixel devices 13 of different colors are located can have the same size, thereby avoiding dark spots that cause the sub-pixel device 13 to fail to display normally due to etching of the isolation structure, thereby improving the display effect of the display panel.

[0093] Furthermore, in this embodiment, the isolation structure 12 includes an isolation portion 122 and a blocking portion 123 which are stacked. Fig. 9 , step S12 can be obtained by the following method.

[0094] First, an isolation layer 30 and a barrier layer 40 are sequentially manufactured on one side of the array substrate 11 .

[0095] Next, the barrier layer 40 is patterned to remove the barrier layer 40 at a position corresponding to the isolation opening 121 , thereby obtaining a barrier portion 124 .

[0096] Then, the isolation layer 30 is patterned to remove the isolation layer 30 between the blocking portions 124 and a portion of the isolation layer 124 below the blocking portions 124 to obtain the isolation portions 123 .

[0097] After the above steps, the orthographic projection of the isolation portion 123 on the array substrate 11 is located within the orthographic projection of the blocking portion 124 on the array substrate 11 .

[0098] Furthermore, in this embodiment, the isolation structure 12 includes an isolation substrate 122 , an isolation portion 123 and a blocking portion 123 which are stacked.

[0099] In a possible implementation of this embodiment, please refer to Fig.10 , step S12 can be obtained by the following method.

[0100] First, an isolation base layer 20 , an isolation layer 30 and a barrier layer 40 are sequentially manufactured on one side of the array substrate 11 .

[0101] Next, the barrier layer 40 is patterned to remove the barrier layer 40 at a position corresponding to the isolation opening, thereby obtaining the barrier portion 124 .

[0102] Then, the isolation layer 30 is patterned to remove the isolation layer 30 between the blocking portions 124 and a portion of the isolation layer 30 below the blocking portions 124 to expose the isolation base layer 20 , thereby obtaining the isolation portion 123 .

[0103] Through the above-mentioned manufacturing, the orthographic projection of the isolation portion 123 on the array substrate 11 can be located within the orthographic projection of the blocking portion 124 on the array substrate 11 .

[0104] Finally, the exposed isolation base layer 20 is patterned to obtain an isolation base 122 extending relative to the isolation portion 123 .

[0105] Through the above-mentioned manufacturing, the orthographic projection of the isolation base 122 on the array substrate 11 can be located within the orthographic projection of the blocking portion 124 on the array substrate 11 .

[0106] In a possible implementation of this embodiment, please refer to Fig.11 , step 12 can be produced in the following way.

[0107] First, an isolation layer 30 and a barrier layer 40 are sequentially manufactured on one side of the array substrate 11 .

[0108] Next, the barrier layer 40 is patterned to remove the barrier layer 40 at a position corresponding to the isolation opening, thereby obtaining the barrier portion 124 .

[0109] Then, the isolation layer 30 is subjected to patterned thinning treatment, and the isolation layer 30 between the blocking portions 124 and a portion of the isolation layer below the blocking portions 124 are thinned to obtain an isolation portion 123 protruding relative to the thinned isolation layer.

[0110] Through the above-mentioned manufacturing, the orthographic projection of the isolation portion 123 on the array substrate 11 can be located within the orthographic projection of the blocking portion 124 on the array substrate 11 .

[0111] Finally, the thinned isolation layer 30 is patterned to obtain an isolation base 124 extending relative to the isolation portion 123 .

[0112] Through the above-mentioned manufacturing, the orthographic projection of the isolation base 124 on the array substrate 11 can be located within the orthographic projection of the blocking portion 124 on the array substrate 11 .

[0113] Based on the same inventive concept, this embodiment also provides an electronic device, which may include the display panel described in the previous embodiment. The above display panel can reduce dark spot defects, which is beneficial to the display effect of the electronic device and enhances the market competitiveness of the electronic device.

[0114] The embodiments of the present application provide a display panel, a method for manufacturing a display panel, and an electronic device. In the display panel, the etching resistance of at least part of the isolation structure is greater than the etching resistance of the sub-pixel device. In the process of manufacturing sub-pixel devices of different colors in sequence, the film layer in the sub-pixel device of the color manufactured first will be manufactured on the entire surface, and it is necessary to etch the film layer covering the area where the sub-pixel device of the color manufactured later is located. The etching material will not affect the isolation structure at the area, thereby ensuring that when the corresponding color sub-pixel device is subsequently manufactured at the area, there will be no dark spots caused by the etching of the isolation structure that cause the sub-pixel device to fail to display normally, thereby improving the display effect of the display panel.

[0115] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: An array substrate; An isolation structure, the isolation structure is located on the array substrate and encloses a plurality of isolation openings; a sub-pixel device, the sub-pixel device being located within the isolation opening; Wherein, the etching resistance of at least part of the isolation structure is greater than the etching resistance of the sub-pixel device.

2. The display panel according to claim 1, wherein: The isolation structure includes an isolation part and a blocking part which are stacked; The orthographic projection of the isolation portion on the array substrate is located within the orthographic projection of the blocking portion on the array substrate; Preferably, the etching resistance of the isolation portion is greater than the etching resistance of the sub-pixel device; Preferably, the display panel further comprises a first encapsulation layer, wherein the first encapsulation layer is arranged on a side of the sub-pixel device away from the array substrate and extends to a side of the isolation structure away from the array substrate; Preferably, the first encapsulation layer comprises a plurality of encapsulation units, each encapsulation unit is used to encapsulate a sub-pixel device in a corresponding isolation opening, and two adjacent encapsulation units are disconnected at a side of the blocking portion away from the array substrate; Preferably, the etching resistance of at least part of the isolation structure is greater than the etching resistance of the first encapsulation layer; Preferably, the etching resistance of the isolation portion is greater than the etching resistance of the first encapsulation layer; Preferably, the material of the isolation portion is an etching-resistant conductive material.

3. The display panel according to claim 2, wherein: The isolation structure further comprises an isolation substrate, wherein the isolation portion and the blocking portion are stacked on a side of the isolation substrate away from the array substrate; The orthographic projection of the isolation portion on the array substrate is located within the orthographic projection of the isolation base on the array substrate; Preferably, the orthographic projection of the isolation substrate on the array substrate is located within the orthographic projection of the blocking portion on the array substrate; Preferably, in the direction toward the isolation opening, the extension dimension of the isolation substrate relative to the isolation portion is a first extension length, and the isolation structures corresponding to the isolation openings where the sub-pixel devices of different colors are located have the same first extension length; Preferably, the extension dimension of the blocking portion relative to the isolation portion is a second extension length, and the isolation structures corresponding to the isolation openings where the sub-pixel devices of different colors are located have the same second extension length; Preferably, in the isolation structures corresponding to the isolation openings where the sub-pixel devices of different colors are located, the blocking portions have the same extension length relative to the isolation substrate in the direction toward the corresponding isolation openings; Preferably, the material of the isolation substrate is an etching-resistant conductive material; Preferably, the isolation substrate and the isolation portion are made of the same material.

4. The display panel according to claim 3, wherein: The display panel further comprises a pixel defining layer, wherein the pixel defining layer is located at one side of the array substrate, and the isolation structure is located at a side of the pixel defining layer away from the array substrate; The pixel defining layer comprises a pixel opening, wherein the pixel opening is connected to the isolation opening, and the sub-pixel device is arranged in the pixel opening; The sub-pixel device comprises a first electrode, a light-emitting material layer and a second electrode which are stacked, wherein the light-emitting material layer extends from the pixel opening to a side of the pixel defining layer away from the array substrate, and the second electrode extends from the pixel opening to a side of the pixel defining layer away from the array substrate and overlaps the isolation structure; Preferably, the second electrode extends from the pixel opening to a side of the pixel defining layer away from the array substrate and overlaps the isolation portion and / or the isolation base.

5. The display panel according to claim 3, wherein: The materials of the isolation substrate and the isolation part include indium tin oxide, and the material of the barrier part includes titanium.

6. The display panel according to claim 3, wherein: The isolation substrate and the isolation portion are an integrated structure; or, The isolation base and the isolation part are separate structures.

7. A method for manufacturing a display panel, characterized in that: The method comprises: Providing an array substrate; Manufacturing an isolation structure on one side of the array substrate, wherein the isolation structure isolates and forms a plurality of isolation openings on the array substrate; A sub-pixel device having an etching resistance lower than that of at least a portion of the isolation structure is fabricated in the isolation opening.

8. The method for manufacturing a display panel according to claim 7, wherein: The isolation structure includes an isolation portion and a blocking portion stacked together, and the step of manufacturing the isolation structure on one side of the array substrate includes: Sequentially forming an isolation layer and a barrier layer on one side of the array substrate; Performing patterning on the barrier layer, removing the barrier layer at a position corresponding to the isolation opening, and obtaining the barrier portion; The isolation layer is patterned to remove the isolation layer between the blocking parts and part of the isolation layer below the blocking parts to obtain the isolation parts, so that the orthographic projection of the isolation parts on the array substrate is located within the orthographic projection of the blocking parts on the array substrate.

9. The method for manufacturing a display panel according to claim 7, wherein: The isolation structure includes an isolation substrate, an isolation portion, and a blocking portion that are stacked, and the step of manufacturing the isolation structure on one side of the array substrate includes: Sequentially manufacturing an isolation base layer, an isolation layer, and a barrier layer on one side of the array substrate; Performing patterning on the barrier layer, removing the barrier layer at a position corresponding to the isolation opening, and obtaining the barrier portion; Performing patterning on the isolation layer, removing the isolation layer between the blocking parts and a portion of the isolation layer below the blocking parts to expose the isolation base layer, and obtaining the isolation parts, so that the orthographic projection of the isolation parts on the array substrate is located within the orthographic projection of the blocking parts on the array substrate; Performing patterning on the exposed isolation base layer to obtain the isolation base extending relative to the isolation portion, so that the orthographic projection of the isolation base on the array substrate is located within the orthographic projection of the blocking portion on the array substrate; Preferably, the isolation structure comprises an isolation substrate, an isolation portion and a blocking portion which are stacked, and the step of manufacturing the isolation structure on one side of the array substrate comprises: Sequentially forming an isolation layer and a barrier layer on one side of the array substrate; Performing patterning on the barrier layer, removing the barrier layer at a position corresponding to the isolation opening, and obtaining the barrier portion; Performing patterned thinning on the isolation layer, thinning the isolation layer between the blocking parts and a portion of the isolation layer below the blocking parts, to obtain an isolation part that is raised relative to the thinned isolation layer, so that the orthographic projection of the isolation part on the array substrate is located within the orthographic projection of the blocking part on the array substrate; The thinned isolation layer is patterned to obtain an isolation base extending relative to the isolation portion, so that the orthographic projection of the isolation base on the array substrate is within the orthographic projection of the blocking portion on the array substrate.

10. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 6.

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