Display substrate and display device

Abstract

The display substrate is provided with a display area and a non-display area and comprises a substrate, a driving circuit group and a virtual driving circuit group, the driving circuit group and the virtual driving circuit group are arranged on the substrate and located in the non-display area, the driving circuit group comprises at least one shifting register, and the virtual driving circuit group comprises at least one virtual shifting register. The virtual shift register comprises a plurality of virtual active patterns and a plurality of virtual control electrodes, the shift register comprises a plurality of transistors, each transistor comprises an active pattern and a control electrode, the shape of at least part of at least one virtual active pattern is the same as the shape of at least part of the active pattern of at least one transistor, and at least one control electrode is arranged on the active pattern of at least one transistor. The shape of at least part of the at least one virtual control electrode is the same as that of at least part of the control electrode of the at least one transistor, and the orthographic projection of the at least one virtual active pattern on the substrate and the orthographic projection of the at least one virtual control electrode on the substrate do not have an overlapping area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area, comprising: a substrate, and a pixel driving circuit disposed on the substrate and located in the display area, and a driving circuit group and a virtual driving circuit group located in the non-display area, wherein the pixel driving circuit is electrically connected to the driving circuit group, the driving circuit group comprises: at least one shift register, the virtual driving circuit group comprises: at least one virtual shift register, the virtual shift register comprises: a plurality of virtual active patterns and a plurality of virtual control electrodes, the shift register comprises: a plurality of transistors, and the transistor comprises: an active pattern and a control electrode;

[0005] The shape of at least a portion of at least one virtual active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, the shape of at least a portion of at least one virtual control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, and there is no overlapping area between the orthographic projection of at least one of the virtual active patterns and the orthographic projection of at least one of the virtual control electrodes on the substrate.

[0006] In an exemplary embodiment, a distance between an orthographic projection of at least one virtual active pattern on the substrate and a target virtual control electrode ranges from 0.8 micrometers to 2 micrometers;

[0007] The orthographic projection of the virtual active pattern on the substrate is adjacent to the orthographic projection of the target virtual control electrode on the substrate.

[0008] In an exemplary embodiment, the non-display area includes: at least one corner area and at least one straight frame area, the driving circuit group includes: a plurality of driving circuits, the plurality of driving circuits are sequentially arranged in a direction close to the display area, the driving circuit includes: a plurality of cascaded shift registers, the virtual driving circuit group includes: a plurality of virtual driving circuits, the plurality of virtual driving circuits are sequentially arranged in a direction close to the display area, the virtual driving circuit includes: a plurality of cascaded virtual shift registers;

[0009] The virtual driving circuit group is at least partially located in the corner area, the driving circuit group is located in the corner area and the straight line frame area, the driving circuit group and the virtual driving circuit group are located on the first side and the second side of the display area, and the first side and the second side of the display area are arranged opposite to each other.

[0010] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one reset signal line, the pixel driving circuit includes: a driving transistor and a reset transistor, the reset transistor is electrically connected to the control electrode of the driving transistor, and the reset signal line is electrically connected to the control electrode of the reset transistor; the plurality of driving circuits include: a reset driving circuit, the reset driving circuit is located on one of the first side and the second side of the display area, and the plurality of virtual driving circuits include: a virtual reset driving circuit;

[0011] The length of the reset driving circuit along a first direction is greater than the length of the dummy reset driving circuit along the first direction, and the first direction is an arrangement direction of the plurality of driving circuits.

[0012] In an exemplary embodiment, the reset driving circuit includes: a plurality of cascaded reset shift registers, and the virtual reset driving circuit includes: at least one virtual reset shift register, and the at least one virtual reset shift register is located between adjacent reset shift registers;

[0013] The reset shift register includes: at least one reset transistor and at least one reset capacitor; at least one virtual driving unit also includes: a plurality of virtual source and drain electrodes;

[0014] At least a portion of at least one virtual active pattern in at least one virtual reset shift register has the same shape as at least a portion of an active pattern of at least one reset transistor, at least a portion of at least one virtual control electrode in at least one virtual reset shift register has the same shape as at least a portion of a control electrode of at least one reset transistor or at least a portion of a reset capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual reset shift register has the same shape as at least a portion of at least one electrode of the first electrode and the second electrode of at least one reset transistor.

[0015] In an exemplary embodiment, the non-display area is further provided with a reset cascade signal line, a reset initial signal line, a first reset clock signal line, a second reset clock signal line, a first reset power line, two second reset power lines and a third reset power line;

[0016] At least one of the reset initial signal line, the first reset clock signal line, the second reset clock signal line, the first reset power line, the second reset power line, the third reset power line and the reset cascade signal line extends along a second direction, and the first direction intersects the second direction;

[0017] The orthographic projections of the reset initial signal line, the first second reset power line, the third reset power line, the first reset clock signal line, the second reset clock signal line, the first reset power line and the second second reset power line on the substrate are arranged in sequence along the direction close to the display area.

[0018] In an exemplary embodiment, the non-display area is provided with the reset cascade signal line, two second reset power lines and a third reset power line, and the reset shift register includes: an input terminal and an output terminal;

[0019] The reset cascade signal line is electrically connected to the output end of at least one reset shift register and the input end of at least one reset shift register, respectively, and the orthographic projection of the reset cascade signal line on the substrate is between the orthographic projection of the first and second reset power lines on the substrate and the orthographic projection of the third reset power line on the substrate.

[0020] In an exemplary embodiment, the non-display area is provided with the reset cascade signal line and a first reset power line;

[0021] The virtual reset shift register is located at a side of the reset cascade signal line close to the display area, and at least one virtual source-drain electrode in the virtual reset shift register is electrically connected to the first reset power line.

[0022] In an exemplary embodiment, it further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0023] The reset cascade signal line, the reset initial signal line and two second reset power supply lines are located in the fourth conductive layer, and the first reset clock signal line, the second reset clock signal line, the first reset power supply line and the third reset power supply line are located in the fifth conductive layer.

[0024] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one light emitting signal line, the pixel driving circuit includes: a driving transistor and a light emitting transistor, the light emitting transistor is electrically connected to at least one of a first electrode and a second electrode of the driving transistor, and the light emitting signal line is electrically connected to a control electrode of the light emitting transistor; the plurality of driving circuits include: a light emitting driving circuit, the light emitting driving circuit is located on the other of the first side and the second side of the display area, and the plurality of virtual driving circuits include: a virtual light emitting driving circuit;

[0025] The length of the light-emitting driving circuit along the first direction is greater than or equal to the length of the virtual light-emitting driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

[0026] In an exemplary embodiment, the light emitting driving circuit includes: a plurality of cascaded light emitting shift registers, and the virtual light emitting driving circuit includes: at least one virtual light emitting shift register, and the at least one virtual light emitting shift register is located between adjacent light emitting shift registers;

[0027] The light-emitting shift register includes: at least one light-emitting transistor and at least one light-emitting capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes;

[0028] At least a portion of at least one virtual active pattern in at least one virtual light-emitting shift register has the same shape as at least a portion of an active pattern of at least one light-emitting transistor, at least a portion of at least one virtual control electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of a control electrode of at least one light-emitting transistor or at least a portion of a light-emitting capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one light-emitting transistor.

[0029] In an exemplary embodiment, the non-display area is further provided with a light emitting cascade signal line, a light emitting initial signal line, a first light emitting clock signal line, a second light emitting clock signal line, a first light emitting power line, two second light emitting power lines and a third light emitting power line;

[0030] At least one of the light emitting initial signal line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power line, the second light emitting power line, the third light emitting power line and the light emitting cascade signal line extends along a second direction, and the first direction intersects the second direction;

[0031] The positive projections of the initial light-emitting signal line, the first second light-emitting power line, the third light-emitting power line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line and the second first light-emitting power line on the substrate are arranged in sequence along the direction close to the display area.

[0032] In an exemplary embodiment, the non-display area is provided with the light emitting cascade signal line, two second light emitting power lines and a third light emitting power line, and the light emitting shift register includes: an input terminal and an output terminal;

[0033] The light-emitting cascade signal line is electrically connected to the output end of at least one light-emitting shift register and the input end of at least one light-emitting shift register, respectively, and the orthographic projection of the light-emitting cascade signal line on the substrate is between the orthographic projection of the first and second light-emitting power lines on the substrate and the orthographic projection of the third light-emitting power line on the substrate.

[0034] In an exemplary embodiment, the non-display area is provided with the light emitting cascade signal line and the first light emitting power line;

[0035] The virtual light emitting shift register is located on a side of the light emitting cascade signal line close to the display area, and at least one virtual source-drain electrode in the virtual light emitting shift register is electrically connected to the first light emitting power line.

[0036] In an exemplary embodiment, it further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0037] The light cascade signal line, the light initial signal line and two second light power lines are located in the fourth conductive layer, and the first light clock signal line, the second light clock signal line, the first light power line and the third light power line are located in the fifth conductive layer.

[0038] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one control signal line, the pixel driving circuit includes: a driving transistor and a compensation transistor, the compensation transistor is electrically connected to the control electrode and the second electrode of the driving transistor, and the control signal line is electrically connected to the control electrode of the compensation transistor; the plurality of driving circuits include: a control driving circuit, the control driving circuit is located at a first side and a second side of the display area, and the plurality of virtual driving circuits include: a virtual control driving circuit;

[0039] The length of the control driving circuit along the first direction is greater than or equal to the length of the virtual control driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

[0040] In an exemplary embodiment, the control driving circuit includes: a plurality of cascaded control shift registers, and the virtual control driving circuit includes: at least one virtual control shift register, and the at least one virtual control shift register is located between adjacent control shift registers;

[0041] The control shift register includes: at least one control transistor and at least one control capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes;

[0042] At least a portion of at least one virtual active pattern in at least one virtual control shift register has the same shape as at least a portion of an active pattern of at least one control transistor, at least a portion of at least one virtual control electrode in at least one virtual control shift register has the same shape as at least a portion of a control electrode of at least one control transistor or at least a portion of a control capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual control shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one control transistor.

[0043] In an exemplary embodiment, the non-display area is further provided with a control cascade signal line, two control initial signal lines, a first control clock signal line, a second control clock signal line, three first control power lines, two second control power lines and a third control power line;

[0044] at least one of the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the second control power line, the third control power line and the control cascade signal line extends along a second direction, the first direction intersecting the second direction;

[0045] The first control initial signal line, the first second control power line, the second control initial signal line, the first control clock signal line, the second control clock signal line, the first first control power line, the third control power line, the second first control power line, the third first control power line and the second second control power line are arranged in sequence along the direction close to the display area.

[0046] In an exemplary embodiment, the non-display area is further provided with a control cascade signal line, two control initial signal lines and a first control clock signal line, and the control shift register includes: an input terminal and an output terminal;

[0047] The control cascade signal line is electrically connected to the output end of at least one stage of control shift register and the input end of at least one stage of control shift register respectively, and the positive projection of the control cascade signal line on the substrate is between the positive projection of the second control initial signal line on the substrate and the positive projection of the first control clock signal line on the substrate.

[0048] In an exemplary embodiment, the non-display area is also provided with a control cascade signal line, three first control power lines and two second control power lines; the control cascade signal line divides the area where the virtual control shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the first second control power lines, and at least one virtual source-drain electrode located in the second area is connected to at least one first control power line.

[0049] In an exemplary embodiment, it further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0050] The control cascade signal line is located in the fourth conductive layer, and the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the two second control power lines, and the third control power line are located in the fifth conductive layer.

[0051] In an exemplary embodiment, the display area is provided with a pixel driving circuit and at least one scanning signal line, the pixel driving circuit includes: a driving transistor and a writing transistor, the writing transistor is electrically connected to the control electrode and the first electrode of the driving transistor, and the scanning signal line is electrically connected to the control electrode of the writing transistor; the plurality of driving circuits include: a scanning driving circuit, the scanning driving circuit is located at the first side and the second side of the display area, and the plurality of virtual driving circuits include: a virtual scanning driving circuit;

[0052] The length of the scan driving circuit along a first direction is greater than or equal to the length of the virtual scan driving circuit along the first direction, and the first direction is an arrangement direction of the plurality of driving circuits.

[0053] In an exemplary embodiment, the scan driving circuit includes: a plurality of cascaded scan shift registers, and the virtual scan driving circuit includes: at least one virtual scan shift register, and the at least one virtual scan shift register is located between adjacent scan shift registers;

[0054] The scanning shift register includes: at least one scanning transistor and at least one scanning capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes;

[0055] At least a portion of at least one virtual active pattern in at least one virtual scan shift register has the same shape as at least a portion of the active pattern of at least one scan transistor, at least a portion of at least one virtual control electrode in at least one virtual scan shift register has the same shape as at least a portion of the control electrode of at least one scan transistor or at least a portion of the scan capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual scan shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one scan transistor.

[0056] In an exemplary embodiment, the non-display area is further provided with a scan cascade signal line, a scan initial signal line, a first scan clock signal line, a second scan clock signal line, a first scan power line, and a second scan power line;

[0057] At least one of the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line, the second scan power line and the scan cascade signal line extends along a second direction, and the first direction intersects the second direction;

[0058] The second scan power line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power line are sequentially arranged in a direction close to the display area.

[0059] In an exemplary embodiment, the non-display area is further provided with a scan cascade signal line, a scan initial signal line, and a second scan clock signal line, and the scan shift register includes: an input terminal and an output terminal;

[0060] The scan cascade signal line is electrically connected to the output end of at least one level of scan shift register and the input end of at least one level of scan shift register, respectively, and the positive projection of the scan cascade signal line on the substrate is between the positive projection of the second scan clock signal line on the substrate and the positive projection of the scan initial signal line on the substrate.

[0061] In an exemplary embodiment, the non-display area is further provided with a scan cascade signal line, a first scan power line, and a second scan power line;

[0062] The scan cascade signal line divides the area where the virtual scan shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the second scan power line, and at least one virtual source-drain electrode located in the second area is connected to the first scan power line.

[0063] In an exemplary embodiment, it further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0064] The scan cascade signal line is located in the fourth conductive layer, and the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line and the second scan power line are located in the fifth conductive layer.

[0065] In an exemplary embodiment, the driving circuit group includes: a scanning driving circuit, a control driving circuit, a light emitting driving circuit, and a reset driving circuit;

[0066] The reset driving circuit, the control driving circuit and the scan driving circuit located on the first side of the display area are arranged in sequence along a direction close to the display area, and the light emitting driving circuit, the control driving circuit and the scan driving circuit located on the second side of the display area are arranged in sequence along a direction close to the display area;

[0067] The scan drive circuit located on the first side of the display area and the scan drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, the control drive circuit located on the first side of the display area and the control drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, the reset drive circuit located on the first side of the display area and the light-emitting drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, and the second direction intersects with the first direction.

[0068] In an exemplary embodiment, the driving circuit group includes: at least one transistor and at least one capacitor, the virtual driving circuit group includes: a plurality of virtual active patterns, a plurality of virtual control electrodes, and a virtual source and drain electrode, the display substrate further includes: a signal output line located in a non-display area, at least one cascade signal line, and a plurality of signal lines, the plurality of signal lines are respectively connected to the driving circuit group and the virtual circuit group, and the signal output line is connected to the driving circuit group;

[0069] The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer;

[0070] The semiconductor layer includes at least: an active pattern of at least one transistor and at least one dummy active pattern among a plurality of dummy active patterns;

[0071] The first conductive layer at least includes: a control electrode of at least one transistor, a plate of at least one capacitor, and at least one virtual active pattern among a plurality of virtual control electrodes;

[0072] The second conductive layer at least includes: another plate of at least one capacitor;

[0073] The third conductive layer at least includes: a signal output line;

[0074] The fourth conductive layer at least includes: at least one signal line and a cascade signal line;

[0075] The fifth conductive layer at least includes: at least one signal line.

[0076] In an exemplary embodiment, further comprising: at least one initial signal line located in the non-display area;

[0077] At least one initial signal line is located on a side of at least one of the plurality of signal lines close to the display area and is located on the fifth conductive layer;

[0078] An orthographic projection of at least one initial signal line on the substrate at least partially overlaps with orthographic projections of the driving circuit group and the dummy driving circuit group on the substrate.

[0079] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0080] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0082] Figure 1 It is a structural schematic diagram of a display substrate;

[0083] Figure 2 A local frame area of ​​the display substrate;

[0084] Figure 3 A partial structural schematic diagram of a first side of a display area of ​​a display substrate provided in an embodiment of the present disclosure;

[0085] Figure 4 A partial structural schematic diagram of a second side of a display area of ​​a display substrate provided in an embodiment of the present disclosure;

[0086] Figure 5 for Figure 3 Schematic diagram of some membrane layers;

[0087] Figure 6 for Figure 4 Schematic diagram of some membrane layers;

[0088] Fig. 7A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0089] Figure 7B for Fig. 7A The working timing diagram of the pixel driving circuit provided;

[0090] Fig. 8A An equivalent circuit diagram of a scan shift register provided for an exemplary embodiment;

[0091] Figure 8B for Fig. 8A The timing diagram of the scan shift register is provided;

[0092] Fig. 9A An equivalent circuit diagram of a control shift register provided for an exemplary embodiment;

[0093] Fig. 9B for Fig. 9A Provided timing diagram for controlling shift register;

[0094] Fig. 10A An equivalent circuit diagram of a reset shift register provided for an exemplary embodiment;

[0095] Fig. 10B for Fig. 10A The timing diagram for resetting the shift register is provided;

[0096] Fig.11A An equivalent circuit diagram of a light emitting shift register provided for an exemplary embodiment;

[0097] Fig. 11B for Fig.11A A timing diagram of the light emitting shift register is provided;

[0098] Fig. 12A Schematic diagram of some film layers of reset shift register and virtual reset shift register Figure 1 ;

[0099] Fig. 12B Schematic diagram of some film layers of reset shift register and virtual reset shift register Figure 2 ;

[0100] Fig.13A Schematic diagram of some film layers of the luminous shift register and the virtual luminous shift register Figure 1 ;

[0101] Fig. 13B Schematic diagram of some film layers of the luminous shift register and the virtual luminous shift register Figure 2 ;

[0102] Fig.14A Schematic diagram of some membrane layers of the control shift register and virtual control shift register Figure 1 ;

[0103] Fig. 14B Schematic diagram of some membrane layers of the control shift register and virtual control shift register Figure 2 ;

[0104] Fig.15A Schematic diagram of some film layers of the scan shift register and the virtual scan shift register Figure 1 ;

[0105] Fig. 15B Schematic diagram of some film layers of the scan shift register and the virtual scan shift register Figure 2 ;

[0106] Fig.16 A schematic diagram of a semiconductor layer pattern formed for a scan shift register and a dummy scan shift register;

[0107] Fig.17 A schematic diagram of a semiconductor layer pattern after forming a control shift register and a dummy control shift register;

[0108] Fig.18 A schematic diagram of a semiconductor layer pattern formed for a reset shift register and a dummy reset shift register;

[0109] Fig.19 is a schematic diagram of a first conductive layer pattern in a scan shift register and a virtual scan shift register;

[0110] Fig. 20 A schematic diagram of a scan shift register and a dummy scan shift register after forming a first conductive layer pattern;

[0111] Fig.21 A schematic diagram of a first conductive layer pattern in a control shift register and a virtual control shift register;

[0112] Fig. 22 It is a schematic diagram of the first conductive layer pattern in the control shift register and the virtual control shift register;

[0113] Fig.23 A schematic diagram of forming a first conductive layer pattern for a reset shift register and a dummy reset shift register;

[0114] Fig.24 Schematic diagram after forming the first conductive layer pattern for the reset shift register and the dummy reset shift register

[0115] Fig.25 is a schematic diagram of a second conductive layer pattern in a scan shift register and a virtual scan shift register;

[0116] Fig.26 A schematic diagram of a scan shift register and a dummy scan shift register after forming a second conductive layer pattern;

[0117] Fig. 27A schematic diagram of a second conductive layer pattern in a control shift register and a virtual control shift register;

[0118] Fig.28 A schematic diagram after forming a second conductive layer pattern for a control shift register and a dummy control shift register;

[0119] Fig.29 is a schematic diagram of a second conductive layer pattern in a reset shift register and a virtual reset shift register;

[0120] Fig.30 A schematic diagram of a reset shift register and a dummy reset shift register after forming a second conductive layer pattern;

[0121] Fig.31 A schematic diagram of a third conductive layer pattern in a control shift register and a virtual control shift register;

[0122] Fig.32 A schematic diagram of a control shift register and a dummy control shift register after a third conductive layer pattern is formed;

[0123] Fig.33 It is a schematic diagram of a reset shift register and a virtual reset shift register after the third conductive layer pattern;

[0124] Fig.34 A schematic diagram of a reset shift register and a dummy reset shift register after a third conductive layer pattern is formed;

[0125] Fig.35 A schematic diagram of a scan shift register and a dummy scan shift register after a fourth insulating layer is formed;

[0126] Fig.36 A schematic diagram of a control shift register and a dummy control shift register after a fourth insulating layer is formed;

[0127] Fig.37 A schematic diagram of a reset shift register and a dummy reset shift register after a fourth insulating layer is formed;

[0128] Fig.38 is a schematic diagram of a fourth conductive layer pattern in a scan shift register and a virtual scan shift register;

[0129] Fig.39 A schematic diagram of a scan shift register and a dummy scan shift register after a fourth conductive layer pattern is formed;

[0130] Fig.40 A schematic diagram of a fourth conductive layer pattern in a control shift register and a virtual control shift register;

[0131] Fig.41A schematic diagram of a control shift register and a dummy control shift register after a fourth conductive layer pattern is formed;

[0132] Fig.42 is a schematic diagram of a fourth conductive layer pattern in a reset shift register and a virtual reset shift register;

[0133] Fig.43 A schematic diagram of a reset shift register and a dummy reset shift register after a fourth conductive layer pattern is formed;

[0134] Fig.44 A schematic diagram of a scan shift register and a dummy scan shift register after a flat layer is formed;

[0135] Fig.45 A schematic diagram after forming a flat layer for a control shift register and a virtual control shift register;

[0136] Fig.46 A schematic diagram after a flat layer is formed for a reset shift register and a dummy reset shift register;

[0137] Fig.47 is a schematic diagram of a fifth conductive layer pattern in a scan shift register and a virtual scan shift register;

[0138] Fig.48 A schematic diagram of a scan shift register and a dummy scan shift register after a fifth conductive layer pattern is formed;

[0139] Fig.49 is a schematic diagram of a fifth conductive layer pattern in a control shift register and a virtual control shift register;

[0140] Fig.50 A schematic diagram of a control shift register and a dummy control shift register after a fifth conductive layer pattern is formed;

[0141] Fig.51 is a schematic diagram of a fifth conductive layer pattern in a reset shift register and a dummy reset shift register;

[0142] Fig.52 A schematic diagram showing a reset shift register and a dummy reset shift register after a fifth conductive layer pattern is formed. DETAILED DESCRIPTION

[0143] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0144] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0145] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0146] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0147] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0148] In this specification, a transistor refers to an element including at least three terminals: a control electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

[0149] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0150] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0151] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0152] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0153] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0154] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0155] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0156] The display substrate uses low-temperature polysilicon (LTPS) technology, which has the advantages of high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption. At this time, the low-temperature polycrystalline oxide combination (LTPO+Oxide) technology solution came into being. Compared with LTPS technology, LTPO technology has smaller leakage current and faster pixel response. The display substrate adds an extra layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed. However, compared with display products using LTPS technology, display products using LTPO technology will cause afterimages due to the bias of the threshold voltage of the driving transistor in the pixel circuit, which reduces the display effect of the display product.

[0157] In order to achieve display, display products are provided with a variety of gate drive circuits, which are matched according to the pixel design of the display area. Generally, at least one gate drive circuit is provided on the left and right borders. Nowadays, most display products have special-shaped designs such as rounded corners, and the borders of display products include straight edge areas and corner areas, such as mobile phones, watches, tablets, notebooks, etc. For panel design, the gate drive circuit is generally a row scanning circuit. The gate drive circuit is generally arranged in a rectangular shape. In the corner area, the multi-stage shift registers in the gate drive circuit are generally arranged in a fan-shaped manner according to the arc shape of the display area to save the frame size. At this time, the number of shift registers densely packed by unit must be greater than the number of pixel rows to be connected to the shift register. Generally, the shift register closest to the pixel is selected to connect to the pixel. The redundant shift registers are not deleted, but replaced with virtual shift registers that do not need to be connected to the display area. The setting of the virtual shift register can ensure the etching uniformity of the display product and avoid the process differences caused by different graphic densities to produce display unevenness.

[0158] During the design process, the layout of the virtual shift register is basically the same as that of the shift register. Part of the structure of the same transistor in the virtual shift register may be connected to high-level signals and low-level signals at the same time, resulting in a short circuit problem, thereby reducing the reliability of the product.

[0159] Figure 1 is a schematic diagram of the structure of a display substrate. Figure 2 To display the local border area of ​​the substrate, Figure 3 A partial structural schematic diagram of a first side of a display area of ​​a display substrate provided in an embodiment of the present disclosure, Figure 4A partial structural schematic diagram of the second side of the display area of ​​the display substrate provided in an embodiment of the present disclosure, Figure 5 for Figure 3 Schematic diagram of some membrane layers, Figure 6 for Figure 4 Schematic diagram of some membrane layers. Figures 1 to 6 As shown, the embodiment of the present disclosure provides a display substrate having a display area 100 and a non-display area 200, including: a substrate and a pixel driving circuit P disposed on the substrate and located in the display area 100, and a driving circuit group and a virtual driving circuit group located in the non-display area, the pixel driving circuit is electrically connected to the driving circuit group, the driving circuit group includes: at least one shift register, the virtual driving circuit group includes: at least one virtual shift register, the virtual shift register includes: a plurality of virtual active patterns DA and a plurality of virtual control electrodes DG, the shift register includes: a plurality of transistors, and the transistor includes: an active pattern and a control electrode. Figure 5 and Figure 6 As shown, at least a portion of the shape of at least one virtual active pattern is the same as at least a portion of the shape of the active pattern of at least one transistor, at least a portion of the shape of at least one virtual control electrode is the same as at least a portion of the shape of the control electrode of at least one transistor, and there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate.

[0160] In an exemplary embodiment, if Figure 5 and Figure 6 As shown, a control electrode of at least one transistor in the shift register at least partially overlaps with an orthographic projection of an active pattern of the control electrode on the substrate.

[0161] In an exemplary embodiment, the shape of at least a portion of at least one virtual active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, and the shape of at least a portion of at least one virtual control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, which can ensure the etching uniformity of the display substrate and improve the display effect of the display substrate.

[0162] The present invention can avoid the short circuit phenomenon caused by the conduction between devices connected to different signal terminals in the virtual shift register unit due to the existence of the virtual active pattern by ensuring that there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate, thereby improving the reliability of the display substrate.

[0163] In example embodiments, the display substrate may be an LTPO display substrate.

[0164] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 5T1C, 5T2C, 7T1C, or 8T1C circuit structure.

[0165] In an exemplary embodiment, Fig. 7A FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Fig. 7A As shown, the pixel driving circuit may include 7 transistors (a first transistor M1 to a seventh transistor M7), a capacitor C and 8 signal terminals (a data signal terminal Data, a control signal terminal Scan, a scan signal terminal Gate, a reset signal terminal Reset, a light emitting signal terminal EM, an initial signal terminal VINIT, a first power supply terminal VDD and a second power supply terminal VSS). Fig. 7A The following description takes 7T1C as an example.

[0166] In an exemplary embodiment, a first plate of the capacitor C is connected to a first power supply terminal VDD, and a second plate of the capacitor C is connected to a first node N1. A control electrode of the first transistor M1 is connected to a reset signal terminal Reset, a first electrode of the first transistor M1 is connected to an initial signal terminal VINIT, and a second electrode of the first transistor is connected to a first node N1; a control electrode of the second transistor M2 is connected to a scan signal terminal Gate, a first electrode of the second transistor M2 is connected to a first node N1, and a second electrode of the second transistor M2 is connected to a second node N2. A control electrode of the third transistor M3 is connected to the first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3. A control electrode of the fourth transistor M4 is connected to a control signal terminal Scan, a first electrode of the fourth transistor M4 is connected to a data signal terminal Data, and a second electrode of the fourth transistor M4 is connected to a third node N3. The control electrode of the fifth transistor M5 is connected to the light emitting signal terminal EM, the first electrode of the fifth transistor M5 is connected to the first power supply terminal VDD, and the second electrode of the fifth transistor M5 is connected to the third node N3; the control electrode of the sixth transistor M6 is connected to the light emitting signal terminal EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device. The control electrode of the seventh transistor M7 is connected to the control signal terminal Scan, the first electrode of the seventh transistor M7 is connected to the initial signal terminal VINIT, the second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device, and the second electrode of the light emitting device is connected to the second power supply terminal VSS.

[0167] In an exemplary embodiment, the first transistor M1 may be referred to as a reset transistor, and when a valid level signal is input to the reset signal terminal Reset, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0168] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor, and when the control signal terminal Scan inputs a valid level signal, the second transistor M2 is turned on to compensate for the signal of the first node N1.

[0169] In an exemplary embodiment, the third transistor M3 may be referred to as a driving transistor, and the third transistor M3 determines a driving current flowing between the first power supply terminal VDD and the second power supply terminal VSS according to a potential difference between the control electrode and the first electrode.

[0170] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor or the like, and when the scan signal terminal Gate inputs an effective level signal, the fourth transistor M4 enables the data voltage of the data signal terminal Data to be input to the pixel driving circuit.

[0171] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light emission control transistors. When the light emission signal terminal EM inputs an effective level signal, the fifth transistor M5 and the sixth transistor M6 enable the light emitting device to emit light by forming a driving current path between the first power supply terminal VDD and the second power supply terminal VSS.

[0172] In an exemplary embodiment, the signal of the first power supply terminal VDD is a continuously provided high level signal, and the signal of the second power supply terminal VSS is a low level signal.

[0173] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are metal oxide transistors and are N-type transistors, and the third transistor M3 to the seventh transistor M7 are low temperature polysilicon transistors and are P-type transistors.

[0174] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are oxide transistors, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce power consumption of the pixel driving circuit.

[0175] In an exemplary embodiment, the first power supply terminal VDD is configured to continuously provide a high level signal, and the second power supply terminal VSS is configured to continuously provide a low level signal.

[0176] Figure 7B for Fig. 7A The working timing diagram of the pixel driving circuit provided is as follows. Figure 7B The operation process of the pixel driving circuit of the example is described in detail. Fig. 7AThe pixel driving circuit includes 7 transistors (first transistor M1 to seventh transistor M7), 1 capacitor C and 8 signal terminals (data signal terminal Data, control signal terminal Scan, scan signal terminal Gate, reset signal terminal Reset, light emitting signal terminal EM, initial signal terminal VINIT, first power supply terminal VDD and second power supply terminal VSS).

[0177] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0178] The first stage A1 is called the reset stage. The signals of the reset signal terminal Reset, the control signal terminal Scan and the light-emitting signal terminal EM are all high-level signals, and the signal of the scan signal terminal Gate is a low-level signal. The signal of the reset signal terminal Reset is a high-level signal, the first transistor M1 is turned on, and the signal of the initial signal terminal VINIT is provided to the first node N1 to initialize the capacitor C and clear the original data voltage in the capacitor C. The signals of the control signal terminal Scan and the light-emitting signal terminal EM are high-level signals, the signal of the scan signal terminal Gate is a low-level signal, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and the OLED does not emit light in this stage.

[0179] The second stage A2 is called the data writing stage or the threshold compensation stage. The signals of the control signal terminal Scan and the reset signal terminal Reset are low-level signals, the signals of the luminous signal terminal EM and the scanning signal terminal Gate are high-level signals, and the data signal terminal Data outputs a data voltage. In this stage, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The signal of the control signal terminal Scan is a low-level signal, the fourth transistor M4 and the seventh transistor M7 are turned on, the signal of the scanning signal terminal Gate is a high-level signal, and the second transistor M2 is turned on. The second transistor M2 and the fourth transistor M4 are turned on so that the data voltage output by the data signal terminal Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2 and the turned-on second transistor M2, and the difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal terminal Data, and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on so that the initial voltage of the initial signal terminal VINIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the reset signal terminal Reset is a low-level signal, and the first transistor M1 is disconnected. The signal of the luminous signal terminal EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are disconnected.

[0180] The third stage A3 is called the light-emitting stage, and the signals of the control signal terminal Scan, the scanning signal terminal Gate, the light-emitting signal terminal EM and the reset signal terminal Reset are all low-level signals. The signal of the light-emitting signal terminal EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the OLED to emit light.

[0181] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0182] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0183] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal terminal Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0184] In an exemplary embodiment, if Figure 5 and Figure 6 As shown, the distance L between the orthographic projection of at least one virtual active pattern on the substrate and the target virtual control electrode ranges from 0.8 micrometers to 2 micrometers; the orthographic projection of the virtual active pattern on the substrate is adjacent to the orthographic projection of the target virtual control electrode on the substrate.

[0185] In an exemplary embodiment, if Figure 2 As shown, the non-display area 200 includes: at least one corner area CR and at least one straight frame area LR, the driving circuit group includes: a plurality of driving circuits, the plurality of driving circuits are arranged in sequence along the direction close to the display area, and the driving circuit includes: a plurality of cascaded shift registers. The virtual driving circuit group includes: a plurality of virtual driving circuits, the plurality of virtual driving circuits are arranged in sequence along the direction close to the display area, and the virtual driving circuit includes: a plurality of cascaded virtual shift registers. Among them, the virtual driving circuit group is at least partially located in the corner area CR, the driving circuit group is located in the corner area CR and the straight frame area LR, the driving circuit group and the virtual driving circuit group are located on the first side and the second side of the display area, and the first side and the second side of the display area are arranged relative to each other.

[0186] In an exemplary embodiment, the boundary of the corner area may be in an arc shape, which is not limited in the present disclosure.

[0187] In an exemplary embodiment, if Figure 1 As shown, the display area 100 is also provided with a reset signal line RL, a light-emitting signal line EL, a control signal line SL and a scanning signal line GL. The reset signal line RL is electrically connected to the control electrode of the reset transistor, the light-emitting signal line EL is electrically connected to the control electrode of the light-emitting transistor, the control signal line SL is electrically connected to the control electrode of the compensation transistor, and the scanning signal line GL is electrically connected to the control electrode of the write transistor. Among them, the multiple driving circuits include: a reset driving circuit, a scanning driving circuit, a control driving circuit and a light-emitting driving circuit. The multiple virtual driving circuits include: a virtual reset driving circuit, a virtual scanning driving circuit, a virtual control driving circuit and a virtual light-emitting driving circuit.

[0188] In an exemplary embodiment, the virtual reset driving circuit and the reset driving circuit are located on the first side of the display area, the virtual scanning driving circuit, the virtual control driving circuit, the scanning driving circuit and the control driving circuit are located on the first side and the second side of the display area, and the virtual light emitting driving circuit and the light emitting driving circuit are located on the second side of the display area. The control driving circuits located on the first side and the second side of the display area are symmetrically arranged relative to the midline of the display area extending along the second direction D2. The scanning driving circuits located on the first side and the second side of the display area are symmetrically arranged relative to the midline of the display area extending along the second direction D2. The reset driving circuit located on the first side of the display area and the light emitting driving circuit located on the second side of the display area are symmetrically arranged relative to the midline of the display area extending along the second direction D2.

[0189] In an exemplary embodiment, the reset driving circuit, the control driving circuit, and the scan driving circuit located at the first side of the display area are sequentially arranged in a direction approaching the display area.

[0190] In an exemplary embodiment, the dummy reset driving circuit, the dummy control driving circuit, and the dummy scan driving circuit located at the first side of the display area are sequentially arranged in a direction approaching the display area.

[0191] In an exemplary embodiment, the light emitting driving circuit, the control driving circuit, and the scanning driving circuit located at the second side of the display area are sequentially arranged in a direction approaching the display area.

[0192] In an exemplary embodiment, the virtual light emitting driving circuit, the virtual control driving circuit, and the virtual scanning driving circuit located at the second side of the display area are sequentially arranged in a direction approaching the display area.

[0193] In an exemplary embodiment, the display substrate may further include a timing controller and a source driving circuit located in the non-display area.

[0194] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the source driving circuit to the source driving circuit, can provide clock signals, scanning start signals, etc. suitable for the specifications of the scanning driving circuit to the scanning driving circuit, can provide clock signals, control start signals, etc. suitable for the specifications of the control driving circuit to the control driving circuit, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driving circuit to the light-emitting driving circuit.

[0195] In an exemplary embodiment, the source driving circuit may generate a grayscale value and a control signal received from the timing controller to be provided to the data signal lines DL1, DL2, DL3, . . . and DL N For example, the source driving circuit may sample the grayscale value using the clock signal and apply the data voltage corresponding to the grayscale value to the data signal lines DL1 to DL N .

[0196] In an exemplary embodiment, the scan driving circuit may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driving circuit may sequentially provide a scan signal having an on-level pulse to the scan signal line. For example, the scan driving circuit may be configured in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal.

[0197] In an exemplary embodiment, the control driving circuit may generate a control signal to be provided to the control signal line by receiving a clock signal, a control start signal, etc. from a timing controller. For example, the control driving circuit may sequentially provide a control signal having an on-level pulse to the control signal line. For example, the control driving circuit may be configured in the form of a shift register, and may generate a control signal in a manner that sequentially transmits a control start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal.

[0198] In an exemplary embodiment, the light emitting driving circuit may generate an emission signal to be provided to the light emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light emitting driving circuit may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal line. For example, the light emitting driving circuit may be configured in the form of a shift register, and may generate a light emitting signal in a manner that a light emitting stop signal provided in the form of a cut-off level pulse is sequentially transmitted to a next stage circuit under the control of a clock signal.

[0199] In an exemplary embodiment, the reset driving circuit may generate a transmission signal to be provided to the reset signal line by receiving a clock signal, a transmission stop signal, etc. from a timing controller. For example, the reset driving circuit may sequentially provide a transmission signal having a cut-off level pulse to the reset signal line. For example, the reset driving circuit may be configured in the form of a shift register, and may generate a reset signal in a manner that sequentially transmits a reset stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal.

[0200] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, the reset drive circuit includes a plurality of cascaded reset shift registers R-GOA, the scan drive circuit includes a plurality of cascaded scan shift registers P-GOA, the control drive circuit includes a plurality of cascaded control shift registers N-GOA, and the light-emitting drive circuit includes a plurality of cascaded light-emitting shift registers E-GOA. Among them, at least one level of reset shift register is connected to at least one reset signal line, at least one level of scan shift register is connected to at least one scan signal line, at least one level of control shift register is connected to at least one control signal line, and at least one level of light-emitting shift register is connected to at least one light-emitting signal line. At least one shift register located on the first side of the display area includes: at least one level of reset shift register, at least one level of control shift register, and at least one level of scan shift register. Figure 3 The example of at least one shift register located on the first side of the display area includes: a first-level reset shift register, a first-level control shift register and a two-level scanning shift register. The at least one shift register located on the second side of the display area includes: at least one-level light-emitting shift register, at least one-level control shift register and at least one-level scanning shift register. Figure 4 The description is made by taking the example that the at least one shift register located at the second side of the display area includes: a one-stage light emitting shift register, a one-stage control shift register and a two-stage scanning shift register.

[0201] In an exemplary embodiment, if Figure 3 and Figure 4As shown, the virtual reset drive circuit includes multiple cascaded virtual reset shift registers DR-GOA, the virtual scan drive circuit includes multiple cascaded virtual scan shift registers DP-GOA, the virtual control drive circuit includes multiple cascaded virtual control shift registers DN-GOA, and the virtual light-emitting drive circuit includes multiple cascaded virtual light-emitting shift registers DE-GOA. Among them, at least one level of virtual reset shift register is connected to at least one virtual reset signal line, at least one level of virtual scan shift register is connected to at least one virtual scan signal line, at least one level of virtual control shift register is connected to at least one virtual control signal line, and at least one level of virtual light-emitting shift register is connected to at least one virtual light-emitting signal line. At least one virtual shift register located on the first side of the display area includes: at least one level of virtual reset shift register, at least one level of virtual control shift register, and at least one level of virtual scan shift register. Figure 3 The example of at least one virtual shift register located on the first side of the display area includes: a first-level virtual reset shift register, a first-level virtual control shift register and two-level virtual scan shift registers. The at least one virtual shift register located on the second side of the display area includes: at least one-level virtual light emitting shift register, at least one-level virtual control shift register and at least one-level virtual scan shift register. Figure 4 The description is made by taking as an example that the at least one virtual shift register located at the second side of the display area includes: a one-stage virtual light emitting shift register, a one-stage virtual control shift register and a two-stage virtual scanning shift register.

[0202] In an exemplary embodiment, the circuit structure of the reset shift register R-GOA, the scanning shift register P-GOA, the control shift register N-GOA and the light emitting shift register E-GOA can be 8T2C, 10T3C, 12T3C, 13T3C, 16T3C or 16T4C, and the present disclosure does not make any limitation on this.

[0203] Fig. 8A FIG. 1 is an equivalent circuit diagram of a scan shift register provided by an exemplary embodiment. Fig. 8A As shown, the scan shift register includes: a first scan transistor PT1 to an eighth scan transistor PT8, a first scan capacitor PC1 and a second scan capacitor PC2. Fig. 8A The circuit structure of the scanning shift register 8T2C is taken as an example for explanation.

[0204] In an exemplary embodiment, a control electrode of the first scanning transistor PT1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first scanning transistor PT1 is electrically connected to the input terminal PIN, and a second electrode of the first scanning transistor PT1 is electrically connected to the first node N1; a control electrode of the second scanning transistor PT2 is electrically connected to the first node N1, a first electrode of the second scanning transistor PT2 is electrically connected to the first clock signal terminal CK, and a second electrode of the second scanning transistor PT2 is electrically connected to the second node N2; a control electrode of the third scanning transistor PT3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third scanning transistor PT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third scanning transistor PT3 is electrically connected to the second node N2; a control electrode of the fourth scanning transistor PT4 is electrically connected to the second node N2, a first electrode of the fourth scanning transistor PT4 is electrically connected to the first power supply terminal VGH, and a second electrode of the fourth scanning transistor PT4 is electrically connected to the output terminal POUT; a control electrode of the fifth scanning transistor PT5 is electrically connected to the third node N3, a first electrode of the fifth scanning transistor PT5 is electrically connected to the second clock signal The first electrode of the scanning capacitor PC1 is electrically connected to the first power supply terminal VGH, and the second electrode of the scanning transistor PC1 is electrically connected to the output terminal POUT; the control electrode of the sixth scanning transistor PT6 is electrically connected to the second node N2, the first electrode of the sixth scanning transistor PT6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth scanning transistor PT6 is electrically connected to the first electrode of the seventh scanning transistor PT7; the control electrode of the seventh scanning transistor PT7 is electrically connected to the second clock signal terminal PCK2, and the second electrode of the seventh scanning transistor PT7 is electrically connected to the first node N1; the control electrode of the eighth scanning transistor PT8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth scanning transistor PT8 is electrically connected to the first node N1, and the second electrode of the eighth scanning transistor PT8 is electrically connected to the third node N3; the first plate PC11 of the first scanning capacitor PC1 is electrically connected to the first power supply terminal VGH, and the second plate PC12 of the first scanning capacitor PC1 is electrically connected to the second node N2; the first plate PC21 of the second scanning capacitor PC2 is electrically connected to the output terminal POUT, and the second plate PC22 of the second scanning capacitor PC2 is electrically connected to the third node N3.

[0205] In an exemplary embodiment, the first to eighth scanning transistors PT1 to PT8 may be P-type transistors or may be N-type transistors.

[0206] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal.

[0207] Figure 8B for Fig. 8A The timing diagram of the scan shift register provided. Taking the first scan transistor PT1 to the eighth scan transistor PT8 as P-type transistors as an example, Figure 8BAs shown, the working process of the scan shift register provided by an exemplary embodiment includes the following stages:

[0208] In the input phase B1, the signals of the first clock signal terminal CK1 and the input terminal PIN are low-level signals, and the signal of the second clock signal terminal CK2 is a high-level signal. Since the signal of the first clock signal terminal CK1 is a low-level signal, the first scanning transistor PT1 is turned on, and the signal of the input terminal PIN is transmitted to the first node N1 via the first scanning transistor PT1. Since the signal of the eighth scanning transistor PT8 receives the low-level signal of the second power supply terminal VGL, the eighth scanning transistor PT8 is turned on. The level of the third node N3 can make the fifth scanning transistor PT5 turned on, and the signal of the second clock signal terminal CK2 is transmitted to the output terminal POUT via the fifth scanning transistor PT5, that is, in the input phase D1, the output terminal POUT is the signal of the second clock signal terminal CK2 of the high-level signal. In addition, since the signal of the first clock signal terminal CK1 is a low-level signal, the third scanning transistor PT3 is turned on, and the low-level signal of the second power supply terminal VGL is transmitted to the second node N2 via the third scanning transistor PT3. At this time, the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned on. Since the signal of the second clock signal terminal PCK2 is a high-level signal, the seventh scanning transistor PT7 is turned off.

[0209] In the output stage B2, the signal of the first clock signal terminal CK1 is a high level signal, the signal of the second clock signal terminal CK2 is a low level signal, and the signal of the input terminal PIN is a high level signal. The fifth scanning transistor PT5 is turned on, and the signal of the second clock signal terminal CK2 is used as the signal of the output terminal POUT via the fifth scanning transistor PT5. In the output stage D2, the level of one end of the second scanning capacitor PC2 connected to the output terminal OUT is changed to the signal of the second power supply terminal VGL. Due to the bootstrap effect of the second scanning capacitor PC2, the eighth scanning transistor PT8 is turned off, the fifth scanning transistor PT5 can be better turned on, and the signal of the output terminal POUT is a low level signal. In addition, the signal of the first clock signal terminal CK1 is a high level signal, so that the first scanning transistor PT1 and the third scanning transistor PT3 are both turned off. The second scanning transistor PT2 is turned on, and the high level signal of the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor PT2, thereby, the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned off. Since the signal of the second clock signal terminal CK2 is a low level signal, the seventh scanning transistor PT7 is turned on.

[0210] In the buffering stage B3, the signals of the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high-level signals, the signal of the input terminal PIN is a high-level signal, the fifth scanning transistor PT5 is turned on, and the second clock signal terminal CK2 is used as the output signal POUT via the fifth scanning transistor PT5. Due to the bootstrap effect of the second scanning capacitor C2, the voltage value of the signal at the first node N1 increases. In addition, the signal of the first clock signal terminal CK1 is a high-level signal, so that the first scanning transistor PT1 and the third scanning transistor PT3 are both turned off, the eighth scanning transistor PT8 is turned on, the second scanning transistor PT2 is turned on, and the high-level signal of the first clock signal terminal CK1 is transmitted to the second node N2 via the second scanning transistor PT2, thereby, the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned off. Since the signal of the second clock signal terminal CK2 is a high-level signal, the seventh scanning transistor PT7 is turned off.

[0211] In the first sub-phase B41 of the stable phase B4, the signal of the first clock signal terminal CK1 is a low-level signal, and the signals of the second clock signal terminal CK2 and the input terminal PIN are high-level signals. Since the signal of the first clock signal terminal CK1 is a low-level signal, the first scanning transistor PT1 is turned on, and the signal of the input terminal PIN is transmitted to the first node N1 via the first scanning transistor PT1, and the second scanning transistor PT2 is turned off. Since the eighth scanning transistor PT8 is turned on, the fifth scanning transistor PT5 is turned off. Since the signal of the first clock signal terminal CK1 is a low-level signal, the third scanning transistor PT3 is turned on, the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the output terminal POUT via the fourth scanning transistor PT4, that is, the signal of the output terminal POUT is a high-level signal.

[0212] In the second sub-phase t42 of the stable phase t4, the signal of the first clock signal terminal CK1 is a high-level signal, the signal of the second clock signal terminal CK2 is a low-level signal, and the signal of the input terminal PIN is a high-level signal. The fifth scanning transistor PT5 and the second scanning transistor PT2 are both turned off. The signal of the first clock signal terminal PCK1 is a high-level signal, so that the first scanning transistor PT1 and the third scanning transistor PT3 are both turned off. Due to the holding effect of the first scanning capacitor PC1, the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned on, and the high-level signal is transmitted to the output terminal POUT via the fourth scanning transistor PT4, that is, the signal of the output terminal POUT is a high-level signal.

[0213] In the second sub-stage t42, since the signal at the second clock signal terminal CK2 is a low-level signal, the seventh scanning transistor PT7 is turned on, so that the high-level signal is transmitted to the third node N3 and the first node N1 via the sixth scanning transistor PT6 and the seventh scanning transistor PT7, so that the signals at the third node N3 and the first node N1 remain high-level signals.

[0214] In the third sub-phase t43, the signals of the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high-level signals, and the signal of the input terminal PIN is a high-level signal. The fifth scanning transistor PT5 and the second scanning transistor PT2 are turned off. The signal of the first clock signal terminal CK1 is a high-level signal, so that the first scanning transistor PT1 and the third scanning transistor PT3 are both turned off, and the fourth scanning transistor PT4 and the sixth scanning transistor PT6 are both turned on. The high-level signal is transmitted to the output terminal POUT via the fourth scanning transistor PT4, that is, the signal of the output terminal POUT is a high-level signal.

[0215] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, the display substrate may further include: a scan initial signal line PSTV, a first scan clock signal line PCK1, a second scan clock signal line PCK2, a first scan power line PVGH, a second scan power line PVGL, and a scan cascade signal line PCL extending along the second direction D2. Among them, the input end of the first-stage scan shift register is electrically connected to the scan initial signal line PSTV, and the scan cascade signal line PCL is electrically connected to the output end of the i-th stage scan shift register and the input end of the i+1-th stage scan shift register; the first clock signal end of the i-th stage scan shift register is electrically connected to the first scan clock signal line PCK1, and the second clock signal end is electrically connected to the second scan clock signal line PCK2; the first clock signal end of the i+1-th stage scan shift register is electrically connected to the second scan clock signal line PCK2, and the second clock signal end is electrically connected to the first scan clock signal line PCK1; the first power end of the i-th stage scan shift register is electrically connected to the first scan power line PVGH, and the second power end of the i-th stage scan shift register is electrically connected to the second scan power line PVGL.

[0216] Fig. 9A FIG. 1 is an equivalent circuit diagram of a control shift register provided in an exemplary embodiment. Fig. 9A As shown, in an exemplary embodiment, the control shift register may include: first control transistor NT1 to sixteenth control transistor NT16 and first control capacitor NC1 to fourth control capacitor NC4, and any control capacitor among the first control capacitor NC1 to fourth control capacitor NC4 includes: a first plate and a second plate. Fig. 9AThe circuit structure of the control shift register is 16T3C as an example for explanation.

[0217] like Fig. 9AAs shown, the control electrode of the first control transistor NT1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first control transistor NT1 is electrically connected to the signal input terminal NIN, and the second electrode of the first control transistor NT1 is electrically connected to the fourth node N4; the control electrode of the second control transistor NT2 is electrically connected to the fourth node N4, the first electrode of the second control transistor NT2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second control transistor NT2 is electrically connected to the fifth node N5; the control electrode of the third control transistor NT3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third control transistor NT3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third control transistor NT3 is electrically connected to the fifth node N5 The control electrode of the fourth control transistor NT4 is electrically connected to the sixth node N6, the first electrode of the fourth control transistor NT4 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fourth control transistor NT4 is electrically connected to the seventh node N7; the control electrode of the fifth control transistor NT5 is electrically connected to the fifth node N5, the first electrode of the fifth control transistor NT5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth control transistor NT5 is electrically connected to the seventh node N7; the control electrode of the sixth control transistor NT6 is electrically connected to the ninth node N9, the first electrode of the sixth control transistor NT6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth control transistor NT6 is electrically connected to the eighth node N8; The control electrode of the seventh control transistor NT7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh control transistor NT7 is electrically connected to the eighth node N8, and the second electrode of the seventh control transistor NT7 is electrically connected to the first node N1; the control electrode of the eighth control transistor NT8 is electrically connected to the fourth node N4, the first electrode of the eighth control transistor NT8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth control transistor NT8 is electrically connected to the first node N1; the control electrode of the ninth control transistor NT9 is electrically connected to the first node N1, the first electrode of the ninth control transistor NT9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth control transistor NT9 is electrically connected to the output terminal NOUT; the tenth control transistor The control electrode of NT10 is electrically connected to the second node N2, the first electrode of the tenth control transistor NT10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth control transistor NT10 is electrically connected to the output terminal NOUT; the control electrode of the eleventh control transistor NT11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh control transistor NT11 is electrically connected to the fifth node N5, and the second electrode of the eleventh control transistor NT11 is electrically connected to the ninth node N9; the control electrode of the twelfth control transistor NT12 is electrically connected to the second power supply terminal VGL, the first electrode of the twelfth control transistor NT12 is electrically connected to the fourth node N4, and the second electrode of the twelfth control transistor NT12 is electrically connected to the second node N2;The control electrode of the thirteenth control transistor NT13 is electrically connected to the third power supply terminal VCX, the first electrode of the thirteenth control transistor NT13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth control transistor NT13 is electrically connected to the fourth node N4; the control electrode of the fourteenth control transistor NT14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth control transistor NT14 is electrically connected to the signal input terminal NIN, and the second electrode of the fourteenth control transistor NT14 is electrically connected to the tenth node N10; the control electrode of the fifteenth control transistor NT15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth control transistor NT15 is electrically connected to the tenth node N10, and the second electrode of the fifteenth control transistor NT15 is electrically connected to the sixth node N6. ; The control electrode of the sixteenth control transistor NT16 is electrically connected to the sixth node N6, the first electrode of the sixteenth control transistor NT16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth control transistor NT16 is electrically connected to the second node N2; the first plate NC11 of the first control capacitor NC1 is electrically connected to the ninth node N9, and the second plate NC12 of the first control capacitor NC1 is electrically connected to the eighth node N8; the first plate NC21 of the second control capacitor NC2 is electrically connected to the first node N1, and the second plate NC22 of the second control capacitor NC2 is electrically connected to the first power supply terminal VGH; the first plate C31 of the third control capacitor NC3 is electrically connected to the sixth node N6, and the second plate NC32 of the third control capacitor NC3 is electrically connected to the seventh node N7. ;

[0218] In an exemplary embodiment, the second clock signal terminal CK2 is a low level signal in the power-on initialization stage to prevent the ninth control transistor NT9 and the tenth control transistor NT10 of the last reset shift register from being turned on at the same time due to the delay of the output signal, or is a low level signal in the abnormal shutdown stage to prevent the ninth control transistor NT9 and the tenth control transistor NT10 from being turned on at the same time. The second clock signal terminal CK2 continuously provides a high level signal in the normal display stage, that is, in the normal display stage, the thirteenth control transistor NT13 is continuously turned off.

[0219] Fig. 9B for Fig. 9A Provides the timing diagram for controlling the shift register. Fig. 9B Take the first control transistor NT1 to the sixteenth control transistor NT16 as P-type control transistors as an example. Fig. 9B As shown, the working process of controlling the shift register may include the following stages:

[0220] In the first stage C1, the signals of the signal input terminal NIN and the second clock signal terminal CK2 are high-level signals, and the signal of the first clock signal terminal CK1 is a low-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, the first control transistor NT1, the third control transistor NT3 and the twelfth control transistor NT12 are turned on, the turned-on first control transistor NT1 transmits the high-level signal of the signal input terminal NIN to the fourth node N4, the signal of the fourth node N4 is a high-level signal, the turned-on twelfth control transistor NT12 transmits the high-level signal of the fourth node N4 to the second node N2, the turned-on fourteenth control transistor NT14 transmits the high-level signal of the signal input terminal NIN to the tenth node N10, the signal of the tenth node N10 is a high-level signal, the turned-on fifteenth control transistor NT15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, the tenth control transistor NT10 and the sixteenth control transistor NT16 are turned off. In addition, the turned-on third control transistor NT3 transmits the low-level signal of the second power supply terminal VGL to the fifth node N5, and the signal of the fifth node N5 is a low-level signal. The turned-on eleventh control transistor NT11 transmits the low-level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low-level signal. The fifth control transistor NT5 and the sixth control transistor NT6 are turned on. Although the signal of the second clock signal terminal CK2 is a high-level signal, since the seventh control transistor NT7 is turned off, the signal of the first node N1 will not be pulled up and remain as a low-level signal. The ninth control transistor NT9 is turned off, and the signal of the output terminal NOUT remains at the previous low level. In the first stage C1, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the output terminal NOUT remains at the previous low-level signal.

[0221] In the second stage C2, the signal of the second clock signal terminal CK2 is a low-level signal, and the signals of the signal input terminal NIN and the first clock signal terminal CK1 are high-level signals. The signal of the second clock signal terminal CK2 is a low-level signal, and the seventh control transistor NT7 is turned on. The signal of the first clock signal terminal CK1 is a high-level signal, and the first control transistor NT1 and the third control transistor NT3 are turned off. Under the action of the third control capacitor NC3, the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 can continue to maintain the high-level signal of the previous stage. Under the action of the first control capacitor NC1, the fifth node N5 and the ninth node N9 can continue to maintain the low-level signal of the previous stage, so the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. The second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8 and the tenth control transistor NT10 are turned off. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on sixth control transistor NT6 and the seventh control transistor NT7, the ninth control transistor NT9 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the output terminal NOUT through the turned-on ninth control transistor NT9. Therefore, in this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the output terminal NOUT is a high-level signal.

[0222] In the third stage C3, the signal of the first clock signal terminal CK1 is a low-level signal, and the signals of the signal input terminal NIN and the second clock signal terminal CK2 are high-level signals. The signal of the second clock signal terminal CK2 is a high-level signal, the seventh control transistor NT7 is turned off, and under the action of the second control capacitor NC2, the first node N1 maintains the low-level signal of the previous stage, the ninth control transistor NT is continuously turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the output terminal NOUT through the turned-on ninth control transistor NT9. The signal of the first clock signal terminal CK1 is a low-level signal, the first control transistor NT1, the third control transistor NT3 and the twelfth control transistor NT12 are turned on, the turned-on first control transistor NT1 transmits the high-level signal of the signal input terminal NIN to the fourth node N4, and the signal of the fourth node N4 is a high-level signal, the turned-on twelfth control transistor NT12 transmits the high-level signal of the fourth node N4 to the second node N2, the turned-on fourteenth control transistor NT14 transmits the high-level signal of the signal input terminal NIN to the tenth node N10, and the signal of the tenth node N10 is a high-level signal, the turned-on fifteenth control transistor NT15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8, the tenth control transistor NT10 and the sixteenth control transistor NT16 are disconnected. In addition, the turned-on third control transistor NT3 transmits the low level signal of the second power supply terminal VGL to the fifth node N5, and the signal of the fifth node N5 is a low level signal. The turned-on eleventh control transistor NT11 transmits the low level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low level signal. The fifth control transistor NT5 and the sixth control transistor NT6 are turned on. In this stage, the first node N1 is a low level signal, the second node N2 is a high level signal, and the signal of the output terminal NOUT is a high level signal.

[0223] In the fourth stage C4, the signals of the signal input terminal NIN and the second clock signal terminal CK2 are low-level signals, and the signal of the first clock signal terminal CK1 is a high-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, and the first control transistor NT1 and the third control transistor NT3 are turned off. The signal of the second clock signal terminal CK2 is a low-level signal, and the seventh control transistor NT7 is turned on. Due to the storage function of the third control capacitor NC3, the signals of the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 maintain the high-level signals of the previous stage, and the second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8 and the tenth control transistor NT10 are turned off. Due to the storage function of the first control capacitor NC1, the ninth node N9 continues to maintain the low-level signal of the previous stage, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. In addition, the low level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on sixth control transistor NT6 and the seventh control transistor NT7, and the high level signal of the first power supply terminal VGH is transmitted to the output terminal NOUT through the turned-on ninth control transistor NT9, and the signal of the output terminal NOUT is still a high level signal. In this stage, the first node N1 is a high level signal, the second node N2 is a low level signal, and the output terminal NOUT is a high level signal.

[0224] In the fifth stage C5, the signal of the second clock signal terminal CK2 is a high level signal, and the signals of the signal input terminal NIN and the first clock signal terminal CK1 are low level signals. The signal of the first clock signal terminal CK1 is a low level signal, and the first control transistor NT1, the third control transistor NT3 and the fourteenth control transistor NT14 are turned on. The signal of the second clock signal terminal CK2 is a high level signal, and the seventh control transistor NT7 is turned off. The first control transistor NT1 is turned on and transmits the low-level signal of the signal input terminal NIN to the fourth node N4, and the signal of the fourth node N4 is a low-level signal. The twelfth control transistor NT12 is turned on and transmits the low-level signal of the fourth node N4 to the first node N1, and the signal of the first node N1 becomes a low-level signal. The fourteenth control transistor NT14 is turned on and transmits the low-level signal of the signal input terminal NIN to the tenth node N10, and the signal of the tenth node N10 is a low-level signal. The fifteenth control transistor NT15 is turned on and transmits the low-level signal of the tenth node N10 to the sixth node N6, and the signal of the sixth node N6 is a low-level signal. The second control transistor NT2, the fourth control transistor NT4, the eighth control transistor NT8 and the tenth control transistor NT10 are turned on. The second control transistor NT2 is turned on and transmits the low-level signal of the first clock signal terminal CK1 to the fifth node N5, so that the fifth node N5 is a low-level signal, so the fifth node N5 and the ninth node N9 continue to maintain the low-level signal of the previous stage, and the fifth control transistor NT5 and the sixth control transistor NT6 are turned on. The signal of the second clock signal terminal CK2 is a high-level signal, and the seventh control transistor NT7 is turned off. In addition, the high-level signal of the first power supply terminal VGH is transmitted to the first node N1 through the turned-on eighth control transistor NT8, and the ninth control transistor NT9 is turned off. The low-level signal of the second power supply terminal VGL is transmitted to the output terminal NOUT through the turned-on tenth control transistor NT10, and the signal of the output terminal NOUT becomes a low-level signal. In this stage, the first node N1 is a high-level signal, the second node N2 is a low-level signal, and the output terminal NOUT is a low-level signal.

[0225] In an exemplary embodiment, if Figure 3 and Figure 4As shown, the display substrate may further include: two control initial signal lines NSTV extending along the second direction D2, a first control clock signal line NCK1, a second control clock signal line NCK2, three first control power lines NVGH, two second control power lines NVGL, a third control power line NVCX and a control cascade signal line NCL. Among them, the input end of the first-level control shift register is electrically connected to the control initial signal line NSTV, the control cascade signal line NCL is electrically connected to the output end of the i-th level control shift register and the input end of the i+1-th level control shift register; the first clock signal end of the i-th level control shift register is electrically connected to the first control clock signal line NCK1, the second clock signal end is electrically connected to the second control clock signal line NCK2, the first clock signal end of the i+1-th level control shift register is electrically connected to the second control clock signal line NCK2, the second clock signal end is electrically connected to the first control clock signal line NCK1, the first power supply end of the i-th level control shift register is electrically connected to the first control power supply line NVGH, the second power supply end of the i-th level control shift register is electrically connected to the second control power supply line NVGL, and the third power supply end of the i-th level control shift register is electrically connected to the third control power supply line NVCX.

[0226] Fig. 10A FIG. 1 is an equivalent circuit diagram of a reset shift register provided by an exemplary embodiment. Fig. 10A As shown, in an exemplary embodiment, the reset shift register includes: first to thirteenth reset transistors RT1 to RT13 and first to third reset capacitors RC1 to RC3. Fig. 10A The circuit structure in which the reset shift register is 13T3C is used as an example for explanation.

[0227] In an exemplary embodiment, a control electrode of the first reset transistor RT1 is electrically connected to the second clock signal terminal CK2, a first electrode of the first reset transistor RT1 is electrically connected to the input terminal RIN, and a second electrode of the first reset transistor RT1 is electrically connected to the first node N1. A control electrode of the second reset transistor RT2 is electrically connected to the first node N1, a first electrode of the second reset transistor RT2 is electrically connected to the second clock signal terminal CK2, and a second electrode of the second reset transistor RT2 is electrically connected to the second node N2. A control electrode of the third reset transistor RT3 is electrically connected to the second clock signal terminal CK2, a first electrode of the third reset transistor RT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third reset transistor RT3 is electrically connected to the second node N2. A control electrode of the fourth reset transistor RT4 is electrically connected to the third node N3, a first electrode of the fourth reset transistor RT4 is electrically connected to the first clock signal terminal CK1, and a second electrode of the fourth reset transistor RT4 is electrically connected to the fifth node N5. A control electrode of the fifth reset transistor RT5 is electrically connected to the fourth node N4, a first electrode of the fifth reset transistor RT5 is electrically connected to the fifth node N5, and a second electrode of the fifth reset transistor RT5 is electrically connected to the first power supply terminal VGH. The control electrode of the sixth reset transistor RT6 is electrically connected to the fourth node N4, the first electrode of the sixth reset transistor RT6 is electrically connected to the first clock signal terminal CK1, and the second electrode of the sixth reset transistor RT6 is electrically connected to the sixth node N6. The control electrode of the seventh reset transistor RT7 is electrically connected to the first clock signal terminal CK1, the first electrode of the seventh reset transistor RT7 is electrically connected to the sixth node N6, and the second electrode of the seventh reset transistor RT7 is electrically connected to the seventh node N7. The control electrode of the eighth reset transistor RT8 is electrically connected to the first node N1, the first electrode of the eighth reset transistor RT8 is electrically connected to the first power supply terminal VGH, and the second electrode of the eighth reset transistor RT8 is electrically connected to the seventh node N7. The control electrode of the ninth reset transistor RT9 is electrically connected to the seventh node N7, the first electrode of the ninth reset transistor RT9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth reset transistor RT9 is electrically connected to the output terminal ROUT. The control electrode of the tenth reset transistor RT10 is electrically connected to the third node N3, the first electrode of the tenth reset transistor RT10 is electrically connected to the second power supply terminal VGL, and the second electrode of the tenth reset transistor RT10 is electrically connected to the output terminal ROUT. The control electrode of the eleventh reset transistor RT11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh reset transistor RT11 is electrically connected to the second node N2, and the second electrode of the eleventh reset transistor RT11 is electrically connected to the fourth node N4. The control electrode of the twelfth reset transistor RT12 is electrically connected to the second power supply terminal VGL, the first electrode of the twelfth reset transistor RT12 is electrically connected to the first node N1, and the second electrode of the twelfth reset transistor RT12 is electrically connected to the third node N3.The control electrode of the thirteenth reset transistor RT13 is electrically connected to the second clock signal terminal CK2, the first electrode of the thirteenth reset transistor RT13 is electrically connected to the first node N1, and the second electrode of the thirteenth reset transistor RT13 is electrically connected to the first power supply terminal VGH. The first plate RC11 of the first reset capacitor RC1 is electrically connected to the fourth node N4, and the second plate RC12 of the first reset capacitor RC1 is electrically connected to the sixth node N6. The first plate RC21 of the second reset capacitor RC2 is electrically connected to the seventh node N7, and the second plate RC22 of the second reset capacitor RC2 is electrically connected to the first power supply terminal VGH. The first plate RC31 of the third reset capacitor RC3 is electrically connected to the third node N3, and the second plate RC32 of the third reset capacitor RC3 is electrically connected to the fifth node N5.

[0228] In exemplary embodiments, the first to thirteenth reset transistors RT1 to RT13 may be P-type transistors or may be N-type transistors.

[0229] In an exemplary embodiment, the first power supply terminal VGH continuously provides a high level signal, and the second power supply terminal VGL continuously provides a low level signal. Since the second power supply terminal VGL continuously provides a low level signal, the eleventh reset transistor RT11 and the twelfth reset transistor RT12 are continuously turned on.

[0230] In an exemplary embodiment, the second clock signal terminal CK2 is a low level signal in the power-on initialization stage to prevent the ninth reset transistor RT9 and the tenth reset transistor RT10 of the last reset shift register from being turned on at the same time due to the delay of the output signal, or is a low level signal in the abnormal shutdown stage to prevent the ninth reset transistor RT9 and the tenth reset transistor RT10 from being turned on at the same time. The second clock signal terminal CK2 continuously provides a high level signal in the normal display stage, that is, in the normal display stage, the thirteenth reset transistor RT13 is continuously turned off.

[0231] Fig. 10B for Fig. 10A Provides the timing diagram for resetting the shift register. Fig. 10B Taking the first reset transistor RT1 to the thirteenth reset transistor RT13 as P-type transistors as an example, the working process of the reset shift register provided by an exemplary embodiment includes the following stages:

[0232] In the first stage D1, the signal of the first clock signal terminal CK1 is a high-level signal, and the signal of the second clock signal terminal CK2 is a low-level signal. The signal of the second clock signal terminal CK2 is a low-level signal, the first reset transistor RT1, the third reset transistor RT3 and the twelfth reset transistor RT12 are turned on, the turned-on first reset transistor RT1 transmits the high-level signal of the input terminal RIN to the first node N1, so that the level of the first node N1 becomes a high-level signal, the turned-on twelfth reset transistor RT12 transmits the high-level signal of the first node N1 to the third node N2, and the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned off. In addition, the turned-on third reset transistor RT3 transmits the low-level signal of the third power supply terminal VGL to the second node N2, so that the level of the second node N2 becomes a low level, the turned-on eleventh reset transistor RT11 transmits the low-level signal of the second node N2 to the fourth node N4, so that the level of the fourth node N4 becomes a low level, and the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. The signal at the first clock signal terminal CK1 is a high level signal, and the seventh reset transistor RT7 is turned off. In addition, under the action of the third reset capacitor RC3, the ninth reset transistor RT9 is turned off. In the first phase P1, since the ninth reset transistor RT9 and the tenth reset transistor RT10 are both turned off, the signal at the output terminal ROUT maintains the previous low level.

[0233] In the second stage D2, the first clock signal terminal CK1 is a low-level signal, and the signal of the second clock signal terminal CK2 is a high-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, and the seventh reset transistor RT7 is turned on. The signal of the second clock signal terminal CK2 is a high-level signal, and the first reset transistor RT1 and the third reset transistor RT3 are turned off. Under the action of the third reset capacitor RC3, the first node N1 and the third node N3 can continue to maintain the high-level signal of the previous stage. Under the action of the first reset capacitor RC1, the fourth node N4 can continue to maintain the low level of the previous stage, so the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. The second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned off. In addition, the low-level signal of the first clock signal terminal CK1 is transmitted to the seventh node N7 through the turned-on sixth reset transistor RT6 and the seventh reset transistor RT7, and the ninth reset transistor RT9 is turned on. The turned-on ninth reset transistor RT9 outputs the high-level signal of the first power supply terminal VGH, so the signal of the output terminal ROUT is a high-level signal. In addition,

[0234] In the third stage D3, the signal of the second clock signal terminal CK2 is a low level signal, and the signal of the first clock signal terminal CK1 is a high level signal. The signal of the first clock signal terminal CK1 is a high level signal, and the seventh reset transistor RT7 is turned off. The second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned off. The signal of the second clock signal terminal CK2 is a low level signal, and the first reset transistor RT1 and the third reset transistor RT3 are turned on. Under the action of the second reset capacitor RC3, the ninth reset transistor RT9 remains in the on state, and the turned-on ninth reset transistor RT9 outputs the high level signal of the first power supply terminal VGH, so the signal of the output terminal ROUT is still a high level signal.

[0235] In the fourth stage D4, the signal of the first clock signal terminal CK1 is a low level signal, and the signal of the second clock signal terminal CK2 is a high level signal. The signal of the second clock signal terminal CK2 is a high level signal, and the first reset transistor RT1 and the third reset transistor RT3 are turned off. The signal of the first clock signal terminal CK1 is a low level, and the seventh reset transistor RT7 is turned on. Due to the storage function of the third reset capacitor RC3, the levels of the first node N1 and the third node N3 maintain the high level signal of the previous stage, so that the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned off. Due to the storage function of the first reset capacitor RC1, the fourth node N4 continues to maintain the low level of the previous stage, so that the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. In addition, the low level signal of the first clock signal terminal CK1 is transmitted to the seventh node N7 through the turned-on sixth reset transistor RT6 and the seventh reset transistor RT7, and the turned-on ninth reset transistor RT9 outputs the high level signal of the first power supply terminal VGH, so the signal of the output terminal ROUT is still a high level signal.

[0236] In the fifth stage D5, the signal of the first clock signal terminal CK1 is a high level signal, and the signal of the second clock signal terminal CK2 is a low level signal. The signal of the second clock signal terminal CK2 is a low level signal, and the first reset transistor RT1 and the third reset transistor RT3 are turned on. The signal of the first clock signal terminal CK1 is a high level signal, and the seventh reset transistor RT7 is turned off. The turned-on first reset transistor RT1 transmits the low level signal of the input terminal RIN to the first node N1, so that the level of the first node N1 becomes a low level, and the turned-on twelfth reset transistor RT12 transmits the low level signal of the first node N1 to the third node N3, so that the level of the third node N3 becomes a low level, and the second reset transistor RT2, the fourth reset transistor RT4, the eighth reset transistor RT8 and the tenth reset transistor RT10 are turned on. The turned-on second reset transistor RT2 transmits the low-level signal of the second clock signal terminal CK2 to the second node N2, so that the level of the second node N2 can be further lowered, so the second node N2 and the fourth node N4 continue to maintain the low level of the previous stage, so that the fifth reset transistor RT5 and the sixth reset transistor RT6 are turned on. The signal of the first clock signal terminal CK1 is a high-level signal, and the seventh reset transistor RT7 is turned off. In addition, the turned-on eighth reset transistor RT8 transmits the high-level signal of the first power supply terminal VGH to the seventh node N7, and the ninth reset transistor RT9 is turned off. The turned-on tenth reset transistor RT10 outputs the low-level signal of the second power supply terminal VGL, so the signal of the output terminal ROUT becomes a low level.

[0237] In an exemplary embodiment, if Figure 3 and Figure 4As shown, the display substrate may further include: a reset initial signal line RSTV extending along the second direction D2, a first reset clock signal line RCK1, a second reset clock signal line RCK2, a first reset power line RVGH, two second reset power lines RVGL, a third reset power line RVCX and a reset cascade signal line RCL. Among them, the input end of the first-level reset shift register is electrically connected to the reset initial signal line RSTV, the reset cascade signal line RCL is electrically connected to the output end of the i-th level reset shift register and the input end of the i+1-th level reset shift register; the first clock signal end of the i-th level reset shift register is electrically connected to the first reset clock signal line RCK1, the second clock signal end is electrically connected to the second reset clock signal line RCK2, the first clock signal end of the i+1-th level reset shift register is electrically connected to the second reset clock signal line RCK2, the second clock signal end is electrically connected to the first reset clock signal line RCK1, the first power supply end of the i-th level reset shift register is electrically connected to the first reset power supply line RVGH, the second power supply end of the i-th level reset shift register is electrically connected to the second reset power supply line RVGL, and the third power supply end of the i-th level reset shift register is electrically connected to the third reset power supply line RVCX.

[0238] Fig.11A FIG. 1 is an equivalent circuit diagram of a light emitting shift register provided by an exemplary embodiment. Fig.11A As shown, in an exemplary embodiment, the light emitting shift register includes: first to thirteenth light emitting transistors ET1 to ET13 and first to third light emitting capacitors EC1 to EC3. Fig.11A The circuit structure of the light emitting shift register is 13T3C as an example for explanation. The circuit structure of the light emitting shift register is the same as that of the reset register, and the present disclosure will not repeat them here.

[0239] Fig. 11B for Fig.11A A timing diagram of the light emitting shift register is provided. The working process of the light emitting shift register from the first stage E1 to the fifth stage E5 is the same as the working process of the reset shift register, and the disclosure will not repeat them here.

[0240] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, the length of the reset driving circuit along the first direction D1 is greater than the length of the dummy reset driving circuit along the first direction D1 , and the first direction is the arrangement direction of the plurality of driving circuits.

[0241] In an exemplary embodiment, at least one dummy reset shift register is located between adjacent reset shift registers.

[0242] Fig. 12A Schematic diagram of some film layers of reset shift register and virtual reset shift register Figure 1 , Fig. 12B Schematic diagram of some film layers of reset shift register and virtual reset shift register Figure 2 .like Fig. 12A and Fig. 12B As shown, the reset shift register includes: at least one reset transistor and at least one reset capacitor; the at least one virtual driving unit also includes: a plurality of virtual source-drain electrodes. At least a portion of at least one virtual active pattern in the at least one virtual reset shift register has the same shape as at least a portion of the active pattern of the at least one reset transistor, at least a portion of at least one virtual control electrode in the at least one virtual reset shift register has the same shape as at least a portion of the control electrode of the at least one reset transistor or at least a portion of the reset capacitor, and at least a portion of at least one virtual source-drain electrode in the at least one virtual reset shift register has the same shape as at least a portion of at least one electrode in the first electrode and the second electrode of the at least one reset transistor.

[0243] In an exemplary embodiment, if Fig. 12AAs shown, at least one virtual reset register includes: a first virtual active pattern DRA1 to a twenty-first virtual active pattern DRA21 and a first virtual control electrode DRG11 to an eighth virtual control electrode DRG18. At least one reset register includes: an active pattern RT1-1 and a control electrode RT1-2 of a first reset transistor to an active pattern RT13-1 and a control electrode RT13-2 of a thirteenth reset transistor. Among them, the shape of the first virtual active pattern DRA1 is the same as the partial shape of the active pattern RT6-1 of the sixth reset transistor. The shape of the second virtual active pattern DRA2 is the same as the partial shape of the active pattern RT2-1 of the second reset transistor. The shape of the third virtual active pattern DRA3 is the same as the partial shape of the active pattern RT6-1 of the sixth reset transistor. The shape of the fourth virtual active pattern DRA4 is the same as the partial shape of the active pattern RT7-1 of the seventh reset transistor. The shape of the fifth virtual active pattern DRA5 is the same as the partial shape of the active pattern RT2-1 of the second reset transistor. The shape of the sixth dummy active pattern DRA6 is the same as the shape of a portion of the active pattern RT8-1 of the eighth reset transistor. The shape of the seventh dummy active pattern DRA7 is the same as the shape of a portion of the active pattern RT13-1 of the thirteenth reset transistor. The shape of the eighth dummy active pattern DRA8 is the same as the shape of a portion of the active pattern RT5-1 of the fifth reset transistor. The shape of the ninth dummy active pattern DRA9 is the same as the shape of a portion of the active pattern RT11-1 of the eleventh reset transistor and the shape of a portion of the active pattern RT12-1 of the twelfth reset transistor. The shape of the tenth dummy active pattern DRA10 is the same as the shape of a portion of the active pattern RT12-1 of the twelfth reset transistor. The shape of the eleventh dummy active pattern DRA11 is the same as the shape of a portion of the active pattern RT11-1 of the eleventh reset transistor. The shape of the twelfth dummy active pattern DRA10 is the same as the shape of a portion of the active pattern RT4-1 of the fourth reset transistor. The shape of any active pattern of the thirteenth virtual active pattern DRA13 to the twenty-first virtual active pattern DRA21 is the same as the shape of the active pattern of the ninth reset transistor and the partial shape of the integrated structure of the tenth reset transistor. The shape of the first virtual control electrode DRG11 is the same as the shape of the partial shape of the integrated structure of the control electrode RT1-2 of the first reset transistor and the control electrode RT3-2 of the third reset transistor. The shape of the second virtual control electrode DRG12 is the same as the part of the integrated structure of the control electrode RT6-2 of the sixth reset transistor and the first electrode plate RC11 of the first reset capacitor. The shape of the second virtual control electrode DRG12 is the same as the shape of the control electrode RT2-2 of the second reset transistor. The shape of the third virtual control electrode DRG13 is the same as the shape of the control electrode RT7-2 of the seventh reset transistor. The shape of the fourth virtual control electrode DRG14 is the same as the shape of the control electrode RT2-2 of the second reset transistor.The shape of the fifth virtual control electrode DRG52 is the same as the partial shape of the control electrode RT8-2 of the eighth reset transistor. The shape of the sixth virtual control electrode DRG62 is the same as the partial shape of the control electrode RT13-2 of the thirteenth reset transistor. The partial shape of the seventh virtual control electrode DRG17 is the same as the part of the integrated structure of the control electrode RT11-2 of the eleventh reset transistor and the control electrode RT12-2 of the twelfth reset transistor. The partial shape of the seventh virtual control electrode DRG17 is the same as the part of the control electrode RT5-2 of the fifth reset transistor. The partial shape of the seventh virtual control electrode DRG17 is the same as the part of the integrated structure of the control electrode RT9-2 of the ninth reset transistor and the first electrode plate RC21 of the second reset capacitor. The partial shape of the seventh virtual control electrode DRG17 is the same as the partial shape of the integrated structure of the control electrode RT4-2 of the fourth transistor, the control electrode RT10-2 of the tenth reset transistor and the first electrode plate RC31 of the third reset capacitor.

[0244] In an exemplary embodiment, if Fig. 12BAs shown, at least one virtual reset register includes: a first virtual source-drain electrode DRS1 to a ninth virtual active pattern DRS9. The shape of a portion of the first virtual source-drain electrode DRS1 is the same as the shape of a portion of the first pole RT1-3 of the first reset transistor, the shape of a portion of the first virtual source-drain electrode DRS1 is the same as the shape of a portion of the integrated structure of the second pole RT6-4 of the sixth reset transistor and the first pole RT7-3 of the seventh reset transistor, the shape of a portion of the first virtual source-drain electrode DRS1 is the same as the shape of a portion of the integrated structure of the first pole RT5-3 of the fifth reset transistor, the first pole RT8-3 of the eighth reset transistor, the first pole RT9-3 of the ninth reset transistor, and the first pole RT13-3 of the thirteenth reset transistor, the shape of a portion of the first virtual source-drain electrode DRS1 is the same as the shape of a portion of the integrated structure of the first pole RT7-7 of the seventh reset transistor and the first pole RT8-4 of the eighth reset transistor, and the shape of a portion of the first virtual source-drain electrode DRS1 is the same as the shape of a portion of the second pole RT13-4 of the thirteenth reset transistor. The shape of a portion of the second virtual source-drain electrode DRS2 is the same as the shape of a portion of the second pole RT11-4 of the eleventh reset transistor. The shape of a portion of the second virtual source-drain electrode DRS2 is the same as the shape of a portion of the integrated structure of the second pole RT2-4 of the second reset transistor, the second pole RT3-4 of the third reset transistor, and the first pole RT11-3 of the eleventh reset transistor. The shape of a portion of the third virtual source-drain electrode DRS3 is the same as the shape of a portion of the integrated structure of the first pole RT4-3 of the fourth reset transistor and the first pole RT6-3 of the sixth reset transistor. The shape of a portion of the fourth virtual source-drain electrode DRS4 is the same as the shape of a portion of the integrated structure of the second pole RT4-4 of the fourth reset transistor and the second pole RT5-4 of the fifth reset transistor. The shape of a portion of any source-drain electrode from the fifth virtual source-drain electrode DRS5 to the ninth virtual source-drain electrode DRS is the same as the shape of a portion of the second pole RT10-4 of the tenth reset transistor.

[0245] In an exemplary embodiment, if Figure 3 and Fig. 12B As shown, the positive projection of the reset cascade signal line RCL on the substrate is between the positive projection of the first second reset power line RVGL on the substrate and the positive projection of the third reset power line RVCX on the substrate.

[0246] In an exemplary embodiment, if Figure 3 and Fig. 12B As shown, the virtual reset shift register is located on a side of the reset cascade signal line RCL close to the display area, and at least one virtual source-drain electrode in the virtual reset shift register is electrically connected to the first reset power line RVGH.

[0247] In an exemplary embodiment, if Figure 3 and Fig. 12B As shown, it also includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; the reset cascade signal line RCL, the reset initial signal line RSTV and the two second reset power lines RVGL are located in the fourth conductive layer, and the first reset clock signal line RCK1, the second reset clock signal line RCK2, the first reset power line RVGH and the third reset power line RVCX are located in the fifth conductive layer.

[0248] In an exemplary embodiment, if Figure 4 As shown, the length of the light-emitting driving circuit along the first direction D1 is greater than or equal to the length of the virtual light-emitting driving circuit along the first direction D1, and the first direction is the arrangement direction of the multiple driving circuits.

[0249] Fig.13A Schematic diagram of some film layers of the luminous shift register and the virtual luminous shift register Figure 1 , Fig. 13B Schematic diagram of some film layers of the luminous shift register and the virtual luminous shift register Figure 2 .like Fig.13A and Fig. 13B As shown, the light-emitting driving circuit includes: a plurality of cascaded light-emitting shift registers, the virtual light-emitting driving circuit includes: at least one virtual light-emitting shift register, and the at least one virtual light-emitting shift register is located between adjacent light-emitting shift registers; the light-emitting shift register includes: at least one light-emitting transistor and at least one light-emitting capacitor; the at least one virtual shift register also includes: a plurality of virtual source-drain electrodes; at least a portion of at least one virtual active pattern in the at least one virtual light-emitting shift register is the same in shape as at least a portion of the active pattern of the at least one light-emitting transistor, at least a portion of at least one virtual control electrode in the at least one virtual light-emitting shift register is the same in shape as at least a portion of the control electrode of the at least one light-emitting transistor or at least a portion of the light-emitting capacitor, and at least a portion of at least one virtual source-drain electrode in the at least one virtual light-emitting shift register is the same in shape as at least a portion of at least one electrode in the first electrode and the second electrode of the at least one light-emitting transistor.

[0250] In an exemplary embodiment, if Fig.13AAs shown, at least one virtual light-emitting register includes: a first virtual active pattern DEA1 to a twenty-first virtual active pattern DEA21 and a first virtual control electrode DEG11 to an eighth virtual control electrode DEG18. At least one light-emitting register includes: an active pattern ET1-1 and a control electrode ET1-2 of a first light-emitting transistor to an active pattern ET13-1 and a control electrode ET13-2 of a thirteenth light-emitting transistor. Among them, the shape of the first virtual active pattern DEA1 is the same as the partial shape of the active pattern ET6-1 of the sixth light-emitting transistor. The shape of the second virtual active pattern DEA2 is the same as the partial shape of the active pattern ET2-1 of the second light-emitting transistor. The shape of the third virtual active pattern DEA3 is the same as the partial shape of the active pattern ET6-1 of the sixth light-emitting transistor. The shape of the fourth virtual active pattern DEA4 is the same as the partial shape of the active pattern ET7-1 of the seventh light-emitting transistor. The shape of the fifth virtual active pattern DEA5 is the same as the partial shape of the active pattern ET2-1 of the second light-emitting transistor. The sixth virtual active pattern DEA6 has the same shape as a portion of the active pattern ET8-1 of the eighth light emitting transistor. The seventh virtual active pattern DEA7 has the same shape as a portion of the active pattern ET13-1 of the thirteenth light emitting transistor. The eighth virtual active pattern DEA8 has the same shape as a portion of the active pattern ET5-1 of the fifth light emitting transistor. The ninth virtual active pattern DEA9 has the same shape as a portion of the active pattern ET11-1 of the eleventh light emitting transistor and the active pattern ET12-1 of the twelfth light emitting transistor. The tenth virtual active pattern DEA10 has the same shape as a portion of the active pattern ET12-1 of the twelfth light emitting transistor. The eleventh virtual active pattern DEA11 has the same shape as a portion of the active pattern ET11-1 of the eleventh light emitting transistor. The twelfth virtual active pattern DEA10 has the same shape as a portion of the active pattern ET4-1 of the fourth light emitting transistor. The shape of any active pattern of the thirteenth virtual active pattern DEA13 to the twenty-first virtual active pattern DEA21 is the same as the shape of part of the integrated structure of the active pattern of the ninth light-emitting transistor and the tenth light-emitting transistor. The shape of the first virtual control electrode DEG11 is the same as the shape of part of the integrated structure of the control electrode ET1-2 of the first light-emitting transistor and the control electrode ET3-2 of the third light-emitting transistor. The shape of the second virtual control electrode DEG12 is the same as the part of the integrated structure of the control electrode ET6-2 of the sixth light-emitting transistor and the first electrode plate EC11 of the first light-emitting capacitor. The shape of the second virtual control electrode DEG12 is the same as the shape of part of the control electrode ET2-2 of the second light-emitting transistor. The shape of the third virtual control electrode DEG13 is the same as the shape of part of the control electrode ET7-2 of the seventh light-emitting transistor. The shape of the fourth virtual control electrode DEG14 is the same as the shape of part of the control electrode ET2-2 of the second light-emitting transistor.The shape of the fifth virtual control electrode DEG52 is the same as the partial shape of the control electrode ET8-2 of the eighth light-emitting transistor. The shape of the sixth virtual control electrode DEG62 is the same as the partial shape of the control electrode ET13-2 of the thirteenth light-emitting transistor. The partial shape of the seventh virtual control electrode DEG17 is the same as the part of the integrated structure of the control electrode ET11-2 of the eleventh light-emitting transistor and the control electrode ET12-2 of the twelfth light-emitting transistor. The partial shape of the seventh virtual control electrode DEG17 is the same as the part of the control electrode ET5-2 of the fifth light-emitting transistor. The partial shape of the seventh virtual control electrode DEG17 is the same as the part of the integrated structure of the control electrode ET9-2 of the ninth light-emitting transistor and the first electrode plate EC21 of the second light-emitting capacitor. The partial shape of the seventh virtual control electrode DEG17 is the same as the partial shape of the integrated structure of the control electrode ET4-2 of the fourth transistor, the control electrode ET10-2 of the tenth light-emitting transistor and the first electrode plate EC31 of the third light-emitting capacitor.

[0251] In an exemplary embodiment, if Fig. 13BAs shown, at least one virtual light-emitting register includes: a first virtual source-drain electrode DES1 to a ninth virtual active pattern DES9. The shape of a portion of the first virtual source-drain electrode DES1 is the same as the shape of a portion of the first electrode ET1-3 of the first light-emitting transistor, the shape of a portion of the first virtual source-drain electrode DES1 is the same as the shape of a portion of the integrated structure of the second electrode ET6-4 of the sixth light-emitting transistor and the first electrode ET7-3 of the seventh light-emitting transistor, the shape of a portion of the first virtual source-drain electrode DES1 is the same as the shape of a portion of the integrated structure of the first electrode ET5-3 of the fifth light-emitting transistor, the first electrode ET8-3 of the eighth light-emitting transistor, the first electrode ET9-3 of the ninth light-emitting transistor, and the first electrode ET13-3 of the thirteenth light-emitting transistor, the shape of a portion of the first virtual source-drain electrode DES1 is the same as the shape of a portion of the integrated structure of the first electrode ET7-7 of the seventh light-emitting transistor and the first electrode ET8-4 of the eighth light-emitting transistor, and the shape of a portion of the first virtual source-drain electrode DES1 is the same as the shape of a portion of the second electrode ET13-4 of the thirteenth light-emitting transistor. The shape of a portion of the second virtual source-drain electrode DES2 is the same as the shape of a portion of the second electrode ET11-4 of the eleventh light-emitting transistor. The shape of a portion of the second virtual source-drain electrode DES2 is the same as the shape of a portion of the integrated structure of the second electrode ET2-4 of the second light-emitting transistor, the second electrode ET3-4 of the third light-emitting transistor, and the first electrode ET11-3 of the eleventh light-emitting transistor. The shape of a portion of the third virtual source-drain electrode DES3 is the same as the shape of a portion of the integrated structure of the first electrode ET4-3 of the fourth light-emitting transistor and the first electrode ET6-3 of the sixth light-emitting transistor. The shape of a portion of the fourth virtual source-drain electrode DES4 is the same as the shape of a portion of the integrated structure of the second electrode ET4-4 of the fourth light-emitting transistor and the second electrode ET5-4 of the fifth light-emitting transistor. The shape of a portion of any source-drain electrode from the fifth virtual source-drain electrode DES5 to the ninth virtual source-drain electrode DES is the same as the shape of a portion of the second electrode ET10-4 of the tenth light-emitting transistor.

[0252] In an exemplary manner, if Figure 4 and Fig. 13B As shown, the light-emitting initial signal line ESTV, the first second light-emitting power line EVGL, the third light-emitting power line EVCX, the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, the first light-emitting power line EVGH and the second first light-emitting power line EVGH are arranged in sequence along the direction close to the display area.

[0253] In an exemplary manner, if Figure 4 and Fig. 13BAs shown, the light emitting cascade signal line ECL is electrically connected to the output end of at least one light emitting shift register and the input end of at least one light emitting shift register, respectively, and the positive projection of the light emitting cascade signal line ECL on the substrate is between the positive projection of the first second light emitting power line EVGL on the substrate and the positive projection of the third light emitting power line EVCX on the substrate. The virtual light emitting shift register is located on the side of the light emitting cascade signal line ECL close to the display area, and at least one virtual source-drain electrode in the virtual light emitting shift register is electrically connected to the first light emitting power line EVGH.

[0254] In an exemplary embodiment, the display substrate further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. Among them, the light cascade signal line ECL, the light initial signal line ESTV and the two second light power lines EVGL are located in the fourth conductive layer, and the first light clock signal line ECK1, the second light clock signal line ECK2, the first light power line EVGH and the third light power line EVCX are located in the fifth conductive layer.

[0255] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, the length of the control driving circuit along the first direction D1 is greater than or equal to the length of the virtual control driving circuit along the first direction D1, and the first direction D1 is the arrangement direction of the multiple driving circuits.

[0256] Fig.14A Schematic diagram of some membrane layers of the control shift register and virtual control shift register Figure 1 , Fig. 14B Schematic diagram of some membrane layers of the control shift register and virtual control shift register Figure 2 .like Fig.14A and Fig. 14B As shown, the control driving circuit includes: a plurality of cascaded control shift registers, the virtual control driving circuit includes: at least one virtual control shift register, at least one virtual control shift register is located between adjacent control shift registers; the control shift register includes: at least one control transistor and at least one control capacitor; at least one virtual shift register also includes: a plurality of virtual source-drain electrodes; at least a portion of at least one virtual active pattern in at least one virtual control shift register is the same shape as at least a portion of the active pattern of at least one control transistor, at least a portion of at least one virtual control electrode in at least one virtual control shift register is the same shape as at least a portion of the control electrode of at least one control transistor or at least a portion of the control capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual control shift register is the same shape as at least a portion of at least one electrode in the first electrode and the second electrode of at least one control transistor.

[0257] In an exemplary embodiment, if Fig.14AAs shown, at least one virtual control register includes: the first virtual active pattern DNA1 to the thirtieth virtual active pattern DNA30 and the first virtual control electrode DNG11 to the ninth virtual control electrode DNG19. At least one control register includes: the active pattern NT1-1 and the control electrode NT1-2 of the first control transistor to the active pattern NT16-1 and the control electrode NT16-2 of the sixteenth control transistor. Among them, the shape of the first virtual active pattern DNA1 is the same as the partial shape of the active pattern NT14-1 of the fourteenth control transistor. The shape of the second virtual active pattern DNA2 is the same as the partial shape of the active pattern NT1-1 of the first control transistor. The shape of the third virtual active pattern DNA3 is the same as the partial shape of the active pattern NT14-1 of the fourteenth control transistor. The shape of the fourth virtual active pattern DNA4 is the same as the partial shape of the active pattern NT1-1 of the first control transistor. The shape of the fifth virtual active pattern DNA5 is the same as the partial shape of the active pattern NT3-1 of the third control transistor. The shape of the sixth virtual active pattern DNA6 is the same as the partial shape of the active pattern NT3-1 of the third control transistor. The shape of the seventh virtual active pattern DNA7 is identical to the partial shape of the active pattern NT14-1 of the fifteenth control transistor. The shape of the eighth virtual active pattern DNA8 is identical to the partial shape of the active pattern NT15-1 of the fifteenth control transistor. The shape of the ninth virtual active pattern DNA9 is identical to the partial shape of the active pattern NT4-1 of the fourth control transistor. The shape of the tenth virtual active pattern DNA10 is identical to the partial shape of the active pattern NT4-1 of the fourth control transistor. The shapes of the eleventh virtual active pattern DNA11 and the fourteenth virtual active pattern DNA14 are identical to the partial shape of the active pattern NT7-1 of the seventh control transistor. The shapes of the twelfth virtual active pattern DNA12 and the thirteenth virtual active pattern DNA13 are identical to the partial shape of the active pattern NT6-1 of the sixth control transistor. The shapes of the fifteenth virtual active pattern DNA15 and the seventeenth virtual active pattern DNA17 are identical to the partial shape of the active pattern NT8-1 of the eighth control transistor. The shape of the sixteenth dummy active pattern DNA16 and the eighteenth dummy active pattern DNA18 are identical to the partial shape of the active pattern NT5-1 of the fifth control transistor. The shape of the twelfth dummy active pattern DNA12 and the thirteenth dummy active pattern DNA13 are identical to the partial shape of the active pattern NT6-1 of the sixth control transistor. The shape of the nineteenth dummy active pattern DNA19 is identical to the partial shape of the active pattern NT13-1 of the thirteenth control transistor. The shape of the twentieth dummy active pattern DNA20 is identical to the partial shape of the active pattern NT16-1 of the sixteenth control transistor. The shape of the twenty-first dummy active pattern DNA21 is identical to the partial shape of the active pattern NT12-1 of the twelfth control transistor.The shape of any active pattern of the twenty-second virtual active pattern DNA22 to the thirtieth virtual active pattern DNA30 is the same as the shape of the active pattern of the ninth control transistor and the partial shape of the integrated structure of the tenth control transistor. The shape of the first virtual control electrode DNG11 is the same as the shape of the partial shape of the integrated structure of the control electrode NT1-2 of the first control transistor, the control electrode NT3-2 of the third control transistor, and the control electrode NT14-2 of the fourteenth control transistor. The shape of the second virtual control electrode DNG12 is the same as the partial shape of the integrated structure of the control electrode NT6-2 of the sixth control transistor and the first electrode plate EC11 of the first control capacitor. The shape of the third virtual control electrode DNG13 is the same as the shape of the partial shape of the control electrode NT7-2 of the seventh control transistor. The shape of the third virtual control electrode DNG13 is the same as the shape of the partial shape of the integrated structure of the control electrode NT8-2 of the ninth control transistor and the first electrode plate NC11 of the second control capacitor. The shape of the fourth virtual control electrode DNG14 is the same as the shape of the control electrode NT11-2 of the eleventh control transistor and the control electrode NT15-2 of the fifteenth control transistor. The partial shape of the fifth virtual control electrode DNG15 is the same as the partial shape of the control electrode NT5-2 of the fifth control transistor. The shape of the fifth virtual control electrode DNG15 is the same as the partial shape of the control electrode NT2-2 of the second control transistor. The partial shape of the sixth virtual control electrode DNG62 is the same as the partial shape of the control electrode NT13-2 of the thirteenth control transistor. The partial shape of the seventh virtual control electrode DNG17 is the same as the partial shape of the integrated structure of the control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor and the first electrode plate NC31 of the third control capacitor. The shape of the eighth virtual control electrode DNG18 is the same as the partial shape of the control electrode NT12-2 of the twelfth control transistor. The partial shape of the ninth virtual control electrode DNG19 is the same as the partial shape of the control electrode NT5102 of the tenth control transistor. The partial shape of the ninth virtual control electrode DNG19 is the same as the partial shape of the integrated structure of the control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor and the first electrode plate NC31 of the third control capacitor.

[0258] In an exemplary embodiment, if Fig. 14BAs shown, at least one virtual control register includes: a first virtual source-drain electrode DNS1 to a fifth virtual source-drain electrode DNS5. The shape of a portion of the first virtual source-drain electrode DNS1 is the same as the shape of a portion of the integrated structure of the first electrode NT1-3 of the first control transistor and the first electrode NT14-3 of the fourteenth control transistor. The shape of a portion of the second virtual source-drain electrode DNS2 is the same as the shape of a portion of the second electrode NT1-4 of the first control transistor, the shape of a portion of the second virtual source-drain electrode DNS2 is the same as the shape of a portion of the first electrode NT3-3 of the third control transistor, the shape of a portion of the second virtual source-drain electrode DNS2 is the same as the shape of a portion of the first electrode NT4-3 of the fourth control transistor, the shape of a portion of the second virtual source-drain electrode DNS2 is the same as the shape of a portion of the second electrode NT15-4 of the fifteenth control transistor, the shape of a portion of the second virtual source-drain electrode DNS2 is the same as the shape of a portion of the integrated structure of the second electrode NT14-2 of the fourteenth control transistor and the first electrode NT15-3 of the fifteenth control transistor, and the shape of a portion of the third virtual source-drain electrode DNS3 is the same as the shape of a portion of the first electrode NT6-3 of the sixth control transistor. The shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the second electrode NT7-4 of the seventh control transistor and the second electrode NT8-4 of the eighth control transistor, the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the second electrode NT9-4 of the ninth control transistor and the second electrode NT10-4 of the tenth control transistor, the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the first electrode NT10-3 of the tenth control transistor, the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the first electrode NT8-3 of the eighth control transistor, the first electrode NT9-9 of the ninth control transistor and the first electrode NT13-3 of the thirteenth control transistor, and the shape of a portion of the fourth virtual source-drain electrode DNS4 is the same as the shape of a portion of the integrated structure of the first electrode NT12-3 of the twelfth control transistor and the second electrode NT13-4 of the thirteenth control transistor. The shape of a portion of the fifth virtual source-drain electrode DNS5 is the same as the shape of a portion of the second electrode NT5-4 of the fifth control transistor, the shape of a portion of the fifth virtual source-drain electrode DNS5 is the same as the shape of a portion of the first electrode NT3-3 of the third control transistor, and the shape of a portion of the fifth virtual source-drain electrode DNS5 is the same as the shape of a portion of the first electrode NT16-3 of the sixteenth control transistor.

[0259] In an exemplary embodiment, if Figure 3 , Figure 4 and Fig. 14BAs shown, at least one of the control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first control power line NVGH, the second control power line NVGL, the third control power line NVCX and the control cascade signal line NCL extends along the second direction, and the first direction intersects the second direction; wherein, the first control initial signal line NSTV, the first second control power line NVGL, the second control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first first control power line NVGH, the third control power line NVCX, the second first control power line NVGH, the third first control power line NVGH and the second second control power line NVGL are arranged in sequence along the direction close to the display area.

[0260] In an exemplary embodiment, if Figure 3 , Figure 4 and Fig. 14B As shown, the control cascade signal line NCL is electrically connected to the output end of at least one stage of control shift register and the input end of at least one stage of control shift register respectively, and the positive projection of the control cascade signal line NCL on the substrate is between the positive projection of the second control initial signal line NSTV on the substrate and the positive projection of the first control clock signal line NCK1 on the substrate.

[0261] In an exemplary embodiment, Fig. 14B As shown, the control cascade signal line NCL divides the area where the virtual control shift register is located into a first area NR1 and a second area NR2, at least one virtual source-drain electrode located in the first area NR1 is connected to the first second control power line NVGL, and at least one virtual source-drain electrode located in the second area NR2 is connected to at least one first control power line NVGH.

[0262] In an exemplary embodiment, it further includes: a driving structure layer; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer. The control cascade signal line NCL is located in the fourth conductive layer, and the control initial signal line NSTV, the first control clock signal line NCK1, the second control clock signal line NCK2, the first control power line NVGH, the two second control power lines NVGL, and the third control power line NVCX are located in the fifth conductive layer.

[0263] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, the length of the scan driving circuit along the first direction is greater than or equal to the length of the virtual scan driving circuit along the first direction D1, and the first direction D1 is the arrangement direction of the multiple driving circuits.

[0264] Fig.15A Schematic diagram of some film layers of the scan shift register and the virtual scan shift register Figure 1 , Fig. 15B Schematic diagram of some film layers of the scan shift register and the virtual scan shift register Figure 2 .like Fig.15A and Fig. 15B As shown, in an exemplary embodiment, the scan driving circuit includes: a plurality of cascaded scan shift registers, the virtual scan driving circuit includes: at least one virtual scan shift register, and the at least one virtual scan shift register is located between adjacent scan shift registers; the scan shift register includes: at least one scan transistor and at least one scan capacitor; and the at least one virtual shift register also includes: a plurality of virtual source-drain electrodes. Among them, at least a portion of at least one virtual active pattern in at least one virtual scan shift register has the same shape as at least a portion of the active pattern of at least one scan transistor, at least a portion of at least one virtual control electrode in at least one virtual scan shift register has the same shape as at least a portion of the control electrode of at least one scan transistor or at least a portion of the scan capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual scan shift register has the same shape as at least a portion of at least one electrode in the first electrode and the second electrode of at least one scan transistor.

[0265] In an exemplary embodiment, if Fig.15AAs shown, at least one virtual scan register includes: the first virtual active pattern DPA1 to the thirteenth virtual active pattern DPA13 and the first virtual control electrode DPG11 to the fifth virtual control electrode DPG15. At least one scan register includes: the active pattern PT1-1 and the control electrode PT1-2 of the first scan transistor to the active pattern PT8-1 and the control electrode PT8-2 of the eighth scan transistor. Among them, the shape of the first virtual active pattern DPA1 and the second virtual active pattern DPA2 are the same as the partial shape of the active pattern PT1-1 of the first scan transistor. The shape of the third virtual active pattern DPA3 and the shape of the fourth virtual active pattern DPA4 are the same as the partial shape of the active pattern PT2-1 of the second scan transistor. The shape of the fifth virtual active pattern DPA5 and the shape of the sixth virtual active pattern DPA6 are the same as the partial shape of the active pattern PT3-1 of the third scan transistor. The shape of the seventh virtual active pattern DPA7 to the shape of the tenth virtual active pattern DPA10 are the same as the partial shape of the active pattern PT4-1 of the fourth scan transistor and the active pattern PT5-1 of the fifth scan transistor. The partial shape of the eleventh virtual active pattern DPA11 is the same as the partial shape of the active pattern PT1-1 of the first scan transistor, and the partial shape of the eleventh virtual active pattern DPA11 is the same as the partial shape of the active pattern PT6-1 of the sixth scan transistor. The shape of the twelfth virtual active pattern DPA12 is the same as the partial shape of the active pattern PT7-1 of the seventh scan transistor. The shape of the thirteenth virtual active pattern DPA13 is the same as the partial shape of the active pattern PT8-1 of the eighth scan transistor. The shape of the first virtual control electrode DPG11 is the same as the partial shape of the integrated structure of the control electrode PT1-2 of the first scan transistor and the control electrode PT3-2 of the third scan transistor. The partial shape of the second virtual control electrode DPG12 is the same as the partial shape of the integrated structure of the control electrode PT2-2 of the second scan transistor. The shape of the third virtual control electrode DPG13 is the same as the partial shape of the control electrode PT8-2 of the eighth scan transistor. The shape of the fourth virtual control electrode DPG14 is the same as the partial shape of the control electrode PT7-2 of the seventh scan transistor. The partial shape of the fifth virtual control electrode DPG15 is the same as the partial shape of the control electrode PT5-2 of the fifth scan transistor. The shape of the fifth virtual control electrode DPG15 is the same as the partial shape of the integrated structure of the control electrode PT2-2 of the fourth scanning transistor, the control electrode PT6-2 of the sixth scanning transistor and the first electrode plate PC11 of the first scanning capacitor. The shape of the fifth virtual control electrode DPG15 is the same as the partial shape of the integrated structure of the control electrode PT5- of the fifth scanning transistor and the first electrode plate PC21 of the second scanning capacitor.

[0266] In an exemplary embodiment, if Fig. 15BAs shown, at least one virtual scan register includes: a first virtual source-drain electrode DPS1 to a fourth virtual source-drain electrode DPS4. The shape of a portion of the first virtual source-drain electrode DPS1 is the same as the shape of a portion of the integrated structure of the first pole PT1-3 of the first scan transistor and the first pole PT14-3 of the fourteenth scan transistor. The shape of a portion of the second virtual source-drain electrode DPS2 is the same as the shape of a portion of the second pole PT1-4 of the first scan transistor, the shape of a portion of the second virtual source-drain electrode DPS2 is the same as the shape of a portion of the first pole PT3-3 of the third scan transistor, the shape of a portion of the second virtual source-drain electrode DPS2 is the same as the shape of a portion of the first pole PT4-3 of the fourth scan transistor, the shape of a portion of the second virtual source-drain electrode DPS2 is the same as the shape of a portion of the second pole PT15-4 of the fifteenth scan transistor, the shape of a portion of the second virtual source-drain electrode DPS2 is the same as the shape of a portion of the integrated structure of the second pole PT14-2 of the fourteenth scan transistor and the first pole PT15-3 of the fifteenth scan transistor, and the shape of a portion of the third virtual source-drain electrode DPS3 is the same as the shape of a portion of the first pole PT6-3 of the sixth scan transistor. The shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the second pole PT7-4 of the seventh scanning transistor and the second pole PT8-4 of the eighth scanning transistor, the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the second pole PT9-4 of the ninth scanning transistor and the second pole PT10-4 of the tenth scanning transistor, the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the first pole PT10-3 of the tenth scanning transistor, the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the first pole PT8-3 of the eighth scanning transistor, the first pole PT9-9 of the ninth scanning transistor and the first pole PT13-3 of the thirteenth scanning transistor, and the shape of a portion of the fourth virtual source-drain electrode DPS4 is the same as the shape of a portion of the integrated structure of the first pole PT12-3 of the twelfth scanning transistor and the second pole PT13-4 of the thirteenth scanning transistor.

[0267] In an exemplary embodiment, if Figure 3 , Figure 4 and Fig. 15B The second scanning power line PVGL, the first scanning clock signal line PCK1, the second scanning clock signal line PCK2, the scanning initial signal line PSTV and the first scanning power line PVGH are sequentially arranged in a direction close to the display area.

[0268] In an exemplary embodiment, if Figure 3 , Figure 4 and Fig. 15BAs shown, the scan cascade signal line PCL is electrically connected to the output end of at least one level of scan shift register and the input end of at least one level of scan shift register, respectively, and the positive projection of the scan cascade signal line PCL on the substrate is between the positive projection of the second scan clock signal line PCK2 on the substrate and the positive projection of the scan initial signal line PSTV on the substrate.

[0269] In an exemplary embodiment, if Fig. 15B As shown, the scanning cascade signal line PCL divides the area where the virtual scanning shift register is located into a first area PR1 and a second area PR2, at least one virtual source-drain electrode located in the first area PR1 is connected to the second scanning power line PVGL, and at least one virtual source-drain electrode located in the second area PR2 is connected to the first scanning power line PVGH.

[0270] In an exemplary embodiment, the display substrate may further include a driving structure layer. The driving structure layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The scanning cascade signal line PCL is located in the fourth conductive layer, and the scanning initial signal line PSTV, the first scanning clock signal line PCK1, the second scanning clock signal line PCK2, the first scanning power line PVGH, and the second scanning power line PVGL are located in the fifth conductive layer.

[0271] In an exemplary embodiment, there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate, so that the area of ​​the virtual active pattern in the virtual driving circuit group is smaller than the area of ​​the active pattern in the driving circuit group, thereby reducing the overlapping area between at least one signal line (for example, a clock signal line) in the display substrate and the virtual active pattern, reducing the coupling capacitance between the signal line and the active pattern, avoiding potential leakage in the display substrate, and reducing the power consumption of the display substrate.

[0272] In an exemplary embodiment, since there is no overlapping area between the orthographic projection of the virtual active pattern DA on the substrate and the orthographic projection of the virtual control electrode DG on the substrate, there is no complete transistor structure in the virtual driving circuit group. Therefore, the display substrate does not need to be connected to a test circuit for verifying the virtual driving circuit group, which can improve the testing efficiency of the display substrate.

[0273] In an exemplary embodiment, the driving circuit group includes: at least one transistor and at least one capacitor, the virtual driving circuit group includes: a plurality of virtual active patterns, a plurality of virtual control electrodes, and a virtual source-drain electrode, the display substrate further includes: a signal output line located in a non-display area, at least one cascade signal line, and a plurality of signal lines, the plurality of signal lines are respectively connected to the driving circuit group and the virtual circuit group, and the signal output line is connected to the driving circuit group. Wherein, the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer.

[0274] The semiconductor layer includes at least: an active pattern of at least one transistor and at least one dummy active pattern among a plurality of dummy active patterns;

[0275] The first conductive layer at least includes: a control electrode of at least one transistor, a plate of at least one capacitor, and at least one virtual active pattern among a plurality of virtual control electrodes;

[0276] The second conductive layer includes at least: another plate of at least one capacitor;

[0277] The third conductive layer at least includes: a signal output line;

[0278] The fourth conductive layer at least includes: at least one signal line and a cascade signal line;

[0279] The fifth conductive layer at least includes: at least one signal line.

[0280] In an exemplary embodiment, the driving structure layer may further include: a first insulating layer located between the semiconductor layer and the first conductive layer, a second insulating layer located between the first conductive layer and the second conductive layer, a third insulating layer located between the second conductive layer and the third conductive layer, a fourth insulating layer located between the third conductive layer and the fourth conductive layer, and a fifth insulating layer and a planarizing layer located between the fourth conductive layer and the fifth conductive layer.

[0281] In an exemplary embodiment, if Figure 3 and Figure 4 As shown, it also includes: at least one initial signal line located in the non-display area. The at least one initial signal line is located on a side of at least one of the plurality of signal lines close to the display area and is located in the fifth conductive layer; the orthographic projection of the at least one initial signal line on the substrate at least partially overlaps with the orthographic projection of the drive circuit group and the dummy drive circuit group on the substrate. Figure 3 and Figure 4 The description is made by taking two initial signal lines INIL1 and INIL2 as an example.

[0282] In an exemplary embodiment, two adjacent virtual scan shift registers are arranged along an arc-shaped boundary of a corner area, and at least one level of scan shift register may be provided between the two adjacent virtual scan shift registers or they may be directly adjacent to each other, and one of the two adjacent virtual scan shift registers may be referred to as a first adjacent virtual scan shift register, and the other may be referred to as a second adjacent virtual scan shift register. At least one virtual source-drain electrode in the first adjacent virtual scan shift register may be electrically connected to one of the first scan clock signal line and the second scan clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual scan shift register may be electrically connected to the other of the first scan clock signal line and the second scan clock signal line.

[0283] In an exemplary embodiment, two adjacent virtual control shift registers are arranged along the arc-shaped boundary of the corner area, and at least one level of control shift register may be provided between the two adjacent virtual control shift registers or they may be directly adjacent, and one of the two adjacent virtual control shift registers may be referred to as a first adjacent virtual control shift register, and the other may be referred to as a second adjacent virtual control shift register. At least one virtual source-drain electrode in the first adjacent virtual control shift register may be electrically connected to one of the first control clock signal line and the second control clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual control shift register may be electrically connected to the other of the first control clock signal line and the second control clock signal line.

[0284] In an exemplary embodiment, two adjacent virtual reset shift registers are arranged along the arc-shaped boundary of the corner area, and at least one level of reset shift register may be provided between the two adjacent virtual reset shift registers or they may be directly adjacent, and one of the two adjacent virtual reset shift registers may be referred to as a first adjacent virtual reset shift register, and the other may be referred to as a second adjacent virtual reset shift register. At least one virtual source-drain electrode in the first adjacent virtual reset shift register may be electrically connected to one of the first reset clock signal line and the second reset clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual reset shift register may be electrically connected to the other of the first reset clock signal line and the second reset clock signal line.

[0285] In an exemplary embodiment, two adjacent virtual light-emitting shift registers are arranged along the arc-shaped boundary of the corner area, and at least one level of light-emitting shift register may be provided between the two adjacent virtual light-emitting shift registers or they may be directly adjacent, and one of the two adjacent virtual light-emitting shift registers may be referred to as a first adjacent virtual light-emitting shift register, and the other may be referred to as a second adjacent virtual light-emitting shift register. At least one virtual source-drain electrode in the first adjacent virtual light-emitting shift register may be electrically connected to one of the first light-emitting clock signal line and the second light-emitting clock signal line, and at least one virtual source-drain electrode in the second adjacent virtual light-emitting shift register may be electrically connected to the other of the first light-emitting clock signal line and the second light-emitting clock signal line.

[0286] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In the exemplary embodiment, the structure of the light-emitting shift register is the same as that of the reset shift register, and the structure of the virtual light-emitting shift register is the same as that of the virtual reset shift register. The following only describes the manufacturing methods of the scanning shift register and the virtual scanning shift register, the control shift register and the virtual control shift register, the reset shift register and the virtual reset shift register. The manufacturing methods of the light-emitting shift register and the virtual light-emitting shift register are the same as the manufacturing methods of the reset shift register and the virtual reset shift register, and are not repeated here.

[0287] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. Figures 16 to 18 As shown, Fig.16 A schematic diagram of a scanning shift register and a dummy scanning shift register after a semiconductor layer pattern is formed. Fig.17 A schematic diagram of a control shift register and a dummy control shift register after a semiconductor layer pattern is formed. Fig.18 Schematic diagram after semiconductor layer patterns are formed for the reset shift register and the dummy reset shift register.

[0288] In an exemplary embodiment, if Figures 16 to 18 As shown, the semiconductor layer pattern may include at least: an active pattern PT1-1 of the first scanning transistor located in the scanning shift register to an active pattern PT8-1 of the eighth scanning transistor, a first virtual active pattern DPA1 to a thirteenth virtual active pattern DPA13 located in the virtual scanning shift register, an active pattern NT1-1 of the first control transistor located in the control shift register to the sixteenth control transistor NT16-1, a first virtual active pattern DNA1 to a thirtieth virtual active pattern DNA30 located in the virtual control shift register, an active pattern RT1-1 of the first reset transistor located in the reset shift register to the active pattern RT13-1 of the thirteenth reset transistor, and a first virtual active pattern DRA1 to a twenty-first virtual active pattern DRA21 located in the virtual reset shift register.

[0289] In an exemplary embodiment, the active pattern PT4-1 of the fourth scanning transistor and the active pattern PT5-1 of the fifth scanning transistor are an integrated structure, the active pattern PT6-1 of the sixth scanning transistor, the active pattern PT7-1 of the seventh scanning transistor and the active pattern PT8-1 of the eighth scanning transistor are an integrated structure, and the active pattern PT1-1 of the first scanning transistor, the active pattern PT2-1 of the second scanning transistor, and the active pattern PT3-1 of the third scanning transistor are separately set.

[0290] In an exemplary embodiment, any active pattern among the first to thirteenth dummy active patterns DPA1 to DPA13 located in the dummy scan shift register is individually provided.

[0291] In an exemplary embodiment, the active pattern NT2-1 of the second control transistor and the active pattern NT11-1 of the eleventh control transistor are an integrated structure, the active pattern NT9-1 of the ninth control transistor and the active pattern NT10-1 of the tenth control transistor are an integrated structure, the active pattern NT8-1 of the eighth control transistor, the active pattern NT12-1 of the twelfth control transistor, the active pattern NT13-1 of the thirteenth control transistor, and the active pattern NT16-1 of the sixteenth control transistor are an integrated structure. The active pattern NT1-1 of the first control transistor, the active pattern NT3-1 of the third control transistor, the active pattern NT4-1 of the fourth control transistor, the active pattern NT5-1 of the fifth control transistor, the active pattern NT6-1 of the sixth control transistor, the active pattern NT7-1 of the seventh control transistor, and the active pattern NT15-1 of the fifteenth control transistor are separately provided.

[0292] In an exemplary embodiment, any one of the first to thirtieth dummy active patterns DNA1 to DNA30 located in the dummy control shift register is individually provided.

[0293] In an exemplary embodiment, the active pattern RT4-1 of the fourth reset transistor, the active pattern RT5-1 of the fifth reset transistor, the active pattern RT7-1 of the seventh reset transistor, the active pattern RT8-1 of the eighth reset transistor, and the active pattern RT13-1 of the thirteenth reset transistor are an integral structure. The active pattern RT9-1 of the ninth reset transistor and the active pattern RT10-1 of the tenth reset transistor are active patterns. The active pattern RT1-1 of the first reset transistor, the active pattern RT2-1 of the second reset transistor, the active pattern RT3-1 of the third reset transistor, the active pattern RT6-1 of the sixth reset transistor, the active pattern RT11-1 of the eleventh reset transistor, and the active pattern RT12-1 of the twelfth reset transistor are separately provided.

[0294] In an exemplary embodiment, any one of the first to twenty-first dummy active patterns DRA1 to DRA21 located in the dummy reset shift register is individually provided.

[0295] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, such as Figures 19 to 24 As shown, Fig.19 is a schematic diagram of a first conductive layer pattern in a scan shift register and a virtual scan shift register, Fig. 20A schematic diagram of a scanning shift register and a dummy scanning shift register after forming a first conductive layer pattern, Fig.21 is a schematic diagram of a first conductive layer pattern in a control shift register and a virtual control shift register, Fig. 22 It is a schematic diagram of the first conductive layer pattern in the control shift register and the virtual control shift register. Fig.23 A schematic diagram of forming a first conductive layer pattern for a reset shift register and a dummy reset shift register, Fig.24 Schematic diagram after forming a first conductive layer pattern for a reset shift register and a dummy reset shift register. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0296] In an exemplary embodiment, the first conductive layer pattern may include at least: the control electrode PT1-2 of the first scan transistor to the control electrode PT8-2 of the eighth scan transistor located in the scan shift register and the first plate PC11 of the first scan capacitor and the first plate PC21 of the second scan capacitor, the first virtual control electrode DPA11 to the fifth virtual control electrode DPG15 located in the virtual scan shift register, the control electrode NT1-2 of the first control transistor to the sixteenth control transistor NT16-2 located in the control shift register and the first plate NC11 of the first control capacitor to the first plate NC31 of the third control capacitor, the first virtual control electrode DNG11 to the ninth virtual control electrode DNG19 located in the virtual control shift register, the control electrode RT1-2 of the first reset transistor to the control electrode RT13-2 of the thirteenth reset transistor located in the reset shift register and the first plate RC11 of the first reset capacitor to the first plate RC31 of the third reset capacitor, and the first virtual control electrode DRG11 to the eighth virtual control electrode DRG18 located in the virtual reset shift register.

[0297] In an exemplary embodiment, the control electrode PT1-2 of the first scanning transistor and the control electrode PT3-2 of the third scanning transistor are an integrated structure. The control electrode PT4-2 of the fourth scanning transistor, the control electrode PT6-2 of the sixth scanning transistor and the first plate PC11 of the first scanning capacitor are an integrated structure. The control electrode PT5-2 of the fifth scanning transistor and the first plate PC21 of the second scanning capacitor are an integrated structure. The control electrode PT2-2 of the second scanning transistor, the control electrode PT7-2 of the seventh scanning transistor and the control electrode PT8-2 of the eighth scanning transistor are separately provided.

[0298] In an exemplary embodiment, any electrode among the first to fifth virtual gate electrodes DPA11 to DPG15 located in the virtual scan shift register is independently provided.

[0299] In an exemplary embodiment, the control electrode NT1-2 of the first control transistor, the control electrode NT3-2 of the third control transistor, and the control electrode NT14-2 of the fourteenth control transistor are an integrated structure. The control electrode NT2-2 of the second control transistor and the control electrode NT8-2 of the eighth control transistor are an integrated structure. The control electrode NT6-2 of the sixth control transistor and the first electrode plate NC11 of the first control capacitor are an integrated structure. The control electrode NT5-2 of the fifth control transistor and the control electrode NT11-2 of the eleventh control transistor are an integrated structure. The control electrode NT4-2 of the fourth control transistor, the control electrode NT16-2 of the sixteenth control transistor and the first electrode plate NC31 of the third control capacitor are an integrated structure, and the control electrode NT9-2 of the ninth control transistor and the first electrode plate NC21 of the second control capacitor are an integrated structure. The control electrode NT5-2 of the fifth control transistor, the control electrode NT7-2 of the seventh control transistor, the control electrode NT10-2 of the tenth control transistor, the control electrode NT12-2 of the twelfth control transistor, and the control electrode NT13-2 of the thirteenth control transistor are separately provided.

[0300] In an exemplary embodiment, any one of the first to ninth virtual control electrodes DNG11 to DNG19 located in the virtual control shift register is independently provided.

[0301] In an exemplary embodiment, the control electrode RT1-2 of the first reset transistor and the control electrode RT3-2 of the third reset transistor are an integrated structure. is an integrated structure. The control electrode RT6-2 of the sixth reset transistor and the first plate RC11 of the first reset capacitor are an integrated structure. The control electrode RT11-2 of the eleventh reset transistor and the control electrode RT12-2 of the twelfth reset transistor are an integrated structure. The control electrode RT4-2 of the fourth reset transistor, the control electrode RT10-2 of the tenth reset transistor and the first plate RC31 of the third reset capacitor are an integrated structure, and the control electrode RT9-2 of the ninth reset transistor and the first plate RC21 of the second reset capacitor are an integrated structure. The control electrode RT2-2 of the second reset transistor, the control electrode RT5-2 of the fifth reset transistor, the control electrode RT7-2 of the seventh reset transistor, the control electrode RT8-2 of the eighth reset transistor and the control electrode RT13-2 of the thirteenth reset transistor are separately provided.

[0302] In an exemplary embodiment, any one of the first to eighth dummy control electrodes DRG11 to DRG18 located in the dummy reset shift register is independently provided.

[0303] In an exemplary embodiment, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern. The orthographic projection of any virtual control electrode on the substrate does not overlap with the orthographic projection of the virtual active pattern on the substrate.

[0304] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern, patterning the second conductive film through a patterning process, forming a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, such as Figures 25 to 30 As shown, Fig.25 is a schematic diagram of a second conductive layer pattern in a scan shift register and a virtual scan shift register, Fig.26 A schematic diagram of a scan shift register and a dummy scan shift register after forming a second conductive layer pattern, Fig. 27 is a schematic diagram of a second conductive layer pattern in a control shift register and a virtual control shift register, Fig.28 A schematic diagram of a control shift register and a virtual control shift register after forming a second conductive layer pattern. Fig.29 A schematic diagram of forming a second conductive layer pattern for a reset shift register and a dummy reset shift register, Fig.30 Schematic diagram after forming a second conductive layer pattern for a reset shift register and a dummy reset shift register. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0305] In an exemplary embodiment, the second conductive layer pattern may include at least: a second plate PC12 of a first scan capacitor located in a scan shift register, a second plate PC22 of a second scan capacitor and a first scan connection line PL1, a first virtual electrode DPG21, a second virtual electrode DPG22 and a third virtual electrode DPG23 located in a virtual scan shift register, a second plate NC12 of a first control capacitor to a second plate NC32 of a third control capacitor and a first scan connection line NL1 located in a control shift register, a first virtual electrode DNG11 to a fourth virtual control electrode DNG14 located in a virtual control shift register, a second plate RC12 of a first reset capacitor to a first plate RC32 of a third reset capacitor located in a reset shift register, and a first virtual electrode DRG21 to a third virtual electrode DRG23 located in a virtual reset shift register.

[0306] In an exemplary embodiment, the shape of the first virtual electrode DPG21 located in the virtual scan shift register is the same as the shape of a portion of the first scan signal line PL1. The shape of the second virtual electrode DPG22 located in the virtual scan shift register is the same as the shape of a portion of the second electrode plate PC12 of the first scan capacitor. The shape of the third virtual electrode DPG23 located in the virtual scan shift register is the same as the shape of a portion of the second electrode plate PC22 of the second scan capacitor.

[0307] In an exemplary embodiment, the shape of the first virtual electrode DNG21 located in the virtual control shift register is the same as the shape of a portion of the second electrode plate NC12 of the first control capacitor. The shape of the second virtual electrode DNG22 located in the virtual control shift register is the same as the shape of a portion of the second electrode plate NC22 of the second control capacitor. The shape of the third virtual electrode DNG23 and the shape of the fourth virtual electrode DNG24 located in the virtual control shift register are the same as the shape of a portion of the first electrode plate NC32 of the third control capacitor.

[0308] In an exemplary embodiment, the shape of the first virtual electrode DRG21 located in the virtual reset shift register is the same as the shape of a portion of the second electrode plate RC12 of the first reset capacitor. The shape of the second virtual electrode DRG22 located in the virtual reset shift register is the same as the shape of a portion of the second electrode plate RC22 of the second reset capacitor. The shape of the third virtual electrode DRG23 located in the virtual reset shift register is the same as the shape of a portion of the first electrode plate RC32 of the third reset capacitor.

[0309] (4) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third insulating film and a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film by a patterning process, and forming a third insulating layer pattern covering the second conductive layer pattern and a third conductive layer pattern located on the third insulating layer pattern, such as Figure 31 to Figure 34 As shown, Fig.31 is a schematic diagram of the third conductive layer pattern in the control shift register and the virtual control shift register, Fig.32 A schematic diagram of a control shift register and a virtual control shift register after a third conductive layer pattern is formed. Fig.33 is a schematic diagram of a third conductive layer pattern in a reset shift register and a virtual reset shift register, Fig.34 Schematic diagram after forming a third conductive layer pattern for a reset shift register and a dummy reset shift register. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0310] In an exemplary embodiment, the third conductive layer pattern may include at least a dummy electrode DNG31 located in the dummy control shift register, a second reset link line RL2 located in the reset shift register, and a dummy electrode DRG31 located in the dummy reset shift register.

[0311] In an exemplary embodiment, the shape of the dummy electrode DRG31 located at the dummy reset shift register is the same as a portion of the second reset link line RL2 .

[0312] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, wherein the fourth insulating layer is provided with a plurality of via patterns, such as Figure 35 to Figure 37 As shown, Fig.35 A schematic diagram of a scan shift register and a dummy scan shift register after a fourth insulating layer is formed, Fig.36 A schematic diagram of a control shift register and a virtual control shift register after a fourth insulating layer is formed. Fig.37 A schematic diagram of a reset shift register and a dummy reset shift register after a fourth insulating layer is formed.

[0313] In an exemplary embodiment, the fourth insulating layer pattern may include at least: the first via V1 to the fourteenth via V14 located in the scanning shift register, the first virtual via DV1 to the nineteenth virtual via V19 located in the virtual scanning shift register, the first via H1 to the twenty-fourth via H24 located in the control shift register, the first virtual via DH1 to the forty-second virtual via DH42 located in the virtual control shift register, the first via K1 to the twenty-second via K22 located in the reset shift register, and the first virtual via DK1 to the thirty-first virtual via DK31 located in the reset scanning shift register.

[0314] (6) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern located on the fourth insulating layer pattern, such as Figures 38 to 43 As shown, Fig.38 is a schematic diagram of a fourth conductive layer pattern in a scan shift register and a virtual scan shift register, Fig.39 A schematic diagram of a scan shift register and a dummy scan shift register after a fourth conductive layer pattern is formed, Fig.40 is a schematic diagram of a fourth conductive layer pattern in a control shift register and a virtual control shift register, Fig.41 A schematic diagram of a control shift register and a virtual control shift register after forming a fourth conductive layer pattern, Fig.42 is a schematic diagram of a fourth conductive layer pattern in a reset shift register and a virtual reset shift register, Fig.43 Schematic diagram after forming a fourth conductive layer pattern for a reset shift register and a dummy reset shift register. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0315] In an exemplary embodiment, the fourth conductive layer pattern may include at least: the first electrode PT1-3 and the second electrode PT1-4 of the first scan transistor located in the scan shift register to the first electrode PT8-3 and the second electrode PT8-4 of the eighth scan transistor, the first virtual source-drain electrode DPS1 to the fourth virtual source-drain electrode DPS4 located in the virtual scan shift register, the first electrode NT1-3 and the second electrode NT1-4 of the first control transistor located in the control shift register to the first electrode NT8-3 and the second electrode NT8-4 of the eighth control transistor, the first virtual source-drain electrode DNS1 to the fifth virtual source-drain electrode DNS5 located in the virtual control shift register, the first electrode RT1-3 and the second electrode RT1-4 of the first reset transistor located in the reset shift register to the first electrode RT8-3 and the second electrode RT8-4 of the eighth reset transistor, the first virtual source-drain electrode DRS1 to the ninth virtual source-drain electrode DRS9 located in the virtual reset shift register, the scan cascade signal line PCL, the control cascade signal line NCL, the reset cascade signal line RCL, the reset initial signal line RSTV and two second reset power lines RVGL.

[0316] In an exemplary embodiment, the first virtual source-drain electrode DPS1 to the third virtual source-drain electrode DPS3 located in the virtual scan shift register are located on the side of the scan cascade signal line PCL away from the display area, and the fourth virtual source-drain electrode DPS4 located in the virtual scan shift register is located on the side of the scan cascade signal line PCL close to the display area.

[0317] In an exemplary embodiment, the first electrodes RT1-3 and the second electrodes RT1-4 of the first reset transistor to the eighth reset transistor RT8-3 and the second electrodes RT8-4 of the reset shift register and the first dummy source-drain electrodes DRS1 to the ninth dummy source-drain electrodes DRS9 of the dummy reset shift register are disposed between the two second reset power lines RVGL.

[0318] In an exemplary embodiment, the first virtual source-drain electrode DNS1 and the second virtual source-drain electrode DNS2 located in the virtual control shift register are located on a side of the control cascade signal line NCL away from the display area, and the third virtual source-drain electrode DNS3 to the fifth virtual source-drain electrode DNS5 located in the virtual control shift register are located on a side of the control cascade signal line NCL close to the display area.

[0319] In an exemplary embodiment, the first to ninth dummy source-drain electrodes DRS1 to DRS9 located in the dummy reset shift register are located on a side of the reset cascade signal line RCL close to the display area.

[0320] (7) Forming a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: depositing a fifth insulating film on the substrate having the aforementioned pattern, and coating a planar film, patterning the fifth insulating film and the planar film by a patterning process to form a fifth insulating layer pattern and a planar layer pattern covering the aforementioned structure, wherein the planar layer is provided with a plurality of via hole patterns, such as Figures 44 to 46 As shown, Fig.44 Schematic diagram of the scan shift register and the virtual scan shift register after the flat layer is formed. Fig.45 Schematic diagram of the control shift register and the virtual control shift register after forming a flat layer. Fig.46 Schematic diagram after forming the planar layer for the reset shift register and the dummy reset shift register.

[0321] In an exemplary embodiment, the multiple vias in the flat layer may include at least: the fifteenth via V15 to the sixteenth via V16 located in the scanning shift register, the twentieth virtual via DV20 to the twenty-first virtual via VD21 located in the virtual scanning shift register, the twenty-fifth via H25 to the thirty-first via H31 located in the control shift register, the forty-third virtual via DH43 to the forty-fifth virtual via DH45 located in the virtual control shift register, the twenty-third via K23 to the twenty-fourth via K24 located in the reset shift register, and the thirty-second virtual via DK32 located in the reset scanning shift register.

[0322] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the fifth insulating layer, such as Figures 47 to 52 As shown, Fig.47 is a schematic diagram of a fifth conductive layer pattern in a scan shift register and a virtual scan shift register, Fig.48 A schematic diagram of a scan shift register and a dummy scan shift register after a fifth conductive layer pattern is formed. Fig.49 is a schematic diagram of a fifth conductive layer pattern in a control shift register and a virtual control shift register, Fig.50 A schematic diagram of a control shift register and a virtual control shift register after a fifth conductive layer pattern is formed. Fig.51 is a schematic diagram of a fifth conductive layer pattern in a reset shift register and a virtual reset shift register, Fig.52 Schematic diagram after forming a fifth conductive layer pattern for a reset shift register and a dummy reset shift register. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0323] In an exemplary embodiment, the fifth conductive layer pattern may include at least: a scan initial signal line PSTV, a first scan clock signal line PCK1, a second scan clock signal line PCK2, a first scan power line PVGH, a second scan power line PVGL, a first initial signal line INIL1 and a second initial signal line INIL2, a control initial signal line NSTV, a first control clock signal line NCK1, a second control clock signal line NCK2, a first control power line NVGH, a second control power line NVGL, a third control power line NVCX, a reset initial signal line RSTV, a first reset clock signal line RCK1, a second reset clock signal line RCK2, a first reset power line RVGH, a second reset power line RVGL, and a third reset power line RVCX.

[0324] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include a plurality of shift registers and a plurality of dummy shift registers. In a plane perpendicular to the display substrate, the drive circuit layer may be arranged on the substrate. The drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a flat layer, and a fifth conductive layer sequentially arranged on the substrate.

[0325] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0326] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0327] In an exemplary embodiment, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0328] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0329] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer, the third insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fourth insulating layer may be referred to as a passivation (PVX) layer.

[0330] In an exemplary embodiment, the planar layer may employ an organic material such as resin or the like.

[0331] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0332] On the substrate forming the aforementioned pattern, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the second flat layer; on the substrate forming the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern; on the substrate formed with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern; on the substrate forming the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.

[0333] At this point, the light-emitting structure layer is prepared on the substrate.

[0334] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns, wherein the plurality of anode patterns may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light emitting device, wherein the anode of the first light emitting device is located at a red sub-pixel emitting red light, the anode of the second light emitting device may be located at a blue sub-pixel emitting blue light, the anode of the third light emitting device may be located at a first green sub-pixel emitting green light, and the anode of the fourth light emitting device may be located at a second green sub-pixel emitting green light.

[0335] In an exemplary embodiment, the anode of the first light emitting device and the anode of the second light emitting device may be alternately arranged along the first direction, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately arranged along the first direction. Alternatively, the anode of the first light emitting device and the anode of the second light emitting device may be alternately arranged along the second direction, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately arranged along the second direction.

[0336] In an exemplary embodiment, the shapes and areas of anode electrodes of four sub-pixels in one pixel unit may be the same, or may be different.

[0337] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0338] In an exemplary embodiment, the organic structure layer may include at least: an organic light emitting layer of a light emitting device.

[0339] In an exemplary embodiment, the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.

[0340] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.

[0341] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0342] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0343] The embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0344] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0345] In an exemplary embodiment, the display device may be any product or component having a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0346] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0347] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0348] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate having a display area and a non-display area, characterized in that: The invention comprises: a substrate, and a pixel driving circuit disposed on the substrate and located in a display area, and a driving circuit group and a virtual driving circuit group located in a non-display area, wherein the pixel driving circuit is electrically connected to the driving circuit group, the driving circuit group comprises: at least one shift register, the virtual driving circuit group comprises: at least one virtual shift register, the virtual shift register comprises: a plurality of virtual active patterns and a plurality of virtual control electrodes, the shift register comprises: a plurality of transistors, and the transistor comprises: an active pattern and a control electrode; The shape of at least a portion of at least one virtual active pattern is the same as the shape of at least a portion of the active pattern of at least one transistor, the shape of at least a portion of at least one virtual control electrode is the same as the shape of at least a portion of the control electrode of at least one transistor, and there is no overlapping area between the orthographic projection of at least one of the virtual active patterns and the orthographic projection of at least one of the virtual control electrodes on the substrate.

2. The display substrate according to claim 1, characterized in that: The distance between the orthographic projection of at least one virtual active pattern on the substrate and the target virtual control electrode ranges from 0.8 micrometers to 2 micrometers; The orthographic projection of the virtual active pattern on the substrate is adjacent to the orthographic projection of the target virtual control electrode on the substrate.

3. The display substrate according to claim 1, characterized in that: The non-display area includes: at least one corner area and at least one straight frame area, the driving circuit group includes: a plurality of driving circuits, the plurality of driving circuits are sequentially arranged in a direction close to the display area, the driving circuit includes: a plurality of cascaded shift registers, the virtual driving circuit group includes: a plurality of virtual driving circuits, the plurality of virtual driving circuits are sequentially arranged in a direction close to the display area, the virtual driving circuit includes: a plurality of cascaded virtual shift registers; The virtual driving circuit group is at least partially located in the corner area, the driving circuit group is located in the corner area and the straight line frame area, the driving circuit group and the virtual driving circuit group are located on the first side and the second side of the display area, and the first side and the second side of the display area are arranged opposite to each other.

4. The display substrate according to claim 3, characterized in that: The display area is provided with a pixel driving circuit and at least one reset signal line, the pixel driving circuit includes: a driving transistor and a reset transistor, the reset transistor is electrically connected to the control electrode of the driving transistor, and the reset signal line is electrically connected to the control electrode of the reset transistor; the multiple driving circuits include: a reset driving circuit, the reset driving circuit is located on one of the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual reset driving circuit; The length of the reset driving circuit along a first direction is greater than the length of the dummy reset driving circuit along the first direction, and the first direction is an arrangement direction of the plurality of driving circuits.

5. The display substrate according to claim 4, characterized in that: The reset driving circuit comprises: a plurality of cascaded reset shift registers, and the virtual reset driving circuit comprises: at least one virtual reset shift register, and at least one virtual reset shift register is located between adjacent reset shift registers; The reset shift register includes: at least one reset transistor and at least one reset capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual reset shift register has the same shape as at least a portion of an active pattern of at least one reset transistor, at least a portion of at least one virtual control electrode in at least one virtual reset shift register has the same shape as at least a portion of a control electrode of at least one reset transistor or at least a portion of a reset capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual reset shift register has the same shape as at least a portion of at least one electrode of the first electrode and the second electrode of at least one reset transistor.

6. The display substrate according to claim 4, characterized in that: The non-display area is also provided with a reset cascade signal line, a reset initial signal line, a first reset clock signal line, a second reset clock signal line, a first reset power line, two second reset power lines and a third reset power line; At least one of the reset initial signal line, the first reset clock signal line, the second reset clock signal line, the first reset power line, the second reset power line, the third reset power line and the reset cascade signal line extends along a second direction, and the first direction intersects the second direction; The orthographic projections of the reset initial signal line, the first second reset power line, the third reset power line, the first reset clock signal line, the second reset clock signal line, the first reset power line and the second second reset power line on the substrate are arranged in sequence along the direction close to the display area.

7. The display substrate according to claim 5, characterized in that: The non-display area is provided with the reset cascade signal line, two second reset power lines and a third reset power line, and the reset shift register includes: an input end and an output end; The reset cascade signal line is electrically connected to the output end of at least one reset shift register and the input end of at least one reset shift register, respectively, and the orthographic projection of the reset cascade signal line on the substrate is between the orthographic projection of the first and second reset power lines on the substrate and the orthographic projection of the third reset power line on the substrate.

8. The display substrate according to claim 5, characterized in that: The non-display area is provided with the reset cascade signal line and the first reset power line; The virtual reset shift register is located at a side of the reset cascade signal line close to the display area, and at least one virtual source-drain electrode in the virtual reset shift register is electrically connected to the first reset power line.

9. The display substrate according to claim 6, characterized in that: Also includes: Driver structure layer; The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The reset cascade signal line, the reset initial signal line and two second reset power supply lines are located in the fourth conductive layer, and the first reset clock signal line, the second reset clock signal line, the first reset power supply line and the third reset power supply line are located in the fifth conductive layer.

10. The display substrate according to claim 3, characterized in that: The display area is provided with a pixel driving circuit and at least one light emitting signal line, the pixel driving circuit includes: a driving transistor and a light emitting transistor, the light emitting transistor is electrically connected to at least one of the first electrode and the second electrode of the driving transistor, and the light emitting signal line is electrically connected to the control electrode of the light emitting transistor; the multiple driving circuits include: a light emitting driving circuit, the light emitting driving circuit is located on the other side of the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual light emitting driving circuit; The length of the light-emitting driving circuit along the first direction is greater than or equal to the length of the virtual light-emitting driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

11. The display substrate according to claim 10, characterized in that: The light-emitting driving circuit comprises: a plurality of cascaded light-emitting shift registers, and the virtual light-emitting driving circuit comprises: at least one virtual light-emitting shift register, and at least one virtual light-emitting shift register is located between adjacent light-emitting shift registers; The light-emitting shift register includes: at least one light-emitting transistor and at least one light-emitting capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual light-emitting shift register has the same shape as at least a portion of an active pattern of at least one light-emitting transistor, at least a portion of at least one virtual control electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of a control electrode of at least one light-emitting transistor or at least a portion of a light-emitting capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual light-emitting shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one light-emitting transistor.

12. The display substrate according to claim 10, characterized in that: The non-display area is also provided with a light emitting cascade signal line, a light emitting initial signal line, a first light emitting clock signal line, a second light emitting clock signal line, a first light emitting power line, two second light emitting power lines and a third light emitting power line; At least one of the light emitting initial signal line, the first light emitting clock signal line, the second light emitting clock signal line, the first light emitting power line, the second light emitting power line, the third light emitting power line and the light emitting cascade signal line extends along a second direction, and the first direction intersects the second direction; The positive projections of the initial light-emitting signal line, the first second light-emitting power line, the third light-emitting power line, the first light-emitting clock signal line, the second light-emitting clock signal line, the first light-emitting power line and the second first light-emitting power line on the substrate are arranged in sequence along the direction close to the display area.

13. The display substrate according to claim 11, characterized in that: The non-display area is provided with the light-emitting cascade signal line, two second light-emitting power lines and a third light-emitting power line, and the light-emitting shift register includes: an input end and an output end; The light-emitting cascade signal line is electrically connected to the output end of at least one light-emitting shift register and the input end of at least one light-emitting shift register, respectively, and the orthographic projection of the light-emitting cascade signal line on the substrate is between the orthographic projection of the first and second light-emitting power lines on the substrate and the orthographic projection of the third light-emitting power line on the substrate.

14. The display substrate according to claim 11, characterized in that: The non-display area is provided with the light-emitting cascade signal line and the first light-emitting power line; The virtual light emitting shift register is located on a side of the light emitting cascade signal line close to the display area, and at least one virtual source-drain electrode in the virtual light emitting shift register is electrically connected to the first light emitting power line.

15. The display substrate according to claim 12, characterized in that: Also includes: Driver structure layer; The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The light cascade signal line, the light initial signal line and two second light power lines are located in the fourth conductive layer, and the first light clock signal line, the second light clock signal line, the first light power line and the third light power line are located in the fifth conductive layer.

16. The display substrate according to claim 3, characterized in that: The display area is provided with a pixel driving circuit and at least one control signal line, the pixel driving circuit includes: a driving transistor and a compensation transistor, the compensation transistor is electrically connected to the control electrode and the second electrode of the driving transistor, and the control signal line is electrically connected to the control electrode of the compensation transistor; the multiple driving circuits include: a control driving circuit, the control driving circuit is located at the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual control driving circuit; The length of the control driving circuit along the first direction is greater than or equal to the length of the virtual control driving circuit along the first direction, and the first direction is the arrangement direction of the multiple driving circuits.

17. The display substrate according to claim 16, characterized in that: The control driving circuit comprises: a plurality of cascaded control shift registers, and the virtual control driving circuit comprises: at least one virtual control shift register, and at least one virtual control shift register is located between adjacent control shift registers; The control shift register includes: at least one control transistor and at least one control capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual control shift register has the same shape as at least a portion of an active pattern of at least one control transistor, at least a portion of at least one virtual control electrode in at least one virtual control shift register has the same shape as at least a portion of a control electrode of at least one control transistor or at least a portion of a control capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual control shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one control transistor.

18. The display substrate according to claim 16, characterized in that: The non-display area is also provided with a control cascade signal line, two control initial signal lines, a first control clock signal line, a second control clock signal line, three first control power lines, two second control power lines and a third control power line; at least one of the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the second control power line, the third control power line and the control cascade signal line extends along a second direction, the first direction intersecting the second direction; The first control initial signal line, the first second control power line, the second control initial signal line, the first control clock signal line, the second control clock signal line, the first first control power line, the third control power line, the second first control power line, the third first control power line and the second second control power line are arranged in sequence along the direction close to the display area.

19. The display substrate according to claim 17, characterized in that: The non-display area is also provided with a control cascade signal line, two control initial signal lines and a first control clock signal line, and the control shift register includes: an input end and an output end; The control cascade signal line is electrically connected to the output end of at least one stage of control shift register and the input end of at least one stage of control shift register respectively, and the positive projection of the control cascade signal line on the substrate is between the positive projection of the second control initial signal line on the substrate and the positive projection of the first control clock signal line on the substrate.

20. The display substrate according to claim 17, characterized in that: The non-display area is also provided with a control cascade signal line, three first control power lines and two second control power lines; The control cascade signal line divides the area where the virtual control shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the first second control power line, and at least one virtual source-drain electrode located in the second area is connected to at least one first control power line.

21. The display substrate according to claim 18, characterized in that Also includes: Driver structure layer; The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The control cascade signal line is located in the fourth conductive layer, and the control initial signal line, the first control clock signal line, the second control clock signal line, the first control power line, the two second control power lines, and the third control power line are located in the fifth conductive layer.

22. The display substrate according to claim 3, characterized in that: The display area is provided with a pixel driving circuit and at least one scanning signal line, the pixel driving circuit includes: a driving transistor and a writing transistor, the writing transistor is electrically connected to the control electrode and the first electrode of the driving transistor, and the scanning signal line is electrically connected to the control electrode of the writing transistor; the multiple driving circuits include: a scanning driving circuit, the scanning driving circuit is located at the first side and the second side of the display area, and the multiple virtual driving circuits include: a virtual scanning driving circuit; The length of the scan driving circuit along a first direction is greater than or equal to the length of the virtual scan driving circuit along the first direction, and the first direction is an arrangement direction of the plurality of driving circuits.

23. The display substrate according to claim 22, characterized in that: The scan driving circuit comprises: a plurality of cascaded scan shift registers, and the virtual scan driving circuit comprises: at least one virtual scan shift register, and at least one virtual scan shift register is located between adjacent scan shift registers; The scanning shift register includes: at least one scanning transistor and at least one scanning capacitor; at least one virtual shift register also includes: a plurality of virtual source and drain electrodes; At least a portion of at least one virtual active pattern in at least one virtual scan shift register has the same shape as at least a portion of the active pattern of at least one scan transistor, at least a portion of at least one virtual control electrode in at least one virtual scan shift register has the same shape as at least a portion of the control electrode of at least one scan transistor or at least a portion of the scan capacitor, and at least a portion of at least one virtual source-drain electrode in at least one virtual scan shift register has the same shape as at least a portion of at least one electrode among the first electrode and the second electrode of at least one scan transistor.

24. The display substrate according to claim 22, characterized in that: The non-display area is also provided with a scan cascade signal line, a scan initial signal line, a first scan clock signal line, a second scan clock signal line, a first scan power line and a second scan power line; At least one of the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line, the second scan power line and the scan cascade signal line extends along a second direction, and the first direction intersects the second direction; The second scan power line, the first scan clock signal line, the second scan clock signal line, the scan initial signal line and the first scan power line are sequentially arranged in a direction close to the display area.

25. The display substrate according to claim 23, characterized in that: The non-display area is also provided with a scan cascade signal line, a scan initial signal line and a second scan clock signal line, and the scan shift register comprises: an input end and an output end; The scan cascade signal line is electrically connected to the output end of at least one level of scan shift register and the input end of at least one level of scan shift register, respectively, and the positive projection of the scan cascade signal line on the substrate is between the positive projection of the second scan clock signal line on the substrate and the positive projection of the scan initial signal line on the substrate.

26. The display substrate according to claim 23, characterized in that: The non-display area is also provided with a scan cascade signal line, a first scan power line and a second scan power line; The scan cascade signal line divides the area where the virtual scan shift register is located into a first area and a second area, at least one virtual source-drain electrode located in the first area is connected to the second scan power line, and at least one virtual source-drain electrode located in the second area is connected to the first scan power line.

27. The display substrate according to claim 24, characterized in that: Also includes: Driver structure layer; The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The scan cascade signal line is located in the fourth conductive layer, and the scan initial signal line, the first scan clock signal line, the second scan clock signal line, the first scan power line and the second scan power line are located in the fifth conductive layer.

28. The display substrate according to claim 3, characterized in that: The driving circuit group includes: a scanning driving circuit, a control driving circuit, a light emitting driving circuit and a reset driving circuit; The reset driving circuit, the control driving circuit and the scan driving circuit located on the first side of the display area are arranged in sequence along a direction close to the display area, and the light emitting driving circuit, the control driving circuit and the scan driving circuit located on the second side of the display area are arranged in sequence along a direction close to the display area; The scan drive circuit located on the first side of the display area and the scan drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, the control drive circuit located on the first side of the display area and the control drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, the reset drive circuit located on the first side of the display area and the light-emitting drive circuit located on the second side of the display area are symmetrically arranged with respect to the center line of the display area extending along the second direction, and the second direction intersects with the first direction.

29. The display substrate according to claim 3, characterized in that: The driving circuit group includes: at least one transistor and at least one capacitor, the virtual driving circuit group includes: a plurality of virtual active patterns, a plurality of virtual control electrodes, and a virtual source-drain electrode, the display substrate further includes: a signal output line located in a non-display area, at least one cascade signal line and a plurality of signal lines, the plurality of signal lines are respectively connected to the driving circuit group and the virtual circuit group, and the signal output line is connected to the driving circuit group; The driving structure layer comprises: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The semiconductor layer includes at least: an active pattern of at least one transistor and at least one dummy active pattern among a plurality of dummy active patterns; The first conductive layer at least includes: a control electrode of at least one transistor, a plate of at least one capacitor, and at least one virtual active pattern among a plurality of virtual control electrodes; The second conductive layer at least includes: another plate of at least one capacitor; The third conductive layer at least includes: a signal output line; The fourth conductive layer includes: at least one signal line and a cascade signal line; The fifth conductive layer includes: at least one signal line.

30. The display substrate according to claim 29, characterized in that: Also includes: at least one initial signal line located in the non-display area; At least one initial signal line is located on a side of at least one of the plurality of signal lines close to the display area and is located on the fifth conductive layer; The orthographic projection of at least one initial signal line on the substrate at least partially overlaps with the orthographic projections of the driving circuit group and the dummy driving circuit group on the substrate.

31. A display device, characterized in that: include: A display substrate as claimed in any one of claims 1 to 30.

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