Photonic content addressable memory and application thereof

Abstract

Photonic content addressable memories (CAMs) and applications thereof are provided. The CAM includes a photonic crossover bar array including a plurality of row and column waveguides, and a plurality of photonic filter devices. Each filter device may be selectively programmed in a first state and a second state representing a respective stored bit value, the filter device filtering light according to the programming. And an encoder for encoding the plurality of input bit strings as optical signals such that bit values in different bit strings are encoded using optical signals in different pairs of optical states, and for simultaneously providing optical signals corresponding to each bit position in the bit strings to respective row waveguides of the array. The CAM also includes a detector for detecting light in each column waveguide in any of the optical states, thereby identifying any mismatch between each input bit string and a bit value stored in a filter device coupling light to that waveguide.

Description

Background Art

[0001] The present disclosure generally relates to photon content addressable memory and its applications. Photon content addressable memory is provided, and devices and methods for utilizing such memory are provided together.

[0002] Content addressable memory is an associative memory that can perform search operations with O(1) time complexity. In a content addressable memory (CAM), data is addressed by the content of the data, rather than by the address of the data as in traditional memories such as RAM (random access memory) and hard disks. The input to the memory is a bit string ("search word" or "search vector"), which is compared with multiple bit strings stored in the memory. The stored bit strings can be stored in an array of memory cells connected between a set of input search lines and a set of output match lines. The input search word is applied to the search lines, and the output on the match line indicates whether the search word matches the word stored in the cell connected to the match line. If any bit in the search word does not match the corresponding bit of the stored word, the match line is usually pulled low (logical 0), whereby a high match line (logical 1) indicates a match. For binary CAM operation, all input search bits must match the corresponding stored bits. In a ternary CAM (TCAM), a memory cell can store a third "don't care" bit value X that matches both input bit values ​​0 and 1.

[0003] CAM is commonly used for high-speed searches of data routes in network switching devices (routers, switches, gateways, etc.). Here, CAM is used to determine the appropriate output port to forward data packets arriving at the input port. The routing bandwidth is limited by the speed at which these searches can be performed. Other applications include cache memory, decision trees, neural networks, and data mining.

[0004] CAM is usually implemented using digital electronics. A typical SRAM (static random access memory) TCAM memory cell requires 2 SRAM bit cells and an additional 4 transistors. Memristor TCAM cells are an emerging hardware solution that reduces the power consumption and space complexity of digital CAM. Typical memristor hardware uses 6T2M (6 transistors, 2 memristors) CAM cells, 2T2M cells, or 5T2M cells, which alleviate the requirements of SRAM-based or DRAM-based CAM cells. Although memristor CAM solves the space and latency issues of digital CAM to some extent, these issues are still difficult for many applications.

[0005] Optical or photonic CAMs are another promising approach. These CAMs process input search words encoded with optical signals rather than electrical signals and provide high-speed operation by processing data at the speed of light. Although such CAMs provide faster operation than their electronic counterparts, they rely on the same basic operating principles, and current photonic CAMs are not area / time and / or energy efficient enough to meet the growing demands for miniaturization, speed, and efficiency in CAM applications. Summary of the invention

[0006] A first aspect of the present invention provides a photonic content addressable memory. A photonic CAM comprises a photonic crossbar array comprising a plurality of row waveguides and column waveguides, and a plurality of photonic filter devices, each of which is located at a corresponding intersection of the row waveguides and the column waveguides, for selectively coupling light from the row waveguides to the column waveguides at the intersection. Each filter device is selectively programmable in a first state and a second state representing a corresponding stored bit value. Each filter device is operable in a first programmable state to filter out light in any of a first plurality of optical states from light coupled to the column waveguide, and is operable in a second programmable state to filter out light in any of a second, different plurality of optical states from light coupled to the column waveguide. The CAM comprises an encoder for encoding a plurality of input bit strings into optical signals, such that bit values ​​in different bit strings are encoded using optical signals in different optical state pairs, each pair comprising one state from each of the first plurality and the second plurality, and the encoder is operable to simultaneously provide an optical signal corresponding to each bit position in the bit string to a corresponding row waveguide of the array. The CAM also includes a detector for detecting light in each column waveguide in any of the optical states, thereby identifying any mismatch between each input bit string and the bit value stored in the filter device coupling the light into the waveguide.

[0007] Unlike existing CAMs that process input search words serially, i.e., one at a time, embodiments of the present disclosure provide a photonic CAM that can search multiple search words simultaneously. If light in any of the optical states used to encode a given input bit string is detected on a column waveguide, then the bit string is mismatched with the bit string stored in the filter device associated with the column waveguide. Since a different pair of optical states is used to encode each input word, multiple input words can be searched in parallel with a time complexity of O(1). This provides orders of magnitude higher processing speed than current state-of-the-art CAMs. In addition, the memory is implemented in a compact array of photonic crossbars, where the photonic filter devices storing the bit strings are identical at each intersection. This provides an exceptionally simple, area-efficient, integrated CAM with ultra-fast operation.

[0008] Embodiments of the present invention can be easily configured for ternary CAM operation. Here, the encoder is adapted to encode an input bit string comprising bit values ​​0, 1, and X, where X indicates a don't care bit. The bit values ​​0 and 1 in the bit string are encoded using an optical signal in an associated optical state pair, and the bit value X is encoded as a zero signal. Therefore, for an input bit of value X, no signal will be detected, indicating a match with the corresponding stored bit value (whether 1 or 0).

[0009] The optical states used to encode the input bit string may correspond to respective wavelengths of light, whereby the optical signal encoding the input bit string is wavelength-division multiplexed on the traveling waveguide.Other embodiments may use different polarization states of light.

[0010] The photon filter device is conveniently implemented by a directional coupler for coupling light from a row waveguide to a column waveguide at a crossover point and a programmable filter for operating in a first programmable state and a second programmable state. Here, the directional coupler may be adapted to equally distribute optical power between the column waveguides of the array, thereby simplifying operation at the detector. In embodiments based on wavelength division multiplexing, the programmable filter may be a frequency filter. In a preferred embodiment, the frequency filter comprises a first ring resonator and a second ring resonator operable to filter out light in a first programmable state and a second programmable state, respectively. These embodiments may utilize multiple resonant wavelengths of the ring resonator to filter out optical signals having a desired wavelength. The ring resonator may include a corresponding storage element, and preferably includes a non-volatile element such as a phase change memory element, which is programmable to tune the ring resonator to operate in a first programmable state and a second programmable state. This provides a non-volatile, easily programmable array for highly energy efficient operation.

[0011] The CAM embodying the present disclosure also provides tools for in-memory logic computations to accommodate application-level requirements. In particular, the encoder may be operable to, for each input bit string, encode at least one additional logic bit associated with the bit string using at least one additional optical signal in at least one additional optical state different from a state in the first plurality of states and the second plurality of states. The additional optical signals for the corresponding logic bits of the bit string are simultaneously provided to the row waveguides of the array. Here, the memory also includes a plurality of programmable logic devices arranged to selectively couple the additional optical signals to the column waveguides, and the detector is operable to detect the additional optical signal in each column waveguide. The operation of such in-memory logic will be further explained below.

[0012] The output of a CAM implementing the present disclosure may be adapted to the requirements of a particular application. For example, for a simple match search, the detector may be adapted to produce an output indicating, for each column waveguide, whether each input bit string matches a bit value stored in a filter device that couples light to that waveguide. Additionally or alternatively, the detector may be connected to logic that is used to perform a desired processing operation based on the detection results. Examples of such processing operations are described below.

[0013] The memory device implementing the present disclosure may include multiple CAMs as described above, and a memory controller for providing input bit strings to multiple CAMs in parallel. Such a memory device may use the CAMs for multiple parallel search operations, thereby allowing parallel searches of more words and / or parallel searches of longer words distributed over multiple arrays.

[0014] Another aspect of the present disclosure provides a network switching device having a plurality of input ports for receiving input data packets and a plurality of output ports for outputting data packets. The device comprises: a switch structure for forwarding input data packets to output ports according to corresponding address bit strings in the input packets; and a switch controller, comprising at least one CAM as described above, which is used to store the address bit strings in the filter device of the CAM. The switch controller is adapted to provide the address bit strings of a plurality of data packets as input bit strings to the at least one CAM, and is adapted to determine the output ports for forwarding those data packets according to the matching of the input bit strings with the stored address bit strings.

[0015] Another aspect of the present invention provides a method for simultaneously comparing a plurality of first bit strings with each of a plurality of second bit strings. The method includes storing each second bit string in the above-mentioned CAM so that successive bits are stored in filter devices located at successive intersections of a column waveguide and a row waveguide. The method also includes providing the plurality of first bit strings as the input bit strings to an encoder of the CAM, and determining a comparison result based on detection of light in any of the optical states in a detector of the CAM.

[0016] Embodiments of the present disclosure will be described in more detail below by way of illustrative and non-limiting examples with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a photonic CAM implementing the present disclosure;

[0018] Figure 2 illustrates the structure of a photon filter device used in an embodiment of a CAM;

[0019] Figure 3 Pictured Figure 2 The operation of the filter device;

[0020] Figure 4 illustrates a binary CAM operation for a simple example;

[0021] Figure 5 illustrates the ternary CAM operation for a simple example;

[0022] Figure 6 is a schematic diagram of a network switching device implementing the present disclosure;

[0023] 7a and 7b illustrate the structure and operation of a CAM integrated with in-memory logic in an embodiment of the present disclosure;

[0024] Figure 8 illustrates the operation of in-memory logic in a routing application;

[0025] Fig. 9 illustrates additional features of a CAM embodying the present disclosure;

[0026] Fig.10 illustrates a memory device using multiple CAMs to implement the present disclosure; and

[0027] Figures 11a and 11b illustrate Fig.10 Different operating modes of the device. DETAILED DESCRIPTION

[0028] Figure 1 Components of an exemplary photonic CAM implementing the present disclosure are shown. CAM 1 includes a photonic cross-bar array, generally indicated at 2, which includes a plurality of row waveguides and column waveguides. Array 2 is an n by m array in this embodiment, having n row waveguides 3 and m column waveguides 4. CAM 1 includes a plurality of photonic filter devices, indicated at f in the figure. ij (i = 1 to m, j = 1 to n). Each filter device f ij The CAM further comprises an encoder (generally indicated by 5) and a detector (generally indicated by 6). The encoder 5 is adapted to encode a plurality of input bit strings into optical signals provided to the row waveguides of the array 2. The detector 6 is adapted to detect the optical signals coupled from the row waveguides of the array to the column waveguides.

[0029] Each filter device f ijcan be selectively programmed to be in a first state and a second state representing a corresponding stored bit value. Thus, each column i=1 to m of these filter devices can be programmed with a stored bit string (stored word) to be compared with an input bit string (input word). When in the first programmable state (corresponding to a stored bit value of 1 in this example), each filter device f ij The filter device f is operable to filter light in any of the first plurality of optical states from light coupled to the column waveguide i. When in the second programmable state (corresponding to a stored bit value of 0 in this example), each filter device f ij The optical state is operable to filter out light in any of a second plurality of optical states from light coupled to the column waveguide i. In this embodiment, the plurality of optical states correspond to respective wavelengths of light. The first plurality of optical states includes wavelengths denoted by λ1, λ2, λ3, ..., etc., and the second plurality of optical states includes wavelengths denoted by λ ′ 1,λ ′ 2,λ ′ 3,…,etc. represent the wavelength.

[0030] The encoder 5 is operable to encode a plurality of input words into the optical signal such that bit values ​​in different input words are encoded using the optical signal in different pairs of optical states, wherein each pair comprises one state from each of the first and second pluralities of states. Figure 1 Three input words are shown, which are represented here by S k (k={1,2,3}) indicates that each of them includes bit s k1 ,s k2 ,...,s kn . Use the wavelength with the corresponding k ,λ ′ k The optical signal for each input word S k In this example, S k The bit value 1 in is encoded as the wavelength λ k The signal S k The bit value 0 in is encoded as the wavelength λ k In this embodiment, the encoder 5 includes a group of bit encoders E1 to E n , used to receive input word S respectively k The corresponding position s k1 to knThus, each bit encoder encodes the input bits of word S1 into an optical signal of wavelength λ1 (if the bit value is 1) or λ1′ (if the bit value is 0). The input bits of word S2 are encoded into an optical signal of wavelength λ2 (if the bit value is 1) or λ2′ (if the bit value is 0). The input bits of word S3 are encoded into an optical signal of wavelength λ3 (if the bit value is 1) or λ3′ (if the bit value is 0). Although three input words are shown here for simplicity, any number of corresponding wavelength pairs λ can be used. k ,λ ′ k In encoder 5, the additional input S is similarly k ,k=4,5,6,etc. for encoding.

[0031] By each bit encoder E1 to E n The output optical signals are provided to corresponding multiplexers (MUX) which are coupled to corresponding row waveguides 3 of array 2. Thus, encoder 5 simultaneously converts the optical signals corresponding to input word S k The optical signal of each bit position in the array is provided to the corresponding row waveguide of the array. ij The programmed state at each array intersection selectively couples the signal on each row waveguide to the column waveguide at that intersection. ij If the filter device f is programmed to store a bit value of 1, the optical signals of wavelengths λ1, λ2, λ3, ..., etc. (which encode an input bit value of 1) will be filtered out. Only the signals of wavelengths λ1′, λ2′, λ3′, ..., etc. (which encode an input bit value of 0) will be transmitted to the column waveguide. ij is programmed to store a bit value of 0, then the optical signals of wavelengths λ1′, λ2′, λ3′, …, etc. (which encode the input bit value of 0) will be filtered out, and the signals of wavelengths λ1, λ2, λ3, …, etc. (which encode the input bit value of 1) will be transmitted to the column waveguide. Therefore, if the input bit s kj With the storage in the device f ij If the bit in is matched, then no optical signal is transmitted to the column waveguide for that bit. k All bits of k1 to kn with the device f stored in a given column i of the array i1 to f in The corresponding bits in match, then there is no wavelength λ k or ′ k The signal will be transmitted to the column waveguide for that column i of the array.

[0032] The detector 6 is adapted to detect light in any of the first plurality of optical states and the second plurality of optical states (here wavelengths λ1, λ2, λ3, ..., and λ1', λ2', λ3', ...,) in each column waveguide of the array. In this embodiment, the detector comprises a set of demultiplexers (DEMUX) coupled to the respective column waveguides, and a corresponding set of photodetectors PD1 to PDm. Each demultiplexer separates the light output on the associated column waveguide 4 into its component wavelengths and provides the resulting signal (if any) to a corresponding photodetector. Each photodetector is adapted to detect a signal for use in evaluating an input word S k All wavelengths λ are encoded k ,λ ′ k If the photodetector PD i Any wavelength λ is detected k ,λ ′ k The light at the corresponding input word S k mismatch with the word stored in column i of the array. Therefore, a given input word can be compared with all stored words in parallel. In addition, since different optical states have different effects on λ k ,λ ′ k is used for each input word S k The encoding is performed so that all input words can be compared with the words stored in the array at the same time. This simultaneous search tool provides a greatly improved throughput for CAM search operations.

[0033] The CAM 1 may be adapted to provide an output depending on the particular search application. For the simple match / mismatch search described above, the detector may provide an output indicating that for each column waveguide i, each input bit string S k matches a bit value stored in a filter device that couples light into the waveguide. For example, each photodetector PD i A k-bit output can be provided, which indicates that each input signal S k is a match (1) or a mismatch (0) with the word stored in column i. Alternatively or additionally, the detector 6 may be connected to logic for performing desired processing operations based on the detector's detection of light. An illustrative example of such application-dependent logic is described below.

[0034] Figure 2 The filter device f in the preferred embodiment of CAM 1 ijA more detailed illustration of the invention. The enlarged view in this figure shows two filter devices 10 at adjacent intersections of a column waveguide 4 with two row waveguides 3. Each filter device 10 includes a directional coupler and a programmable filter. Here, the directional coupler is implemented by a broadband coupling waveguide 11, which is used to couple light of all operating wavelengths from the row waveguides to the column waveguides. (Note that no coupling occurs here at the actual intersections of the row waveguides and column waveguides in the array, and any coupling losses here are negligible for the described operation). The directional couplers 11 of all filter devices 10 in the array are adapted for equal distribution of optical power between the column waveguides of the array.

[0035] In this embodiment, the programmable filter that can be selectively programmed into a first programmable state and a second programmable state includes a frequency filter. The frequency filter (generally represented by 12) includes first and second ring resonators R1 and R2, and a removal port implemented by a waveguide 13 and a grating 14. In the first programmable state of the frequency filter 12, the first ring resonator R1 is operable to filter out light having any wavelength of the first plurality of wavelengths λ1, λ2, λ3, ..., from the light transmitted to the column waveguide via the directional coupler 11. In the second programmable state of the frequency filter, the second ring resonator R2 is operable to filter out light having any wavelength of the second plurality of wavelengths λ1', λ2', λ3', ..., from the light transmitted to the column waveguide.

[0036] As shown, the ring resonators R1 and R2 include respective memory elements, here phase change memory (PCM) elements, which are programmable to tune the ring resonators for operation in a first programmable state and a second programmable state. Each PCM element may be implemented by a layer of PCM material (e.g., a chalcogenide such as GST (germanium-antimony-tellurium)) overlying a portion of the ring resonator waveguide. As is known in the art, by heating the PCM material, such a PCM element may be programmed to an amorphous or crystalline state with different optoelectronic properties. Here, heat may be applied by applying a programming voltage to a heater (e.g., a metal layer, overlying the PCM material). Alternatively, heating may be achieved by applying an optical signal to the PCM material using an appropriate power to induce a desired phase state.

[0037] The selective filtering of the filter device 10 utilizes wavelengths in the resonance spectra of the ring resonators R1 and R2. Figure 3Tuning of a ring resonator is illustrated for operation in two programmable states of a filter device. Here, the upper schematic diagram shows the resonance spectrum of the ring R1 in two programmable states (crystalline and amorphous) of the PCM element of the ring. In the ON (e.g., crystalline) state, wavelengths λ1, λ2, λ3, ..., are evanescently coupled into the ring R1 from the directional coupler 11. These wavelengths are then coupled from R1 to the drop port 13 and dispersed by the grating 14. Therefore, when R1 is ON, all wavelengths λ1, λ2, λ3, ..., on the associated row waveguide 3 are transmitted to the drop port and are therefore filtered out from the light coupled to the column waveguide 4. In the OFF state of the ring R1, the resonant wavelength changes as indicated so that wavelengths λ1, λ2, λ3, ..., will be transmitted to the column waveguide. Similarly, when the ring R2 is on as indicated in the schematic diagram below, all wavelengths λ1′, λ2′, λ3′, ..., on the row waveguides are transmitted to the drop port and are therefore filtered out from the light coupled to the column waveguide 4. When the ring R2 is off, all wavelengths λ1′, λ2′, λ3′, ..., will be transmitted to the column waveguides.

[0038] In a first programmable state of the filter device 10, the ring R1 is on (indicating that the stored bit value is 1), and the ring R2 is off. Therefore, the wavelengths λ1, λ2, λ3, ..., (which encode the bit value 1 in the input word) will be removed, and the wavelengths λ1', λ2', λ3', ..., (which encode the bit value 0 in the input word) will be transmitted to the column waveguide. In a second programmable state of the device 10, the ring R2 is on (indicating that the stored bit value is 0), and the ring R2 is off. Therefore, the wavelengths λ1', λ2', λ3', ..., (which encode the bit value 0) will be removed, and the wavelengths λ1, λ2, λ3, ..., (which encode the bit value 1) will be transmitted. Figure 4 is a schematic diagram of the resulting filtering operation in conjunction with a simple example. The figure shows two columns of an array having n=4 filter devices 10 per column. The devices in the first column (labeled here as a1 to a4) store the corresponding bits of the first word A as indicated. The devices in the second column (labeled as b1 to b4) store the corresponding bits of the second word B. The corresponding states of the resonators R1 and R2 for these devices are indicated in the table in the figure.

[0039] The diagram shows the array operation of three input words S1 to S3, using the corresponding wavelength pair λ k ,λ ′ kThe bit values ​​of the three input words are encoded as shown. The labeled arrows on the column waveguides near each filter device indicate the input wavelength transmitted by that device. For the first column, photodetector PD1 detects the wavelength used to encode inputs S1 and S3, indicating a mismatch with word A. However, at wavelengths λ2, λ ′ At 2, no signal is detected (or is less than a predetermined threshold level to accommodate expected coupling losses), indicating a match between S2 and A. Therefore, the output of PD1 correctly indicates a match with S2. Similarly, the output of PD2 correctly indicates a match between S1 and word B.

[0040] It will be appreciated that the CAM 1 can be fabricated as an integrated on-chip structure using standard material processing techniques. The array 2 can be used for filter devices f ij The rings R1 and R2 are implemented as microring resonators (MMR) and nanophotonic waveguides. Note that all filter devices f ij are all identical, thereby providing a particularly simple design and facilitating the manufacture of the array. The encoder 5 and detector 6 may be implemented using well-known equipment and well-known techniques as will be clear to those skilled in the art. For example, the optical signal at the required wavelength may be generated by an integrated laser in the encoder 5. The photodetector PD i This can be achieved by a photodiode in the detector 6.

[0041] The above-described embodiments provide an exceptionally area-efficient and energy-efficient CAM implementation with ultra-fast operation resulting from simultaneous searching of multiple input bit strings. Although operation with three input words is described for simplicity, a ring resonator can support hundreds of resonant modes. This provides orders of magnitude higher throughput for parallel searching, constrained only by the number of signal wavelengths that can be generated in a practical design. For example, with current technology, simultaneous searching of up to about one hundred input words is feasible, with about 20 to 30 parallel input words being sufficient for many applications.

[0042] Array 2 can be programmed by the controller ( Figure 1 The method of performing the above steps (not shown) is performed in a known manner, for example by a processor which receives the word to be stored in the array and applies appropriate programming signals to the filter device f ij . Figure 2The filter design provides ease of programming (and reprogramming) by using PCM elements as described above and non-volatile storage for low energy operation. The ring resonator pair storing respective bits 1 and 0 provides high SNR (signal to noise ratio) operation. Signal detection in detector 6 is a simple two-state operation whereby any signal above a predetermined match threshold can be considered a mismatch. This match threshold can be low and can be set to just above the noise threshold for the detector operation.

[0043] In general, the input bit string of the encoder 5 can be defined by an electrical or optical input signal. It should also be noted that although Figure 1 A regular array of parallel, orthogonal row and column waveguides is shown, but in general the waveguides need not be parallel or regularly spaced, and the row and column waveguides need not be orthogonal. However, this array structure provides a particularly efficient implementation. The "row" and "column" waveguides are of course interchangeable, and are not intended to imply any particular array orientation. Likewise, the programming / coding of the 1s and 0s described above can of course be interchanged.

[0044] It is conceivable that the filter device f ij Various other embodiments are possible. For example, in some embodiments other non-volatile memory elements may be used, such as resistive memory elements. Other embodiments may use volatile memory elements based on modulators using nanomechanical, electro-optical, plasma dispersion, or thermal effects. Directional couplers may be implemented by other devices such as MZIs (Mach-Zehnder interferometers), and programmable filters may be implemented by, for example, tunable gratings. Furthermore, embodiments may be envisioned in which the optical states used to encode the input bits correspond to different polarization states of light, rather than different wavelengths. In this case, the filter device may be implemented using devices such as meta-waveguides. ij , which is sensitive to different polarizations of light and can be tuned to selectively filter out desired polarization states. Based on the operations described herein, suitable implementations herein will be clear to those skilled in the art.

[0045] The CAM embodying the present disclosure can be easily adapted for three-state CAM operation. In particular, the encoder 5 can be adapted to encode an input bit string including bit values ​​0, 1 and X (where X indicates a don't care bit) so that the input bit string is encoded using the state pair λ. k ,λ′ k The optical signal encodes the bit values ​​0 and 1 in the bit string, and the bit value X is encoded as a zero signal. Figure 5 The diagram shows the Figure 4The same example operates, but where the input S3 contains two don't care bits X. Since X is encoded as a zero signal in the encoder 5, for these bits, no wavelength λ3 or λ3' is transmitted by the filter devices a3, a4, b3 or b4, whereby X matches both the stored bit values ​​1 and 0. The detector 6 thus detects an additional match for S3 with the word A stored there.

[0046] A CAM embodying the present disclosure may be particularly advantageously employed in network switching devices, such as routers, switches, gateways, etc., where input data packets must be forwarded to appropriate device output ports for onward transmission in the network. Figure 6 FIG. 2 is a schematic diagram of an embodiment of such a switching device. In this example, a router 20 has a set of input ports I1 to I2 for receiving input data packets from network nodes. p , and a set of output ports O1 to O2 for outputting data packets to the network node m The packets received at the input port are forwarded to the output port via the high-speed switch fabric 21. The input packets are queued in the input queue buffer Q as needed. IN Packets forwarded to an output port are queued in the output queue buffer Q as needed before being processed and transmitted forward to the network. OUT In the queue.

[0047] The appropriate output port for forwarding an incoming packet depends on the destination address bit string contained in the incoming packet. The forwarding operation is controlled by the switch controller 22, which compares the address bit string in the incoming packet with the network address stored in the CAM. In particular, the switch controller 22 includes the CAM 1 as described above and a routing processor 23 for controlling the address lookup operation. The processor 23 stores the network address to be compared with the incoming packet address in the filter device f in the CAM 1. ij These columns are schematically indicated in the figure as C1 to C m , where the typical address space is 7 to 15 bits. Each column C1 to C m Corresponding to the corresponding output ports O1 to O m If the input packet address matches the address stored in the given column C i If the address in matches, the packet should be forwarded to the corresponding output port O. i The output of the CAM detector 6 (omitted in this figure) is provided to the address logic 24. The address logic returns the output port address of the corresponding input packet to the routing processor 23. The routing processor then controls the switch fabric 21 to forward the packet to the correct output port.

[0048] In operation of router 20, routing processor 23 reads addresses from packets arriving at input ports and provides addresses from multiple input packets as input bit strings to CAM 1. Address logic 24 thus simultaneously determines appropriate output ports for those data packets based on matching the input packet addresses with the addresses stored in the CAM.

[0049] In a typical network, multiple network nodes will communicate with router 20 at any given time. When the arrival rate of packets exceeds the rate of output routing, data traffic (queuing) occurs. Therefore, the routing bandwidth is limited by the speed at which the output port address of a given input data packet can be searched. Even with the fastest conceivable electronic CAM, data traffic cannot be alleviated due to the serial nature of the CAM search. This represents a serious bottleneck and causes large communication delays. By searching multiple input packet addresses in CAM 1 simultaneously, router 20 provides a greatly increased throughput, alleviating this bottleneck and significantly improving network bandwidth.

[0050] Another emerging requirement for network switching equipment is the ability to program the CAM on-the-fly for flexible use and for in-memory logic computations, for example, to make routing decisions, change output port addresses, or perform application-level computations on packets. The CAM embodying the present disclosure provides tools for in-memory logic operations to accommodate such requirements. In particular, the CAM encoder can be adapted to encode, for each input search word, at least one additional optical signal in at least one additional optical state to encode at least one additional logic bit associated with the word, the at least one additional optical state being different from the states in the first plurality of states and the second plurality of states used to encode the search word. The additional optical signals for the corresponding logic bits of the search word are simultaneously provided to the row waveguides of the array. In addition, a plurality of programmable logic devices can be provided in the array, which are arranged to selectively couple the additional optical signals to the column waveguides. The CAM detector is then operable to detect the additional optical signals in each column waveguide. An exemplary embodiment herein is described below with reference to FIGS. 7a and 7b.

[0051] FIG. 7a shows a CAM 30, wherein the CAM 1 ( Figure 1 ) corresponding features are denoted by the same reference numerals. Here, each input word S k Including address bit string s k1 to kn , and an additional logic bit (here set to the value 1). The encoder 31 comprises an additional bit encoder E for encoding these logic bits L In particular, using the additional wavelength λ″ k For input word S k The wavelength λ″k Different from all other operating wavelengths λ k ,λ′ k , and may be different for different input words, as indicated in the figure. The generated optical signals at wavelengths λ″1, λ″2 and λ″3 are wavelength division multiplexed onto the traveling waveguides 32 of the array.

[0052] A plurality of programmable logic devices are provided at the corresponding intersections of the column waveguide 4 and the row waveguide 32, using L1 to L m These logic devices L i The structure and operation of each device L is shown in FIG7b. i The directional coupler comprises a broadband coupling waveguide 34 for coupling light from the row waveguide 32 to the column waveguide and a programmable frequency filter. The directional coupler is implemented by a ring resonator RL with a memory element (PCM element) which can be programmed to tune the resonator RL to filter out the light with a wavelength λ″ k In the on state of the resonator RL (corresponding to the value of the stored logic bit being 1), the wavelengths λ″1, λ″2 and λ″3 are coupled to the unloading port 35 and are therefore not transmitted to the column waveguide. In the off state of the RL (corresponding to the value of the stored logic bit being 0), the wavelengths λ″1, λ″2 and λ″3 will be transmitted to the column waveguide. The CAM detector 6 (not shown in FIG. 7 a) is operable to detect light at the wavelengths λ″1, λ″2 and λ″3 on each column waveguide, thereby identifying the input logic bit and the value stored in the logic device L. i any mismatch between the logic bits in the

[0053] Figure 8 A simple example of the operation of CAM 30 is shown. This example corresponds to Figure 5 , where there are additional logic devices L1 and L2 in the corresponding columns of the array. Here, in order for routing to occur, the k The address bit string S in the packet k The address bit string in the columns of the CAM must match, and the logic bits must also match. Therefore, in this example, with L1 set to 0, detector PD1 will output 0 (mismatch) due to the logic bit comparison in the first column. Therefore, the router address logic ( Figure 6 24) in will indicate a "route fail" decision for packets from nodes N2 and N3. However, in the second column, the logic bit of node N1 matches, and the address logic will return the output port address of node N1 corresponding to column 2.

[0054] The simple in-memory logic scheme described above can be used to control routing decisions. For example, if the output port is overloaded or if the destination node does not want to provide access (e.g., for maintenance or confidentiality reasons), the logic device for the output port address can be set to off. Although simple examples are described here, it should be understood that various other routing control schemes can be implemented using one or a combination of different logic bits, and more complex Boolean operations can be performed using the detector outputs from the columns of the array. These embodiments provide full flexibility in CAM programming, both for reconfiguring for different output port addresses and for performing in-memory logic operations.

[0055] Optical losses in a photonic cross-bar array increase quadratically with the array size (n times m), which constrains the scalability of the cross-bar size. To improve signal quality, a CAM implementing the present disclosure may include an optical amplifier disposed between each column waveguide and the detector, such as Fig. 9 Here, a broadband optical amplifier (OA) is provided at the output of each column for amplifying the accumulated optical signal in the column waveguide before feeding into a detector (not shown). Additionally or alternatively, the encoder may be adapted to scale the amplitude of the optical signal provided to the row waveguide. This can be achieved using high input coupling into the row and / or amplification by a broadband optical amplifier at the row input, as shown. However, generally, limiting the array size can reduce optical losses to an acceptable level. For example, an array size of 64×64 for routing applications allows search operations on MAC address (6 bytes) and IPv4 (4 bytes), IPv6 (8 bytes) protocols. Of course, other protocols that rely on reduced word lengths (3 bytes and smaller) may also be used.

[0056] Network switching devices and other apparatuses implementing the present disclosure may utilize multiple CAMs to perform parallel search operations. For example, for searches over a large number of output port addresses, the search operation may be broadcast across multiple arrays. Fig.10 An example of such a memory device is shown. The device 40 comprises a plurality of CAMs (here four CAM1 as described above), and a memory controller 41 for providing input bit strings to the CAMs in parallel. The memory controller 41 may comprise an optical or electronic processor compatible with the passive / quasi-passive photonic array as described above.

[0057] 11a and 11b illustrate an exemplary mode of operation of the memory device 40, which for simplicity is a 4 by 4 array. In FIG. 11a, each input search word S kis provided to each of a plurality (here two) of CAMs 1, each storing a different set of memory words (A to D, and E to H respectively). This allows searching over a large number of words (e.g., output port addresses) in parallel using arrays of modest size, thereby allowing N times M parallel searches, where N is the number of columns and M is the number of arrays. In FIG. 11 b, each input search word S k The CAM 1 is parsed into segments (here two segments), and different segments are provided to corresponding CAMs 1, each storing a different segment (e.g., from bits a1 to a4, and from bits a5 to a8 of word A) of the same set of stored words (from A to D). A logical AND is then applied to the outputs of the two arrays for a given input word to determine if there is an overall match. This allows parallel search operations to be performed for longer word lengths distributed over different arrays.

[0058] CAMs implementing the present disclosure can be advantageously applied in various applications other than routing, and the outputs of these CAMs can be appropriately processed for the applications in question. As an example, an embodiment can be adapted to perform Hamming difference calculations for multiple input bit strings simultaneously. In this application, for each column, the CAM detector can detect the intensity of light having any one of the wavelength pairs encoding a given input bit string. The intensity then provides a measure of the number of bits by which the input bit string differs from the stored bit string. Various other applications including cache memories, decision trees, associative search operations of neural networks, and data mining applications can also benefit from CAMs implementing the present disclosure. In general, these CAMs can be used in any application where multiple first bit strings need to be compared with each of multiple second bit strings to determine the comparison result. The comparison can be performed simultaneously by: storing each second bit string in a CAM implementing the present disclosure so that successive bits are stored in filter devices located at successive intersections of column waveguides and row waveguides; providing multiple first bit strings as input bit strings to a CAM encoder; and determining the required comparison result based on light detection in the CAM detector.

[0059] It can be seen that the above-described embodiments provide a compact and efficient architecture for an ultra-fast, energy-efficient CAM. Of course, it should be understood that various changes and modifications may be made to the exemplary embodiments described. As an example, substitutions / modifications described with respect to one embodiment may be appropriately applied to other embodiments. In general, where features are described herein with reference to a CAM implementing the present disclosure, corresponding features may be provided in a memory device / method using such a CAM, and vice versa.

[0060] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A photon content addressable memory, comprising: A photonic crossbar array including a plurality of row waveguides and column waveguides; a plurality of photon filter devices, each of the plurality of photon filter devices being located at a respective intersection of the row waveguide and the column waveguide for selectively coupling light from the row waveguide to the column waveguide at the intersection, wherein each filter device is selectively programmable to be in a first state and a second state representing a respective stored bit value, and each filter device is operable in the first state to filter out light in any of a first plurality of optical states from light coupled to the column waveguide, and is operable in the second state to filter out light in any of a second, different plurality of optical states from light coupled to the column waveguide; an encoder for encoding a plurality of input bit strings into optical signals such that bit values ​​in different bit strings are encoded using optical signals in different pairs of optical states, each pair comprising one state from each of the first and second pluralities, and the encoder for simultaneously providing an optical signal corresponding to each bit position in the bit string to a respective traveling waveguide of the array; as well as A detector is provided for detecting light in each column waveguide in any of the optical states to thereby identify any mismatch between each input bit string and the bit value stored in the filter device coupling the light into the waveguide.

2. A content addressable memory according to claim 1, wherein the encoder is adapted to encode an input bit string comprising bit values ​​0, 1 and X, wherein X indicates a don't care bit, so that the bit values ​​0 and 1 in the bit string are encoded using the optical signal in the optical state pair, and the bit value X is encoded as a zero signal.

3. The content addressable memory of claim 1, wherein the optical state corresponds to one of a corresponding wavelength of light and a corresponding polarization state of light.

4. The content addressable memory of claim 1, wherein each filter device comprises a directional coupler for coupling light from a row waveguide to a column waveguide, and a programmable filter for operating in a first programmable state and a second programmable state.

5. A content addressable memory according to claim 4, wherein the directional coupler is adapted to distribute the optical power equally between the column waveguides of the array.

6. A content addressable memory according to claim 4, wherein the optical states correspond to corresponding wavelengths of light, and the programmable filter includes a frequency filter for filtering out light having any wavelength in a first plurality of wavelengths in a first programmable state and filtering out light having any wavelength in a second plurality of wavelengths in a second programmable state.

7. The content addressable memory of claim 6, wherein the frequency filter comprises a first ring resonator and a second ring resonator operable to filter out the light in a first programmable state and a second programmable state, respectively.

8. The content addressable memory of claim 7, wherein the ring resonator comprises corresponding memory elements programmable to tune the ring resonator to operate in the first programmable state and the second programmable state.

9. A content addressable memory as claimed in claim 8, wherein each memory element comprises a phase change memory element.

10. The content addressable memory according to claim 1, wherein: an encoder operable to, for each input bit string, encode at least one additional logic bit associated with the bit string using at least one additional optical signal in at least one additional optical state different from a state in said first plurality of states and a second plurality of states, and operable to simultaneously provide said additional optical signals for corresponding logic bits of said bit string to the traveling waveguides of the array; The memory comprises a plurality of programmable logic devices arranged to selectively couple additional optical signals to the column waveguides; as well as The detector is operable to detect additional optical signals in each column waveguide.

11. A content addressable memory according to claim 10, wherein the at least one additional optical state is different for different input bit strings.

12. The content addressable memory according to claim 10, wherein: The first plurality of optical states and the second plurality of optical states correspond to respective wavelengths of light; The additional optical states correspond to additional wavelengths of light; as well as Each programmable logic device includes a directional coupler for coupling light from the row waveguide to the column waveguide, and a programmable frequency filter for selectively filtering light having the additional wavelength from the light coupled to the column waveguide.

13. The content addressable memory of claim 12, wherein the frequency filter comprises a ring resonator and a memory element, the memory element being programmable to tune the ring resonator to filter out light having the additional wavelength.

14. A content addressable memory according to claim 1, wherein the detector is adapted to generate an output indicating, for each column waveguide, whether each input bit string matches a bit value stored in a filter device coupling light into that waveguide.

15. The content addressable memory of claim 1, wherein the detector is coupled to logic for performing a processing operation based on detection of light in any of the optical states by the detector.

16. The content addressable memory according to claim 1, comprising an optical amplifier provided between each column waveguide and the detector for amplifying light in the column waveguide.

17. The content addressable memory of claim 1, wherein the encoder is adapted to scale the amplitude of the optical signal provided to the traveling waveguide.

18. A memory device comprising a plurality of content addressable memories as claimed in claim 1, and a memory controller for providing input bit strings to the plurality of memories in parallel.

19. A network switching device, comprising: a plurality of input ports for receiving input data packets and a plurality of output ports for outputting data packets; a switch structure for forwarding input data packets to output ports based on corresponding address bit strings in the input packets; as well as A switch controller comprising at least one content addressable memory as claimed in claim 1 for storing said address bit string in its filter device, wherein the switch controller is adapted to provide the address bit strings of a plurality of data packets as input bit strings to said at least one content addressable memory, and is adapted to determine output ports for forwarding those data packets based on a match between the input bit strings and the stored address bit strings.

20. A method for simultaneously comparing a plurality of first bit strings with each of a plurality of second bit strings, the method comprising: storing each second bit string in a content addressable memory as claimed in claim 1 such that successive bits are stored in filter devices located at successive intersections of a column waveguide and a row waveguide; providing the plurality of first bit strings as the input bit strings to an encoder of the memory; as well as The comparison result is determined based on the detection of light in any of the optical states in a detector of the memory.

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