Amplification circuit, comparator, and solid-state imaging device

Abstract

[Problem] To provide an amplifier circuit capable of suppressing RTS noise, a comparator, and a solid-state imaging device. [Solution] An amplifier circuit according to the present invention comprises: an active load; and a plurality of input transistors electrically connected to the active load, in which gates of the plurality of input transistors are electrically connected to each other, and the plurality of input transistors include two or more input transistors connected to each other in series.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, a comparator and a solid-state imaging device. Background Art

[0002] Countermeasures for random vertical stripe noise generated in image sensors and the like have been conventionally studied. Random vertical stripe noise is stripe noise generated in an image. In addition, random vertical stripe noise is caused by RTS noise (also called random telegraph signal noise) of input transistors in comparators and the like.

[0003] A technology for suppressing RTS noise in a circuit of an image sensor including a comparator has been proposed. The signal processing device includes a short-circuit section capable of short-circuiting a gate of an amplifying transistor to a potential that reduces a voltage between the gate and a source. Citation list Patent Literature

[0004] Patent Document 1: Japanese Patent Application No. 2016-545441 Summary of the invention Technical problem to be solved by the invention

[0005] Since the signal processing device includes a short-circuit portion in the circuit, it is not suitable for miniaturization of the design area and low power consumption.

[0006] Therefore, the present invention provides an amplifier circuit, a comparator, and a solid-state imaging device capable of suppressing RTS noise. Solutions to technical problems

[0007] The amplifier circuit according to the first aspect of the present invention includes an active load and a plurality of input transistors electrically connected to the active load, wherein the gates of the plurality of input transistors are electrically connected to each other, and the plurality of input transistors include two or more input transistors connected in series to each other. Therefore, the input transistor on the active load side operates in a saturation region, and the input transistor on the ground side operates in a linear region. In the linear region, since carriers also pass through a position away from the oxide film interface, the probability of trapping or detrapping is reduced, and RTS noise is improved.

[0008] Furthermore, in the first aspect, the two or more input transistors may include a first input transistor and a second input transistor, the drain of the second input transistor being electrically connected to the source of the first input transistor. Therefore, the input transistor on the active load side operates in a saturation region, and the input transistor on the ground side operates in a linear region. In the linear region, since carriers also pass through a position away from the oxide film interface, the probability of capture or decapture is reduced, and RTS noise is improved.

[0009] In addition, in the first aspect, the two or more input transistors may further include a third input transistor, the drain of which is electrically connected to the source of the second input transistor. Therefore, the input transistor on the active load side operates in a saturation region, and the input transistor on the ground side operates in a linear region. In the linear region, since carriers also pass through a position away from the oxide film interface, the probability of capture or decapture is reduced, and RTS noise is improved.

[0010] Furthermore, in the first aspect, the active region used as the source of the first input transistor may be an active region different from the active region used as the drain of the second input transistor. Therefore, the input transistor on the active load side operates in the saturation region, and the input transistor on the ground side operates in the linear region. In the linear region, since carriers also pass through a position away from the oxide film interface, the probability of capture or decapture is reduced, and RTS noise is improved.

[0011] In addition, in the first aspect, the active region used as the source of the first input transistor can be the same active region as the active region used as the drain of the second input transistor. Therefore, the design area of ​​the amplifier circuit is reduced, and the transconductance characteristics can be improved. In addition, in a solid-state imaging device using an amplifier circuit, high resolution based on further miniaturization can be achieved, or sensor characteristics can be improved while maintaining the number of pixels.

[0012] In addition, in the first aspect, the plurality of input transistors may include a first group of two or more input transistors connected in series with each other and a second group of two or more input transistors connected in series with each other, and all or part of the first group of two or more input transistors and all or part of the second group of two or more input transistors may be connected in parallel with each other. This increases the gate width of the input transistor, thereby improving the transconductance characteristics of the input transistor. Therefore, the thermal noise characteristics of the transistor are improved, and the RTS noise is improved.

[0013] In addition, in the first aspect, each of the plurality of input transistors may have a planar structure or a fin structure. Therefore, the controllability of the gate of the input transistor 3 is improved, and the transconductance characteristic is improved. Therefore, the thermal noise characteristic of the input transistor is improved, and the RTS noise is improved. In addition, by adopting a fin type, the influence of the increase of the voltage threshold due to the substrate bias effect is suppressed, which improves the RTS noise.

[0014] Furthermore, in the first aspect, the two or more input transistors may include a first input transistor and a second input transistor, the gate length of the second input transistor being different from the gate length of the first input transistor. Therefore, by reducing the area of ​​the input transistor in the saturation region connected to the active load, the probability of capture or decapture becomes lower than the case where the gate lengths of the input transistors connected in series to each other are equally divided. Therefore, the RTS noise of the amplifier circuit is improved.

[0015] Furthermore, in the first aspect, the gate length of the first input transistor may be the shortest among the two or more input transistors, the drain of the first input transistor may be electrically connected to the active load and the first power supply, and the source of the second input transistor may be electrically connected to the second power supply. Therefore, by reducing the area of ​​the input transistor in the saturation region connected to the active load, the probability of capture or decapture becomes lower than the case where the gate lengths of the input transistors connected in series to each other are equally divided. Therefore, the RTS noise of the amplifier circuit is improved.

[0016] Furthermore, in the first aspect, the two or more input transistors may be NMOS and the voltage of the first power supply may be higher than the voltage of the second power supply, or the two or more input transistors may be PMOS and the voltage of the second power supply may be higher than the voltage of the first power supply. Therefore, by reducing the area of ​​the input transistors in the saturation region connected to the active load in the amplifier circuit, the probability of capture or decapture becomes lower than the case where the gate lengths of the input transistors connected in series to each other are equally divided. Therefore, the RTS noise of the amplifier circuit is improved.

[0017] Furthermore, in the first aspect, a voltage threshold of at least one of the two or more input transistors may be different from a voltage threshold of the other of the two or more input transistors. Therefore, the amplifier circuit improves RTS noise by using input transistors with different voltage thresholds.

[0018] The comparator according to the second aspect of the present invention includes: a first amplifier circuit to which a reference signal is input, a second amplifier circuit to which a comparison signal is input, and a tail portion for controlling a tail current, the tail portion being electrically connected to the first amplifier circuit and the second amplifier circuit, wherein each of the first amplifier circuit and the second amplifier circuit includes: an active load and a plurality of input transistors electrically connected to the active load, the gates of the plurality of input transistors being electrically connected to each other, and the plurality of input transistors may include more than two input transistors connected in series to each other. Therefore, in the comparator, the signal / noise ratio (S / N ratio) is improved as the RTS noise is improved. Therefore, the random vertical stripe noise is improved.

[0019] In addition, in the second aspect, the tail portion may include a plurality of transistors electrically connected to the first amplifying circuit and the second amplifying circuit, the gates of the plurality of transistors of the tail portion may be electrically connected to each other, and the plurality of transistors of the tail portion may include two or more transistors connected in series to each other. Therefore, the comparator can reduce the RTS noise generated in the tail current control transistor. The improvement of the signal-to-noise ratio (S / N ratio) accompanying the reduction of the RTS noise leads to the realization of high image quality in a solid-state imaging device or the like using a comparator.

[0020] A solid-state imaging device according to a third aspect of the present invention includes: a pixel array, in which a plurality of pixels each including a photoelectric conversion unit is arranged in a matrix form; and an AD conversion unit, which converts a pixel signal output from the pixel of the pixel array from an analog signal to a digital signal, the AD conversion unit includes a comparator, wherein the comparator includes: a first amplifier circuit to which a reference signal is input, a second amplifier circuit to which the analog signal is input as a comparison signal, and a tail portion for controlling a tail current, the tail portion being electrically connected to the first amplifier circuit and the second amplifier circuit, each of the first amplifier circuit and the second amplifier circuit including an active load; and a plurality of input transistors electrically connected to the active load, the gates of the plurality of input transistors being electrically connected to each other, and the plurality of input transistors including two or more input transistors connected in series to each other. Therefore, in the solid-state imaging device, random vertical stripe noise is improved, and the S / N ratio is improved. In addition, it is possible to improve sensor characteristics, such as achieving high resolution (miniaturization) without degrading characteristics.

[0021] In addition, in the third aspect, the present invention may include: a first substrate provided with the photoelectric conversion unit and the pixel transistor and a second substrate provided with the comparator. Therefore, the stacked solid-state imaging device can reduce the RTS noise generated by the comparator. The S / N ratio is improved with the reduction of the RTS noise, which leads to high image quality in the stacked solid-state imaging device.

[0022] In addition, in the third aspect, it may include: a first substrate provided with the photoelectric conversion unit and a second substrate provided with a pixel transistor and the comparator, and the first substrate and the second substrate may be stacked on each other with an insulating layer interposed therebetween. Therefore, the 3D stacked solid-state imaging device can reduce the RTS noise generated by the comparator. The S / N ratio is improved with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device.

[0023] In addition, in the third aspect, the first substrate may be disposed on the second substrate. Therefore, the 3D stacked solid-state imaging device can reduce the RTS noise generated by the comparator. The S / N ratio is improved along with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device.

[0024] In addition, in the third aspect, it may include: a first substrate provided with the photoelectric conversion unit, a second substrate provided with pixel transistors, and a third substrate provided with the comparator, and the first substrate and the second substrate may be stacked on each other with an insulating layer interposed therebetween. Therefore, the 3D stacked solid-state imaging device can reduce the RTS noise generated by the comparator. The S / N ratio is improved with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device.

[0025] In addition, in the third aspect, the first substrate may be disposed on the second substrate, and the second substrate may be disposed on the third substrate. Therefore, the 3D stacked solid-state imaging device can reduce the RTS noise generated by the comparator. The S / N ratio is improved with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device.

[0026] Furthermore, in the third aspect, the solid-state imaging device may be provided in an electronic device that receives data output from the solid-state imaging device. Therefore, random vertical stripe noise is improved, and high resolution can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is an example of the amplifier circuit according to the first embodiment. Figure 2 is another example of the amplifier circuit according to the first embodiment. Figure 3 is another example of the amplifier circuit according to the first embodiment. Figure 4 is an example of an amplifier circuit according to the second embodiment. Figure 5 is a cross-sectional view of an amplifier circuit according to a second embodiment. Figure 6 is another example of the amplifier circuit according to the second embodiment. Figure 7 is an example of an amplifier circuit according to the third embodiment. Figure 8 is an example of an amplifier circuit according to the fourth embodiment. Fig. 9 is another example of the amplifier circuit according to the fourth embodiment. Fig.10 is an example of a comparator according to the fifth embodiment. Fig.11 is an example of a solid-state imaging device according to the sixth embodiment. Fig.12 is an example of a solid-state imaging device according to the seventh embodiment. Fig.13 is an example of a solid-state imaging device according to the eighth embodiment. Fig.14 is a cross-sectional view showing a structure of a solid-state imaging device according to a ninth embodiment. Fig.15 is a circuit diagram showing a configuration of a solid-state imaging device according to a ninth embodiment. Fig.16 is a block diagram showing an example of a functional configuration of a solid-state imaging device according to a tenth embodiment. Fig.17 It shows Fig.16 A schematic plan view of the schematic configuration of the imaging device shown. Fig.18 It is along Fig.17 Schematic diagram of the cross-sectional structure taken along line III-III' in FIG. Fig.19 yes Fig.16 The equivalent circuit diagram of the pixel sharing unit is shown. Fig. 20 is a diagram showing an example of a connection pattern between a plurality of pixel sharing units and a plurality of vertical signal lines. Fig.21 It shows Fig.18 A schematic cross-sectional view showing an example of a specific configuration of the imaging device shown. Fig.22A It shows Fig.21 A schematic diagram showing an example of a planar configuration of a main portion of the first substrate is shown. Fig. 22B is a diagram showing the pad portion and Fig.22A A schematic diagram of the planar structure of the main part of the first substrate is shown. Fig.23 It shows Fig.21 A schematic diagram showing an example of a planar structure of the second substrate (semiconductor layer) is shown. Fig.24 is shown with Fig.21 FIG. 1 is a schematic diagram showing an example of a planar configuration of a main portion of a pixel circuit and a first substrate together with a first wiring layer. Fig.25 It shows Fig.21 Schematic diagram of an example of a planar configuration of a first wiring layer and a second wiring layer shown. Fig.26 It shows Fig.21 Schematic diagram of an example of a planar configuration of a second wiring layer and a third wiring layer shown. Fig. 27 It shows Fig.21 Schematic diagram of an example of a planar configuration of a third wiring layer and a fourth wiring layer shown. Fig.28 It is used to illustrate Fig.18 A schematic diagram of the path of the input signal of the camera device is shown. Fig.29 It is used to illustrate Fig.18 Schematic diagram of the signal path of the pixel signal of the camera device shown. Fig.30 It shows Fig.23 Schematic diagram of a modification of the planar structure of the second substrate (semiconductor layer) shown. Fig.31 is a diagram showing the main parts of the first wiring layer and the first substrate and Fig.30 Schematic diagram of the planar structure of the pixel circuit shown. Fig.32 is a diagram showing the second wiring layer and Fig.31 Schematic diagram of an example of a planar configuration of a first wiring layer is shown. Fig.33 is a diagram showing the third wiring layer and Fig.32 Schematic diagram of an example of a planar configuration of a second wiring layer shown. Fig.34 is shown in the fourth wiring layer and Fig.33 Schematic diagram of an example of a planar configuration of a third wiring layer shown. Fig.35 It shows Fig.22A Schematic diagram of a modified example of the planar structure of the first substrate shown. Fig.36 is shown stacked in Fig.35 A schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate is shown. Fig.37 is a diagram showing the first wiring layer and Fig.36 A schematic diagram of an example of a planar configuration of a pixel circuit is shown. Fig.38 is a diagram showing the second wiring layer and Fig.37 Schematic diagram of an example of a planar configuration of a first wiring layer is shown. Fig.39 is a diagram showing the third wiring layer and Fig.38 Schematic diagram of an example of a planar configuration of a second wiring layer shown. Fig.40 is a diagram showing the fourth wiring layer and Fig.39 Schematic diagram of an example of a planar configuration of a third wiring layer shown. Fig.41 It shows Fig.35 FIG. 4 is a schematic diagram of another example of the planar structure of the first substrate shown. Fig.42 It is shown that the stacking Fig.41 A schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate is shown. Fig.43 is a diagram showing the first wiring layer and Fig.42 A schematic diagram of an example of a planar configuration of a pixel circuit is shown. Fig.44 is a diagram showing the second wiring layer and Fig.43 Schematic diagram of an example of a planar configuration of a first wiring layer is shown. Fig.45 is shown as the third wiring layer and Fig.44 Schematic diagram of an example of a planar configuration of a second wiring layer shown. Fig.46 is a diagram showing the fourth wiring layer and Fig.45 Schematic diagram of an example of a planar configuration of a third wiring layer shown. Fig.47 yes Fig.18 A schematic cross-sectional view of another example of the imaging device shown. Fig.48 It is used to illustrate Fig.47 A schematic diagram of the path of the input signal of the camera device is shown. Fig.49 It is used to illustrate Fig.47 Schematic diagram of the signal path of the pixel signal of the camera device shown. Fig.50 yes Fig.21 A schematic cross-sectional view of another example of the imaging device shown. Fig.51 yes Fig.19 FIG. 1 is a diagram of another example of an equivalent circuit shown. Fig.52It shows Fig.22A Schematic plan view of another example of a pixel isolation portion shown in FIG. Fig.53 : is a diagram showing an example of a schematic configuration of an imaging system including an imaging device according to one of the above-described embodiment and its modified examples. Fig.54 It shows Fig.53 A diagram showing an example of an imaging process of the imaging system shown. Fig.55 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig.56 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging section. Fig.57 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. Fig.58 is a block diagram showing an example of the functional configuration of a camera and a CCU. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0029] (First Implementation Method) Figure 1 is an example of the amplifier circuit according to the first embodiment.

[0030] Figure 1 A is a circuit diagram showing a circuit configuration of an amplifier circuit, and Figure 1 B is a plan view showing the planar structure of the amplifier circuit.

[0031] Figure 1 B shows an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other. The X-direction and the Y-direction correspond to the lateral direction (horizontal direction), and the Z-direction corresponds to the longitudinal direction (vertical direction). In addition, the +Z direction corresponds to the upward direction, and the -Z direction corresponds to the downward direction. Note that the -Z direction may be strictly consistent with the gravity direction, but does not necessarily have to be strictly consistent with the gravity direction.

[0032] Figure 1 The amplifier circuit 2 in A is a source mounted amplifier circuit 2 including an active load 4. The amplifier circuit 2 includes a PMOS active load 4 and a plurality of NMOS input transistors 3. Figure 1 B is Figure 1 A is a plan view of a portion corresponding to input transistor 3 in the circuit diagram of FIG. Figure 1In FIG. 1B, the three input transistors 3 are referred to as input transistor 3a, input transistor 3b, and input transistor 3c from top to bottom. In the following description, input transistor 3a is an example of a first input transistor of the present invention, input transistor 3b is an example of a second input transistor of the present invention, and input transistor 3c is an example of a third input transistor of the present invention.

[0033] For example, in a solid-state imaging device, the amplifier circuit 2 is used not only to amplify the pixel signal read from the pixel supply unit, but also for the comparator of the AD converter (ADC). The comparator includes, for example, a differential pair circuit and a tail current control transistor (tail) electrically connected to the differential pair circuit. The amplifier circuit 2 is, for example, a differential pair circuit, and is used for amplification of a reference signal and amplification of a comparison signal. The reference signal amplifier circuit is an example of a first amplifier circuit of the present invention, and the comparison signal amplifier circuit is an example of a second amplifier circuit of the present invention.

[0034] exist Figure 1 In the amplifier circuit 2 of A, the input transistors 3 are arranged in different active regions, and the sources and drains are alternately connected in series with each other. Figure 1 As shown in FIG. 1B, the active region of the source 82 used as the input transistor 3a is set in a region different from the active region of the drain 81 used as the input transistor 3b, and these active regions are electrically connected to each other through a wiring 86. The active region of the source 82 used as the input transistor 3b is set in a region different from the active region of the drain 81 used as the input transistor 3c, and these active regions are electrically connected to each other through another wiring 86. In addition, the gates 80 of the input transistors 3 are connected to each other, and are electrically connected to each other through, for example, another wiring 86. In addition, as shown in FIG. Figure 1 As shown in FIG. 8B , the drain 81 , the gate 80 , and the source 82 of each of the first to third input transistors 3 a to 3 c are arranged linearly in the Y-axis direction.

[0035] The number of these input transistors 3 is not limited to three, and any number of input transistors 3 can be connected in series with each other. For example, in the case of adding an input transistor 3d, it is conceivable that the source 82 of the input transistor 3c and the drain of the input transistor 3d are electrically connected in series with each other, and the gates 80 of the input transistors 3a to 3d are electrically connected to each other. Alternatively, the drain 81 of the input transistor 3a and the source of the input transistor 3d can be electrically connected in series with each other, and the gates 80 of the input transistors 3a to 3d can be electrically connected to each other. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and only a structure including more than two input transistors 3 arranged in series with each other is required.

[0036] according to Figure 1In the configuration, the input transistor 3 on the active load 4 side (in this example, the input transistor 3a) operates in the saturation region, and the input transistor 3 on the ground side (in this example, the second input transistor 3c) operates in the linear region. In the linear region, since carriers also pass through a position away from the oxide film interface, the probability of capture or decapture is reduced, and the RTS noise is improved.

[0037] In addition, by using Figure 1 The signal-to-noise ratio (S / N ratio) of the comparator of the amplifier circuit 2 is improved as the RTS noise is improved. Therefore, the random vertical stripe noise is improved.

[0038] In addition, by using a solid-state imaging device including the above-mentioned comparator, the solid-state imaging device also improves random vertical stripe noise and S / N ratio. In addition, it is possible to improve sensor characteristics such as achieving high resolution (miniaturization) without deteriorating characteristics.

[0039] Furthermore, by using the above-described solid-state imaging device in electronic equipment, random vertical stripe noise is improved and high resolution can be achieved.

[0040] Figure 2 is another example of the amplifier circuit 2 according to the first embodiment.

[0041] exist Figure 2 In the example of FIG. 1 , the three input transistors 3 are referred to as input transistor 3a, input transistor 3b, and input transistor 3c in order from the left. Figure 2 In the amplifier circuit 2, Figure 1 Similarly, the three input transistors 3 are arranged in different active regions, and the drains 81 and the sources 82 are alternately connected in series. For example, the active region of the drain 81 used as the input transistor 3a is arranged in a region different from the active region of the source 82 used as the input transistor 3b, and these active regions are electrically connected to each other through the wiring 86. The active region of the drain 81 used as the input transistor 3b is arranged in a region different from the active region of the source 82 used as the input transistor 3c, and these active regions are electrically connected to each other through another wiring.

[0042] In addition, Figure 1 Unlike the structure in FIG. 1 , the drain 81 and the source 82 of the input transistor 3 are connected in series with each other in the X-axis direction. In addition, the gates 80 of the plurality of input transistors 3 are connected to each other. For example, the gates are electrically connected to each other through another wiring 86. In this structure, the gates 80 of the input transistors 3 are arranged in a straight line in the X-axis direction and can be composed of one polysilicon or metal gate.

[0043] In addition, the number of these input transistors 3 is not limited to three, and any number of input transistors 3 can be connected to each other. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and only a structure including more than two input transistors 3 arranged in series is required.

[0044] Figure 3 is another example of the amplifier circuit according to the first embodiment.

[0045] Figure 3 A is the circuit diagram of comparator 5, and Figure 3 B is a plan view of a portion corresponding to the input transistor 3 in the reference signal amplifying circuit 8 and the comparison signal amplifying circuit 9 in the circuit diagram.

[0046] like Figure 3 As shown in B of FIG. 1 , in this example, three input transistors 3 in the reference signal amplifying circuit 8 of the comparator 5 and three input transistors 3 in the comparison signal amplifying circuit 9 are arranged in a staggered manner. Here, the configuration of the reference signal amplifying circuit 8 will be described. In this example, the three input transistors 3 are referred to as input transistor 3a, input transistor 3b, and input transistor 3c in order from top to bottom.

[0047] In the reference signal amplifying circuit 8, three transistors are arranged in different active regions in a staggered manner, and the sources 82 and drains 81 of the plurality of input transistors 3 are alternately connected to each other. Figure 3 As shown in FIG. 1B , the active regions of the sources 82 used as the input transistors 3a are arranged in a staggered manner in a region different from the active regions of the drains 81 used as the input transistors 3b, and these active regions are electrically connected to each other through wiring 86. The active regions of the sources 82 used as the input transistors 3b are arranged in a staggered manner in a region different from the active regions of the drains 81 used as the input transistors 3c, and these active regions are electrically connected to each other through another wiring 86. In addition, the gates 80 of the input transistors 3 are electrically connected to each other through another wiring 86.

[0048] In addition, the number of these input transistors 3 is not limited to three, and any number of input transistors 3 can be connected to each other. In addition, in the amplifier circuit 2, it is not necessary for the drains 81 and sources 82 of all input transistors 3 to be arranged alternately, and it is only necessary for the amplifier circuit 2 to have a structure in which the drains 81 and sources 82 of more than two input transistors 3 are arranged alternately.

[0049] use Figure 3 The structure can improve the freedom of circuit design layout. In addition, since the matching characteristics of each input transistor 3 can be improved, the signal-to-noise ratio of the comparator 5 is improved.

[0050] (Second Implementation Method) Figure 4 is an example of an amplifier circuit according to the second embodiment.

[0051] Figure 4 is with Figure 1 A plan view of a portion of a similar amplifier circuit 2 corresponding to the input transistor 3. In this example, the three input transistors 3 are referred to as input transistor 3a, input transistor 3b, and input transistor 3c in order from top to bottom. Figure 4 In the amplifier circuit 2, a plurality of input transistors 3 are connected in series to each other through the same active region 87. For example, the active region 87 used as the source of the input transistor 3a and the active region 87 used as the drain of the input transistor 3b are the same active region 87. The active region 87 used as the source of the input transistor 3b and the active region 87 used as the drain of the input transistor 3c are the same active region 87. In addition, the gates 80 of the plurality of input transistors 3 are connected to each other. For example, the gates are electrically connected to each other through another wiring 86.

[0052] In addition, the number of these input transistors 3 is not limited to three, and any number of input transistors 3 can be connected to each other. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and it is only necessary to include a structure in which more than two input transistors 3 are arranged in series.

[0053] Figure 5 is a cross-sectional view of an amplifier circuit according to a second embodiment.

[0054] Figure 5 Shows Figure 4 A-A' cross-sectional view. The gate electrode 90 of each input transistor 3 is formed on the substrate 94 via the gate insulating film 91, and the sidewall insulating film 92 of each input transistor 2 is formed on the side surface of the gate electrode 90. The interlayer insulating film 93 is formed on the substrate 94 in a manner covering each input transistor 3. In addition, each contact plug 89 is formed in the interlayer insulating film 93 and is formed on one of the gate electrodes 90 or one of the parts of the active region 87. Figure 5 As shown, the input transistors 3a to 3c are connected to each other through the same active region 87. In addition, the gate electrodes 90 of the input transistors 3a to 3c are electrically connected to each other through the wiring 86 formed on the contact plug 89. Figure 5 Three wiring lines 86 formed in the same wiring layer are shown.

[0055] use Figure 5 The design area of ​​the amplifier circuit 2 is smaller than Figure 1In addition, in a solid-state imaging device or the like using the amplifier circuit 2, a high resolution based on further miniaturization can be achieved, or sensor characteristics can be improved while maintaining the number of pixels.

[0056] Figure 6 is another example of the amplifier circuit according to the second embodiment.

[0057] Figure 6 The input transistors 3 shown in the plan view of FIG. 1 include a first group of three input transistors 3 connected in series with each other and a second group of three input transistors 3 connected in series with each other. In this example, Figure 6 The input transistors 3 in the left group of FIG. 1 are referred to as input transistors of the first group, and the input transistors 3 in the right group of FIG. 1 are referred to as input transistors of the second group. Figure 5 Similarly, the three input transistors 3 of the first group and the second group are connected in series to each other through the same active region 87. In addition, a part of the two or more input transistors 3 of the first group and a part of the two or more input transistors 3 of the second group are connected in parallel to each other. The three input transistors 3 of the first group are referred to as input transistor 3a, input transistor 3b, and input transistor 3c in order from top to bottom. In addition, the three input transistors 3 of the second group are referred to as input transistor 3a', input transistor 3b', and input transistor 3c' in order from top to bottom.

[0058] The number of the first group and the second group of input transistors 3 is not limited to three, and any number of input transistors 3 can be connected to each other. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and it is only necessary to include a structure in which more than two input transistors 3 are arranged in series with each other. In addition, part or all of the first group of input transistors and the second group of input transistors, that is, any number of the first group of input transistors and the second group of input transistors can be connected in parallel to each other.

[0059] use Figure 6 The structure of the input transistor 3 increases the gate width of the input transistor 3, thereby improving the transconductance characteristics of the input transistor 3. Therefore, the thermal noise characteristics of the transistor are improved, and the RTS noise is improved.

[0060] (Third Implementation Option) Figure 7 is an example of an amplifier circuit according to the third embodiment.

[0061] Figure 7 A is a perspective view of a portion of the amplifier circuit 2 according to the present embodiment corresponding to the input transistor 3, and Figure 7 B is a plan view of a portion corresponding to the input transistor 3 .

[0062] exist Figure 7 In B, the three input transistors 3 are referred to as input transistor 3a, input transistor 3b and input transistor 3c from top to bottom. Figure 7 In B, Figure 4 Similarly, the three input transistors 3 are connected in series to each other through the same active region 87. For example, the active region 87 used as the source of the input transistor 3a and the active region 87 used as the drain of the input transistor 3b are the same active region 87. In addition, the gates (gate electrodes) 80 of the plurality of input transistors 3 are electrically connected to each other. For example, the gates are electrically connected to each other through another wiring 86. The respective amplifier circuits 2 according to the first and second embodiments have a planar structure, while the amplifier circuit 2 according to the third embodiment has a planar structure as shown in FIG. Figure 7 The fin structure shown in A. Figure 7 As shown in FIG. 8A , in this example, an insulating film 84 is provided on a silicon substrate 85 , and a drain electrode (drain region) 81 and a source electrode (source region) 82 are provided below a gate electrode 80 via a gate insulating film 83 .

[0063] In addition, the number of these input transistors 3 is not limited to three, and any number of input transistors 3 can be connected to each other. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and it is only necessary to include the following structure: wherein more than two input transistors 3 are arranged in series with each other.

[0064] use Figure 7 The structure improves the controllability of the gate 80 of the input transistor 3, thereby improving the transconductance characteristics. Therefore, the thermal noise characteristics of the input transistor 3 are improved, and the RTS noise is improved. In addition, by adopting the fin type, the influence of the increase in the voltage threshold due to the substrate bias effect is suppressed, thereby improving the RTS noise.

[0065] (Fourth Implementation Scheme) Figure 8 is an example of an amplifier circuit according to the fourth embodiment.

[0066] Figure 8 A is the circuit diagram of amplifier circuit 2, and Figure 8 B is a plan view of a portion corresponding to the input transistor 3 in the circuit diagram.

[0067] exist Figure 8 In the example of B, the two input transistors 3 are referred to as input transistor 3a and input transistor 3b from top to bottom. Figure 8As shown in B, the gate lengths of the input transistor 3a and the input transistor 3b are different. In this example, the gate length of the input transistor 3a connected to the active load 4 is the shortest. In addition, the source 82 of the input transistor 3a and the drain 81 of the input transistor 3b are connected in series with each other. In addition, the gates 80 of the input transistors 3 are electrically connected to each other. For example, the gates 80 are electrically connected to each other through the wiring 86. In addition, as Figure 8 As shown in FIG. 1B , the drain 81, gate 80 and source 82 of the input transistors 3a and 3b are arranged in a straight line in the Y-axis direction. In addition, the drain 81 of the input transistor 3a is connected to the first power supply 6a via the active load 4. The source 82 of the input transistor 3b is connected to the second power supply 6b (ground in this example). In addition, the source 82 of the input transistor 3b can be connected to the second power supply 6b via other circuits such as a tail current control transistor.

[0068] In addition, the number of these input transistors 3 is not limited to two, and any number of input transistors 3 can be connected to each other. In addition, in the case of using more than three input transistors 3, more than three gate lengths can be included, and the transistor with the shortest gate length can be connected to the active load 4. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and it is only necessary to include a structure in which more than two input transistors 3 are arranged in series with each other.

[0069] In addition, regarding the relationship between each input transistor 3 and the power supply, the amplifier circuit 2 may have a configuration in which the input transistor 3a and the input transistor 3b are NMOS, and the voltage of the first power supply 6a is higher than the voltage of the second power supply 6b. Alternatively, the amplifier circuit 2 may have a configuration in which the input transistor 3a and the input transistor 3b are PMOS, and the voltage of the second power supply 6b is higher than the voltage of the first power supply 6a.

[0070] use Figure 8 In the configuration, since the area of ​​the input transistor 3 in the saturation region connected to the active load 4 is reduced in the amplifier circuit 2, the probability of capture or decapture becomes lower than the case where the gate lengths of the input transistors 3 connected in series to each other are equally divided. Therefore, the RTS noise of the amplifier circuit 2 is improved. In addition, since the amplifier circuit 2 uses the input transistors 3 having different voltage thresholds, the RTS noise is improved.

[0071] Generally speaking, as the value of the voltage threshold becomes smaller, the RTS noise tends to decrease. Therefore, even in the case where the gate length of the input transistor 3 is designed to be the same in this example, if a transistor with a small voltage threshold is used as the input transistor 3, the RTS noise will be improved. On the other hand, from the perspective of the element reliability of the transistor, as the value of the voltage threshold becomes smaller, the shortest gate length that can be designed in the design rule generally tends to be larger. Although in this example, since the RTS noise improves as the gate area of ​​the input transistor 3 in the saturation region connected to the active load 4 becomes smaller, the total gate length of the input transistor 3 is the same as when a single input transistor 3 is used for the amplifier circuit 2, the RTS noise is further improved when a transistor with a high voltage threshold that can be designed to have a shorter gate length is used as the input transistor 3 in the saturation region connected to the active load 4 and a transistor with a smaller voltage threshold is used as the input transistor 3 in the linear region.

[0072] Fig. 9 is another example of the amplifier circuit according to the fourth embodiment.

[0073] Fig. 9 A is a plan view of a portion of the amplifier circuit 2 corresponding to the input transistor 3, and Fig. 9 B is its AA' cross-sectional view.

[0074] exist Fig. 9 In the example of A of FIG. 1 , the two input transistors 3 are referred to as input transistor 3a and input transistor 3b from top to bottom. The gate lengths of input transistor 3a and input transistor 3b are different. In this example, the gate length of input transistor 3a connected to active load 4 is the shortest. In addition, the source of input transistor 3a and the drain of input transistor 3b are connected in series with each other. In addition, the gates 80 of input transistors 3 are connected to each other.

[0075] In addition, if Fig. 9As shown in FIG. 1B , the back gates of the input transistor 3 a and the input transistor 3 b are separated from each other and connected to the same potential as the corresponding source 82. In this example, a p-well 95 for each input transistor 3 is formed on an n-well 96 in a substrate 94. In addition, a gate electrode 90, a gate insulating film 91, and a sidewall insulating film 92 of each input transistor 3 are formed on different p-wells 95. In addition, an element isolation insulator 97 is formed on the p-well 95 to insulate elements such as the first power supply 6 a and the drain 81 or the second power supply 6 b and the source 82 from each other. The element isolation insulator 97 is also called a shallow trench isolation (STI) insulating film. An interlayer insulating film 93 is formed on the p-well 95 in a manner covering each input transistor 3. In addition, each contact plug 89 is formed in the interlayer insulating film 93 and is formed on any gate electrode 90, drain 81, source 82, first power supply 6 a, and second power supply 6 b. In addition, the gate electrodes 90 of the input transistors 3 a and 3 b are electrically connected to each other through the wiring 86 formed on the contact plug 89 . Fig. 9 B shows four wirings 86 formed in the same wiring layer (however, for ease of viewing the drawing, one of these wirings 86 is shown at a higher position than the other three wirings 86).

[0076] In addition, the number of these input transistors 3 is not limited to two, and any number of input transistors 3 can be connected to each other. In addition, in the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and it is only necessary to include a structure in which more than two input transistors 3 are arranged in series.

[0077] In addition, regarding the relationship between each input transistor 3 and the power supply, the amplifier circuit 2 may have a configuration in which the input transistor 3a and the input transistor 3b are NMOS, and the voltage of the first power supply 6a is higher than the voltage of the second power supply 6b. Alternatively, the amplifier circuit 2 may have a configuration in which the input transistor 3a and the input transistor 3b are PMOS, and the voltage of the second power supply 6b is higher than the voltage of the first power supply 6a.

[0078] use Fig. 9 In the configuration, since the back gates of the input transistors 3a and 3b are connected to the same potential as the corresponding sources, the influence of the voltage threshold due to the substrate bias effect is suppressed, thereby improving the RTS noise.

[0079] (Fifth Implementation Option) Fig.10 An example of a comparator according to the fifth embodiment is shown.

[0080] Fig.10The circuit diagram shows a comparator 5 including a tail current control transistor 10 for controlling a tail current. In this example, in the tail current control transistor 10 connected to the differential pair circuit, three input transistors 3 are connected in series with each other, and the gates of the three input transistors 3 are electrically connected with each other. The tail current control transistor 10 can use any one of the amplifier circuits 2 according to the first to fourth embodiments (including modified examples) described above.

[0081] In addition, in the tail current control transistor 10, the number of input transistors 3 is not limited to three, and any number of input transistors 3 can be connected to each other. In the amplifier circuit 2, it is not necessary for all input transistors 3 to be arranged alternately in series, and it is only necessary to include a structure in which more than two input transistors 3 are arranged in series.

[0082] With this structure, the comparator 5 can reduce the RTS noise generated in the tail current control transistor 10. The S / N ratio is improved along with the reduction of the RTS noise, which leads to high image quality of the solid-state imaging device or the like using the comparator 5.

[0083] (Sixth Implementation Plan) Fig.11 is an example of a solid-state imaging device according to the sixth embodiment.

[0084] Fig.11 A is a circuit diagram of the solid-state imaging device 1 according to the present embodiment, and Fig.11 B is a schematic diagram of the solid-state imaging device.

[0085] like Fig.11 As shown in FIG. 1B , the stacked solid-state imaging device 1 includes a first substrate 100, the first substrate 100 includes a pixel array 73 in which a plurality of pixels 72 are gathered, and each pixel 72 includes a photoelectric conversion unit 70 and a pixel transistor 71. The stacked solid-state imaging device 1 also includes a second substrate 200, and the second substrate 200 includes a logic circuit 74. The first substrate 100 is provided on the second substrate 200.

[0086] like Fig.11 As shown in A of FIG. 1 , the first substrate 100 includes a photodiode PD as a photoelectric conversion unit 70 and a transfer transistor TR, a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL as a pixel transistor 71, and also includes a floating diffusion region FD. In addition, the second substrate 200 includes a comparator 5, a counter circuit 13, and a ramp generator 14 as components of the logic circuit 74. In this embodiment, the solid-state imaging device 1 includes a comparator 5 having an amplifier circuit 2 described in one of the first to fourth embodiments, or a comparator 5 described in the fifth embodiment on the second substrate.

[0087] The photodiode PD performs photoelectric conversion of incident light. The anode of the photodiode PD is electrically connected to the ground potential, and the cathode of the photodiode PD is electrically connected to the transfer transistor TR. The entry of light into the photodiode PD is referred to as exposure of the photodiode PD.

[0088] The transfer transistor TR transfers the charge generated as a result of the photoelectric conversion to the floating diffusion region FD. One of the source and the drain of the transfer transistor TR is electrically connected to the photodiode PD, and the other of the source and the drain of the transfer transistor TR is electrically connected to the floating diffusion region FD, the reset transistor RST and the amplifier transistor AMP.

[0089] Before starting exposure of the photodiode PD, the reset transistor RST discharges the charge from the floating diffusion region FD and resets the potential of the floating diffusion region FD to the power supply voltage (VDD). One of the source and the drain of the reset transistor RST is electrically connected to the power supply voltage, and the other of the source and the drain of the reset transistor RST is electrically connected to the transfer transistor TR, the floating diffusion region FD, and the amplifier transistor AMP.

[0090] The floating diffusion region FD accumulates the charge transferred by the transfer transistor TR. The floating diffusion region FD functions as a capacitor. The floating diffusion region FD is electrically connected to the transfer transistor TR, the reset transistor RST, and the amplifier transistor AMP.

[0091] The amplifier transistor AMP receives the charge transferred to the floating diffusion region FD at its gate, and outputs the charge to the selection transistor SEL using a source follower. The gate of the amplifier transistor AMP is electrically connected to the transfer transistor TR, the floating diffusion region FD, and the reset transistor RST. One of the source and the drain of the amplifier transistor AMP is electrically connected to the power supply voltage, and the other of the source and the drain of the amplifier transistor AMP is electrically connected to the selection transistor SEL.

[0092] The selection transistor SEL can electrically connect the amplifier transistor AMP and the vertical signal line to each other. When the selection transistor SEL is turned on, the amplifier transistor AMP and the vertical signal line are electrically connected to each other; and when the selection transistor SEL is turned off, the amplifier transistor AMP and the vertical signal line are electrically insulated from each other. One of the source and the drain of the selection transistor SEL is electrically connected to the amplifier transistor AMP, and the other of the source and the drain of the selection transistor SEL is electrically connected to or can be electrically connected to the vertical signal line.

[0093] With this structure, the stacked solid-state imaging device 1 can reduce the RTS noise generated by the comparator 5. The S / N ratio is improved along with the reduction of the RTS noise, which leads to high image quality in the stacked solid-state imaging device 1.

[0094] (Seventh Implementation Plan) Fig.12 is an example of a solid-state imaging device according to the seventh embodiment.

[0095] Fig.12 A is a circuit diagram of the solid-state imaging device 1 according to the present embodiment, and Fig.12 B is a schematic diagram of the solid-state imaging device 1 .

[0096] like Fig.12 As shown in FIG. 1B , the 3D stacked solid-state imaging device 1 includes: a first substrate 100 including a photoelectric conversion unit 70, a second substrate 200 including a pixel transistor 71, and a third substrate 300 including a logic circuit 74. The first substrate 100 and the second substrate 200 are stacked with an insulating layer disposed therebetween. In addition, the first substrate 100 is disposed on the second substrate 200, and the second substrate 200 is disposed on the third substrate 300. Some pixel transistors 71 may be included in the first substrate 100 instead of in the second substrate 200.

[0097] like Fig.12 As shown in A of FIG. 1 , the first substrate 100 includes a photodiode PD, a transfer transistor TR, and a floating diffusion region FD. In addition, the second substrate 200 includes a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, and a comparator 5. In addition, the third substrate 300 includes a counter circuit 13 and a ramp generator 14. In this embodiment, the solid-state imaging device 1 includes a comparator 5 having an amplifier circuit 2 described in one of the first to fourth embodiments, or a comparator 5 described in the fifth embodiment on the second substrate. In addition, the solid-state imaging device 1 may include a fourth substrate including a memory circuit below the third substrate 300.

[0098] With this structure, the 3D stacked solid-state imaging device 1 can reduce the RTS noise generated by the comparator 5. The S / N ratio is improved along with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device 1.

[0099] (Eighth Implementation Plan) Fig.13 is an example of a solid-state imaging device according to the eighth embodiment. Fig.13 A is a circuit diagram of the solid-state imaging device 1 according to the present embodiment, and Fig.13 B is a schematic diagram of the solid-state imaging device 1 .

[0100] like Fig.13As shown in FIG. 1B , the 3D stacked solid-state imaging device 1 includes: a first substrate 100 including a photoelectric conversion unit 70, a second substrate including a pixel transistor 71, and a third substrate including a logic circuit 74. The first substrate 100 and the second substrate 200 are stacked with an insulating layer disposed therebetween. In addition, the first substrate 100 is disposed on the second substrate 200, and the second substrate 200 is disposed on the third substrate 300. Some pixel transistors 71 may be included in the first substrate 100 instead of the second substrate 200.

[0101] like Fig.13 As shown in A of , the first substrate 100 includes a photodiode PD, a transfer transistor TR, and a floating diffusion region FD. In addition, the second substrate 200 includes a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. In addition, the third substrate 300 includes a comparator 5, a counter circuit 13, and a slope generator 14. In this embodiment, the solid-state imaging device 1 includes a comparator 5 having an amplifier circuit 2 described in one of the first to fourth embodiments, or a comparator 5 described in the fifth embodiment on the second substrate. In addition, the solid-state imaging device 1 may include a fourth substrate below the third substrate 300, the fourth substrate including a storage circuit.

[0102] With this structure, the 3D stacked solid-state imaging device 1 can reduce the RTS noise generated by the comparator 5. The S / N ratio is improved along with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device 1.

[0103] (Ninth Implementation Plan) Fig.14 is a cross-sectional view showing a structure of a solid-state imaging device according to a ninth embodiment.

[0104] Fig.14 A cross section of two pixels 11 (one pixel common unit 12 ) included in the 3D stacked solid-state imaging device 1 having an AD converter function is shown.

[0105] Fig.14 The X-axis, Y-axis, and Z-axis are shown to be perpendicular to each other. The X-direction and the Y-direction correspond to the lateral direction (horizontal direction), and the Z-direction corresponds to the longitudinal direction (vertical direction). In addition, the +Z direction corresponds to the upward direction, and the -Z direction corresponds to the downward direction. Note that the -Z direction may be strictly consistent with the direction of gravity, but does not necessarily have to be strictly consistent with the direction of gravity.

[0106] like Fig.14As shown, the solid-state imaging device 1 according to the present embodiment includes a first substrate 100, a second substrate 200, a third substrate 300, a filter layer 24, an on-chip lens layer 25, and a through plug 26. The first substrate 100 is provided on the second substrate 200, and the second substrate 200 is provided on the third substrate 300. The filter layer 24 and the on-chip lens layer 25 are sequentially formed on the first substrate 100. The through plug 26 is formed in the first substrate 100 and the second substrate 200 in such a manner as to penetrate the boundary surface between the first substrate 100 and the second substrate 200.

[0107] The first substrate 100 includes a semiconductor substrate 31, an element isolation insulating film 32, a gate insulating film 33 and a gate electrode 34 of each transistor Tr1, an electrode portion 35, an interlayer insulating film 36, and a photodiode PD of each pixel 11. The semiconductor substrate 31 includes an N-type region 31a, a P-type region 31b, and a floating diffusion portion 31c for each pixel 11.

[0108] The second substrate 200 includes a semiconductor substrate 41, a gate insulating film 42 and a gate electrode 43 of each transistor Tr2, an interlayer insulating film 44, an interlayer insulating film 45, a plurality of plugs 46a to 46d, a plurality of wiring layers 47a to 47c, and a plurality of pads 48. The semiconductor substrate 41 includes a plurality of diffusion regions 41a.

[0109] The third substrate 300 includes a semiconductor substrate 51, a gate insulating film 52 and a gate electrode 53 of each transistor Tr3, an interlayer insulating film 54, an interlayer insulating film 55, a plurality of plugs 56a to 56c, a plurality of wiring layers 57a and 57b, and a plurality of pads 58. The semiconductor substrate 51 includes a plurality of diffusion regions 51a.

[0110] The semiconductor substrate 31 is, for example, a silicon (Si) substrate. Fig.14 , the surface (lower surface) of the semiconductor substrate 31 along the -Z direction is the front surface of the semiconductor substrate 31, and the surface (upper surface) of the semiconductor substrate 31 along the +Z direction is the back surface thereof. Since the solid-state imaging device according to the present embodiment is a back-illuminated type, the back surface of the semiconductor substrate 31 is the light incident surface (light receiving surface) of the semiconductor substrate 31.

[0111] The semiconductor substrate 31 includes a photodiode PD for each pixel 11. The photodiode PD of each pixel 11 is mainly formed by a pn junction between an N-type region 31a and a P-type region 31b, and serves as a photoelectric conversion portion. The photodiode PD of each pixel 11 receives light from the back side of the semiconductor substrate 31, generates a signal charge corresponding to the light amount of the received light, and accumulates the generated signal charge in the floating diffusion portion 31c.

[0112] The element isolation insulating film 32 is provided in the semiconductor substrate 31 and penetrates the semiconductor substrate 31 between the front and back surfaces of the semiconductor substrate 31. The element isolation insulating film 32 is, for example, a silicon oxide film (SiO2 film). The solid-state imaging device according to the present embodiment may further include a light shielding layer (for example, a W (tungsten) layer) buried in the element isolation insulating film 32. The element isolation insulating film 32 has a grid shape surrounding the above-mentioned plurality of pixels 11 for each pixel 11 in a plan view.

[0113] The first substrate 100 includes a plurality of transistors Tr1. These transistors Tr1 include, for example, pixel transistors such as transfer transistors TR. The gate insulating film 33 and the gate electrode 34 of each transistor Tr1 are sequentially formed on the front surface of the semiconductor substrate 31. The gate insulating film 33 is, for example, a SiO2 film. The gate electrode 34 is, for example, a polysilicon layer.

[0114] The electrode portion 35 is formed on the front surface of the semiconductor substrate 31 and is in contact with the floating diffusion portion 31c. The electrode portion 35 is, for example, a polysilicon layer. The gate electrode 34 and the electrode portion 35 according to the present embodiment are formed by processing the same material.

[0115] The interlayer insulating film 36 is formed on the front surface of the semiconductor substrate 31, and covers the gate electrode 34 and the electrode portion 35. The interlayer insulating film 36 is, for example, a SiO2 film.

[0116] The semiconductor substrate 41 is, for example, a Si substrate. The semiconductor substrate 41 is provided on the lower surface of the interlayer insulating film 36. Fig.14 , the surface (lower surface) of the semiconductor substrate 41 in the −Z direction is the front surface of the semiconductor substrate 41 , and the surface (upper surface) of the semiconductor substrate 41 in the +Z direction is the back surface of the semiconductor substrate 41 .

[0117] The second substrate 200 includes a plurality of transistors Tr2. These transistors Tr2 include, for example, pixel transistors such as a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. The gate insulating film 42 and the gate electrode 43 of each transistor Tr2 are sequentially formed on the front surface of the semiconductor substrate 41. Fig.14 As shown, the gate insulating film 42 and the gate electrode 43 of at least some transistors Tr2 can be buried in a trench formed in the semiconductor substrate 41. The gate insulating film 42 is, for example, a SiO2 film. The gate electrode 43 is, for example, a polysilicon layer. Each diffusion region 41a in the semiconductor substrate 41 is used as, for example, a source region or a drain region of one of the transistors Tr2.

[0118] An interlayer insulating film 44 is formed on the front surface of the semiconductor substrate 41, and covers the gate electrode 43. An interlayer insulating film 45 is formed on the lower surface of the interlayer insulating film 44. These interlayer insulating films 44 and 45 are, for example, SiO2 films.

[0119] Plugs 46a to 46d, wiring layers 47a to 47c, and pads 48 are formed in the interlayer insulating films 44 and 45. Specifically, the wiring layers 47a to 47c are sequentially formed below the semiconductor substrate 41. The pads 48 are formed below the wiring layers 47a to 47c and are located on the lower surface of the second substrate 200. Each plug 46a is a contact plug that electrically connects the diffusion region 41a or the gate electrode 43 and the wiring layer 47a to each other. Each plug 46b is a through-hole plug that electrically connects the wiring layer 47a to the wiring layer 47b to each other. Each plug 46c is a through-hole plug that electrically connects the wiring layer 47b to the wiring layer 47c to each other. Each plug 46d is a through-hole plug that electrically connects the wiring layer 47c to any one of the pads 48 to each other.

[0120] The semiconductor substrate 51 is, for example, a Si substrate. The semiconductor substrate 51 is provided below the interlayer insulating films 44 and 45 via the interlayer insulating films 54 and 55. Fig.14 , the surface (upper surface) of the semiconductor substrate 51 in the +Z direction is the front surface of the semiconductor substrate 51 , and the surface (lower surface) of the semiconductor substrate 51 in the −Z direction is the back surface of the semiconductor substrate 51 .

[0121] The third substrate 300 includes a plurality of transistors Tr3. These transistors Tr3 form, for example, a logic circuit. The gate insulating film 52 and the gate electrode 53 of each transistor Tr3 are sequentially formed on the front surface of the semiconductor substrate 51. The gate insulating film 52 is, for example, a SiO2 film. The gate electrode 53 is, for example, a polysilicon layer. Each diffusion region 51a in the semiconductor substrate 51 is used as, for example, a source region or a drain region of one of the transistors Tr3.

[0122] An interlayer insulating film 54 is formed on the front surface of the semiconductor substrate 51 and covers the gate electrode 53. An interlayer insulating film 55 is formed on the upper surface of the interlayer insulating film 54. These interlayer insulating films 54 and 55 are, for example, SiO2 films. Fig.14 As shown, the interlayer insulating film 55 is bonded to the lower surface of the interlayer insulating film 45 .

[0123] Plugs 56a to 56c, wiring layers 57a and 57b, and pads 58 are formed in the interlayer insulating films 54 and 55. Specifically, the wiring layers 57a and 57b are sequentially formed above the semiconductor substrate 51. The pads 58 are formed above the wiring layers 57a and 57b and are located on the upper surface of the third substrate 300. Each plug 56a is a contact plug that electrically connects the diffusion region 51a or the gate electrode 53 and the wiring layer 57a to each other. Each plug 56b is a through-hole plug that electrically connects the wiring layer 57a and the wiring layer 57b to each other. Each plug 56c is a through-hole plug that electrically connects the wiring layer 57b and any one of the pads 58 to each other. Fig.14 As shown, solder pad 58 is bonded to a lower surface of solder pad 48 and is electrically connected to solder pad 48 .

[0124] The solid-state imaging device 1 according to the present embodiment has a three-layer structure including first, second and third substrates 100 to 300. The solid-state imaging device 1 according to the present embodiment further includes a filter layer 24 and an on-chip lens layer 25 on the first substrate 100, and includes a through plug 26 in the first substrate 100 and the second substrate 200.

[0125] The filter layer 24 includes a plurality of filters having the effect of transmitting light having a predetermined wavelength. For example, filters for red (R), green (G), and blue (B) are respectively arranged above the photodiodes PD of the red, green, and blue pixels 11. In addition, a filter for infrared light may be arranged above the photodiode PD of the pixel 11 for infrared light.

[0126] The on-chip lens layer 25 includes a plurality of on-chip lenses having an effect of collecting incident light. In the present embodiment, the light incident on each on-chip lens is collected by the on-chip lens, passes through the corresponding filter, and is incident on the corresponding photodiode PD. The photodiode PD converts the light into charge by photoelectric conversion to generate signal charge. The generated signal charge is accumulated in the floating diffusion 31c.

[0127] The through plug 26 is formed in the interlayer insulating film 36, the semiconductor substrate 41, and the interlayer insulating film 44. The through plug 26 is a contact plug that electrically connects the electrode portion 35 and the wiring layer 47a to each other. The first substrate 100 and the second substrate 200 according to the present embodiment are electrically connected to each other via the through plug 26. On the other hand, the second substrate 200 and the third substrate 300 according to the present embodiment are electrically connected to each other via the pads 48 and 58.

[0128] Fig.15 is a circuit diagram showing a configuration of a solid-state imaging device according to a ninth embodiment.

[0129] Fig.15The first substrate 100, the second substrate 200 and the third substrate 300 are shown. As described above, Fig.15 The first substrate 100 and the second substrate 200 are shown to be electrically connected to each other via a through plug 26, and Fig.15 The second substrate 200 and the third substrate 300 are shown to be electrically connected to each other via the pads 48 and 58 .

[0130] like Fig.15 As shown, the first substrate 100 includes a photodiode PD for each pixel 11 . Fig.15 The photodiodes PD of eight pixels 11a to 11d of the two pixel sharing units 12 are shown. The cathode of each photodiode PD is electrically connected to the through plug 26 via the corresponding transfer transistor TR, and is electrically connected to the power supply line (VDD) via the corresponding overflow gate transistor OFG. On the other hand, the anode of each photodiode PD is electrically connected to another power supply line or a ground line. The transfer transistor TR and the overflow gate transistor OFG are included in the above-mentioned transistor Tr1 ( Fig.15 )middle.

[0131] In this embodiment, the solid-state imaging device 1 includes a comparator 5 having the amplifier circuit 2 described in one of the first to third embodiments, or the comparator 5 described in the fourth embodiment on the second substrate 200. The comparator 5 is provided in the AD converter of the column signal processing section, compares the pixel signal with the reference signal, and outputs the comparison result between these signals. The comparator 5 includes transistors Tp1 and Tp2 as PMOS transistors, and transistors Tn1a to Tn1c, Tn2a to Tn3c, Tn3, and Tn4 as NMOS transistors. These transistors Tp1, Tp2, Tn1a to Tn1c, Tn2a to Tn3c, Tn3, and Tn4 are included in the above-mentioned transistor Tr2 ( Fig.14 )middle.

[0132] The transistors Tp1 and Tp2 form an active load 62. The gate of the transistor Tp1 is electrically connected to the gate of the transistor Tp2. The sources of the transistors Tp1 and Tp2 are electrically connected to the power supply line (VDD). The drain of the transistor Tp1 is electrically connected to the drain of the transistor Tn1a and the gates of the transistors Tp1 and Tp2. The drain of the transistor Tp2 is electrically connected to the drains of the transistors Tn2 and Tn4 and the pad 48. The active load 62 is a current mirror circuit that causes a current corresponding to a mirror ratio to flow through the transistors Tp1 and Tp2.

[0133] Transistors Tn1a, Tn1b, Tn1c, Tn2a, Tn2b and Tn2c form a differential pair circuit 63. The gates of input transistors Tn1a to Tn1c are electrically connected to each other. In addition, the gates of input transistors Tn1a to Tn1c are also electrically connected to the reference signal line. The gates of input transistors Tn2a to Tn2c are electrically connected to each other. In addition, the gates of input transistors Tn2a to Tn2c are electrically connected to the comparison signal line (through plug 26), and are electrically connected to the source of transistor Tn4. The source and drain of each group of three input transistors Tn1a to Tn1c and Tn2a to Tn2c are connected in series to each other. In addition, the source of transistors Tn1c and Tn2c is electrically connected to the drain of transistor Tn3. The differential pair circuit 63 outputs the comparison result (voltage difference) between the comparison signal and the reference signal to the node between transistor Tp2 and transistor Tn2a, and outputs the result from the node to pad 48.

[0134] The transistor Tn3 is a tail part and is used as a current source. The gate of the transistor Tn3 is electrically connected to a wiring for applying a predetermined voltage. The source of the transistor Tn3 is electrically connected to a ground line (GND). The current source maintains the total current flowing through the transistors Tn1a to Tn1c and Tn2a to Tn2c at a predetermined value.

[0135] The transistor Tn4 is provided between the through-plug 26 and the above-mentioned node, and functions as an AZ transistor. The gate of the transistor Tn4 is electrically connected to the reset signal line. The source of the transistor Tn4 is electrically connected to the through-plug 26. The drain of the transistor Tn4 is electrically connected to the above-mentioned node. The AZ transistor electrically connects the through-plug 26 (floating diffusion 31 c) and the above-mentioned node to each other before the output signal is detected, and performs an auto-zero operation.

[0136] With this structure, it is possible to reduce the RTS noise generated by the comparator 5. The S / N ratio is improved along with the reduction of the RTS noise, which leads to high image quality in the 3D stacked solid-state imaging device 1 with an AD converter function.

[0137] (Tenth Implementation Plan) Fig.16 is a block diagram showing an example of a functional configuration of a solid-state imaging device according to a tenth embodiment.

[0138] <1. Implementation> [Functional Structure of Solid-State Imaging Device 1] Fig.16 The solid-state imaging device 1 includes, for example, an input section 510A, a row driving section 520 , a timing control section 530 , a pixel array section 540 , a column signal processing section 550 , an image signal processing section 560 , and an output section 510B.

[0139] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel common unit 539 including a plurality of pixels is a repeating unit, and is repeatedly arranged in an array in the row direction and the column direction. Note that in this specification, for convenience, the row direction is also referred to as the H direction, and the column direction perpendicular to the row direction is also referred to as the V direction. Fig.16 In the example of FIG. 5 , each pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D includes a photodiode PD (hereinafter referred to as Fig.21 The pixel sharing unit 539 is a pixel sharing circuit (see later). Fig.18 In other words, one pixel circuit (the pixel circuit 210 to be described later) is provided for every four pixels (pixels 541A, 541B, 541C, and 541D). By operating the pixel circuit in a time-division manner, the pixel signals of the respective pixels 541A, 541B, 541C, and 541D are read out in sequence. The pixels 541A, 541B, 541C, and 541D are arranged, for example, in two rows and two columns. In the pixel array section 540, a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided together with the pixels 541A, 541B, 541C, and 541D. The row drive signal line 542 drives the pixel 541 included in each of the plurality of pixel sharing units 539 arranged side by side in the row direction in the pixel array section 540. In the pixel sharing unit 539, the respective pixels arranged side by side in the row direction are driven. As will be described later with reference to Fig.19 To be described in detail, the pixel common unit 539 is provided with a plurality of transistors. In order to drive each of the plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel common unit 539. The pixel common unit 539 is connected to one of the vertical signal lines (column readout lines) 543. Pixel signals are read from each of the pixels 541A, 541B, 541C, and 541D included in the pixel common unit 539 via the vertical signal line (column readout line) 543.

[0140] The row driving section 520 includes, for example, a row address control section that determines the position of a row for driving pixels, that is, a row decoder section, and a row driving circuit section that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0141] The column signal processing section 550 includes, for example, a load circuit section that is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (the pixel common unit 539). The column signal processing section 550 may include an amplifier circuit section that amplifies a pixel signal read from the pixel common unit 539 via the vertical signal line 543. The column signal processing section 550 may include a noise processing section. In the noise processing section, for example, a system noise level is removed from a signal read from the pixel common unit 539 as a result of photoelectric conversion.

[0142] The column signal processing unit 550 includes, for example, an AD converter. In the AD converter, the signal read from the pixel sharing unit 539 or the analog signal subjected to the above-mentioned noise processing is converted into a digital signal. The AD converter includes, for example, a comparator 5 and a counter circuit. The comparator 5 compares the analog signal to be converted with the reference signal to be compared. In the counter circuit, the time until the comparison result in the comparator 5 is reversed is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that performs control for scanning the column to be read. The comparator 5 may be the comparator 5 including the amplifier circuit 2 described in the first to fourth embodiments or the comparator 5 described in the fifth embodiment.

[0143] The timing control section 530 supplies a signal for controlling timing to the row driving section 520 and the column signal processing section 550 based on the reference clock signal and the timing control signal input to the device.

[0144] The image signal processing section 560 is a circuit that performs various types of signal processing on data obtained as a result of photoelectric conversion (that is, data obtained as a result of the imaging operation of the solid-state imaging device 1). The image signal processing section 560 includes, for example, an image signal processing circuit section and a data holding section. The image signal processing section 560 may include a processor section.

[0145] An example of the signal processing performed by the image signal processing section 560 is a tone curve correction process for providing more grayscale levels in the case where the image data obtained as a result of AD conversion is data obtained by capturing an image of a dark subject, and providing less grayscale levels in the case where the image data obtained as a result of AD conversion is data obtained by capturing an image of a bright subject. In this case, it is desirable to store feature data about the tone curve in advance in the data holding section of the image signal processing section 560 to determine how the tone curve corrects the grayscale levels of the image data.

[0146] The input section 510A is used, for example, to input the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the device to the solid-state imaging device 1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, etc. For example, the characteristic data is stored in the data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0147] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is used to take the signal input to the input terminal 511 into the solid-state imaging device 1. In the input amplitude change unit 513, the amplitude of the signal taken in by the input circuit unit 512 is changed to an amplitude that can be easily used in the solid-state imaging device 1. In the input data conversion circuit unit 514, the arrangement of the data string of the input data is changed. The input data conversion circuit unit 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, the serial signal received as input data is converted into a parallel signal. Note that in the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 can be omitted. The power supply unit supplies power set to various voltages required inside the solid-state imaging device 1 based on the power supplied to the solid-state imaging device 1 from the outside.

[0148] The input section 510A may be provided with a memory interface circuit, and when the solid-state imaging device 1 is connected to an external memory device, the memory interface circuit receives data from the external memory device. The external memory device is, for example, a flash memory, an SRAM, a DRAM, or the like.

[0149] The output section 510B outputs image data to the outside of the device. The image data is, for example, image data obtained by capturing an image using the solid-state imaging device 1, image data subjected to signal processing by the image signal processing section 560, etc. The output section 510B includes, for example, an output data conversion circuit section 515, an output amplitude changing section 516, an output circuit section 517, and an output terminal 518.

[0150] The output data conversion circuit section 515 includes, for example, a parallel-to-serial conversion circuit, and in the output data conversion circuit section 515, a parallel signal used inside the solid-state imaging device 1 is converted into a serial signal. The output amplitude change section 516 changes the amplitude of the signal used inside the solid-state imaging device 1. The signal with the changed amplitude can be easily used in an external device connected to the outside of the solid-state imaging device 1. The output circuit section 517 is a circuit that outputs data from the inside of the solid-state imaging device 1 to the outside of the device, and the output circuit section 517 drives the wiring outside the solid-state imaging device 1 connected to the output terminal 518. At the output terminal 518, data is output from the solid-state imaging device 1 to the outside of the device. In the output section 510B, the output data conversion circuit section 515 and the output amplitude change section 516 can be omitted.

[0151] The output section 510B may be provided with a memory interface circuit, and when the solid-state imaging device 1 is connected to an external memory device, the memory interface circuit outputs data to the external memory device, such as a flash memory, SRAM, or DRAM.

[0152] [Schematic Configuration of Solid-State Imaging Device 1> Fig.17 and Fig.18 is a diagram showing an example of a schematic configuration of the solid-state imaging device 1. The solid-state imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Fig.17 The planar configurations of the first substrate 100, the second substrate 200 and the third substrate 300 are schematically shown, and Fig.18 The cross-sectional configuration of the first substrate 100 , the second substrate 100 , and the third substrate 300 stacked on each other is schematically shown. Fig.18 Corresponding to along Fig.17The cross-sectional structure taken along the line III-III' is described. The solid-state imaging device 1 is a solid-state imaging device having a three-dimensional structure formed by bonding three substrates (a first substrate 100, a second substrate 200, and a third substrate 300) together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, a combination of wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and an interlayer insulating film around the wiring is referred to as a wiring layer (100T, 200T, or 300T) provided in each substrate (the first substrate 100, the second substrate 100, and the third substrate 300). The first substrate 100, the second substrate 200 and the third substrate 300 are sequentially stacked on each other, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T and the semiconductor layer 300S are sequentially arranged along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200 and the third substrate 300 will be described later. Fig.18 The arrow shown indicates the direction in which the light L is incident on the solid-state imaging device 1. In this specification, for the sake of convenience, the light incident side of the solid-state imaging device 1 may be referred to as "downward", "lower side" and "below" in the following cross-sectional views, and the side opposite to the light incident side may be referred to as "upward", "upper side" and "above". In addition, in this specification, for a substrate including a semiconductor layer and a wiring layer, for the sake of convenience, the wiring layer side may be referred to as the front side, and the semiconductor layer side may be referred to as the back side. Note that the description in the specification is not limited to the above terms. The solid-state imaging device 1 is, for example, a back-illuminated solid-state imaging device onto which light is incident from the back side of the first substrate 100 including a photodiode.

[0153] The pixel array section 540 and the pixel common unit 539 included in the pixel array section 540 are both constructed using the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel common unit 539. Each of these pixels 541 includes a photodiode (photodiode PD to be described later) and a transfer transistor (to be described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 to be described later) included in the pixel common unit 539. The pixel circuit reads a pixel signal transmitted from the photodiode of each of the pixels 541A, 541B, 541C, and 541D via a transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes a power supply line 544 extending in the row direction. The third substrate 300 includes, for example, an input section 510A, a row drive section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row drive section 520 is, for example, disposed in a region where a portion of the stacking direction (hereinafter, simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300 overlaps with the pixel array section 540. More specifically, the row drive section 520 is disposed in a region where it overlaps with the vicinity of the end of the pixel array section 540 in the H direction in the stacking direction ( Fig.17 ). The column signal processing unit 550 is provided, for example, in a region that partially overlaps with the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is provided in a region that overlaps with the vicinity of the end portion of the pixel array unit 540 in the V direction in the stacking direction ( Fig.17 ). Although not shown, the input section 510A and the output section 510B may be provided in a portion other than the third substrate 300, and alternatively, for example, may be provided on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100. Note that the pixel circuit provided in the second substrate 200 described above may be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit as another name. In this specification, the term "pixel circuit" is used.

[0154] The first substrate 100 and the second substrate 200 are connected to each other by, for example, through electrodes (which will be described later). Fig.21The through electrodes 120E and 121E in the second substrate 200 are electrically connected to each other. The second substrate 200 and the third substrate 300 are electrically connected to each other via, for example, contact portions 201, 202, 301, and 302. The contact portions 201 and 202 are provided in the second substrate 200, and the contact portions 301 and 302 are provided in the third substrate 300. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 201R and 301R are provided between the pixel array section 540 and the row drive section 520 along the stacking direction ( Fig.18 ). In other words, the contact regions 201R and 301R are provided in a region where, for example, the row drive section 520 (third substrate 300) overlaps with the pixel array section 540 (second substrate 200) in the stacking direction or in a region near the row drive section 520 (third substrate 300). The contact regions 201R and 301R are provided, for example, at the end of the region in the H direction ( Fig.17 ). For example, in the third substrate 300, the contact region 301R is provided at a position overlapping with a portion of the row drive section 520, or more specifically, at a position overlapping with an end portion of the row drive section 520 in the H direction ( Fig.17 and Fig.18 ). The contact portions 201 and 301 connect, for example, the row driving portion 520 provided in the third substrate 300 and the row driving signal line 542 provided in the second substrate 200. For example, the contact portions 201 and 301 can connect the input portion 510A provided in the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS to be described later). The contact regions 202R and 302R are provided between the pixel array portion 540 and the column signal processing portion 550 in the stacking direction ( Fig.18 ). In other words, the contact regions 202R and 302R are provided in, for example, a region where the column signal processing section 550 (third substrate 300) overlaps with the pixel array section 540 (second substrate 200) in the stacking direction or in a region near the column signal processing section 550 (third substrate 300). The contact regions 202R and 302R are provided, for example, at the end of the region in the V direction ( Fig.17 In the third substrate 300 , for example, the contact region 301R is provided at a position overlapping with a portion of the column signal processing section 550 , or more specifically, at an end portion of the column signal processing section 550 in the V direction ( Fig.17 and Fig.18). The contact portions 202 and 302 are used, for example, to connect a pixel signal (a signal corresponding to the amount of charge generated as a result of photoelectric conversion of a photodiode) output from each of the plurality of pixel common units 539 included in the pixel array portion 540 to a column signal processing portion 550 provided in the third substrate 300. The pixel signal is transmitted from the second substrate 200 to the third substrate 300.

[0155] Fig.18 is an example of a cross-sectional view of the solid-state imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected to each other via wiring layers 100T, 200T, and 300T. For example, the solid-state imaging device 1 includes an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other. Specifically, the contact portions 201, 202, 301, and 302 are composed of electrodes composed of a conductive material. The conductive material includes, for example, a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly bonding, for example, wiring formed as electrodes, and enable signal input and / or output between the second substrate 200 and the third substrate 300.

[0156] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other may be provided at a desired position. Fig.18 As shown in the contact regions 201R, 202R, 301R, and 302R in FIG. 1 , the electrical connection portion may be provided in a region overlapping with the pixel array portion 540 in the stacking direction. In addition, the electrical connection portion may be provided in a region not overlapping with the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region overlapping with the peripheral portion arranged outside the pixel array portion 540 in the stacking direction.

[0157] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 ( Fig.18 The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping with the pixel array section 540 ) ( Fig.17). For example, the connection hole H1 is arranged outside the pixel array section 540 in the H direction, and the connection hole H2 is arranged outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided in the third substrate 300, and the connection hole H2 reaches the output section 510B provided in the third substrate 300. The connection holes H1 and H2 may be hollow, or at least a portion thereof may contain a conductive material. For example, there is a structure in which a bonding wire is connected to an electrode formed as the input section 510A and / or the output section 510B. Alternatively, there is a structure in which an electrode formed as the input section 510A and / or the output section 510B is connected to a conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be buried in a part or all of the connection holes H1, H2, and the conductive material may be formed on the side walls of the connection holes H1, H2.

[0158] Note that Fig.18 In the embodiment, the input section 510A and the output section 510B are provided in the third substrate 300, but the structure adopted is not limited thereto. For example, by transmitting the signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T, the input section 510A and / or the output section 510B may be provided in the second substrate 200. Similarly, by transmitting the signal of the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T, the input section 510A and / or the output section 510B may be provided in the first substrate 100.

[0159] Fig.19 is an equivalent circuit diagram showing a configuration example of a pixel common unit 539. The pixel common unit 539 includes a plurality of pixels 541 ( Fig.19 , four pixels 541, i.e., pixels 541A, 541B, 541C, and 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210 are shown. The pixel circuit 210 includes, for example, four transistors, or more specifically, an amplifying transistor AMP, a selecting transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, the pixel sharing unit 539 sequentially outputs the pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating the one pixel circuit 210 in a time-division manner. The mode in which the plurality of pixels 541 are connected to the one pixel circuit 210, and the pixel circuit 210 outputs the pixel signals of the plurality of pixels 541 in a time-division manner is referred to as "a plurality of pixels 541 share one pixel circuit 210".

[0160] Pixels 541A, 541B, 541C, and 541D include common components. In order to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, hereinafter, identification number 1 is assigned to the end of the reference numeral of the component of pixel 541A, identification number 2 is assigned to the end of the reference numeral of the component of pixel 541B, identification number 3 is assigned to the end of the reference numeral of the component of pixel 541C, and identification number 4 is assigned to the end of the reference numeral of the component of pixel 541D. In the case where it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the components of pixels 541A, 541B, 541C, and 541D are omitted.

[0161] The pixels 541A, 541B, 541C, and 541D each include, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion region FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, or PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light to generate a charge corresponding to the amount of light received. The transfer transistor TR (transfer transistor TR1, TR2, TR3, or TR4) is, for example, an n-type complementary metal oxide semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion region FD, and the gate is electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 542 (refer to Fig.16 ). The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusion FD1, FD2, FD3, or FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding device for temporarily holding the charge transferred from the photodiode PD, and is a charge-voltage conversion device for generating a voltage corresponding to the amount of charge.

[0162] The four floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, and FD4) included in each pixel common unit 539 are electrically connected to each other, and are electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one pixel common unit 539. The gate of the amplifier transistor AMP is connected to the floating diffusion region FD, the drain of the amplifier transistor AMP is connected to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel common unit 539 .

[0163] The transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion region FD when it is turned on. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and as will be described later Fig.21 As shown, from the semiconductor layer (which will be described later) Fig.21 The reset transistor RST resets the potential of the floating diffusion region FD to a predetermined potential. The reset transistor RST resets the potential of the floating diffusion region FD to the potential of the power supply line VDD when turned on. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a voltage signal corresponding to the charge level maintained in the floating diffusion region FD as a pixel signal. The amplifier transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. The amplifier transistor AMP is connected to the load circuit portion of the vertical signal line 543 connected to the column signal processing portion 550 (refer to Fig.16 ) together constitute a source follower. When the selection transistor SEL is turned on, the amplifier transistor AMP outputs the voltage of the floating diffusion region FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are, for example, n-type CMOS transistors.

[0164] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion of the floating diffusion area FD. Generally speaking, when taking an image in a dark place, the pixel signal is small. Since Q = CV, if the capacitance (FD capacitance C) of the floating diffusion area FD is high when performing charge-voltage conversion, the V obtained by the amplifier transistor AMP as a result of conversion to voltage becomes low. On the other hand, since the pixel signal becomes larger in a bright place, the floating diffusion area FD cannot receive the charge of the photodiode PD unless the FD capacitance C is very high. In addition, the FD capacitance C needs to be very high so that the V obtained by the amplifier transistor AMP as a result of conversion to voltage does not become too high (in other words, becomes low). For these reasons, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, and the entire FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C decreases. Therefore, the FD capacitance C can be made variable, and the conversion efficiency can be switched by turning on and off the FD conversion gain switching transistor FDG. The FD conversion gain switching transistor FDG is, for example, an n-type CMOS transistor.

[0165] Note that a configuration in which the FD conversion gain switching transistor FDG is not provided is also possible. In this case, for example, the pixel circuit 210 includes three transistors, that is, for example, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 includes, for example, at least one of the pixel transistors such as the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG.

[0166] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (refer to Fig.16 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Note that, although not shown, the number of pixels 541 that share one pixel circuit 210 may be a number other than four. For example, two or eight pixels 541 may share one pixel circuit 210 instead.

[0167] Fig. 20543 and 544. For example, four pixel common units 539 arranged in the column direction are divided into four groups, and the vertical signal line 543 is connected to each of the four groups. Fig. 20 An example is shown in which four groups each include one pixel common unit 539, but the four groups may each include a plurality of pixel common units 539. Therefore, in the solid-state imaging device 1, a plurality of pixel common units 539 arranged in the column direction may be divided into a plurality of groups each including one or more pixel common units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each group, and pixel signals may be read from each group at the same time. Alternatively, in the solid-state imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel common units 539 arranged in the column direction. At this time, pixel signals are sequentially read from the plurality of pixel common units 539 connected to one vertical signal line 543 in a time-division manner.

[0168] [Specific Structure of Solid-State Imaging Device 1] Fig.21 An example of a cross-sectional configuration in a direction perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the solid-state imaging device 1 is shown. For ease of understanding, Fig.21 The positional relationship of the components is schematically shown and may be different from the actual cross section. In the solid-state imaging device 1, the first substrate 100, the second substrate 200 and the third substrate 300 are stacked in sequence. The solid-state imaging device 1 also includes a light receiving lens 401 located on the back side (light incident side) of the first substrate 100. A filter layer (not shown) can be provided between the light receiving lens 401 and the first substrate 100. The light receiving lens 401 is, for example, provided in each of the pixels 541A, 541B, 541C and 541D. The solid-state imaging device 1 is, for example, a back-illuminated solid-state imaging device. The solid-state imaging device 1 includes a pixel array portion 540 arranged in a central portion and a peripheral portion 540B arranged outside the pixel array portion 540.

[0169] The first substrate 100 includes an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T in order from the light receiving lens 401 side. The semiconductor layer 100S includes, for example, a silicon substrate. The semiconductor layer 100S includes, for example, a p-well layer 115 in a portion of its front side (the surface on the wiring layer 100T side) and near the portion, and an n-type semiconductor region 114 in another region (a region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0170] Fig.22AAn example of a planar configuration of the first substrate 100 is shown. Fig.22A The planar structure of the pixel isolation part 117, the photodiode PD, the floating diffusion region FD, the VSS contact region 118 and the transfer transistor TR of the first substrate 100 is mainly shown. Fig.22A and Fig.21 The structure of the first substrate 100 will be described.

[0171] The floating diffusion region FD and the VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion regions FD each include an n-type semiconductor region provided in the p-well layer 115. For example, in the central portion of the pixel sharing unit 539, the floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, or FD4) of the respective pixels 541A, 541B, 541C, and 541D are provided close to each other ( Fig.22A ). Although the details will be described later, the four floating diffusion regions (floating diffusion regions FD1, FD2, FD3, and FD4) included in the pixel sharing unit 539 are electrically connected to each other in the first substrate 100 (more specifically, in the wiring layer 100T) via an electrical connection device (a pad portion 120 to be described later). In addition, the floating diffusion region FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical device (a through electrode 120E to be described later). In the second substrate 200 (more specifically, within the wiring layer 200T), the floating diffusion region FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG through the electrical device.

[0172] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is disposed away from the floating diffusion region FD. For example, in each of the pixels 541A, 541B, 541C, and 541D, the floating diffusion region FD is disposed at one end of the pixel in the V direction, and the VSS contact region 118 is disposed at the other end ( Fig.22A ). The VSS contact region 118 includes, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Therefore, a reference potential is supplied to the semiconductor layer 100S.

[0173] The transfer transistor TR is provided in the first substrate 100 together with the photodiode PD, the floating diffusion region FD and the VSS contact region 118. The photodiode PD, the floating diffusion region FD, the VSS contact region 118 and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C and 541D. The transfer transistor TR is provided on the front side of the semiconductor layer 100S (the side opposite to the light incident surface side, the second substrate 200 side). The transfer transistor TR includes a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transmission failure of the pixel signal hardly occurs, and the readout efficiency of the pixel signal can be improved.

[0174] The horizontal portion TGb of the transfer gate TG extends from a position facing the vertical portion TGa along the H direction toward, for example, the central portion of the pixel common unit 539 ( Fig.22A ). Therefore, the position of the through electrode (through electrode TGV to be described later) reaching the transfer gate TG in the H direction can be close to the position of the through electrodes (through electrodes 120E and 121E to be described later) connected to the floating diffusion region FD and the VSS contact region 118 in the H direction. For example, the plurality of pixel common units 539 provided in the first substrate 100 have the same configuration ( Fig.22A ).

[0175] The semiconductor layer 100S is provided with a pixel isolation portion 117 that isolates the pixels 541A, 541B, 541C, and 541D from each other. The pixel isolation portion 117 is formed in a manner extending in the normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). The pixel isolation portion 117 is provided in a manner that separates the pixels 541A, 541B, 541C, and 541D from each other, and has, for example, a grid-like planar shape ( Fig.22A and Fig. 22B). For example, the pixel isolation portion 117 electrically and optically isolates the pixels 541A, 541B, 541C, and 541D from each other. The pixel isolation portion 117 includes, for example, a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light shielding film 117A. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B includes, for example, silicon oxide (SiO). The pixel isolation portion 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel isolation portion 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S may be adopted. The pixel isolation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0176] In the semiconductor layer 100S, for example, a first pinning region 113 and a second pinning region 116 are provided. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is provided between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side surface of the pixel isolation portion 117, or more specifically, between the pixel isolation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 include, for example, a p-type semiconductor region.

[0177] The fixed charge film 112 having negative fixed charges is provided between the semiconductor layer 100S and the insulating film 111. The first pinning region 113 of the hole accumulation layer is formed at the interface on the light receiving surface (back surface) side of the semiconductor layer 100S by the electric field induced by the fixed charge film 112. Therefore, the dark current generated due to the interface state on the light receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 includes, for example, an insulating film having negative fixed charges. Examples of the material of the insulating film having negative fixed charges include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, and the like.

[0178] A light shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light shielding film 117A may be provided continuously with the light shielding film 117A constituting the pixel separation portion 117. The light shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separation portion 117 in the semiconductor layer 100S. The insulating film 111 is provided in a manner covering the light shielding film 117A. The insulating film 111 includes, for example, silicon oxide.

[0179] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 includes an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating layer 123, and a bonding film 124 in order from the semiconductor layer 100S side. The horizontal portion TGb of the transmission gate TG is provided in the wiring layer 100T, for example. The interlayer insulating film 119 is provided on the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 includes, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above configuration, and may be a configuration including wiring and an insulating film.

[0180] Fig. 22B The configuration of the pad portions 120 and 121 and Fig.22A The pad portions 120 and 121 are provided in selected regions on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. For example, in the plan view, the pad portion 120 is arranged in the central portion ( Fig. 22B The pad portion 120 is provided across the pixel isolation portion 117 and is arranged in a manner overlapping at least a portion of each of the floating diffusion regions FD1, FD2, FD3, and FD4 ( Fig.21 and Fig. 22B ). Specifically, the pad portion 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 and at least a portion of the pixel isolation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection hole 120C for electrically connecting the pad portion 120 and the floating diffusion regions FD1, FD2, FD3, and FD4 to each other. The connection hole 120C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, by burying a portion of the pad portion 120 in the connection hole 120C, the pad portion 120 and the floating diffusion regions FD1, FD2, FD3, and FD4 are electrically connected to each other.

[0181] The pad portion 121 is used to connect the plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D in one pixel sharing unit 539 adjacent to each other in the V direction and the VSS contact regions 118 in the pixels 541A and 541B in another pixel sharing unit 539 are electrically connected to each other through the pad portion 121. For example, the pad portion 121 is provided across the pixel isolation portion 117 and is arranged in a manner overlapping at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel isolation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection hole 121C for electrically connecting the pad portion 121 and the VSS contact region 118 to each other. The connection hole 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, by burying a portion of the pad portion 121 in the connection hole 121C, the pad portion 121 and the VSS contact area 118 are electrically connected to each other. For example, the pad portion 120 and the pad portion 121 of each of the plurality of pixel sharing units 539 arranged along the V direction are arranged at substantially the same position in the H direction ( Fig. 22B ).

[0182] By providing the pad portion 120, the number of wirings for connecting each floating diffusion region FD to the pixel circuit 210 (for example, the gate electrode of the amplifier transistor AMP) in the entire chip can be reduced. Similarly, by providing the pad portion 121, the number of wirings for supplying a potential to each VSS contact region 118 can be reduced in the entire chip. Therefore, it is possible to reduce the area of ​​the entire chip, suppress electrical interference between wirings in a miniaturized pixel, and / or reduce costs by reducing the number of components.

[0183] The pad portions 120 and 121 may be disposed at desired positions in the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 may be disposed in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200S. In the case where the pad portions 120 and 121 are disposed in the wiring layer 100T, the pad portions 120 and 121 may be directly contacted with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 may be directly connected to at least a portion of each of the floating diffusion region FD and / or the VSS contact region 118. In addition, connection holes 120C and 121C may be provided from each of the floating diffusion region FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 may be disposed at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0184] In particular, in the case where the pad portions 120 and 121 are provided in the wiring layer 100T, the number of wirings connected to the floating diffusion region FD and / or the VSS contact region 118 can be reduced in the insulating region 212 of the semiconductor layer 200S. Therefore, in the second substrate 200 on which the pixel circuit 210 is formed, the area of ​​the insulating region 212 for forming the through wiring for connecting the floating diffusion region FD to the pixel circuit 210 can be reduced. Therefore, a large area of ​​the second substrate 200 on which the pixel circuit 210 is formed can be ensured. By ensuring the area of ​​the pixel circuit 210, a large pixel transistor can be formed, and it contributes to image quality improvement by reducing noise and the like.

[0185] In particular, since a floating diffusion region FD and / or a VSS contact region 118 is preferably provided in each pixel 541 when the FTI structure is used in the pixel isolation portion 117, the number of wirings connecting the first substrate 100 and the second substrate 200 to each other can be greatly reduced by using the structure of the pad portions 120 and 121.

[0186] In addition, if Fig. 22B As shown, for example, a pad portion 120 connected to a plurality of floating diffusion regions FD and a pad portion 121 connected to a plurality of VSS contact regions 118 are alternately arranged in a straight line in the V direction. In addition, the pad portions 120 and 121 are formed at a position surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusion regions FD. Therefore, elements other than the floating diffusion regions FD and the VSS contact regions 118 can be freely arranged in the first substrate 100 in which a plurality of elements are formed, and the layout efficiency of the entire chip can be improved. In addition, the symmetry of the layout of the elements formed in each pixel common unit 539 can be ensured, and the characteristic variation of each pixel 541 can be suppressed.

[0187] The pad portions 120 and 121 include, for example, polysilicon (Poly-Si), or more specifically, doped polysilicon doped with impurities. The pad portions 120 and 121 preferably include a conductive material having high heat resistance such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN). Therefore, it is possible to form the pixel circuit 210 after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. Hereinafter, the reason will be explained. Note that in the following description, the method of forming the pixel circuit 210 after the semiconductor layer 200S of the first substrate 100 and the second substrate 200 are bonded to each other is referred to as a first manufacturing method.

[0188] Here, it is also conceivable that after the pixel circuit 210 is formed on the second substrate 200, the second substrate 100 is bonded to the first substrate 100 (hereinafter, referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are formed in advance on each of the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded to each other, the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200 are in contact with each other. Therefore, electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the configuration of the solid-state imaging device 1 using the second manufacturing method, for example, it is possible to manufacture using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality and high-performance solid-state imaging device can be manufactured.

[0189] In this second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded to each other, an alignment error may occur due to the manufacturing device used for bonding. In addition, the first substrate 100 and the second substrate 200 have a size of, for example, about several tens of centimeters in diameter, but when the first substrate 100 and the second substrate 100 are bonded to each other, there is a possibility that the substrate expands and contracts in the microscopic regions of each part of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrate is caused by a slight offset when contacting between the substrates. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the positions of the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200. In the second manufacturing method, even if such an error occurs, it is preferred to take measures to make the electrodes of the first substrate 100 and the second substrate 200 contact each other. Specifically, in view of the above-mentioned error, at least one of the electrodes of the first substrate 100 or the second substrate 200, preferably both, is increased. Therefore, when the second manufacturing method is used, for example, the size of the electrode formed on the surface of the first substrate 100 or the second substrate 200 (the size in the substrate plane direction) is larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 100 to the surface in the thickness direction.

[0190] On the other hand, in the case where the pad portions 120 and 121 include a heat-resistant conductive material, the above-described first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD, the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded to each other. At this time, the second substrate 200 is in a state where the active elements and wiring layers, etc. constituting the pixel circuit 210, are not patterned. Since the second substrate 200 is in a state before patterning, even if an error occurs in the bonding position when bonding the first substrate 100 and the second substrate 100, an error does not occur in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200 due to the bonding error. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 100 are bonded. Note that when forming a pattern on the second substrate, for example, in an exposure device for pattern formation, the pattern is formed while setting the pattern formed on the first substrate as an alignment target. For the above reasons, when the solid-state imaging device 1 is manufactured in the first manufacturing method, an error in the bonding position between the first substrate 100 and the second substrate 200 does not cause a problem. For similar reasons, when the solid-state imaging device 1 is manufactured in the first manufacturing method, an error caused by expansion and contraction of the substrate caused by the second manufacturing method does not cause a problem.

[0191] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded in this manner, an active element is formed on the second substrate 100. Then, the through electrodes 120E and 121E and the through electrode TGV ( Fig.21 ). In the process of forming the through electrodes 120E, 121E and TGV, for example, reduced projection exposure is performed using an exposure device to form a pattern of the through electrodes from above the second substrate 200. Since reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the size of the error in the second substrate 200 is only a small portion of the error size of the above-mentioned second manufacturing method (the inverse of the reduced exposure projection magnification). Therefore, by adopting the configuration of the solid-state imaging device 1 using the first manufacturing method, it is possible to easily align the elements formed on each of the first substrate 100 and the second substrate 200, and it is possible to manufacture a high-quality and high-performance solid-state imaging device.

[0192] The solid-state imaging device 1 manufactured using this first manufacturing method has different features from the solid-state imaging device manufactured by the second manufacturing method. Specifically, in the solid-state imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E and TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, in the case where the through electrodes 120E, 121E and TGV have a tapered shape, they have a tapered shape with a constant inclination. In the solid-state imaging device 1 including such through electrodes 120E, 121E and TGV, the pixel 541 can be easily miniaturized.

[0193] Here, when the solid-state imaging device 1 is manufactured by the first manufacturing method, since the active element is formed in the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, the first substrate 100 is also affected by the heat treatment required to form the active element. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided in the first substrate 100. For example, the pad portions 120 and 121 preferably include a material having a higher melting point (that is, higher heat resistance) than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad portions 120 and 121. Therefore, the solid-state imaging device 1 can be manufactured using the above-mentioned first manufacturing method.

[0194] The passivation film 122 is provided on the entire surface of the semiconductor layer 100S in a manner covering the pad portions 120 and 121, for example. Fig.21). The passivation film 122 includes, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 via the passivation film 122. The interlayer insulating film 123 is, for example, provided on the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 includes, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided on the entire main surface of the first substrate 100. The bonding film 124 includes, for example, a silicon nitride film.

[0195] For example, the light receiving lens 401 faces the semiconductor layer 100S ( Fig.21 ). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0196] The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T in order from the first substrate 100 side. The semiconductor layer 200S includes a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 arranged for each pixel common unit 539. The pixel circuit 210 is, for example, provided on the front side (wiring layer 200T side) of the semiconductor layer 200S. In the solid-state imaging device 1, the second substrate 200 is bonded to the first substrate 100 so that the back side (semiconductor layer 200S side) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 in a face-to-back manner.

[0197] Figure 23 to Figure 27 An example of a planar configuration of the second substrate 200 is schematically shown. Fig.23 The configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S is shown. Fig.24 The configurations of the wiring layer 200T (specifically, a first wiring layer W1 to be described later), the semiconductor layer 200S connected to the wiring layer 200T, and the respective parts of the first substrate 100 are schematically shown. Figure 25 to Figure 27 An example of a planar configuration of the wiring layer 200T is shown. Figure 23 to Figure 27 as well as Fig.21 The structure of the second substrate 200 is described. Fig.23 and Fig.24, the outer shape of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is indicated by a broken line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 212 in the portion overlapping with the gate electrode of each transistor constituting the pixel circuit 210 is indicated by a dotted line. In the portion overlapping with the gate electrode of the amplifier transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213 and the boundary between the element isolation region 213 and the insulating region 212 are set on one side in the channel width direction.

[0198] The second substrate 200 is provided with an insulating region 212 that separates the semiconductor layer 200S and an element isolation region 213 ( Fig.21 For example, the through electrodes 120E and 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel common units 539 of the two pixel circuits 210 are arranged in the insulating region 212 provided between the two pixel circuits 210 adjacent in the H direction ( Fig.24 ).

[0199] The thickness of the insulating region 212 is substantially the same as the thickness of the semiconductor layer 200S ( Fig.21 ). The semiconductor layer 200S is divided by an insulating region 212. The through electrodes 120E and 121E and the through electrode TGV are provided in the insulating region 212. The insulating region 212 includes, for example, silicon oxide.

[0200] The through electrodes 120E and 121E are provided in such a manner as to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings (first wirings W1, second wirings W2, third wirings W3, and fourth wirings W4 to be described later) of the wiring layer 200T. The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends thereof are connected to the pad portions 120 and 121 ( Fig.21 ). The through electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210. That is, the floating diffusion region FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 120E. The through electrode 121E is used to electrically connect the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the VSS contact area 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the through electrode 121E.

[0201] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. The through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG ( Fig.21 ). This through electrode TGV is used to electrically connect the transfer gate TG (transfer gates TG1, TG2, TG3, and TG4) of each of the pixels 541A, 541B, 541C, and 541D to the wiring layer 200T (part of the row drive signal line 542, specifically, Fig.25 That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and a driving signal is sent to each transfer transistor TR (transmission transistors TR1, TR2, TR3, and TR4).

[0202] The insulating region 212 is a region for insulating the through electrodes 120E and 121E and the through electrode TGV for electrically connecting the first substrate 100 and the second substrate 200 to each other from the semiconductor layer 200S. For example, the through electrodes 120E and 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to two pixel circuits 210 are arranged in the insulating region 212 provided between two pixel circuits 210 (pixel common unit 539) adjacent to each other in the H direction. For example, the insulating region 212 is provided to extend in the V direction ( Fig.23 and Fig.24 Here, by designing the arrangement of the horizontal portion TGb of the transfer gate TG, the through electrode TGV is arranged so that the position of the through electrode TGV in the H direction is close to the position of the through electrodes 120E and 121E in the H direction compared to the position of the vertical portion TGa ( Fig.22A , Fig.24). For example, the through electrode TGV is arranged at approximately the same position as the through electrodes 120E and 121E in the H direction. Therefore, the through electrodes 120E and 121E and the through electrode TGV can be arranged together in the insulating region 212 extending in the V direction. As another arrangement example, it is also conceivable to arrange the horizontal portion TGb only in the area overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, for example, the through electrode TGV is arranged in the approximately central part of the H direction and the V direction of each pixel 541. At this time, the position of the through electrode TGV in the H direction greatly deviates from the position of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is arranged around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate them from the adjacent semiconductor layer 200S. In the case where the position of the through electrode TGV in the H direction and the position of the through electrodes 120E and 121E in the H direction are greatly separated from each other, it is necessary to independently set the insulating region 212 around each of the through electrodes 120E, 121E and TGV. Therefore, the semiconductor layer 200S is finely divided. In contrast, the layout in which the through electrodes 120E and 121E and the through electrode TGV are commonly arranged in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. Therefore, a large area of ​​the semiconductor element formation region in the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0203] As reference Fig.19 As described above, the pixel sharing unit 539 has a structure in which the floating diffusion regions FD provided in each of the plurality of pixels 541 are electrically connected, and the plurality of pixels 541 share one pixel circuit 210. In addition, the floating diffusion regions FD are electrically connected to each other through the pad portion 120 provided on the first substrate 100 ( Fig.21 and Fig. 22B ). The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via a through electrode 120E. As another structural example, it is also conceivable that the electrical connection portion between the floating diffusion regions FD is provided on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes respectively connected to the floating diffusion regions FD1, FD2, FD3 and FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S is increased, and the insulating region 212 that insulates the periphery of these through electrodes is increased. In contrast, in the structure in which the pad portion 120 is provided on the first substrate 100 ( Fig.21 and Fig. 22B), the number of through electrodes can be reduced, and the insulating region 212 can be reduced. Therefore, a large area of ​​the semiconductor element formation region in the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0204] The element isolation region 213 is provided on the front side of the semiconductor layer 200S. The element isolation region 213 has a shallow trench isolation (STI) structure. In the element isolation region 213, the semiconductor layer 200S is excavated in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and an insulating film is buried in the excavation. The insulating film includes, for example, silicon oxide. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (the deep part of the semiconductor layer 200S).

[0205] Here, we will refer to Fig.22A , Fig. 22B and Fig.23 The difference between the outer shape of the pixel common unit 539 on the first substrate 100 (outer shape in the substrate plane direction) and the outer shape of the pixel common unit 539 on the second substrate 200 is described.

[0206] In the solid-state imaging device 1, the pixel common unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel common unit 539 provided on the first substrate 100 is different from the outer shape of the pixel common unit 539 provided on the second substrate 200.

[0207] exist Fig.22A and Fig. 22B , the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by a single-dot chain line, and the outer shape of the pixel common unit 539 is indicated by a bold line. For example, the pixel common unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel common unit 539 of the first substrate 100 includes four pixels 541 in two adjacent rows × two columns, and the pixel common unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array section 540, such a pixel common unit 539 is arranged adjacent to each other with a two-pixel pitch in the H direction (corresponding to the pitch of the two pixels 541) and a two-pixel pitch in the V direction.

[0208] exist Fig.23 and Fig.24, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by a single-dot chain line, and the outer shape of the pixel common unit 539 is indicated by a thick line. For example, the outer shape of the pixel common unit 539 of the second substrate 200 is smaller than that of the pixel common unit 539 of the first substrate 100 in the H direction, and is larger than that of the pixel common unit 539 of the first substrate 100 in the V direction. For example, the pixel common unit 539 of the second substrate 200 is formed in a size (area) corresponding to one pixel in the H direction, and is formed in a size corresponding to four pixels in the V direction. That is, the pixel common unit 539 of the second substrate 200 is formed in a size corresponding to pixels of 1 row×4 columns arranged adjacently, and the pixel common unit 539 of the second substrate 200 has a substantially rectangular outer shape.

[0209] For example, in each pixel circuit 210, a selection transistor SEL, an amplifier transistor AMP, a reset transistor RST, and an FD conversion gain switching transistor FDG ( Fig.23 As described above, by setting the outer shape of each pixel circuit 210 to be approximately rectangular, it is possible to Fig.23 Four transistors (select transistor SEL, amplifier transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) are arranged side by side in the V direction in the direction of the V axis. Therefore, the drain of the amplifier transistor AMP and the drain of the reset transistor RST can be shared by one diffusion region (a diffusion region connected to the power supply line VDD). For example, the formation region of each pixel circuit 210 can be set to a substantially square shape (refer to the later described Fig.36 ). In this case, the two transistors are arranged in one direction, and it is difficult to share the drain of the amplifier transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by setting the formation area of ​​the pixel circuit 210 to a substantially rectangular shape, the four transistors can be easily arranged close to each other, and the formation area of ​​the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. In addition, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, the formation area of ​​the amplifier transistor AMP can be increased to suppress noise.

[0210] For example, near the surface of the semiconductor layer 200S, in addition to the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 includes, for example, a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. The VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG across the element isolation region 213 ( Fig.23 ).

[0211] Next, we will refer to Fig. 22B and Fig.23 The positional relationship between the pixel common unit 539 disposed on the first substrate 100 and the pixel common unit 539 disposed on the second substrate 200 is described. For example, one of the two pixel common units 539 arranged along the V direction on the first substrate 100 (for example, Fig. 22B The pixel sharing unit 539 (on the upper side of the paper) is connected to one of the two pixel sharing units 539 arranged along the H direction on the second substrate 200 (for example, in Fig.23 For example, the other of the two pixel sharing units 539 arranged along the V direction on the first substrate 100 (for example, Fig. 22B The pixel sharing unit 539 is connected to the other pixel sharing unit 539 (eg, Fig.23 on the right side of the paper).

[0212] For example, in two pixel common units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel common unit 539 is substantially equal to the layout obtained by inverting the other pixel common unit 539 in the V direction and the H direction. Hereinafter, the effect obtained by this layout will be described.

[0213] In the two pixel sharing units 539 arranged along the V direction of the first substrate 100, each pad portion 120 is arranged at the central portion of the outer shape of the pixel sharing unit 539, that is, the central portion of the pixel sharing unit 539 in the V direction and the H direction ( Fig. 22B). On the other hand, as described above, since the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape that is longer in the V direction, for example, the amplifier transistor AMP connected to the pad portion 120 is arranged at a position offset in the V direction from the center of the pixel sharing unit 539 on the paper. For example, when the internal layout of two pixel sharing units 539 arranged along the H direction of the second substrate 200 is the same, the distance between the amplifier transistor AMP of one pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper of FIG. 22) becomes relatively short. However, the distance between the amplifier transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 20 of the pixel sharing unit 539 on the lower side of the paper of FIG. 22) becomes longer. Therefore, the area of ​​the wiring required to connect the amplifier transistor AMP and the pad portion 120 increases, and the wiring layout of the pixel sharing unit 539 becomes complicated. This affects the miniaturization of the solid-state imaging device 1.

[0214] On the other hand, by reversing the internal layout of the two pixel common units 539 arranged along the H direction of the second substrate 200 at least in the V direction, the distance between the amplifier transistor AMP in both of the two pixel common units 539 and the pad portion 120 can be shortened. Therefore, compared with a configuration in which the internal layout of the two pixel common units 539 arranged along the H direction of the second substrate 200 is the same, it is easy to miniaturize the solid-state imaging device 1. Note that the planar layout of each of the plurality of pixel common units 539 of the second substrate 200 is different in the V direction. Fig.23 The range shown is bilaterally symmetrical, but includes Fig.24 The layout of the first wiring layer W1 to be described later is left-right asymmetric.

[0215] In addition, preferably, the internal layout of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 is also reversed along the H direction. The reason will be described below. Fig.24 As shown, each of the two pixel sharing units 539 arranged along the H direction on the second substrate 200 is connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged at the central portion along the H direction of the two pixel sharing units 539 arranged along the H direction on the second substrate 200 (between the two pixel sharing units 539 arranged along the H direction). Therefore, by reversing the internal layout of the two pixel sharing units 539 arranged along the H direction of the second substrate 200 in the H direction, the distance between each of the plurality of pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, it is easier to miniaturize the solid-state imaging device 1.

[0216] In addition, the position of the outline of the pixel common unit 539 of the second substrate 200 may not be aligned with the position of any outline of the pixel common unit 539 of the first substrate 100. For example, one of the two pixel common units 539 arranged along the H direction on the second substrate 200 (e.g., Fig.24 In the pixel sharing unit 539 on the left side of the paper, one (for example, Fig.24 The outline of the pixel common unit 539 (eg, Fig. 22B In addition, the other of the two pixel sharing units 539 arranged along the H direction on the second substrate 200 (for example, Fig.24 In the pixel sharing unit 539 on the right side of the paper, the other pixel sharing unit 539 in the V direction (for example, Fig.24 The outline of the pixel common unit 539 (eg, Fig. 22B As described above, by arranging the pixel common unit 539 of the second substrate 200 and the pixel common unit 539 of the first substrate 100 with each other, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the solid-state imaging device 1.

[0217] In addition, the positions of the contour lines of the plurality of pixel sharing units 539 of the second substrate 200 may not be aligned. For example, two pixel sharing units 539 arranged along the H direction of the second substrate 200 are arranged so that the positions of the contour lines in the V direction are offset. Therefore, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the solid-state imaging device 1.

[0218] Will refer to Fig. 22B and Fig.24 The pixel common unit 539 in the pixel array section 540 is described as being repeatedly arranged. The pixel common unit 539 of the first substrate 100 has a size of two pixels 541 in the H direction and a size of two pixels 541 in the V direction ( Fig. 22B). For example, in the pixel array portion 540 of the first substrate 100, the pixel sharing units 539 having a size corresponding to four pixels 541 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch corresponding to two pixels 541) and at a pitch of two pixels in the V direction (a pitch corresponding to two pixels 541). Alternatively, the pixel array portion 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539, wherein the two pixel sharing units 539 are arranged adjacent to each other in the V direction. For example, in the pixel array portion 540 of the first substrate 100, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch corresponding to two pixels 541) and at a pitch of four pixels in the V direction (a pitch corresponding to four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( Fig.24 ). For example, the pixel array portion 540 of the second substrate 200 is provided with a pair of pixel sharing units 539, which include two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and arranged offset in the V direction. In the pixel array portion 540 of the second substrate 200, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other without gaps in the H direction at a pitch of two pixels (corresponding to the pitch of two pixels 541) and in the V direction at a pitch of four pixels (corresponding to the pitch of four pixels 541). This repeated arrangement of the pixel sharing units 539 enables the pixel sharing units 539 to be arranged without gaps. Therefore, it is easy to miniaturize the solid-state imaging device 1.

[0219] The amplifier transistor AMP preferably has a three-dimensional structure such as a fin type, for example. Fig.21 ). Therefore, the size of the effective gate width is increased, and noise can be suppressed. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplifier transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0220] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221, for example, contacts the surface of the semiconductor layer 200S and covers the entire surface of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4) are separated by the interlayer insulating film 222. The interlayer insulating film 222 includes, for example, silicon oxide.

[0221] In the wiring layer 200T, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 are sequentially provided from the semiconductor layer 200S side, and these layers are insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 is provided with a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 and the lower layer thereof. The connection portion is a portion in which a conductive material is buried in a connection hole provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 is provided with a connection portion 218V that connects the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of the connection portion that connects the elements of such a second substrate 200 is different from the aperture of the through electrodes 120E and 121E and the through electrode TGV. Specifically, the aperture of the connection hole connecting the element of the second substrate 200 is preferably smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV. The reason will be described below. The depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E and 121E and the through electrode TGV. Therefore, the connection portion can easily fill the conductive material into the connection hole compared with the through electrodes 120E and 121E and the through electrode TGV. By making the aperture of the connection portion smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV, the solid-state imaging device 1 can be easily miniaturized.

[0222] For example, the through electrode 120E is connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG) through the first wiring layer W1. The first wiring layer W1 connects, for example, the through electrode 121E and the connection portion 218V, whereby the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S are electrically connected.

[0223] Next, we will refer to Figure 25 to Figure 27 The planar structure of the wiring layer 200T will be described. Fig.25 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Fig.26 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Fig. 27 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0224] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction). Fig.26 ). These wirings correspond to the reference Fig.19 The multiple row drive signal lines 542 are illustrated. The wirings TRG1, TRG2, TRG3 and TRG4 are used to send drive signals to the transmission gates TG1, TG2, TG3 and TG4, respectively. The wirings TRG1, TRG2, TRG3 and TRG4 are connected to the transmission gates TG1, TG2, TG3 and TG4, respectively, via the second wiring layer W2, the first wiring layer W1 and the through-electrode 120E. The wiring SELL is used to send a drive signal to the gate of the selection transistor SEL, the wiring RSTL is used to send a drive signal to the gate of the reset transistor RST, and the wiring FDGL is used to send a drive signal to the gate of the FD conversion gain switching transistor FDG. The wirings SELL, RSTL and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0225] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 ( Fig. 27 ). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0226] The contact portions 201 and 202 may be disposed at positions overlapping with the pixel array portion 540 in a plan view (eg, Fig.18), or may even be in the peripheral portion 540B outside the pixel array portion 540 (e.g., as Fig.21 ). The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side). The contact portions 201 and 202 are made of, for example, a metal such as copper (Cu) and aluminum (Al). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding between the second substrate 200 and the third substrate 300.

[0227] Fig.21 2 shows an example of a peripheral circuit disposed in the peripheral portion 540B of the second substrate 200. The peripheral circuit may include a portion of the row driving portion 520, a portion of the column signal processing portion 550, and the like. Fig.18 As shown, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200 , and the connection holes H1 and H2 may be arranged near the pixel array portion 540 .

[0228] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in sequence from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S includes a silicon substrate. The circuit is arranged in the portion of the front side of the semiconductor layer 300S. Specifically, for example, at least a portion of the input portion 510A, the row drive portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B is arranged in the portion of the front side of the semiconductor layer 300S. The wiring layer 300T arranged between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers isolated by the interlayer insulating film, and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface on the second substrate 200 side), the contact portion 301 contacts the contact portion 201 of the second substrate 200, and the contact portion 302 contacts the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to the circuit formed in the semiconductor layer 300S (for example, at least one of the input portion 510A, the row driving portion 520, the timing control portion 520, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B). The contact portions 301 and 302 are composed of, for example, a metal such as copper (Cu) and aluminum (Al). For example, the external terminal TA is connected to the input portion 510A via the connection hole H1, and the external terminal TB is connected to the output portion 510B via the connection hole H2.

[0229] Here, features of the solid-state imaging device 1 will be described.

[0230] Generally, the solid-state imaging device 1 mainly includes a photodiode PD and a pixel circuit. Here, in the case of increasing the area of ​​the photodiode, the charge generated as a result of photoelectric conversion increases, and thus the signal-to-noise ratio (S / N ratio) of the pixel signal is improved, and the solid-state imaging device can output better image data (image information). On the other hand, in the case of increasing the size of the transistor included in the pixel circuit (particularly, the size of the amplifying transistor), the noise generated by the pixel circuit is reduced, and thus the signal-to-noise ratio of the imaging signal is improved, and the solid-state imaging device can output better image data (image information).

[0231] However, if the area of ​​the photodiode PD is increased in a limited area of ​​the semiconductor substrate of the imaging device in which the photodiode PD and the pixel circuit are arranged in the same semiconductor substrate, the size of the transistor included in the pixel circuit will be reduced. In addition, if the size of the transistor included in the pixel circuit is increased, the area of ​​the photodiode PD will be reduced.

[0232] In order to solve these problems, for example, the solid-state imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged in a manner overlapping the photodiode PD. Therefore, it is possible to make the area of ​​the photodiode PD as large as possible within the limited area of ​​the semiconductor substrate, and to make the size of the transistor included in the pixel circuit 210 as large as possible. Therefore, the S / N ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better image data (image information).

[0233] When a structure is implemented in which a plurality of pixels 541 share one pixel circuit 210 and the pixel circuits are superimposed and arranged on the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion region FD of each of the plurality of pixels 541. In order to ensure a large area of ​​the semiconductor layer 200S in which the pixel circuit 210 is formed, for example, a connection wiring in which the plurality of wirings extending are connected to each other and integrated into one may be formed. Similarly, for a plurality of wirings extending from the VSS contact region 118, a connection wiring in which the plurality of wirings extending are connected to each other and integrated into one may be formed.

[0234] For example, in the case where a connection wiring that interconnects a plurality of wirings extending from the floating diffusion regions FD of each of the plurality of pixels 541 is formed in the semiconductor layer 200S forming the pixel circuit 210, it is conceivable that the area for forming the transistor included in the pixel circuit 201 is reduced. Similarly, in the case where a connection wiring that interconnects a plurality of wirings extending from the VSS contact regions 118 of each of the plurality of pixels 541 and combines the plurality of wirings into one is formed on the semiconductor layer 200S forming the pixel circuit 210, it is conceivable that the area for forming the transistor included in the pixel circuit 210 is reduced.

[0235] In order to solve these problems, for example, the solid-state imaging device 1 of the present embodiment may have a structure in which a plurality of pixels 541 share a pixel circuit 210, and the shared pixel circuit 210 is arranged to overlap on the photodiode PD, and a structure in which a connection wiring that connects the floating diffusion regions FD of each of the plurality of pixels 541 to each other and integrates them into one and a connection wiring that connects the VSS contact regions 118 included in each of the plurality of pixels 541 to each other and integrates them into one are provided on the first substrate 100.

[0236] Here, in the case of using the above-mentioned second manufacturing method as a manufacturing method for providing connection wirings that connect the floating diffusion regions FD of each of the plurality of pixels 541 to each other and integrate them into one and connection wirings that connect the VSS contact regions 118 of each of the plurality of pixels 541 to each other and integrate them into one on the first substrate 100, for example, it is possible to manufacture a high-quality and high-performance solid-state imaging device 1 using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200. In addition, the connection wirings of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, in the case of using the above-mentioned second manufacturing method, an electrode connected to the floating diffusion region FD and an electrode connected to the VSS contact region 118 are respectively provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding interfaces of the first substrate 100 and the second substrate 200. In addition, it is preferable to expand the electrodes formed on the surfaces of the two substrates so that when the first substrate 100 and the second substrate 200 are combined together, even if a positional deviation occurs between the electrodes provided on the surfaces of the two substrates, the electrodes formed on the two substrates are in contact with each other. In this case, it is conceivable that it becomes difficult to arrange the above-mentioned electrodes in a limited area of ​​each pixel included in the solid-state imaging device 1 .

[0237] In order to solve the problem that a large electrode is required at the bonding boundary surface between the first substrate 100 and the second substrate 200, for example, the solid-state imaging device 1 of the present embodiment can use the above-mentioned first manufacturing method as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to overlap on the photodiode PD. Therefore, it is easy to align the elements formed on the first substrate 200 and the second substrate 100, and it is possible to manufacture a high-quality and high-performance solid-state imaging device 1. In addition, it is possible to provide a unique structure generated by using this manufacturing method. That is, the solid-state imaging device includes a structure in which a semiconductor layer 100S and a wiring layer 100T of a first substrate 100 and a semiconductor layer 200S and a wiring layer 200T of a second substrate 200 are stacked in sequence, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked face to back; and through electrodes 120E and 121E that penetrate the semiconductor layer 200S, the wiring layer 100T of the first substrate 100 and reach the surface of the semiconductor layer 100S of the first substrate 100 from the front side of the semiconductor layer 200S of the second substrate 100.

[0238] In a structure in which connection wiring that connects the floating diffusion regions FD of a plurality of pixels 541 to one another and integrates them into one, and connection wiring that connects the VSS contact regions 118 of a plurality of pixels 541 to one another and integrates them into one are provided on a first substrate 100, when the structure and a second substrate 200 are stacked using a first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the influence of heat treatment required when forming active elements included in the pixel circuit 210 will reach the above-mentioned connection wiring formed on the first substrate 100.

[0239] Therefore, in order to solve the problem that the above-mentioned connection wiring is affected by the heat treatment when the above-mentioned active elements are formed, it is desirable that the solid-state imaging device 1 of the present embodiment uses a conductive material having high heat resistance as a connection wiring that connects the floating diffusion regions FD of the plurality of pixels 541 to each other and integrates them into one and a connection wiring that connects the VSS contact regions 118 of the plurality of pixels to each other and integrates them into one. Specifically, as the conductive material having high heat resistance, a material having a higher melting point than the melting point of at least a part of the wiring material included in the wiring layer 200T of the second substrate 200 can be used.

[0240] As described above, for example, the solid-state imaging device 1 of the present embodiment includes: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked in a face-to-back manner (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring film 200T of the second substrate 200 are stacked in sequence); (2) a structure in which the through electrodes 120E and 121E are provided from the front side of the semiconductor layer 200S of the second substrate 200, penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the connecting wiring that connects the floating diffusion regions FD included in the plurality of pixels 541 to each other and integrates them into one and the connecting wiring that connects the VSS contact regions 118 included in the plurality of pixels 541 to each other and integrates them into one are made of a conductive material having high heat resistance. Therefore, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 may be provided with a connection wiring that connects the floating diffusion regions FD included in the plurality of pixels 541 to one another and integrates them into one, and a connection wiring that connects the VSS contact regions 118 included in the plurality of pixels 541 to one another and integrates them into one.

[0241] [Operation of the Solid-State Imaging Device 1] Next, we will refer to Fig.28 and Fig.29 The operation of the solid-state imaging device 1 will be described. Fig.28 and Fig.29 In Fig.18 Arrows indicating the paths of each signal are added. Fig.28 In FIG. 1 , arrows indicate paths of input signals, power supply potential, and reference potential input from the outside to the solid-state imaging device 1. Fig.29, a signal path of a pixel signal output from the solid-state imaging device 1 to the outside is indicated by an arrow. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the solid-state imaging device 1 via the input portion 510A is transmitted to the row driving portion 520 of the third substrate 300, and the row driving portion 520 creates a row driving signal. The row driving signal is sent to the second substrate 200 via the contact portions 301 and 201. In addition, the row driving signal reaches each pixel common unit 539 of the pixel array portion 540 via the row driving signal line 542 in the wiring layer 200T. Among the row driving signals reaching the pixel common unit 539 of the second substrate 200, a driving signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven ( Fig.28 ). In addition, the power supply potential and the reference potential supplied from the outside of the solid-state imaging device 1 to the input portion 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contacts 301 and 201, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, for each pixel common unit 539, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is sent to the pixel circuit 210 of the second substrate 200 via the through electrode 120E. A pixel signal based on the pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 202 and 302. The pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300 and then output to the outside via the output section 510B.

[0242] [Effect] In the present embodiment, the pixels 541A, 541B, 541C, and 541D (pixel common unit 539) and the pixel circuit 210 are arranged on different substrates (first substrate 100 and second substrate 200). Therefore, compared with the case where the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate, the area of ​​the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be enlarged. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased, and the transistor noise of the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the solid-state imaging device 1 can output better pixel data (image information). In addition, the solid-state imaging device 1 can be miniaturized (in other words, the pixel size can be reduced, and the size of the solid-state imaging device can be reduced). The solid-state imaging device 1 can increase the number of pixels per unit area by reducing the pixel size, and can output a high-quality image.

[0243] In addition, in the solid-state imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other through the through electrodes 120E and 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting the first substrate 100 and the second substrate 100 by through wiring (for example, through silicon via (TSV)) penetrating the semiconductor layer can be considered. Compared with this method, by providing the through electrodes 120E and 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, the pixel size can be reduced, and the solid-state imaging device 1 can be further miniaturized. In addition, by further reducing the area of ​​each pixel, the resolution can be further improved. Without reducing the chip size, the formation area of ​​the pixels 541A, 541B, 541C and 541D and the pixel circuit 210 can be enlarged. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased, and the noise of the transistor included in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0244] Furthermore, in the solid-state imaging device 1, the pixel circuit 210 and the column signal processing section 550 and the image signal processing section 560 are provided on different substrates (the second substrate 200 and the third substrate 300). Therefore, compared with the case where the pixel circuit 210 and the column signal processing section 550 and the image signal processing section 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the area of ​​the column signal processing module 550 and the image signal processing section 560 can be expanded. Therefore, the noise generated by the column signal processing section 550 can be reduced, and an advanced image processing circuit can be installed by the image signal processing section 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0245] In addition, in the solid-state imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. In addition, the contact sections 201, 202, 301 and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 201, 202, 301 and 302 can be freely laid out without being disturbed by the layout of various wirings provided in the pixel array. Therefore, the contact sections 201, 202, 301 and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. For example, by using the contact sections 201, 202, 301 and 302, the column signal processing section 550 and the image signal processing section 560 have a higher degree of freedom in layout. Therefore, the noise generated in the column signal processing section 550 can be reduced, and an advanced image processing circuit can be installed through the image signal processing section 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0246] In addition, in the solid-state imaging device 1, the pixel isolation portion 117 penetrates the semiconductor layer 100S. Therefore, even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is shortened due to the miniaturization of the area per pixel, color mixing between the pixels 541A, 541B, 541C, and 541D can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0247] In addition, in the solid-state imaging device 1, the pixel circuit 210 is provided for each pixel common unit 539. Therefore, compared with the case where the pixel circuit 210 is provided in each of the pixels 541A, 541B, 541C, and 541D, the formation area of ​​the transistors (amplifier transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) constituting the pixel circuit 210 can be expanded. For example, noise can be suppressed by increasing the formation area of ​​the amplifier transistor AMP. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0248] Furthermore, in the solid-state imaging device 1, a pad portion 120 electrically connecting the floating diffusion regions FD (floating diffusion regions FD1, FD2, FD3, and FD4) of four pixels (pixels 541A, 541B, 541C, and 541D) is provided on the first substrate 100. Therefore, compared with the case where the pad portion 120 is provided on the second substrate 200, the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 100 can be reduced. Therefore, the insulating region 212 can be made smaller, and a sufficient size can be ensured for the transistor formation region (semiconductor layer 200S) constituting the pixel circuit 210. Therefore, the noise of the transistor included in the pixel circuit 210 can be reduced, the signal-to-noise ratio of the pixel signal can be improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0249] Hereinafter, a modification of the body imaging device 1 according to the above-described embodiment will be described. In the following modification, the same configuration as that of the above-described embodiment is given the same reference numeral.

[0250] <2. Modification 1> Figure 30 to Figure 34 A modification example of the planar configuration of the solid-state imaging device 1 according to the above-described embodiment is shown. Fig.30 The planar structure near the surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and corresponds to the above-described embodiment. Fig.23 . Fig.31 The configurations of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 are schematically shown, and correspond to the configurations of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100. Fig.24 . Fig.32 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.25 . Fig.33 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.26. Fig.34 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the above-described embodiment. Fig. 27 .

[0251] In this variation, if Fig.31 As shown, it has such a structure that, of the two pixel sharing units 539 arranged along the H direction on the second substrate 200, the internal layout of one (for example, the right side of the paper) pixel sharing unit 539 is the internal layout of the other (for example, the left side of the paper) pixel sharing unit 539 is reversed only in the H direction. In addition, the offset between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 in the V direction is greater than the offset described in the above embodiment ( Fig.24 ). In this way, by increasing the offset in the V direction, the distance between the amplifier transistor AMP of the other pixel common unit 539 and the pad portion 120 connected thereto (the other (lower side of the paper) pad portion 120 of the two pixel common units 539 arranged in the V direction shown in FIG. 22) can be reduced. With such a layout, Figure 30 to Figure 34 The modified example 1 of the solid-state imaging device 1 shown can make the plan layout area of ​​the two pixel common units 539 arranged in the H direction the same as the area of ​​the pixel common units 539 of the second substrate 200 described in the above embodiment, without reversing the plan layout of the two pixel common units 539 in the V direction. Note that the plan layout of the pixel common units 539 of the first substrate 100 is different from the plan layout described in the above embodiment ( Fig.22A , Fig. 22B ). Therefore, the solid-state imaging device 1 of this modification can obtain effects similar to those of the solid-state imaging device 1 described in the above embodiment. The arrangement of the pixel common unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0252] <3. Modification 2> Figures 35 to 40 A modification example of the planar configuration of the solid-state imaging device 1 according to the above-described embodiment is shown. Fig.35 The planar structure of the first substrate 100 is schematically shown, and corresponds to the planar structure of the first substrate 100 described in the above embodiment. Fig.22A . Fig.36 The planar structure near the surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and corresponds to the above-described embodiment. Fig.23 . Fig.37 The configurations of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 are schematically shown, and correspond to the configurations of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100. Fig.24 . Fig.38An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.25 . Fig.39 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.26 . Fig.40 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the above-described embodiment. Fig. 27 .

[0253] In this modification, the outer shape of each pixel circuit 210 has a substantially square planar shape ( Fig.36 In this respect, the planar configuration of the solid-state imaging device 1 of this modification example is different from the planar configuration of the solid-state imaging device 1 described in the above-mentioned embodiment.

[0254] For example, as described in the above embodiment, the pixel common unit 539 of the first substrate 100 is formed on a pixel region of two rows×two columns and has a substantially square planar shape ( Fig.35 ). For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixel 541A and the pixel 541C of one pixel column extend from a position overlapping with the vertical portion TGa along the H direction toward the direction of the central portion of the pixel sharing unit 539 (more specifically, the direction toward the outer edges of the pixels 541A, 541C and the direction toward the central portion of the pixel sharing unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixel 541B and the pixel 541D of the other pixel column extend from a position overlapping with the vertical portion TGa along the H direction toward the outside of the pixel sharing unit 539 (more specifically, the direction toward the outer edges of the pixels 541B and 541D and the direction toward the outside of the pixel sharing unit 539). The pad portion 120 connected to the floating diffusion region FD is provided in the central portion of the pixel sharing unit 539 (the central portion of the pixel sharing unit 539 in the H direction and the V direction), and the pad portion 121 connected to the VSS contact region 118 is provided in the pixel sharing unit 539 ( Fig.35 At least the end in the H direction (in the H direction and V direction).

[0255] As another arrangement example, it is also conceivable to provide the horizontal portion TGb of the transfer gates TG1, TG2, TG3, and TG4 only in the region facing the vertical portion TGa. In this case, as described in the above embodiment, the semiconductor layer 200S may be finely divided. Therefore, it is difficult to form a large transistor of the pixel circuit 210. On the other hand, when the horizontal portion TGb of the transfer gates TG1, TG2, TG3, and TG4 extends along the H direction from a position overlapping with the vertical portion TGa as in the above modification example, the width of the semiconductor layer 200S can be increased as described in the above embodiment. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 in the H direction can be arranged close to the position of the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 in the H direction can be arranged close to the position of the through electrode 121E in the H direction ( Fig.37 ). Therefore, as described in the above embodiment, the width of the semiconductor layer 200S extending in the V direction (the size in the H direction) can be increased. Therefore, the size of the transistor of the pixel circuit 210, in particular, the size of the amplifier transistor AMP can be increased. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the solid-state imaging device 1 can output better pixel data (image information).

[0256] For example, the pixel sharing unit 539 of the second substrate 200 has approximately the same size as the pixel sharing unit 539 of the first substrate 100 in the H direction and the V direction, and is provided on an area corresponding to, for example, a pixel area of ​​approximately two rows × two columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction. One semiconductor layer 200S in which the selection transistor SEL and the amplifier transistor AMP are provided and one conductor layer 200S in which the FD conversion gain switching transistor FDG and the reset transistor RST are provided are arranged in the H direction with the insulating region 212 therebetween. The insulating region 212 extends in the V direction ( Fig.36 ).

[0257] Here, we will refer to Fig.36 and Fig.37 The appearance of the pixel sharing unit 539 of the second substrate 200 is described. For example, Fig.35 The pixel sharing unit 539 of the first substrate 100 shown is connected to one side ( Fig.37 The amplification transistor AMP and the selection transistor SEL are arranged on the left side of the paper, and the other side of the pad portion 120 in the H direction ( Fig.37 The outer shape of the pixel common unit 539 of the second substrate 200 including the amplifying transistor AMP, the selecting transistor SEL, the FD conversion gain switching transistor FDG and the reset transistor RST is determined by the following four outer edges.

[0258] The first outer edge is one end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP ( Fig.37 The first outer edge is set at the end of the upper side of the paper of the amplification transistor AMP included in the pixel sharing unit 539 and the side of the pixel sharing unit 539 in the V direction ( Fig.37 The first outer edge is disposed at the center of the element isolation region 213 in the V direction between the amplifying transistor AMP and the selecting transistor SEL. The second outer edge is the other end in the V direction of the semiconductor layer 200S including the selecting transistor SEL and the amplifying transistor AMP. Fig.37 The second outer edge is set in the selection transistor SEL included in the pixel sharing unit 539 and the other side ( Fig.37 The second outer edge is disposed at the center of the element isolation region 213 in the V direction between the selection transistor SEL and the amplifier transistor AMP. The third outer edge is the other end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. Fig.37 The third outer edge is set to the FD conversion gain switching transistor FDG included in the pixel sharing unit 539 and the other side ( Fig.37 The third outer edge is disposed at the center of the element isolation region 213 in the V direction between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is one end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. Fig.37 The fourth outer edge is set on the reset transistor RST included in the pixel sharing unit 539 and one side of the pixel sharing unit 539 in the V direction ( Fig.37More specifically, the fourth outer edge is disposed at the center portion in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0259] In the outer shape of the pixel common unit 539 of the second substrate 200 including such first, second, third and fourth outer edges, the third and fourth outer edges are arranged to be shifted toward one side of the V direction relative to the first and second outer edges (in other words, offset to one side in the V direction). By using this layout, the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close to the pad portion 120 as possible. Therefore, the area of ​​the wiring connecting them is reduced, and the solid-state imaging device 1 can be easily miniaturized. Note that the VSS contact area 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplifier transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, a plurality of pixel circuits 210 have the same arrangement.

[0260] The solid-state imaging device 1 including such a second substrate 200 can also obtain effects similar to those described in the above embodiment. The arrangement of the pixel common unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0261] <4. Modification 3> Figure 41 to Figure 46 A modification example of the planar configuration of the solid-state imaging device 1 according to the above-described embodiment is shown. Fig.41 The planar structure of the first substrate 100 is schematically shown, and corresponds to the planar structure of the first substrate 100 described in the above embodiment. Fig. 22B . Fig.42 The planar structure near the surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and corresponds to the above-described embodiment. Fig.23 . Fig.43 The configurations of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 are schematically shown, and correspond to the configurations of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100. Fig.24 . Fig.44 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.25 . Fig.45 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.26 . Fig.46An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the above-described embodiment. Fig. 27 .

[0262] In this modification, the semiconductor layer 200S of the second substrate 200 extends along the H direction ( Fig.43 ). That is, it roughly corresponds to the above Fig.36 The planar structure of the solid-state imaging device 1 shown in FIG. 1 is a structure rotated by 90 degrees.

[0263] For example, as described in the above embodiment, the pixel common unit 539 of the first substrate 100 is formed on a pixel region of two rows×two columns and has a substantially square planar shape ( Fig.41 ). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixel 541A and the pixel 541B of one pixel row extend toward the central portion of the pixel sharing unit 539 in the V direction, and the transfer gates TG3 and TG4 of the pixel 541C and the pixel 541D of another pixel row extend in the outer direction of the pixel sharing unit 539 in the V direction. The pad portion 120 connected to the floating diffusion region FD is provided in the central portion of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is provided at the ( Fig.41 At this time, the positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 in the V direction are close to the position of the through electrode 120E in the V direction, and the positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 in the V direction are close to the position of the through electrode 121E in the V direction ( Fig.43 ). Therefore, for reasons similar to those described in the above embodiment, the width of the semiconductor layer 200S extending in the H direction (the dimension in the V direction) can be increased. Therefore, the size of the amplifier transistor AMP can be increased and noise can be suppressed.

[0264] In each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged at a position adjacent to the selection transistor SEL in the V direction across the insulating region 212 ( Fig.42 ). The FD conversion gain switching transistor FDG is arranged side by side with the reset transistor RST along the H direction. The VSS contact region 218 is provided in the insulating region 212 in an island shape. For example, the third wiring layer W3 extends along the H direction ( Fig.45 ), and the fourth wiring layer W4 extends along the V direction ( Fig.46 ).

[0265] The solid-state imaging device 1 including such a second substrate 200 can also obtain effects similar to those described in the above embodiment. The arrangement of the pixel common unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification. For example, the semiconductor layer 200S described in the above embodiment and modification 1 may extend along the H direction.

[0266] <5. Modification 4> Fig.47 Modifications of the cross-sectional configuration of the solid-state imaging device 1 according to the above-described embodiment are schematically shown. Fig.47 Corresponding to the above-mentioned embodiment Fig.18 In this modification, in addition to the contact portions 201, 202, 301 and 302, the solid-state imaging device 1 further includes contact portions 203, 204, 303 and 304 at positions facing the central portion of the pixel array portion 540. In this respect, the solid-state imaging device 1 of this modification is different from the solid-state imaging device 1 described in the above-mentioned embodiment.

[0267] The contact portions 203 and 204 are provided on the second substrate 200 and exposed on the bonding surface with the third substrate 300. The contact portions 303 and 304 are provided on the third substrate 300 and exposed on the bonding surface with the second substrate 200. The contact portion 203 contacts the contact portion 303, and the contact portion 204 contacts the contact portion 304. That is, in the solid-state imaging device 1, in addition to the contact portions 201, 202, 301, and 302, the second substrate 200 and the third substrate 300 are connected by the contact portions 203, 204, 303, and 304.

[0268] Next, we will refer to Fig.48 and Fig.49 The operation of the solid-state imaging device 1 will be described. Fig.48 In FIG. 1 , arrows indicate paths of input signals, power supply potential, and reference potential input from the outside to the solid-state imaging device 1. Fig.49In the figure, the signal path of the pixel signal output from the solid-state imaging device 1 to the outside is indicated by an arrow. For example, the input signal input to the solid-state imaging device 1 via the input portion 510A is transmitted to the row driving portion 520 of the third substrate 300, and the row driving portion 520 creates a row driving signal. The row driving signal is sent to the second substrate 200 via the contact portions 303 and 203. In addition, the row driving signal reaches each pixel common unit 539 of the pixel array portion 540 via the row driving signal line 542 in the wiring layer 200T. Among the row driving signals reaching the pixel common unit 539 of the second substrate 200, the driving signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C and 541D are driven. In addition, the power supply potential and the reference potential supplied from the outside of the solid-state imaging device 1 to the input portion 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via the contacts 303 and 203, and are supplied to the pixel circuit 210 of each pixel common unit 539 via the wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through-electrode 121E. On the other hand, for each pixel common unit 539, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200. The pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 204 and 304. The pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300 and then output to the outside via the output section 510B.

[0269] The solid-state imaging device 1 including such contacts 203, 204, 303 and 304 can also obtain effects similar to those described in the above embodiments. The positions and number of contacts can be changed according to the design of the circuits of the third substrate 300 connected to the wiring via the contacts 303 and 304.

[0270] <6. Modification 5> Fig.50 A modification example of the cross-sectional configuration of the solid-state imaging device 1 according to the above-described embodiment is shown. Fig.50 Corresponding to the above-mentioned embodiment Fig.21In this modification, the transfer transistor TR having a planar structure is provided on the first substrate 100. In this respect, the solid-state imaging device 1 of this modification is different from the solid-state imaging device 1 described in the above embodiment.

[0271] In the transfer transistor TR, the transfer gate TG is composed of only the horizontal portion TGb. In other words, the transfer gate TG does not have the vertical portion TGa, and is disposed to face the semiconductor layer 100S.

[0272] The solid-state imaging device 1 including the transfer transistor TR having such a planar structure can also obtain effects similar to those described in the above-described embodiment. In addition, it is also conceivable that the photodiode PD is formed closer to the surface of the semiconductor layer 100S by providing the planar transfer gate TG on the first substrate, thereby increasing the saturation signal amount (Qs). In addition, it is considered that the method of forming the planar transfer gate TG on the first substrate 100 has fewer manufacturing steps than the method of forming the vertical transfer gate TG on the first substrate, and the photodiode PD is less likely to be adversely affected by the manufacturing process.

[0273] <7. Modification 6> Fig.51 A modification example of the pixel circuit of the solid-state imaging device 1 according to the above-described embodiment is shown. Fig.51 Corresponding to the above-mentioned embodiment Fig.19 In this modification, the pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by a plurality of pixels. In this respect, the solid-state imaging device 1 of this modification is different from the solid-state imaging device 1 described in the above embodiment.

[0274] The solid-state imaging device 1 of this modification is similar to the solid-state imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, the solid-state imaging device 1 according to this modification can also obtain effects similar to those described in the above embodiment.

[0275] <8. Modification 7> Fig.52 1 shows a modified example of the planar structure of the pixel isolation section 117 described in the above embodiment. A gap may be provided in the pixel isolation section 117 surrounding each of the pixels 541A, 541B, 541C, and 541D. That is, the pixel isolation section 117 does not need to surround the entire periphery of the pixels 541A, 541B, 541C, and 541D. For example, the gap of the pixel isolation section 117 is provided near the pad sections 120 and 121 (see Fig. 22B ).

[0276] In the above-mentioned embodiment, it has been described that the pixel isolation portion 117 has a FTI structure that penetrates the semiconductor layer 100S (refer to Fig.21 ), but the pixel isolation part 117 may have a configuration other than the FTI structure. For example, the pixel isolation part 117 may be provided so as not to completely penetrate the semiconductor layer 100S, and may have a so-called deep trench isolation (DTI) structure.

[0277] <9. Application examples> Fig.53 An example of a schematic configuration of an imaging system 7 including the solid-state imaging device 1 according to one of the above-described embodiment and its modified examples is shown.

[0278] For example, the imaging system 7 is an electronic device such as an imaging device such as a digital camera or a video camera, or a portable terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples, a DSP circuit 243, a frame memory 244, a display section 245, a storage section 246, an operation section 247, and a power supply section 248. In the imaging system 7, the solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, the operation section 247, and the power supply section 248 are connected to each other via a bus 249.

[0279] The solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples outputs image data according to incident light. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) output from the solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in units of frames. The display section 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image captured by the solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples. The storage section 246 records the image data of the moving image or the still image captured by the solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation section 247 issues operation commands for various functions of the imaging system 7 according to the user's operation. The power supply section 248 appropriately supplies various power sources used as operation power sources of the solid-state imaging device 1, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246 and the operation section 247 according to one of the above-described embodiments and their modifications to these supply targets.

[0280] Next, an image capturing process in the image capturing system 7 will be described.

[0281] Fig.54 An example of a flowchart of an imaging operation of the imaging system 7 is shown. The user instructs to start imaging by operating the operating unit 247 (step S101). Then, the operating unit 247 sends an imaging command to the solid-state imaging device 1 (step S102). Upon receiving the imaging command, the solid-state imaging device 1 performs imaging by a predetermined imaging method (step S103).

[0282] The solid-state imaging device 1 outputs the image data obtained as a result of imaging to the DSP circuit 243. Here, the image data is data of all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion region FD. The DSP circuit 243 performs predetermined signal processing (for example, noise reduction processing, etc.) based on the image data input from the solid-state imaging device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data subjected to the predetermined signal processing, and the frame memory 244 causes the storage section 246 to store the image data (step S105). In this way, imaging in the imaging system 7 is performed.

[0283] In this application example, the solid-state imaging device 1 according to one of the above-described embodiments and their modifications is applied to an imaging system 7. Therefore, since the solid-state imaging device 1 can be reduced in size or improved in definition, a small or high-definition imaging system 7 can be provided.

[0284] <10. Application examples> [Application Example 1] The technology according to the present invention is applicable to various products. For example, the technology of the present invention can be implemented in the form of a device installed on any type of mobile body such as an automobile, an electric car, a hybrid car, a motorcycle, a bicycle, a personal transportation vehicle, an airplane, a drone, a ship, or a robot.

[0285] Fig.55 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present invention can be applied.

[0286] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.55 In the example shown, the vehicle control system 12000 is provided with a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0287] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force.

[0288] The body system control unit 12020 controls the operation of various types of devices provided on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal light, or a fog light. In this case, a radio wave transmitted from a mobile device that replaces the key or a signal of various types of switches may be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, or a light, etc. of the vehicle.

[0289] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing of objects such as people, vehicles, obstacles, signs, or characters on the road surface, or can perform detection processing of the distance to the above-mentioned objects.

[0290] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared rays.

[0291] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that takes a picture of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0292] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information outside or inside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following driving based on the vehicle-to-vehicle distance, speed keeping driving, vehicle collision warning or vehicle lane departure warning, etc.

[0293] In addition, by controlling the driving force generating device, steering mechanism or braking device, etc. based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform collaborative control aimed at achieving automatic driving, etc., wherein the automatic driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0294] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam, for example, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0295] The audio and video output unit 12052 sends an output signal of at least one of audio and video to an output device capable of visually or auditorily notifying the vehicle's passengers or the outside of the vehicle of the information. Fig.55 In the example of , as the output device, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0296] Fig.56 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0297] exist Fig.56 In the figure, the vehicle 12100 includes cameras 12101, 12102, 12103, 12104 and 12105 as the camera 12031.

[0298] The camera units 12101, 12102, 12103, 12104 and 12105 are, for example, arranged at the front nose, rearview mirror, rear bumper and rear door of the vehicle 12100 and at the upper part of the windshield in the vehicle compartment. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly obtain images on both sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains images behind the vehicle 12100. The front images obtained by the camera units 12101 and 12105 are mainly used to detect the front vehicle, pedestrians, obstacles, traffic lights, traffic signs and lanes, etc.

[0299] Note that Fig.56 , an example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from above is obtained.

[0300] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0301] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100), thereby extracting the nearest three-dimensional object as the leading vehicle, in particular, the three-dimensional object that exists on the driving path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be maintained with the leading vehicle, and perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform cooperative control such as automatic driving that aims to make the vehicle travel autonomously without relying on the operation of the driver.

[0302] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data of the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, electric poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 is difficult to visually identify. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle. In the case where the collision risk is higher than or equal to the set value and therefore there is a possibility of collision, the microcomputer 12051 can output a warning to the driver via the audio speaker 12061 or the display unit 12062, and perform forced deceleration or evasive steering via the drive system control unit 12010 to perform assisted driving for avoiding collision.

[0303] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 is capable of identifying pedestrians, for example, by determining whether there are pedestrians in the camera images of the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following steps: a step of extracting feature points in the camera images of the camera units 12101 to 12104 as infrared cameras; and a step of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that there are pedestrians in the camera images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a manner superimposed on the identified pedestrian. The sound image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0304] An example of a mobile body control system to which the technology according to the present invention can be applied has been described above. The technology of the present invention can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, the solid-state imaging device 1 according to one of the above-mentioned embodiments and their modified examples can be applied to the imaging unit 12031. By applying the technology according to the present invention to the imaging unit 12031, a high-definition image with little noise can be obtained, and therefore, the image can be used in the mobile body control system for high-precision control.

[0305] [Application Example 2] Fig.57: is a view showing a schematic configuration example of an endoscopic surgery system to which the technology according to the embodiment of the present invention (the present technology) can be applied.

[0306] exist Fig.57 , a state is shown in which a surgeon (doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 (such as a pneumoperitoneum tube 11111 and an energy therapy device 11112), a support arm device 11120 (on which the endoscope 11100 is supported), and a cart 11200 (on which various devices for endoscopic surgery are loaded).

[0307] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102 connected to the proximal end of the lens barrel 11101, and the lens barrel 11101 has a predetermined length from its distal end for insertion into a body cavity of a patient 11132. In the example shown, the endoscope 11100 is described as an endoscope configured as a so-called rigid endoscope having a rigid lens barrel 11101. However, the endoscope 11100 may also be configured as a flexible endoscope having a flexible lens barrel 11101.

[0308] The lens barrel 11101 has an opening at its distal end for mounting an objective lens. The light source device 11203 is connected to the endoscope 11100 so that the light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 through a light guide extending inside the lens barrel 11101 and irradiated toward an observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 may be a forward-looking endoscope, or may be an oblique-looking endoscope or a side-looking endoscope.

[0309] An optical system and an imaging element are provided inside the camera head 11102, so that the reflected light (observation light) from the observation target is focused on the imaging element by the optical system. The imaging element performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the camera control unit (CCU) 11201 as raw data.

[0310] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU) or the like, and centrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing for displaying an image based on the image signal, such as development processing (demosaic processing), on the image signal.

[0311] The display device 11202 displays an image based on an image signal that has been image-processed by the CCU 11201 under the control of the CCU 11201 .

[0312] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and supplies irradiation light for imaging the operation area to the endoscope 11100 .

[0313] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user will input instructions through the endoscope 11100 to change the imaging conditions (type of irradiation light, magnification or focal length, etc.).

[0314] The treatment tool control device 11205 controls the driving of the energy treatment device 11112 for cauterizing or cutting tissue, sealing blood vessels, etc. The pneumoperitoneum device 11206 delivers gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity to ensure the field of view of the endoscope 11100 and to ensure the working space of the surgeon. The recorder 11207 is a device capable of recording various types of information related to the operation. The printer 11208 is a device capable of printing various types of information related to the operation in various forms (such as text, images, or graphics).

[0315] It should be noted that the light source device 11203 that provides the irradiation light when the surgical area is to be imaged to the endoscope 11100 may include a white light source such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance adjustment of the captured image can be performed by the light source device 11203. In addition, in this case, if the laser beams from each RGB laser light source are irradiated onto the observation target in a time-sharing manner, and the driving of the imaging element of the camera 11102 is controlled in synchronization with the irradiation timing, it is also possible to capture images corresponding to each of R, G, and B in a time-sharing manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0316] In addition, the light source device 11203 can be controlled so that the intensity of the light to be output changes at predetermined intervals. By controlling the drive of the camera device of the camera 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-sharing manner and synthesize these images, it is possible to create an image with a high dynamic range without underexposed shadows and overexposed highlights.

[0317] In addition, the light source device 11203 can be configured to provide light of a predetermined wavelength band that can be used for special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in human tissue to irradiate light of a narrower wavelength band than the irradiation light (i.e., white light) during ordinary observation, it is possible to perform narrow band light observation (Narrow Band Imaging) for imaging predetermined tissues (e.g., blood vessels on the surface of the mucosa, etc.) with high contrast. Alternatively, in special light observation, fluorescence observation for obtaining images from fluorescence generated by irradiation with excitation light can be performed. In fluorescence observation, fluorescence from body tissue can be observed by irradiating excitation light onto body tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) and irradiating excitation light corresponding to the fluorescence wavelength of the reagent onto human tissue. The light source device 11203 can be configured to provide narrow band light and / or excitation light suitable for special light observation as described above.

[0318] Fig.58 It shows Fig.57 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0319] The camera 11102 includes a lens unit 11401, an imaging section 11402, a driving section 11403, a communication section 11404, and a camera control section 11405. The CCU 11201 includes a communication section 11411, an image processing section 11412, and a control section 11413. The camera 11102 and the CCU 11201 are connected to each other through a transmission cable 11400 for communication.

[0320] The lens unit 11401 is an optical system provided at a connection position with the lens barrel 11101. Observation light taken from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0321] The imaging unit 11402 includes an imaging element. The number of imaging elements included in the imaging unit 11402 may be one (single-board type) or multiple (multi-board type). For example, in the case where the imaging unit 11402 is configured as a multi-board type, image signals corresponding to each of R, G, and B are generated by the imaging element, and these image signals can be synthesized to obtain a color image. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring right-eye and left-eye image signals corresponding to a three-dimensional (3D) display. If a 3D display is performed, the surgeon 11131 can more accurately understand the depth of living tissue in the surgical area. It should be noted that in the case where the imaging unit 11402 is configured as a multi-board type imaging unit, multiple systems of lens units 11401 are provided corresponding to the respective imaging elements.

[0322] In addition, the imaging unit 11402 does not have to be provided on the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 immediately behind the objective lens.

[0323] The driving section 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control section 11405. Therefore, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0324] The communication section 11404 includes a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication section 11404 transmits an image signal acquired from the imaging section 11402 to the CCU 11201 as RAW data via the transmission cable 11400.

[0325] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. The control information includes, for example, information related to imaging conditions, such as information specifying a frame rate of an image to be captured, information specifying an exposure value during imaging, and / or information specifying a magnification and a focus of an image to be captured.

[0326] It should be noted that imaging conditions such as frame rate, exposure value, magnification, or focus may be specified by a user or may be automatically set based on an acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, the endoscope 11100 includes an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function.

[0327] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404 .

[0328] The communication section 11411 includes a communication device for sending various types of information to the camera 11102 and receiving various types of information from the camera 11102. Through the transmission cable 11400, the communication section 11411 receives an image signal sent thereto from the camera 11102.

[0329] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0330] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data sent thereto from the camera 11102 .

[0331] The control unit 11413 performs various types of control related to the imaging of the operation area, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0332] In addition, the control unit 11413 controls the display device 11202 to display a captured image of the surgical area, etc., based on the image signal that has been image-processed by the image processing unit 11412. Therefore, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living body areas, bleeding, fog when the energy treatment device 11112 is used, etc. by detecting the shape, color, etc. of the edge of the object contained in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result so that various types of surgical support information are displayed in a manner overlapping with the image of the surgical area. When the surgical support information is displayed in an overlapping manner and presented to the surgeon 11131, the burden of the surgeon 11131 can be reduced, and the surgeon 11131 can perform the operation with confidence.

[0333] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable capable of being used for electric signal communication, an optical fiber capable of being used for optical communication, or a composite cable capable of being used for electric communication and optical communication.

[0334] Here, although in the illustrated example, communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0335] An example of an endoscopic surgical system to which the technology according to the present invention can be applied has been described above. The technology according to the present invention can be appropriately applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100 in the above-mentioned structure. By applying the technology according to the present invention to the imaging unit 11402, the size of the imaging unit 11402 can be reduced or the definition can be improved, thereby being able to provide an endoscope 11100 having a small size or high definition.

[0336] Although the present invention has been described above with reference to the embodiments, their variations, application examples, and application examples, the present invention is not limited to the embodiments, etc., and various variations are possible. Note that the effects described in this specification are merely examples. The effects of the present invention are not limited to the effects described herein. The present invention may have effects other than the effects described herein.

[0337] In addition, for example, the present invention may also have the following configurations.

[0338] (1) An amplifier circuit comprising: Active loads; and a plurality of input transistors electrically connected to the active load, wherein: The gates of the plurality of input transistors are electrically connected to each other, and The plurality of input transistors include two or more input transistors connected in series with each other. (2) According to the amplifier circuit described in (1) above, the two or more input transistors include a first input transistor and a second input transistor, and the drain of the second input transistor is electrically connected to the source of the first input transistor. (3) According to the amplifier circuit described in (2) above, the two or more input transistors further include a third input transistor, and a drain of the third input transistor is electrically connected to a source of the second input transistor. (4) The amplifier circuit according to the above (2), wherein an active region serving as a source of the first input transistor is different from an active region serving as a drain of the second input transistor. (5) The amplifier circuit according to the above (2), wherein an active region serving as a source of the first input transistor is the same active region as an active region serving as a drain of the second input transistor. (6) The amplifier circuit according to (1) above, wherein the plurality of input transistors include a first group of two or more input transistors connected in series with each other and a second group of two or more input transistors connected in series with each other, and All or part of the two or more input transistors of the first group and all or part of the two or more input transistors of the second group are connected in parallel to each other. (7) The amplifier circuit according to the above (1), wherein each of the plurality of input transistors has a planar structure or a fin structure. (8) According to the amplifier circuit described in (1) above, the two or more input transistors include a first input transistor and a second input transistor, and a gate length of the first input transistor is different from a gate length of the second input transistor. (9) The amplifier circuit according to (8) above, wherein the gate length of the first input transistor is the shortest among the two or more input transistors, The drain of the first input transistor is electrically connected to the active load and a first power supply, and A source of the second input transistor is electrically connected to a second power source. (10) The amplifier circuit according to the above (9), wherein the two or more input transistors are NMOS and the voltage of the first power supply is higher than the voltage of the second power supply, or the two or more input transistors are PMOS and the voltage of the second power supply is higher than the voltage of the first power supply. (11) The amplifier circuit according to (8) above, wherein a voltage threshold of at least one of the two or more input transistors is different from a voltage threshold of the other of the two or more input transistors. (12) A comparator comprising: a first amplifier circuit, into which a reference signal is input; a second amplifying circuit to which the comparison signal is input; and A tail portion of the tail current is controlled, the tail portion being electrically connected to the first amplifying circuit and the second amplifying circuit, wherein: Each of the first amplifying circuit and the second amplifying circuit includes: Active loads; and a plurality of input transistors electrically connected to the active load, The gates of the plurality of input transistors are electrically connected to each other, and The plurality of input transistors include two or more input transistors connected in series with each other. (13) The comparator according to (12) above, wherein the tail portion includes a plurality of transistors electrically connected to the first amplifying circuit and the second amplifying circuit, The gates of the plurality of transistors in the tail portion are electrically connected to each other, and The plurality of transistors in the tail portion include two or more transistors connected in series with each other. (14) A solid-state imaging device, comprising: a pixel array in which a plurality of pixels each including a photoelectric conversion portion is arranged in a matrix form; and An AD conversion unit converts a pixel signal output from the pixel of the pixel array from an analog signal to a digital signal, the AD conversion unit including a comparator, wherein: The comparator comprises: a first amplifier circuit, into which a reference signal is input; a second amplifying circuit to which the analog signal is input as a comparison signal; and A tail portion of the tail current is controlled, the tail portion being electrically connected to the first amplifying circuit and the second amplifying circuit, wherein: Each of the first amplifying circuit and the second amplifying circuit includes: Active loads; and a plurality of input transistors electrically connected to the active load, The gates of the plurality of input transistors are electrically connected to each other, and The plurality of input transistors include two or more input transistors connected in series with each other. (15) The solid-state imaging device according to the above (14), further comprising: a first substrate provided with the photoelectric conversion unit and the pixel transistor; and A second substrate having the comparator is provided. (16) The solid-state imaging device according to (14) above, further comprising: A first substrate provided with the photoelectric conversion unit; and A second substrate is provided with pixel transistors and the comparator, wherein: The first substrate and the second substrate are stacked on each other with an insulating layer interposed therebetween. (17) The solid-state imaging device according to the above (16), wherein the first substrate is provided on the second substrate. (18) The solid-state imaging device according to the above (14), further comprising: a first substrate provided with the photoelectric conversion unit; A second substrate provided with pixel transistors; and A third substrate having the comparator is provided, wherein: The first substrate and the second substrate are stacked on each other with an insulating layer interposed therebetween. (19) The solid-state imaging device according to the above (18), wherein the first substrate is arranged on the second substrate, and the second substrate is arranged on the third substrate. (20) The solid-state imaging device according to the above (14), wherein the solid-state imaging device is provided in an electronic device, and the electronic device receives image data output from the solid-state imaging device. Reference numerals list 1: Solid-state imaging device 2: Amplifier circuit 3: Input transistor 3a: Input transistor 3b: Input transistor 3c: Input transistor 3a': Input transistor 3b': Input transistor 3c': Input transistor 4: Active load 5: Comparator 6a: First Power Supply 6b: Second power supply 7: Camera system 8: Reference signal amplifier circuit 9: Comparison signal amplifier circuit 10: Tail current control transistor 11: Pixel 11a: Pixel 11b: Pixel 11c: Pixel 11d: Pixel 12: Pixel sharing unit 13: Counter circuit 14: Ramp Generator 24: Filter layer 25: On-chip lens layer 26: Through plug 31: Semiconductor substrate 31a: N-type region 31b: P-type region 31c: Floating diffusion 32: Component isolation insulation film 33: Gate insulation film 34: Gate electrode 35: Electrode 36: Interlayer insulation film 41: Semiconductor substrate 41a: Diffusion area 42: Gate insulation film 43: Gate electrode 44: Interlayer insulation film 45: Interlayer insulation film 46a: Plug 46b: Plug 46c: Plug 46d: Plug 47a: Wiring layer 47b: Wiring layer 47c: Wiring layer 48: Pad 51: Semiconductor substrate 51a: Diffusion area 52: Gate insulation film 53: Gate electrode 54: Interlayer insulation film 55: Interlayer insulation film 56a: Plug 56b: Plug 56c: Plug 57a: Wiring layer 57b: Wiring layer 58: Pad 62: Active load 63: Differential Pair Circuit 70: Photoelectric conversion unit 71: Pixel transistor 72: Pixels 73: Pixel Array 74: Logic Circuits 80: Gate 81: Drain 82: Source 83: Gate insulation film 84: Insulation film 85: Silicon substrate 86: Wiring 87: Active area 89: Contact plug 90: Gate electrode 91: Gate insulation film 92: Side wall insulation film 93: Interlayer insulation film 94: Substrate 100: First substrate 100S: Semiconductor layer 100T: Wiring layer 111: Insulation film 112: Fixed Charge Membrane 113: First pinning area 114: N-type semiconductor region 115: P well layer 116: Second pinning area 117: Pixel isolation unit 117A: Light-shielding film 117B: Insulation film 118: VSS contact area 119: Interlayer insulation film 120: pad part 121: Pad 120C: Connection hole 120E: Through electrode 121C: Connection hole 121E: Through electrode 122: Passivation film 123: Interlayer insulation film 124: Bonding film 200: Second substrate 200S: Semiconductor layer 200T: Wiring layer 201: Contact Department 201R: Contact area 202R: Contact area 202: Contact Department 203: Contact Department 204: Contact Department 210: Pixel circuit 211: Well region 212: Insulation area 213: Component isolation area 218: VSS contact area 218V: Connection 221: Passivation film 222: Interlayer insulation film 243: DSP Circuit 244: Frame memory 245: Display unit 246: Storage 247: Operation Department 248: Power Supply Department 249: Bus 300: The third substrate 300S: Semiconductor layer 300T: Wiring layer 301: Contact Department 301R: Contact area 302: Contact Department 302R: Contact area 303: Contact Department 304: Contact Department 401: Light receiving lens 510A: Input 510B: Output 511: Input terminal 512: Input circuit 513: Input amplitude change unit 514: Input data conversion circuit 515: Output data conversion circuit 516: Output amplitude change unit 517: Output circuit 518: Output terminal 520: Row drive unit 530: Timing Control Unit 539: Pixel sharing unit 540: Pixel array unit 540B: ​​Peripheral 541A: Pixel 541B: Pixel 541C: Pixel 541D: Pixel 542: Row drive signal line 543: Vertical signal line 550: Column signal processing unit 560: Image signal processing unit TR: Transfer transistor TG: Transmission Gate RST: Reset transistor AMP: Amplifier Transistor SEL: Select transistor FDG: FD conversion gain switching transistor FD: Floating Diffusion PD: Photodiode TGV: Through-hole electrode W1: First wiring layer W2: Second wiring layer W3: The third wiring layer W4: The fourth wiring layer SELL: Wiring RSTL: Wiring FDGL: Wiring H1: Connection hole H2: Connection hole TA: external terminal TB: external terminal.

Claims

1. An amplifier circuit, comprising: Active load; and a plurality of input transistors electrically connected to the active load, wherein: The gates of the plurality of input transistors are electrically connected to each other, and The plurality of input transistors include two or more input transistors connected in series with each other.

2. The amplifier circuit according to claim 1, wherein: The more than two input transistors include a first input transistor and a second input transistor, a drain of the second input transistor being electrically connected to a source of the first input transistor.

3. The amplifier circuit according to claim 2, wherein: The more than two input transistors further include a third input transistor having a drain electrically connected to a source of the second input transistor.

4. The amplifier circuit according to claim 2, wherein: An active region serving as a source of the first input transistor is a different active region from an active region serving as a drain of the second input transistor.

5. The amplifier circuit according to claim 2, wherein: An active region serving as a source of the first input transistor is the same active region as an active region serving as a drain of the second input transistor.

6. The amplifier circuit according to claim 1, wherein: The plurality of input transistors include a first group of two or more input transistors connected in series with each other and a second group of two or more input transistors connected in series with each other, and All or part of the two or more input transistors of the first group and all or part of the two or more input transistors of the second group are connected in parallel to each other.

7. The amplifier circuit according to claim 1, wherein: Each of the plurality of input transistors has a planar structure or a fin type structure.

8. The amplifier circuit according to claim 1, wherein: The two or more input transistors include a first input transistor and a second input transistor, and a gate length of the first input transistor is different from a gate length of the second input transistor.

9. The amplifier circuit according to claim 8, wherein: The gate length of the first input transistor is the shortest among the two or more input transistors, The drain of the first input transistor is electrically connected to the active load and a first power supply, and A source of the second input transistor is electrically connected to a second power source.

10. The amplifier circuit according to claim 9, wherein: The two or more input transistors are NMOS and the voltage of the first power supply is higher than the voltage of the second power supply, or the two or more input transistors are PMOS and the voltage of the second power supply is higher than the voltage of the first power supply.

11. The amplifier circuit according to claim 8, wherein: A voltage threshold of at least one of the two or more input transistors is different from a voltage threshold of the other of the two or more input transistors.

12. A comparator, comprising: a first amplifier circuit, into which a reference signal is input; a second amplifying circuit to which the comparison signal is input; and A tail portion of the tail current is controlled, the tail portion being electrically connected to the first amplifying circuit and the second amplifying circuit, wherein: Each of the first amplifying circuit and the second amplifying circuit includes: Active loads; and a plurality of input transistors electrically connected to the active load, The gates of the plurality of input transistors are electrically connected to each other, and The plurality of input transistors include two or more input transistors connected in series with each other.

13. The comparator according to claim 12, wherein: The tail portion includes a plurality of transistors electrically connected to the first amplifying circuit and the second amplifying circuit, The gates of the plurality of transistors in the tail portion are electrically connected to each other, and The plurality of transistors in the tail portion include two or more transistors connected in series with each other.

14. A solid-state imaging device, comprising: a pixel array in which a plurality of pixels each including a photoelectric conversion portion is arranged in a matrix form; and An AD conversion unit converts a pixel signal output from the pixel of the pixel array from an analog signal to a digital signal, the AD conversion unit including a comparator, wherein: The comparator comprises: a first amplifier circuit, into which a reference signal is input; a second amplifying circuit to which the analog signal is input as a comparison signal; and A tail portion of the tail current is controlled, the tail portion being electrically connected to the first amplifying circuit and the second amplifying circuit, wherein: Each of the first amplifying circuit and the second amplifying circuit includes: Active loads; and a plurality of input transistors electrically connected to the active load, The gates of the plurality of input transistors are electrically connected to each other, and The plurality of input transistors include two or more input transistors connected in series with each other.

15. The solid-state imaging device according to claim 14, further comprising: A first substrate provided with the photoelectric conversion unit and the pixel transistor; and A second substrate having the comparator is provided.

16. The solid-state imaging device according to claim 14, further comprising: A first substrate provided with the photoelectric conversion unit; and A second substrate is provided with pixel transistors and the comparator, wherein: The first substrate and the second substrate are stacked on each other with an insulating layer interposed therebetween.

17. The solid-state imaging device according to claim 16, wherein: The first substrate is disposed on the second substrate.

18. The solid-state imaging device according to claim 14, further comprising: A first substrate provided with the photoelectric conversion unit; A second substrate provided with pixel transistors; and A third substrate having the comparator is provided, wherein: The first substrate and the second substrate are stacked on each other with an insulating layer interposed therebetween.

19. The solid-state imaging device according to claim 18, wherein The first substrate is arranged on the second substrate, and the second substrate is arranged on the third substrate.

20. The solid-state imaging device according to claim 14, wherein The solid-state imaging device is provided in an electronic device, and the electronic device receives image data output from the solid-state imaging device.

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