Simulation test method for FPGA (Field Programmable Gate Array) in dual-channel digital electronic controller
By building a simulation test environment for FPGA in a dual-channel digital electronic controller, and compiling and executing test cases for channel synchronization, communication and switching functions, the problems of insufficient comprehensiveness of black box testing and high difficulty in injection of faults are solved, and efficient and reliable FPGA function verification is achieved.
Patent Information
- Application Number
- CN202510157795.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-05-16
AI Technical Summary
In the prior art, black box testing is insufficient in the comprehensiveness of the inter-channel functional test of FPGAs in dual-channel digital electronic controllers, making it difficult to inject inter-channel faults, and the test is difficult and costly.
It provides a simulation test method for FPGA in a dual-channel digital electronic controller. By building a simulation test environment, a test case for channel synchronization, communication and switching functions is compiled, and simulation tests are carried out in the simulation environment to achieve comprehensive verification of FPGA functions and fault injection.
It improves the comprehensiveness and confidence in testing between channels functions, enables rapid failure injection and analysis, reduces testing costs, and adopts a modular design to facilitate the reuse of test environments and use cases.
Smart Images
Figure CN120010287A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of safety-critical electronic equipment, and in particular to a simulation test method for FPGA in a dual-channel digital electronic controller. Background Art
[0002] In safety-critical controllers, two or more identical control channels are usually designed to ensure high safety, and the channels serve as hot backups for each other. The controller needs to implement channel switching, channel communication, and channel synchronization between the two channels. The above-mentioned channel-to-channel functions are all implemented by FPGA, and the verification method of the channel-to-channel functions uses black-box whole-machine testing. The testing method has the following deficiencies: 1. Black box testing is not comprehensive enough for testing inter-channel functions. As a device inside the controller, FPGA completes algorithms such as channel switching, inter-channel synchronization, and inter-channel communication. The whole machine test is not sufficient to verify the algorithm level; 2. It is difficult to inject faults between channels, because the control signals between the two channels of the controller are connected through printed circuit boards or connectors. To simulate faults such as short circuits and open circuits of signals, the printed circuit boards need to be modified and irreversible effects may occur, which makes the test difficult and costly. Summary of the invention
[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a simulation test method for FPGA in a dual-channel digital electronic controller to solve the problem that the black box test in the prior art is not comprehensive enough for testing the inter-channel functions and is difficult to implement inter-channel fault injection.
[0004] As a first aspect of the present invention, a simulation test method for an FPGA in a dual-channel digital electronic controller is provided, and the simulation test method for an FPGA in a dual-channel digital electronic controller comprises: Step S1: Building a simulation test environment for FPGA in a dual-channel digital electronic controller; Step S2: compiling a channel synchronization function test case, and performing a simulation test on the channel synchronization function between the dual channels according to the channel synchronization function test case in the simulation test environment; Step S3: compile a channel communication function test case, and perform a simulation test on the channel communication function between the dual channels according to the channel communication function test case in the simulation test environment; Step S4: compile a channel switching function test case, and perform a simulation test on the channel switching function between the dual channels according to the channel switching function test case in the simulation test environment.
[0005] Furthermore, the simulation test environment for building the FPGA in the dual-channel digital electronic controller also includes: Step S11: Instantiate the A channel and the B channel of the digital electronic controller in the simulation test environment respectively; wherein the A channel corresponds to one FPGA under test, and the B channel corresponds to one FPGA under test; Step S12: connecting the interconnection lines between channel A and channel B; wherein, connecting the synchronous transmission signal sync_tx_A of channel A with the synchronous reception signal sync_rx_B of channel B, and connecting the synchronous transmission signal sync_tx_B of channel B with the synchronous reception signal sync_rx_A of channel A; connecting the communication transmission signal com_tx_A of channel A with the communication reception signal com_rx_B of channel B, and connecting the communication transmission signal com_tx_B of channel B with the communication reception signal com_rx_A of channel A; connecting the local channel master control signal sa_A of channel A with the opposite channel master control signal sb_B of channel B, and connecting the local channel master control signal sa_B of channel B with the opposite channel master control signal sb_A of channel A; Step S13: Performing environment configuration on channel A and channel B in the simulation test environment, respectively. The environment configuration includes the following elements: a) Run clock frequency configuration; b) Power-on phase configuration; c) Communication rate configuration between channels; d) Delay configuration of control signal between channels; Step S14: Perform fault configuration in the simulation test environment. The fault configuration includes the following elements: a) Clock failure configuration; b) Short circuit and open circuit fault configuration of control signals between channels; c) Inter-channel control signal crosstalk fault configuration.
[0006] Furthermore, the preparation of the channel synchronization function test case and the simulation test of the channel synchronization function between the dual channels according to the channel synchronization function test case in the simulation test environment also includes: Step S21: compiling a channel synchronization function test case, and instantiating the simulation test environment in the channel synchronization function test case; Step S22: performing environment configuration on channel A and channel B respectively according to the test items in the channel synchronization function test case; Step S23: performing fault configuration on the synchronization control signal between channel A and channel B according to the test items in the channel synchronization function test case; wherein the synchronization control signal includes any one or more of the synchronization transmission signal sync_tx_A of channel A, the synchronization reception signal sync_rx_B of channel B, the synchronization transmission signal sync_tx_B of channel B, and the synchronization reception signal sync_rx_A of channel A; Step S24: Execute the channel synchronization function test case to simulate the channel synchronization function between channel A and channel B to obtain the channel synchronization function simulation test process data between channel A and channel B, and determine the channel synchronization function simulation test result between channel A and channel B based on the channel synchronization function simulation test process data.
[0007] Furthermore, the preparation of the channel communication function test case and the simulation test of the channel communication function between the dual channels according to the channel communication function test case in the simulation test environment also includes: Step S31: compile a channel communication function test case, and instantiate the simulation test environment in the channel communication function test case; Step S32: performing environment configuration on channel A and channel B respectively according to the test items in the channel communication function test case; Step S33: performing fault configuration on the communication control signal between channel A and channel B according to the test items in the channel communication function test case; wherein the communication control signal includes any one or more of the communication transmission signal com_tx_A of channel A, the communication reception signal com_rx_B of channel B, the communication transmission signal com_tx_B of channel B and the communication reception signal com_rx_A of channel A; Step S34: Execute the channel communication function test case to simulate the channel communication function between channel A and channel B to obtain the channel communication function simulation test process data between channel A and channel B, and determine the channel communication function simulation test result between channel A and channel B based on the channel communication function simulation test process data.
[0008] Furthermore, the preparation of the channel switching function test case and the simulation test of the channel switching function between the dual channels according to the channel switching function test case in the simulation test environment also includes: Step S41: compiling a channel switching function test case, and instantiating the simulation test environment in the channel switching function test case; Step S42: performing environment configuration on channel A and channel B respectively according to the test items in the channel switching function test case; Step S43: performing fault configuration on the switching control signal between channel A and channel B according to the test items in the channel switching function test case; wherein the switching control signal includes any one or more of the channel master control signal sa_A of channel A, the counterpart channel master control signal sb_B of channel B, the channel master control signal sa_B of channel B, and the counterpart channel master control signal sb_A of channel A; Step S44: Execute the channel switching function test case to simulate the channel switching function between channel A and channel B to obtain the channel switching function simulation test process data between channel A and channel B, and determine the channel switching function simulation test result between channel A and channel B based on the channel switching function simulation test process data.
[0009] The simulation test method of FPGA in the dual-channel digital electronic controller provided by the present invention has the following advantages: (1) The simulation test environment of the FPGA in the dual-channel digital electronic controller restores the actual controller test environment, with high test confidence; (2) The simulation test environment of the FPGA in the dual-channel digital electronic controller is highly configurable, which facilitates the analysis of test results under different configurations; (3) Ability to quickly perform fault injection, observe test results and analyze them; (4) By adopting a modular design concept, the test environment and test cases can be reused between projects. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.
[0011] Figure 1 The present invention provides a flow chart of a simulation test method for FPGA in a dual-channel digital electronic controller.
[0012] Figure 2 This is a structural diagram of the simulation test environment of the FPGA in the dual-channel digital electronic controller provided by the present invention. DETAILED DESCRIPTION
[0013] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0014] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.
[0015] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0016] In this embodiment, a simulation test method for FPGA in a dual-channel digital electronic controller is provided. Figure 1 The flowchart of the simulation test method of FPGA in the dual-channel digital electronic controller provided by the present invention. Figure 1 As shown, the simulation test method of FPGA in the dual-channel digital electronic controller includes: Step S1: Building a simulation test environment for FPGA in a dual-channel digital electronic controller; Preferably, if Figure 2 As shown, the simulation test environment for building the FPGA in the dual-channel digital electronic controller also includes: Step S11: Instantiate the A channel and the B channel of the digital electronic controller in the simulation test environment respectively; wherein the A channel corresponds to one FPGA under test, and the B channel corresponds to one FPGA under test; Step S12: connecting the interconnection lines between channel A and channel B; wherein, connecting the synchronous transmission signal sync_tx_A of channel A with the synchronous reception signal sync_rx_B of channel B, and connecting the synchronous transmission signal sync_tx_B of channel B with the synchronous reception signal sync_rx_A of channel A; connecting the communication transmission signal com_tx_A of channel A with the communication reception signal com_rx_B of channel B, and connecting the communication transmission signal com_tx_B of channel B with the communication reception signal com_rx_A of channel A; connecting the local channel master control signal sa_A of channel A with the opposite channel master control signal sb_B of channel B, and connecting the local channel master control signal sa_B of channel B with the opposite channel master control signal sb_A of channel A; Step S13: Performing environment configuration on channel A and channel B in the simulation test environment, respectively. The environment configuration includes the following elements: a) Run clock frequency configuration; b) Power-on phase configuration; c) Communication rate configuration between channels; d) Delay configuration of control signal between channels; Step S14: Perform fault configuration in the simulation test environment. The fault configuration includes the following elements: a) Clock failure configuration; b) Short circuit and open circuit fault configuration of control signals between channels; c) Inter-channel control signal crosstalk fault configuration.
[0017] Step S2: compiling a channel synchronization function test case, and performing a simulation test on the channel synchronization function between the dual channels according to the channel synchronization function test case in the simulation test environment; Preferably, the preparing of channel synchronization function test cases and performing simulation test on the channel synchronization function between the dual channels according to the channel synchronization function test cases in the simulation test environment further includes: Step S21: compiling a channel synchronization function test case, and instantiating the simulation test environment in the channel synchronization function test case; Step S22: performing environment configuration on channel A and channel B respectively according to the test items in the channel synchronization function test case; Step S23: performing fault configuration on the synchronization control signal between channel A and channel B according to the test items in the channel synchronization function test case; wherein the synchronization control signal includes any one or more of the synchronization transmission signal sync_tx_A of channel A, the synchronization reception signal sync_rx_B of channel B, the synchronization transmission signal sync_tx_B of channel B, and the synchronization reception signal sync_rx_A of channel A; Step S24: Execute the channel synchronization function test case to simulate the channel synchronization function between channel A and channel B to obtain the channel synchronization function simulation test process data between channel A and channel B, and determine the channel synchronization function simulation test result between channel A and channel B based on the channel synchronization function simulation test process data.
[0018] Step S3: compile a channel communication function test case, and perform a simulation test on the channel communication function between the dual channels according to the channel communication function test case in the simulation test environment; Preferably, the preparing of channel communication function test cases and performing simulation test on the channel communication function between the dual channels according to the channel communication function test cases in the simulation test environment further includes: Step S31: compile a channel communication function test case, and instantiate the simulation test environment in the channel communication function test case; Step S32: performing environment configuration on channel A and channel B respectively according to the test items in the channel communication function test case; Step S33: performing fault configuration on the communication control signal between channel A and channel B according to the test items in the channel communication function test case; wherein the communication control signal includes any one or more of the communication transmission signal com_tx_A of channel A, the communication reception signal com_rx_B of channel B, the communication transmission signal com_tx_B of channel B and the communication reception signal com_rx_A of channel A; Step S34: Execute the channel communication function test case to simulate the channel communication function between channel A and channel B to obtain the channel communication function simulation test process data between channel A and channel B, and determine the channel communication function simulation test result between channel A and channel B based on the channel communication function simulation test process data.
[0019] Step S4: compile a channel switching function test case, and perform a simulation test on the channel switching function between the dual channels according to the channel switching function test case in the simulation test environment.
[0020] Preferably, the preparing of the channel switching function test case and performing a simulation test on the channel switching function between the dual channels according to the channel switching function test case in the simulation test environment further includes: Step S41: compiling a channel switching function test case, and instantiating the simulation test environment in the channel switching function test case; Step S42: performing environment configuration on channel A and channel B respectively according to the test items in the channel switching function test case; Step S43: performing fault configuration on the switching control signal between channel A and channel B according to the test items in the channel switching function test case; wherein the switching control signal includes any one or more of the channel master control signal sa_A of channel A, the counterpart channel master control signal sb_B of channel B, the channel master control signal sa_B of channel B, and the counterpart channel master control signal sb_A of channel A; Step S44: Execute the channel switching function test case to simulate the channel switching function between channel A and channel B to obtain the channel switching function simulation test process data between channel A and channel B, and determine the channel switching function simulation test result between channel A and channel B based on the channel switching function simulation test process data.
[0021] In the embodiment of the present invention, a dual-channel desktop simulation environment is built, and the FPGA under test in the two channels is instantiated in the desktop simulation environment, and the channel switching signal, the inter-channel synchronization signal, and the inter-channel communication signal are interconnected according to the hardware connection relationship of the dual channels inside the controller. Finally, by setting and compiling test cases, the dual-channel desktop simulation environment is configured, faults are injected, and test results are collected in the test cases.
[0022] like Figure 2 As shown, the simulation test environment provided by the present invention includes controller A channel and B channel, A channel environment configuration, B channel environment configuration and fault configuration. In the test environment, the synchronous transmission signal sync_tx_A of channel A is connected with the synchronous reception signal sync_rx_B of channel B, and the synchronous transmission signal sync_tx_B of channel B is connected with the synchronous reception signal sync_rx_A of channel A; the communication transmission signal com_tx_A of channel A is connected with the communication reception signal com_rx_B of channel B, and the communication transmission signal com_tx_B of channel B is connected with the communication reception signal com_rx_A of channel A; the local channel master control signal sa_A of channel A is connected with the opposite channel master control signal sb_B of channel B, and the local channel master control signal sa_B of channel B is connected with the opposite channel master control signal sb_A of channel A.
[0023] This example simulates the channel synchronization function between two channels. The steps are as follows: 1. Configure the A channel and B channel environment configuration. The specific parameters are as follows: a) Configure the operating clock frequency of channel A to 30.0003MHz and the operating clock frequency of channel B to 29.9997MHz; b) Configure the power-on phase to 0ms for channel A and 24ms for channel B; c) The delay of sync_tx and sync_rx signals between channels A and B is 10ns.
[0024] 2. Perform fault injection tests in sequence. The fault configuration steps are as follows: a) Both channel A and channel B are configured to be fault-free; b) The clock of configuration channel A fails, but the clock of configuration channel B is normal; c) The synchronous transmission signal sync_tx of channel A is configured to be always 0.
[0025] 3. Execute the channel synchronization function test cases between dual channels and record the synchronization function test results.
[0026] The simulation test method of FPGA in a dual-channel digital electronic controller provided by the present invention can realize white-box testing by simulating the full circuit environment inside the controller where the FPGA under test is located, including bus communication between the CPU and FPGA, control between FPGA and peripherals, and control and interaction between dual-channel controllers. The function simulation of the FPGA in the controller can be performed on the desktop, the process of building the simulation environment is fast and simple, the simulation confidence is high, and the simulation results are clearly visible.
[0027] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A simulation test method for FPGA in a dual-channel digital electronic controller, characterized in that: The simulation test method of FPGA in the dual-channel digital electronic controller includes: Step S1: Building a simulation test environment for FPGA in a dual-channel digital electronic controller; Step S2: compiling a channel synchronization function test case, and performing a simulation test on the channel synchronization function between the dual channels according to the channel synchronization function test case in the simulation test environment; Step S3: compile a channel communication function test case, and perform a simulation test on the channel communication function between the dual channels according to the channel communication function test case in the simulation test environment; Step S4: compile a channel switching function test case, and perform a simulation test on the channel switching function between the dual channels according to the channel switching function test case in the simulation test environment.
2. The simulation test method of FPGA in a dual-channel digital electronic controller according to claim 1, characterized in that: The simulation test environment for building the FPGA in the dual-channel digital electronic controller also includes: Step S11: Instantiate the A channel and the B channel of the digital electronic controller in the simulation test environment respectively; wherein the A channel corresponds to one FPGA under test, and the B channel corresponds to one FPGA under test; Step S12: connecting the interconnection lines between channel A and channel B; wherein, connecting the synchronous transmission signal sync_tx_A of channel A with the synchronous reception signal sync_rx_B of channel B, and connecting the synchronous transmission signal sync_tx_B of channel B with the synchronous reception signal sync_rx_A of channel A; connecting the communication transmission signal com_tx_A of channel A with the communication reception signal com_rx_B of channel B, and connecting the communication transmission signal com_tx_B of channel B with the communication reception signal com_rx_A of channel A; connecting the local channel master control signal sa_A of channel A with the opposite channel master control signal sb_B of channel B, and connecting the local channel master control signal sa_B of channel B with the opposite channel master control signal sb_A of channel A; Step S13: Performing environment configuration on channel A and channel B in the simulation test environment, respectively. The environment configuration includes the following elements: a) Run clock frequency configuration; b) Power-on phase configuration; c) Communication rate configuration between channels; d) Delay configuration of control signal between channels; Step S14: Perform fault configuration in the simulation test environment. The fault configuration includes the following elements: a) Clock failure configuration; b) Short circuit and open circuit fault configuration of control signals between channels; c) Inter-channel control signal crosstalk fault configuration.
3. The simulation test method of FPGA in a dual-channel digital electronic controller according to claim 2, characterized in that: The preparation of the channel synchronization function test case and the simulation test of the channel synchronization function between the dual channels according to the channel synchronization function test case in the simulation test environment also includes: Step S21: compiling a channel synchronization function test case, and instantiating the simulation test environment in the channel synchronization function test case; Step S22: performing environment configuration on channel A and channel B respectively according to the test items in the channel synchronization function test case; Step S23: performing fault configuration on the synchronization control signal between channel A and channel B according to the test items in the channel synchronization function test case; wherein the synchronization control signal includes any one or more of the synchronization transmission signal sync_tx_A of channel A, the synchronization reception signal sync_rx_B of channel B, the synchronization transmission signal sync_tx_B of channel B, and the synchronization reception signal sync_rx_A of channel A; Step S24: Execute the channel synchronization function test case to simulate the channel synchronization function between channel A and channel B to obtain the channel synchronization function simulation test process data between channel A and channel B, and determine the channel synchronization function simulation test result between channel A and channel B based on the channel synchronization function simulation test process data.
4. The simulation test method of FPGA in a dual-channel digital electronic controller according to claim 2, characterized in that: The preparation of the channel communication function test case and the simulation test of the channel communication function between the dual channels according to the channel communication function test case in the simulation test environment also includes: Step S31: compile a channel communication function test case, and instantiate the simulation test environment in the channel communication function test case; Step S32: performing environment configuration on channel A and channel B respectively according to the test items in the channel communication function test case; Step S33: performing fault configuration on the communication control signal between channel A and channel B according to the test items in the channel communication function test case; wherein the communication control signal includes any one or more of the communication transmission signal com_tx_A of channel A, the communication reception signal com_rx_B of channel B, the communication transmission signal com_tx_B of channel B and the communication reception signal com_rx_A of channel A; Step S34: Execute the channel communication function test case to simulate the channel communication function between channel A and channel B to obtain the channel communication function simulation test process data between channel A and channel B, and determine the channel communication function simulation test result between channel A and channel B based on the channel communication function simulation test process data.
5. The simulation test method of FPGA in a dual-channel digital electronic controller according to claim 2, characterized in that: The preparation of the channel switching function test case and the simulation test of the channel switching function between the dual channels according to the channel switching function test case in the simulation test environment also includes: Step S41: compiling a channel switching function test case, and instantiating the simulation test environment in the channel switching function test case; Step S42: performing environment configuration on channel A and channel B respectively according to the test items in the channel switching function test case; Step S43: performing fault configuration on the switching control signal between channel A and channel B according to the test items in the channel switching function test case; wherein the switching control signal includes any one or more of the channel master control signal sa_A of channel A, the counterpart channel master control signal sb_B of channel B, the channel master control signal sa_B of channel B, and the counterpart channel master control signal sb_A of channel A; Step S44: Execute the channel switching function test case to simulate the channel switching function between channel A and channel B to obtain the channel switching function simulation test process data between channel A and channel B, and determine the channel switching function simulation test result between channel A and channel B based on the channel switching function simulation test process data.