Instruction translation method and device in dynamic binary translation

Abstract

The invention provides an instruction translation method and device in dynamic binary translations, and the method comprises the steps: firstly, searching a specific instruction sequence in an instruction of a source instruction set architecture by analyzing the difference between the source instruction set architecture and a target instruction set architecture, and designing a translation rule of the specific instruction sequence according to the characteristics of the target instruction set architecture; during dynamic binary translation, a specific instruction sequence in a binary file of a source instruction set architecture is scanned, namely translation is performed by adopting the translation rule, otherwise, a conventional translation mode is still adopted. The binary instructions of the source instruction set architecture are translated according to the self-defined translation rule, the number of translated instructions of the target instruction set architecture is reduced, the translation quality is improved, and therefore the binary translation efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of binary translation, and in particular relates to an instruction translation method and device in dynamic binary translation. Background Art

[0002] With the advent of the golden age of architecture, a variety of emerging processor architectures continue to emerge. Since software compiled based on different instruction set architectures cannot run across platforms, the software ecosystem of new processor platforms has become an important bottleneck restricting their promotion. In order to break this dilemma and accelerate ecosystem construction and market promotion, migrating the software resources of existing mainstream architectures to new architectures has become an efficient solution. Binary translation technology has the characteristic of enabling cross-platform operation of software without the need for source code, so it has become a key means of software cross-architecture migration.

[0003] Binary translation is divided into static binary translation and dynamic binary translation. The former can translate the complete binary code on the source platform into an executable binary program on the target platform. The translated program can be reused many times, with high operating efficiency. The program execution and translation process are independent of each other, leaving more time for deep optimization. The latter parses and translates code fragments during program execution, and is more suitable for handling issues such as indirect jumps, indirect calls, and self-modifying code. At the same time, dynamic translation can discover some optimization opportunities that static translation cannot capture during the translation process. It is a more flexible and scalable binary translation method, and has therefore become the mainstream choice in the field of binary translation.

[0004] There is a certain semantic gap between instruction sets of different styles. For example, for the traditional complex instruction set X86 platform, in order to save the intermediate operation process, it specially designs a flag register and corresponding calculation logic in the hardware circuit, which mainly stores the additional results of the execution of related instructions, provides a basis for the behavior of executing related instructions, and controls the working mode of the CPU. However, in some emerging reduced instruction set architectures, in order to maintain the simplicity and consistency of the instruction set, no dedicated flag register is designed. In binary translation, if the source platform uses a complex instruction set (CISC) and the target platform uses a reduced instruction set (RISC), the flag bits in the flag register need to be translated. The translation of flag bits refers to translating and generating instructions with the same functions on the target platform according to the operation semantics of the flag bits of the source platform instructions, and executing these generated target instructions to achieve the same functions as the flag bits on the source platform. However, the expressive power of the reduced instruction set is usually weaker than that of the complex instruction set, and more instructions are usually required to express the same semantics. Therefore, when performing binary translation, in order to maintain semantic equivalence, the number of instructions in the translated target platform is usually more than the number of instructions in the source platform, resulting in code expansion and reduced translation quality.

[0005] A flag bit translation optimization strategy in binary translation is also proposed in the Chinese national patent "Optimization Processing Method of Flag Bits in Binary Translation" (Publication No.: CN1296815A). This invention proposes a solution combining immediate calculation and delayed calculation for interpretive execution in binary translation, which is used to optimize flag bit processing in interpretive execution and reduce redundant target instructions.

[0006] China's national patent "A translation method in dynamic binary translation" (publication number: CN1332308A) also introduces a dynamic binary translation strategy, which searches for translation code fragments that frequently appear in the translation code and affect the translation quality, and proposes a translation method based on instruction pattern recognition to reduce the system overhead caused by repeated code optimization. Summary of the invention

[0007] In order to solve the problem of instruction redundancy generated during binary translation flag operation, the present invention proposes an instruction translation method in dynamic binary translation, including: obtaining the difference between a source instruction set architecture and a target instruction set architecture, identifying a specific instruction sequence in the source instruction set; designing a translation rule for the specific instruction sequence based on the target instruction set architecture; in the dynamic binary translation process, detecting a specific instruction sequence in a binary file of the source instruction set architecture; and translating the detected specific instruction sequence using a corresponding translation rule.

[0008] Furthermore, the translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

[0009] The specific instruction sequence includes the instruction sequence involving the flag bit in the source instruction set. For the common instructions other than the specific instruction sequence in the binary file of the source instruction set architecture, a conventional translation method is adopted for translation.

[0010] The present invention also proposes an instruction translation device in dynamic binary translation, including: a difference comparison module, used to obtain the difference between the source instruction set architecture and the target instruction set architecture, and identify the specific instruction sequence in the source instruction set; a rule generation module, used to design the translation rules of the specific instruction sequence based on the target instruction set architecture; a dynamic translation module, used to detect the specific instruction sequence in the binary file of the source instruction set architecture during the dynamic binary translation process; for the detected specific instruction sequence, the corresponding translation rules are used for translation.

[0011] Furthermore, the translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

[0012] The specific instruction sequence includes an instruction sequence involving a flag bit in the source instruction set. The dynamic translation module also includes: for the common instructions other than the specific instruction sequence in the source instruction set architecture binary file, a conventional translation method is used to translate.

[0013] The present invention also provides an electronic device, comprising the instruction translation device in the dynamic binary translation as described above.

[0014] The present invention provides a computer-readable storage medium storing computer-executable instructions, characterized in that when the computer-executable instructions are executed, the instruction translation method in the dynamic binary translation as described above is implemented.

[0015] The instruction translation method in the dynamic binary translation of the present invention is based on the identified specific instruction sequence and formulates corresponding translation rules to maximize the elimination of instruction redundancy caused by translation, thereby effectively improving the quality of binary translation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the instruction translation method in the dynamic binary translation of the present invention.

[0017] Figure 2 It is a partial detailed flow chart of the instruction translation method in the dynamic binary translation of the present invention.

[0018] Figure 3 It is a pseudo code schematic diagram of the flag instruction sequence translation optimization algorithm of the present invention.

[0019] Figure 4 It is a schematic diagram of the translation rules of the present invention.

[0020] Figure 5 It is a schematic diagram of the instruction translation device in the dynamic binary translation of the present invention.

[0021] Figure 6 It is a schematic diagram of an electronic device of the present invention.

[0022] Figure 7 It is a schematic diagram of the hardware structure of an electronic device of the present invention.

[0023] Wherein, the accompanying drawings are marked as follows:

[0024] 100: electronic device 10: command translation device

[0025] 11: Difference comparison module 12: Rule generation module

[0026] 13: Dynamic translation module

[0027] S1, S2, S21, S22, S23, S24, S25, S26, S3: Steps DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation method described herein is only used to explain the present invention and is not used to limit the present invention.

[0029] It should be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0030] Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0031] The technical solution of the present invention is expected to translate the binary instruction sequence of the source instruction set architecture into a fully optimized binary instruction sequence of the target instruction set architecture. Based on this expectation, the instruction translation method of the present invention first analyzes the semantic difference between the source instruction set architecture and the target instruction set architecture. Secondly, according to the semantic difference between the instruction sets, combined with the statistical analysis of the actual binary code, corresponding translation methods are designed for several instruction sequences of the source instruction set architecture. The binary file of the source instruction set architecture is input into the binary translation system provided by the present invention, and the binary file of the source instruction set architecture is scanned instruction by instruction for several rounds to find the instruction sequence involved in the present invention. If the instruction sequence involved in the present invention is encountered, the corresponding mark is set, and the instruction sequence is recorded in a dedicated table. Then the binary instructions of the source instruction set architecture are translated. If the corresponding mark is encountered and the instruction sequence exists in the record table, the translation is optimized according to the specific translation method provided by the present invention; otherwise, the translation is performed according to the conventional translation method. Repeat the above steps until the entire source instruction set architecture binary file is translated, and finally the optimized target instruction sequence is output.

[0032] Figure 1 FIG. 1 is a flow chart of the instruction translation method in the dynamic binary translation of the present invention. Figure 1As shown, in the first embodiment of the present invention, a method for translating instructions in dynamic binary translation is proposed, and the binary translation from X86 to RISC-V is taken as an example to illustrate the translation method of the present invention. The binary translation from X86 to other RISC instruction sets (such as ARM) is similar.

[0033] The instruction translation method of the present invention comprises:

[0034] Step S1, analyzing and obtaining the difference between the source instruction set architecture and the target instruction set architecture, and identifying a specific instruction sequence in the source instruction set relative to the target instruction set;

[0035] The semantic differences between X86 architecture and RISC-V architecture are analyzed. As a complex instruction set, X86 uses the concept of "flags" in arithmetic and logical operations to save intermediate operation processes. The X86 architecture platform specially designs flag registers and corresponding calculation logic in the hardware circuit, which are mainly used to store additional results of related instruction execution, provide a basis for the behavior of executing related instructions, and control the working mode of the CPU. RISC-V is an emerging reduced instruction set architecture. In order to maintain the simplicity and consistency of the instruction set, no dedicated flag register is designed, and there is no corresponding flag calculation circuit. Therefore, in the binary translation from X86 to RISC-V, in order to maintain the consistency of semantics before and after the translation and prevent information loss, additional RISC-V instructions are needed to simulate the flag calculation in X86. In actual binary translation, the flag change caused by an arithmetic or logical operation of an X86 instruction is often simulated by additional 10 to 30 RISC-V instructions. Such translation will result in the number of instructions in the target platform being usually much greater than the number of instructions in the source platform, which will cause higher code bloat and reduce binary translation performance.

[0036] The specific instruction sequence of this embodiment includes an instruction sequence involving a flag bit, but the present invention is not limited thereto.

[0037] Step S2, designing translation rules for specific instruction sequences based on the target instruction set architecture; the translation rules generate optimized target instructions based on operand information of the source instruction pattern to reduce the number of target instructions. The translation rules include merging multiple source instructions into a single or multiple target instructions to reduce the number of target instructions.

[0038] According to the semantic differences, the corresponding translation method is designed for the specific instruction sequence in the source instruction set architecture. If a flag bit modified by an instruction is not used in the subsequent instruction, or is modified again before being used, then the modification of the flag bit by this instruction is redundant. For example, in the X86 instruction set, the function of the JG (Jump if Greater) instruction is to compare the results of two signed integers and jump to the target address when the first operand is greater than the second operand. The JG instruction decides whether to jump based on the values ​​of the sign flag (SF), overflow flag (OF), and zero flag (ZF). The judgment logic is: when SF=OF and ZF=0, jump to the target address, otherwise continue to execute the next instruction. The CMP instruction is used to compare two operands. Its function is to subtract the two operands, but do not store the result, only update the status of the flag register. Since the JG instruction needs to use the three flags ZF, OF, and SF, nearly 30 additional RISC-V instructions are needed to simulate the calculation of the above three flags. Compared with the original two X86 instructions, serious code expansion has occurred.

[0039] However, through semantic difference analysis, it is found that when CMP and JG instructions appear in pairs and the modification of the flag bit by CMP is not used by subsequent instructions, the BLT instruction provided in the RISC-V instruction set can be used. After reasonable register mapping, only one target instruction is needed to complete the translation, which can greatly reduce the redundancy of target instructions.

[0040] Similar to the above example, after designing several instruction sequence translation methods and implementing them in the binary translation system, the binary file of the source instruction set architecture can be input. The binary translation system scans the binary file of the source instruction set architecture and recognizes each instruction one by one. Figure 2 As shown, including:

[0041] Step S21, sequentially scanning the basic blocks of the source instruction set, and first scanning to set "modify" and "use" marks for the instructions related to the flag bits respectively;

[0042] Step S22, scanning again, when encountering a Jcc type conditional jump instruction, start searching backward until encountering the first instruction included in the preset instruction sequence and marked with "modify";

[0043] Step S23, if no other "modify" mark is encountered in the search, proceed to step S24, otherwise return to step S22;

[0044] Step S24, recording the pair of instructions into a dedicated table;

[0045] Step S25: If all basic blocks have been scanned, go to step S26; otherwise, return to step S22 and repeat the scanning operation until the entire code block has been scanned.

[0046] Step S26, translating the code blocks in sequence to generate an optimized target instruction sequence.

[0047] The pseudo code of the proposed flag instruction sequence translation optimization algorithm is as follows: Figure 3 As shown in the figure. In line 1, the input X86_64 instruction stream I and the output optimized local instruction stream O are defined. In line 3, the flag instruction sequence record table P is initialized to store instruction sequences such as CMP that modify flags. In lines 4-16 of the algorithm, the input instruction stream is traversed and each instruction is processed.

[0048] First, in lines 6-7, if the current instruction is an instruction that modifies the flag, such as CMP, its operand is extracted and recorded in the flag instruction sequence record table P. Then, in lines 8-9, if the current instruction is a conditional jump instruction Jcc, and its predecessor instruction exists in the instruction sequence record table P, the corresponding CMP and other instruction sequences are searched from P. In lines 10-11, if the search is successful, an optimized jump instruction is generated based on the sequence and added to the optimized instruction stream O.

[0049] For other instructions that do not meet the above conditions, in line 13, they are translated into local instructions according to the default rules and added to the optimized instruction stream O. Finally, the optimized local instruction stream O is returned.

[0050] Step S3, based on the translation rules obtained in step S2, the source instruction set is dynamically binary translated; during the dynamic binary translation process, a specific instruction sequence in the source instruction set architecture binary file is detected; for the detected specific instruction sequence, predefined translation rules are used for translation, and for the ordinary instruction sequence in the source instruction set architecture binary file, conventional translation methods are used for translation.

[0051] During the translation process, a flag instruction sequence record table is used to store the operand information of the instruction. The flag instruction sequence record table is used to match subsequent conditional jump instructions (Jcc) to optimize the translation of conditional jump instructions and generate optimized target instruction set architecture instructions.

[0052] Taking the binary translation from X86 to RISC-V as an example, some instruction sequence translation rules are as follows: Figure 4As shown. The source instruction sequence refers to the instruction sequence in the source instruction set architecture involved in the present invention. Generating the target instruction sequence refers to the corresponding instruction sequence on the target platform after the source platform instruction sequence is binary translated. Semantics refers to the overall meaning expressed by the combination of specific instruction sequences. Only some translation rules are listed in the figure, and the content of the present invention includes but is not limited to the instruction sequence in the figure.

[0053] The above instruction translation method can effectively reduce the target code expansion rate and improve the performance of dynamic binary translation by reducing redundant flag generation operations.

[0054] It should be noted that, in various embodiments of the present invention, the sequence numbers of the above steps do not mean the order of execution. The order of execution of the steps should be determined by their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0055] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0056] Figure 5 Schematic diagram of the instruction translation device in the dynamic binary translation of the present invention. Figure 5 As shown, in a second embodiment of the present invention, a command translation device 10 is provided, comprising:

[0057] A difference comparison module 11 is used to obtain the difference between the source instruction set architecture and the target instruction set architecture, and identify a specific instruction sequence in the source instruction set;

[0058] A rule generation module 12, used for designing a translation rule for the specific instruction sequence based on a target instruction set architecture;

[0059] The dynamic translation module 13 is used to detect a specific instruction sequence in a source instruction set architecture binary file during the dynamic binary translation process; for the detected specific instruction sequence, the corresponding translation rules are used for translation, and for the ordinary instructions other than the specific instruction sequence in the source instruction set architecture binary file, the conventional translation method is used for translation.

[0060] In the third embodiment of the present invention, a computer-readable storage medium is proposed. The instruction translation device in the dynamic binary translation of the present invention, if its function is implemented in the form of a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer-readable storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. Therefore, in the third embodiment of the present invention, a computer-readable storage medium is provided for storing a computer program of an instruction translation method in dynamic binary translation. It should be understood that the computer-readable storage medium in the embodiment of the present invention can be a volatile memory and / or a non-volatile memory. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM) and direct rambus RAM (DRRAM).

[0061] Figure 6 Schematic diagram of an electronic device of the present invention. Figure 6As shown, in the fourth embodiment of the present invention, an electronic device 100 is proposed, including the instruction translation device 10 in the dynamic binary translation as described above. A person of ordinary skill in the art can understand that all or part of the steps in the above method can be completed by instructing related hardware (such as a processor, FPGA, ASIC, etc.) through a program. All or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module in the above embodiment can be implemented in the form of hardware, such as implementing its corresponding functions through an integrated circuit, or it can be implemented in the form of a software function module, such as implementing its corresponding functions through a processor executing a program / instruction stored in a memory. The embodiments of the present invention are not limited to any specific form of combination of hardware and software.

[0062] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0063] The electronic device of the present invention may be any device with data processing capability, and the device with data processing capability may be a device or apparatus such as a computer. The device embodiment may be implemented by software, or by hardware or a combination of software and hardware. Taking software implementation as an example, as a device in a logical sense, the processor of any device with data processing capability reads the corresponding computer program instructions in the non-volatile memory into the memory and runs the instructions. Figure 5 This is a schematic diagram of the hardware structure of an electronic device of the present invention. Figure 5 As shown in the figure, from the hardware level, it is a hardware structure diagram of any device with data processing capability where the instruction translation device in the dynamic binary translation of the present invention is located, except Figure 5 In addition to the processor, memory, network interface, and non-volatile memory shown, any device with data processing capabilities in which the apparatus in the embodiments is located may also include other hardware, generally based on the actual functions of the device with data processing capabilities, which will not be described in detail.

[0064] When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media sets. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium may be a solid-state hard disk.

[0065] The instruction translation method in the dynamic binary translation of the present invention is used for optimizing the binary translation efficiency in the computer system, which can not only eliminate redundant instructions, but also further compress the existing flag calculation operations without affecting the program semantics, thereby greatly reducing the target instruction redundancy, obtaining a larger optimization space, and reducing the expansion of the target code instructions to a greater extent.

[0066] The above implementation modes are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the present invention. The patent protection scope of the present invention should be defined by the claims.

Claims

1. A method for translating instructions in dynamic binary translation, characterized in that: include: Obtain the differences between the source instruction set architecture and the target instruction set architecture, and identify specific instruction sequences in the source instruction set; Designing a translation rule for the specific instruction sequence based on the target instruction set architecture; During the dynamic binary translation process, a specific instruction sequence in the source instruction set architecture binary file is detected; for the detected specific instruction sequence, the corresponding translation rules are used for translation.

2. The instruction translation method according to claim 1, characterized in that: The translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

3. The instruction translation method according to claim 1 or 2, characterized in that: The specific instruction sequence includes an instruction sequence involving a flag bit in the source instruction set.

4. The instruction translation method according to claim 1, characterized in that: Also includes: For common instructions in the source instruction set architecture binary file except for the specific instruction sequence, a conventional translation method is used for translation.

5. An instruction translation device in dynamic binary translation, characterized in that: include: A difference comparison module, used to obtain the difference between the source instruction set architecture and the target instruction set architecture, and identify a specific instruction sequence in the source instruction set; A rule generation module, used for designing a translation rule for the specific instruction sequence based on the target instruction set architecture; The dynamic translation module is used to detect a specific instruction sequence in a source instruction set architecture binary file during a dynamic binary translation process; for the detected specific instruction sequence, the corresponding translation rules are used for translation.

6. The instruction translation device according to claim 5, characterized in that: The translation rule includes: merging multiple source instructions in the specific instruction sequence into one or more target instructions.

7. The instruction translation device according to claim 5 or 6, characterized in that: The specific instruction sequence includes an instruction sequence involving a flag bit in the source instruction set.

8. The instruction translation device according to claim 5, characterized in that: The dynamic translation module also includes: translating common instructions other than the specific instruction sequence in the source instruction set architecture binary file using a conventional translation method.

9. An electronic device, comprising the instruction translation device in the dynamic binary translation as claimed in any one of claims 5 to 8.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that: When the computer executable instruction is executed, the instruction translation method in the dynamic binary translation as claimed in any one of claims 1 to 4 is implemented.

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