Method, device and apparatus for calculating maximum latency supported by a DRAM system

Abstract

The present invention discloses a method, apparatus, and device for calculating the maximum latency supported by a DRAM system, relating to the field of storage technology. The method includes establishing a simulation environment whose simulation circuit includes an RDL model, an IBIS IO model, and a DFE model; setting ODT parameters to independently simulate two ranks based on the established simulation environment to obtain DQ and DMI time-domain waveforms; processing the DQ and DMI time-domain waveforms based on a WCK Trigger method and generating an eye diagram; and calculating the Timing Margin and the maximum tWCK2CK_Rank2Rank based on the eye diagram. This application enables accurate calculation of the maximum latency.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method, apparatus, and device for calculating the maximum latency that a DRAM system can support. Background Art

[0002] LPDDR5 SDRAM (Low Power Double Data Rate 5 SDRAM, a high-performance, low-power memory technology designed for mobile devices) uses two clock frequencies: WCK (write clock) and CK (address and command clock). The WCK frequency is four times or twice that of the CK. WCK is the DQ (data signal) data clock, and CK is the command and address clock. Before sending a WRITE or READ command, a WCK2CK Sync operation (synchronization between WCK and CK) is required using a CAS command (a mechanism used to ensure cache data consistency and security). This aligns the phases of the WCK and CK within the SDRAM (Synchronous Dynamic Random Access Memory), preparing for DQ data transmission.

[0003] LPDDR5 (a memory technology) provides a write-leveling feature. During the DDR training phase, the system-on-chip (SoC) clock (WCK) phase is continuously adjusted to align the WCK and CK clocks. This determines the optimal WCK delay (the delay between the WCK signal and the DQ signal), denoted as WCKTxDly. WCKTxDly is then used to perform WCK2CK synchronization before subsequent read and write operations. After WCK2CK synchronization is complete, the WCK sampled DQ signals have the optimal margin (time redundancy).

[0004] For dual-rank SDRAM (a rank is a group of DRAM chips connected to the same chip select), the WCK and CK clocks are connected to both ranks simultaneously. The SoC needs to access both ranks, requiring WCK2CK Sync for both ranks. The difference between the optimal WCKTxDly values obtained after DDR training between one rank and the other is determined by the DRAM (Dynamic Random Access Memory) characteristic parameter tWCK2CK_Rank2Rank. tWCK2CK_Rank2Rank is a characteristic parameter related to timing parameters and is typically used to describe the timing relationship between WCK and CK in DDR5 DRAM, namely, the timing delay from WCK to CK in rank-to-rank operations.

[0005] When accessing dual-rank SDRAM, there are two methods for handling WCK2CK Sync. One method is to perform a WCK2CK Sync on one rank after the DQburst operation on the other rank, with each rank using its own WCKTxDly value. Since a WCK2CK Sync is performed before each read or write, there is a certain performance loss in the LPDDR5 system.

[0006] Performance is a key metric for DDR (double-rate synchronous dynamic random access memory). To improve system performance, the LPDDR5 system must be in WCK always-on mode. In this mode, both ranks share the same WCKTxDly, requiring only a single WCK2CK Sync operation. However, this setting cannot simultaneously meet the optimal WCK Delay values for both ranks, resulting in margin loss for the DQ signals of both ranks.

[0007] Therefore, for a SoC-LPDDR5 DRAM system, SI simulation (signal integrity simulation) must be performed to determine whether the DQ signal eye diagram meets design requirements. However, existing SI simulation cannot simulate the DRAM's tWCK2CK_Rank2Rank parameter. SI simulation for each rank is independent, and there is no unified standard to quantify whether the SoC-DRAM system can operate stably in WCK always-on mode. Furthermore, simulation tools often use a UI (one symbol duration) trigger method to generate DQ eye diagrams, which differs from the on-chip process of sampling data signals using WCK to determine the actual eye diagram. Summary of the Invention

[0008] The present application provides a method, apparatus, and device for calculating the maximum delay that a DRAM system can support, which can achieve accurate calculation of the maximum delay.

[0009] In a first aspect, an embodiment of the present application provides a method for calculating a maximum latency that a DRAM system can support. The method for calculating a maximum latency that a DRAM system can support includes:

[0010] Building a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model;

[0011] Set ODT parameters to simulate the two ranks independently based on the established simulation environment to obtain DQ and DMI time domain waveforms;

[0012] The DQ and DMI time domain waveforms are processed based on the WCK Trigger method to generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

[0013] In conjunction with the first aspect, in one embodiment,

[0014] The link structure of the simulation circuit includes a SoC IBIS model, a SoC PKG model, a PCB model, and a Dram PKG model connected in sequence, and the Dram PKG model is also connected to two DRAM IBIS models, wherein one of the two DRAM IBIS models corresponds to one of the two ranks, and the other DRAM IBIS model corresponds to the other of the two ranks.

[0015] In conjunction with the first aspect, in one embodiment,

[0016] The SoC IBIS model is used to describe the electrical behavior of the DDR interface input / output buffer of the SoC;

[0017] The SoC PKG model is an S-parameter model of the SoC package, which characterizes the high-frequency transmission characteristics of the SoC package structure;

[0018] The PCB model is an S-parameter model of the PCB;

[0019] The Dram PKG model is an S-parameter model of DRAM packaging, which is used to quantify the impact of DRAM chip packaging on signals;

[0020] The DRAM IBIS model is used to simulate the driver and receiver behaviors of the DRAM chip interface.

[0021] In conjunction with the first aspect, in one implementation, the ODT parameters are specifically set as follows:

[0022] When simulating one of the two ranks, the ODT value of the DRAM IBIS model corresponding to the rank is selected according to the transmission line impedance, and the ODT of the DRAM IBIS model corresponding to the other rank is turned off.

[0023] In conjunction with the first aspect, in one embodiment, the WCK Trigger-based method for processing DQ and DMI time domain waveforms and generating eye diagrams specifically includes:

[0024] According to the WCK time domain waveform, the DQ time domain waveform is sliced according to the time length of a complete cycle of the WCK time domain waveform, and the DQ time domain waveform is divided into multiple DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes the first jump edge, level, second jump edge, level and third jump edge;

[0025] Each DQ time domain waveform segment is aligned at the second transition edge time and overlapped to generate an eye diagram.

[0026] In combination with the first aspect, in one embodiment, after generating the eye diagram, the method further includes:

[0027] Determine the unified Vref based on all DQ eye diagrams and DMI eye diagrams of the entire Byte, thereby determining the Eye Mask position;

[0028] Based on the eye diagram and the determined Eye Mask position, the DQ Margin and DMI Margin are calculated.

[0029] In conjunction with the first aspect, in one embodiment, the calculation of the Timing Margin specifically includes:

[0030] For each bit's 3 setup margins and 3 hold margins, record the minimum value of the 3 setup margins and 3 hold margins contained in the current bit as tBit_Margin_Min;

[0031] The minimum value of tBit_Margin_Min of all single-byte signals in the current Rank is used as the tByte_Margin_Min of the current Rank.

[0032] In combination with the first aspect, in one implementation, the maximum tWCK2CK_Rank2Rank is calculated as follows:

[0033] Max tWCK2CK_rank2rank=2Min(tByte_Margin_Min[0], tByte_Margin_Min[1])

[0034] Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents the tByte_Margin_Min of one of the two ranks, and tByte_Margin_Min[1] represents the tByte_Margin_Min of the other of the two ranks.

[0035] In a second aspect, an embodiment of the present application provides a computing device in which a DRAM system can support a maximum latency, wherein the computing device in which the DRAM system can support a maximum latency includes:

[0036] A building module is used to build a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model;

[0037] The simulation module is used to set ODT parameters to simulate two ranks independently based on the established simulation environment to obtain WCK, DQ, and DMI time domain waveforms;

[0038] The calculation module is used to process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

[0039] In a third aspect, an embodiment of the present application provides a computing device for a DRAM system that can support a maximum delay, wherein the computing device for a DRAM system that can support a maximum delay includes a processor, a memory, and a computing program for the maximum delay that the DRAM system can support stored in the memory and executable by the processor, wherein when the computing program for the maximum delay that the DRAM system can support is executed by the processor, the steps of the above-mentioned method for calculating the maximum delay that the DRAM system can support are implemented.

[0040] The beneficial effects of the technical solutions provided in the embodiments of the present application include:

[0041] By building a simulation environment and then setting ODT parameters to independently simulate the two ranks based on the built simulation environment, the DQ and DMI time domain waveforms are obtained. Then, based on the WCK Trigger method, the DQ and DMI time domain waveforms are processed and an eye diagram is generated. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated to quantify the maximum tWCK2CK_rank2rank supported by the SoC-LPDDR5DRAM system and generate the DQ / DMI data signal eye diagram using the WCK Trigger according to the simulation time domain diagram. After the system design is completed, the maximum tWCK2CK_Rank2Rank supported by the system can be directly calculated, thereby proposing requirements for DRAM indicators and reducing testing costs. In addition, it can be pointed out which signals have greater risks before the system is produced, indicating the direction of improvement for the SoC-LPDDR5DRAM system simulation link. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A flowchart illustrating a method for calculating the maximum latency that a DRAM system can support is provided in this application;

[0043] Figure 2 It is the link structure diagram of the simulation circuit;

[0044] Figure 3 This is a functional module diagram of a computing device with the maximum latency supported by the DRAM system of this application;

[0045] Figure 4 This is a schematic diagram of the hardware structure of a computing device with the maximum latency that the DRAM system in this application can support. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0048] First, embodiments of the present application provide a method for calculating the maximum latency a DRAM system can support. This method includes calculating and quantifying the maximum tWCK2CK_rank2rank supported by a SoC-LPDDR5 DRAM system, and generating DQ / DMI data signal eye diagrams using a WCK Trigger based on simulated time domain diagrams. DQ and DMI are key data signals in memory technology.

[0049] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of a method for calculating the maximum delay that a DRAM system can support in this application. Figure 1 As shown in Figure 2, the calculation methods for the maximum latency that a DRAM system can support include:

[0050] S1: Building a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model;

[0051] Among them, RDL stands for Re-distributed Layer, which is the redistribution layer; IBIS stands for Input / Output Buffer Information Specification, which is a behavioral level model; IO stands for input and output; DFE stands for Decision Feedback Equalizer, which is the decision feedback equalizer;

[0052] S2: Set ODT parameters to simulate the two ranks independently based on the established simulation environment to obtain the WCK, DQ, and DMI time domain waveforms;

[0053] S3: Process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, calculate the Timing Margin and the maximum tWCK2CK_Rank2Rank.

[0054] For further information, see Figure 2 As shown, the link structure of the simulation circuit includes a SoC IBIS model, a SoCPKG model, a PCB model, and a Dram PKG model connected in sequence, and the Dram PKG model is also connected to two DRAM IBIS models, wherein one of the two DRAM IBIS models corresponds to one of the two ranks, and the other DRAM IBIS model corresponds to the other of the two ranks.

[0055] Specifically, the SoC IBIS model is used to describe the electrical behavior of the SoC's DDR interface input / output buffer, including the driver's output voltage, current waveform, rise / fall time, output impedance, and the receiver's input impedance and threshold voltage. The SoC PKG model is an S-parameter model (scattering parameter model, a general benchmark behavioral model used to describe the behavior of linear, passive interconnect structures) of the SoC package. It characterizes the high-frequency transmission characteristics of the SoC package structure (such as pins, solder balls, and internal interconnects), and quantifies the signal reflection, insertion loss, crosstalk, and phase delay in the package through scattering parameters.

[0056] The PCB model is an S-parameter model of a printed circuit board (PCB). It describes the frequency domain response of passive structures such as PCB traces, vias, and power / ground planes, including insertion loss, return loss, crosstalk, and impedance discontinuity.

[0057] The DRAM PKG model is an S-parameter model of DRAM packaging, which is used to quantify the impact of DRAM chip packaging (such as BGA packaging) on signals, including impedance changes of package interconnects and signal distortion caused by parasitic parameters.

[0058] The DRAM IBIS model is used to simulate the driver and receiver behaviors of the DRAM chip interface, defining its output drive strength, input logic threshold, and termination characteristics.

[0059] Furthermore, in one embodiment, the ODT parameter setting is specifically as follows: when simulating one of the two ranks, the ODT value of the DRAM IBIS model corresponding to that rank is selected based on the transmission line impedance, and the ODT value of the DRAM IBIS model corresponding to the other rank is disabled. ODT, short for On-Die Termination, is a technology used in DDR SDRAM for signal integrity and reflection reduction.

[0060] Furthermore, the time domain waveforms of WCK, DQ, and DMI obtained by Rank simulation are described in detail as follows.

[0061] The simulation of one of the two ranks (denoted as Rank 0) is used as an example. First, the ODT parameters are set. As the receiving end, DRAM must enable ODT to achieve impedance matching and suppress signal reflections. Therefore, the ODT value of the DRAM IBIS model corresponding to Rank 0 is selected based on the transmission line impedance (such as 40Ω or 48Ω). The ODT of the DRAM IBIS model corresponding to the other Rank must be disabled. Then, the code element sequence of the IBIS input of the DQ / DMI on the SoC side is set to PRBS7, and the code element of the WCK IBIS input is a 0 / 1 sequence. Transient analysis is run in the simulation tool. Finally, the time domain waveform is viewed using the voltage probe Vprobe on the DRAM IBIS model corresponding to Rank 0.

[0062] Furthermore, in one embodiment, the DQ and DMI time domain waveforms are processed based on the WCK Trigger method and the eye diagram is generated, specifically including:

[0063] S301: Slicing the DQ time domain waveform according to the WCK time domain waveform by the time length of a complete cycle of the WCK time domain waveform, dividing the DQ time domain waveform into multiple DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes a first transition edge, a level, a second transition edge, a level, and a third transition edge;

[0064] S302: Align each DQ time domain waveform segment according to the second transition edge time, and overlap to generate an eye diagram.

[0065] Specifically, a complete cycle of the WCK time domain waveform is obtained, and the complete cycle of the WCK time domain waveform is recorded as the target time domain waveform. The DQ time domain waveform is sliced using the time length of the target time domain waveform to obtain multiple DQ time domain waveform segments. Each DQ time domain waveform segment is aligned according to the moment of the second jump edge of the target time domain waveform, and overlapped to generate an eye diagram.

[0066] Furthermore, after the eye diagram is generated, the following steps are also included:

[0067] a: Determine a unified Vref (reference voltage) based on all DQ eye diagrams and DMI eye diagrams of the entire byte, thereby determining the Eye Mask position; the Eye Mask position is the boundary used to specify the minimum eye opening in the eye diagram test;

[0068] b: Calculate the DQ margin and DMI margin based on the eye diagram and the determined eye mask position.

[0069] Furthermore, in one embodiment, the calculation of the Timing Margin specifically includes:

[0070] S311: For the 3 setup margins and 3 hold margins included in each Bit, record the minimum value among the 3 setup margins (setup time redundancy) and 3 hold margins (hold time redundancy) included in the current Bit as tBit_Margin_Min;

[0071] S312: Take the minimum value of tBit_Margin_Min of all signals of a single Byte in the current Rank as the tByte_Margin_Min of the current Rank. Here, Timing Margin is denoted as time redundancy.

[0072] Specifically, each Bit (bit) contains 3 setup margins and 3 hold margins. Define the minimum value among the 6 margins as tBit_Margin_Min. At the same time, for a single Rank, define the minimum value of tBit_Margin_Min of all signals of a single Byte in the Rank as tByte_Margin_Min.

[0073] Further, in one embodiment, for the maximum tWCK2CK_Rank2Rank, the calculation method is:

[0074] Max tWCK2CK_rank2rank = 2Min(tByte_Margin_Min[0], tByte_Margin_Min[1])

[0075] Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents the tByte_Margin_Min of one of the two Ranks, and tByte_Margin_Min[1] represents the tByte_Margin_Min of the other Rank of the two Ranks.

[0076] Specifically, in the WCK always on mode, the offset of WCK relative to the center of the DQ eye diagram is: tWCK2CK_rank2rank / 2, and it affects all signals of a single Byte. Therefore, for the system to work properly, it needs to satisfy: tWCK2CK_rank2rank / 2 < tByte_Margin_Min[rank], that is, the calculation method of Max tWCK2CK_rank2rank is 2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]).

[0077] The DRAM system of the embodiment of the present application can support a method for calculating the maximum latency. By building a simulation environment and then setting ODT parameters to independently simulate two ranks based on the built simulation environment, DQ and DMI time domain waveforms are obtained, and then the DQ and DMI time domain waveforms are processed based on the WCK Trigger method to generate an eye diagram. According to the eye diagram, the TimingMargin and the maximum tWCK2CK_Rank2Rank are calculated to achieve quantification of the maximum tWCK2CK_rank2rank supported by the SoC-LPDDR5 DRAM system, and the generation of the DQ / DMI data signal eye diagram by the WCK Trigger based on the simulation time domain diagram. The maximum tWCK2CK_Rank2Rank supported by the system can be directly calculated after the system design is completed, thereby putting forward requirements for DRAM indicators and reducing testing costs. It can also indicate which signals have greater risks before the system is produced, indicating the direction of improvement for the SoC-LPDDR5 DRAM system simulation link.

[0078] In a second aspect, an embodiment of the present application further provides a computing device in which a DRAM system can support maximum latency.

[0079] In one embodiment, referring to Figure 3 , Figure 3 This is a functional module diagram of a computing device that can support the maximum latency supported by the DRAM system of this application. Figure 3 As shown, the computing devices with the maximum latency that the DRAM system can support include: building module, simulation module, and computing module.

[0080] The construction module is used to build a simulation environment, and the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model and a DFE model; the simulation module is used to set the ODT parameters to independently simulate the two ranks based on the built simulation environment to obtain WCK, DQ, and DMI time domain waveforms; the calculation module is used to process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated.

[0081] On the third aspect, an embodiment of the present application provides a computing device with a maximum latency supported by a DRAM system. The computing device with a maximum latency supported by the DRAM system can be a personal computer (PC), a laptop, a server, or other device with data processing capabilities.

[0082] Reference Figure 4 , Figure 4Schematic diagram of the hardware structure of a computing device with a maximum latency supported by a DRAM system involved in an embodiment of the present application. In the embodiment of the present application, the computing device with a maximum latency supported by a DRAM system may include a processor, a memory, a communication interface, and a communication bus.

[0083] The communication bus may be of any type and is used to interconnect the processor, memory, and communication interface.

[0084] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces. These interfaces interconnect components within the computing device with the maximum latency supported by the DRAM system, as well as interfaces that interconnect the computing device with other devices (such as other computing devices or user devices). Physical interfaces can include Ethernet, fiber, and ATM interfaces; user devices can include displays and keyboards.

[0085] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0086] The processor may be a general-purpose processor that can call a calculation program for the maximum latency that a DRAM system can support stored in a memory and execute the method for calculating the maximum latency that a DRAM system can support provided in the embodiments of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the calculation program for the maximum latency that a DRAM system can support is called can be referenced by referring to the various embodiments of the method for calculating the maximum latency that a DRAM system can support in the present application, and will not be further described here.

[0087] Those skilled in the art will understand that Figure 4 The hardware structure shown in the figure does not constitute a limitation to the present application and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0088] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit the "first", "second" and "third" to different types.

[0089] In the description of the embodiments of this application, the words "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0090] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0091] In some processes described in the embodiments of the present application, multiple operations or steps are included that appear in a specific order. However, it should be understood that these operations or steps may not be performed in the order in which they appear in the embodiments of the present application or may be performed in parallel. The sequence numbers of the operations are only used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be performed in sequence or in parallel, and these operations or steps may be combined.

[0092] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above and includes a number of instructions for enabling a terminal device to execute the methods described in each embodiment of this application.

[0093] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for calculating the maximum latency supported by a DRAM system, characterized in that: The calculation method of the maximum latency that the DRAM system can support includes: Building a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model; Set ODT parameters to simulate the two ranks independently based on the established simulation environment to obtain DQ and DMI time domain waveforms; Process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, calculate the Timing Margin and the maximum tWCK2CK_Rank2Rank; The WCK Trigger-based method for processing DQ and DMI time domain waveforms and generating eye diagrams specifically includes: According to the WCK time domain waveform, the DQ time domain waveform is sliced according to the time length of a complete cycle of the WCK time domain waveform, and the DQ time domain waveform is divided into multiple DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes the first jump edge, level, second jump edge, level and third jump edge; Align each DQ time domain waveform segment according to the second transition edge time, and overlap to generate an eye diagram; After the eye diagram is generated, the following steps are also included: Determine a unified Vref based on all DQ eye diagrams and DMI eye diagrams of the entire Byte, thereby determining the Eye Mask position; Based on the eye diagram and the determined Eye Mask position, calculate the DQ Margin and DMI Margin; The calculation of Timing Margin specifically includes: For each bit's 3 setup margins and 3 hold margins, record the minimum value of the 3 setup margins and 3 hold margins contained in the current bit as tBit_Margin_Min; The minimum value of tBit_Margin_Min of all single-byte signals in the current Rank is used as the tByte_Margin_Min of the current Rank; Among them, for the maximum tWCK2CK_Rank2Rank, the calculation method is: Max tWCK2CK_rank2rank=2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]) Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents the tByte_Margin_Min of one of the two ranks, and tByte_Margin_Min[1] represents the tByte_Margin_Min of the other of the two ranks.

2. The method for calculating the maximum latency supported by a DRAM system according to claim 1, wherein: The link structure of the simulation circuit includes a SoC IBIS model, a SoC PKG model, a PCB model, and a DramPKG model connected in sequence, and the Dram PKG model is also connected to two DRAM IBIS models, wherein one of the two DRAM IBIS models corresponds to one of the two ranks, and the other DRAM IBIS model corresponds to the other of the two ranks.

3. The method for calculating the maximum latency supported by a DRAM system according to claim 2, wherein: The SoC IBIS model is used to describe the electrical behavior of the DDR interface input / output buffer of the SoC; The SoC PKG model is an S-parameter model of the SoC package, which characterizes the high-frequency transmission characteristics of the SoC package structure; The PCB model is an S-parameter model of the PCB; The Dram PKG model is an S-parameter model of DRAM packaging, which is used to quantify the impact of DRAM chip packaging on signals; The DRAM IBIS model is used to simulate the driver and receiver behaviors of the DRAM chip interface.

4. The method for calculating the maximum delay that a DRAM system can support according to claim 3, wherein: The ODT parameter settings are as follows: When simulating one of the two ranks, the ODT value of the DRAM IBIS model corresponding to the rank is selected according to the transmission line impedance, and the ODT of the DRAM IBIS model corresponding to the other rank is turned off.

5. A computing device with a DRAM system capable of supporting a maximum latency, characterized in that: The computing devices with the maximum latency supported by the DRAM system include: A building module is used to build a simulation environment, wherein the simulation circuit of the simulation environment includes an RDL model, an IBIS IO model, and a DFE model; The simulation module is used to set ODT parameters to simulate two ranks independently based on the established simulation environment to obtain WCK, DQ, and DMI time domain waveforms; A calculation module is used to process the DQ and DMI time domain waveforms based on the WCK Trigger method and generate an eye diagram. According to the eye diagram, the Timing Margin and the maximum tWCK2CK_Rank2Rank are calculated; The WCK Trigger-based method for processing DQ and DMI time domain waveforms and generating eye diagrams specifically includes: According to the WCK time domain waveform, the DQ time domain waveform is sliced according to the time length of a complete cycle of the WCK time domain waveform, and the DQ time domain waveform is divided into multiple DQ time domain waveform segments, wherein a complete cycle of the WCK time domain waveform includes the first jump edge, level, second jump edge, level and third jump edge; Align each DQ time domain waveform segment according to the second transition edge time, and overlap to generate an eye diagram; After the eye diagram is generated, the following steps are also included: Determine a unified Vref based on all DQ eye diagrams and DMI eye diagrams of the entire Byte, thereby determining the Eye Mask position; Based on the eye diagram and the determined Eye Mask position, calculate the DQ Margin and DMI Margin; The calculation of Timing Margin specifically includes: For each bit's 3 setup margins and 3 hold margins, record the minimum value of the 3 setup margins and 3 hold margins contained in the current bit as tBit_Margin_Min; The minimum value of tBit_Margin_Min of all single-byte signals in the current Rank is used as the tByte_Margin_Min of the current Rank; Among them, for the maximum tWCK2CK_Rank2Rank, the calculation method is: Max tWCK2CK_rank2rank=2Min(tByte_Margin_Min[0], tByte_Margin_Min[1]) Among them, Max tWCK2CK_rank2rank represents the maximum tWCK2CK_Rank2Rank, tByte_Margin_Min[0] represents the tByte_Margin_Min of one of the two ranks, and tByte_Margin_Min[1] represents the tByte_Margin_Min of the other of the two ranks.

6. A computing device with a DRAM system capable of supporting a maximum latency, characterized in that: The computing device for the maximum delay that the DRAM system can support includes a processor, a memory, and a computing program for the maximum delay that the DRAM system can support, which is stored in the memory and can be executed by the processor. When the computing program for the maximum delay that the DRAM system can support is executed by the processor, the steps of the computing method for the maximum delay that the DRAM system can support as described in any one of claims 1 to 4 are implemented.

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