A high-speed master-slave dual-sampling D flip-flop with an input approximation clock

Abstract

The application discloses a high-speed master-slave type double-sampling D flip-flop with input approximation clock, comprising a control signal generating circuit, a master trigger circuit and a slave trigger circuit; the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the CK is at a low level, the master trigger circuit receives data input, and the slave trigger circuit is at a maintaining state; when the CK is at a high level, the master trigger circuit is at a maintaining state without being affected by the input signal, and the slave trigger circuit receives the storage state of the master trigger circuit to update the flip-flop state. Compared with the conventional D flip-flop with a scanning structure, the control of the data input signal D of the flip-flop of the application is more accurate, which is not only controlled by the clock signal, but also controlled by an enabling signal and an internal signal of the master trigger circuit; meanwhile, the slave trigger circuit receives the output signal of the master trigger circuit by using a double-sampling structure, so that the delay characteristics of the flip-flop are improved, the average delay is reduced by 8.74%, and the maximum delay is reduced by 24.9%.

Description

TECHNICAL FIELD

[0001] The present application mainly relates to the technical field of digital circuit, and particularly relates to a high-speed master-slave type double-sampling D flip-flop which is inputted with an approximate clock. BACKGROUND

[0002] With the rapid development of digital circuit technology, the trigger, as one of the core components in digital integrated circuits, is facing higher and higher performance requirements. In particular, in high-speed digital circuits, the stability and speed of the trigger directly affect the performance of the entire digital circuit and chip. Among them, the D flip-flop has the widest range of applications and the strongest adaptability. The traditional D flip-flop design faces many challenges in high-speed applications, such as large signal delay, high power consumption, poor anti-interference ability, etc. The signal path of the traditional D flip-flop is relatively long, resulting in large signal transmission delay, which limits the improvement of the working frequency. Therefore, in order to overcome the problem of large delay of the traditional trigger and improve the working frequency, it has important practical significance to develop a high-performance high-speed master-slave type double-sampling D flip-flop which is inputted with an approximate clock.

[0003] Figure 1 as shown is a D flip-flop unit schematic diagram with a scan structure, Figure 2 as shown is a traditional scan structure master-slave type flip-flop structure (Scan-Enabled Conventional Transmission-Gate Flip-Flop (STGFF)) circuit, Figure 3 as shown is a master-slave type D flip-flop structure (Conventional transmission-gate flip-flop (TGFF)) circuit, which is widely used in the design of commercial digital circuit standard cell library under various process nodes. The advantage of this structure is simple structure but fixed performance under fixed process, which is difficult to improve. Therefore, a high-speed master-slave type double-sampling D flip-flop which is inputted with an approximate clock can be designed to improve the delay characteristics of the trigger and be applied to higher performance digital integrated circuit design. SUMMARY

[0004] In view of the technical problems existing in the prior art, the present application provides a high-speed master-slave type double-sampling D flip-flop which is inputted with an approximate clock and greatly improves the delay characteristics of the trigger.

[0005] To solve the above technical problems, the technical solution provided by the present application is:

[0006] A high-speed master-slave type double-sampling D flip-flop which is inputted with an approximate clock, comprising a master trigger circuit, a control signal generation circuit and a slave trigger circuit.

[0007] The master trigger circuit comprises:

[0008] PMOS transistor MP1, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to control signal cks2n, drain driving signal v1;

[0009] PMOS transistor MP2, substrate connected to power supply VDD, source connected to signal v1, gate connected to clock complementary signal ckn, drain driving signal ml_ax;

[0010] PMOS transistor MP3, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal ml_b, drain driving signal v1;

[0011] PMOS transistor MP4, substrate connected to power supply VDD, source connected to signal v1, gate connected to data input signal D, drain driving signal ml_ax;

[0012] NMOS transistor MN1, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to control signal cks3n, drain driving signal v2;

[0013] NMOS transistor MN2, substrate connected to power supply VSS, source connected to signal v2, gate connected to clock signal ckn, drain driving signal ml_ax;

[0014] NMOS transistor MN3, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to signal ml_b, drain driving signal v2;

[0015] NMOS transistor MN4, substrate connected to power supply VSS, source connected to signal v2, gate connected to data signal D, drain driving signal ml_ax;

[0016] Inverter X5, input driven by signal ml_ax, output driving signal ml_b;

[0017] Scanning structure, input connected to signal sen, signal SI, clock signal ckn, enable signal SE and clock signal ckn, output driving signal ml_ax;

[0018] The control signal generating circuit, input driven by clock signal CK and enable signal SE, output driving clock complementary signal ckn, signal ckn and enable signal SE complementary signal sen; and signal ckn and signal sen to generate control signal cks2n and control signal cks3n;

[0019] The slave trigger circuit, input connected to signal ml_ax and sl_ax signal, output driving output signal Q.

[0020] Preferably, the slave trigger circuit, comprising:

[0021] Transmission gate TG1, data input terminal connected to signal ml_b, data output terminal connected to signal sl_ax, clock signal PMOS input terminal connected to signal ckn, clock signal NMOS input terminal connected to signal cknn;

[0022] Transmission gate TG2, data input terminal connected to signal ml_ax, data output terminal connected to signal sl_b, clock signal PMOS input terminal connected to signal ckn, clock signal NMOS input terminal connected to signal cknn;

[0023] Transmission gate TG3, data input terminal connected to signal sl_ax, data output terminal connected to signal sl_bn, clock signal PMOS input terminal connected to signal cknn, clock signal NMOS input terminal connected to signal ckn;

[0024] Inverter X6, input terminal driven by signal sl_ax, output terminal driving signal sl_b;

[0025] Inverter X7, input terminal driven by signal sl_b, output terminal driving signal sl_bn;

[0026] Inverter X8, input terminal driven by signal sl_b, output terminal driving output signal Q.

[0027] Preferably, the trigger circuit further comprises:

[0028] Inverter X9, input terminal driven by signal sl_ax, output terminal driving signal QN.

[0029] Preferably, the scan structure comprises:

[0030] PMOS transistor MP5, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal sen, drain driving signal v3;

[0031] PMOS transistor MP6, substrate connected to power supply VDD, source connected to signal v3, gate scan signal SI, drain driving signal v4;

[0032] PMOS transistor MP7, substrate connected to power supply VDD, source connected to signal v4, gate connected to clock signal cknn, drain driving signal ml_ax;

[0033] NMOS transistor MN5, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to enable signal SE, drain driving signal v6;

[0034] NMOS transistor MN6, substrate connected to power supply VSS, source connected to signal v6, gate scan signal SI, drain driving signal v5;

[0035] NMOS transistor MN7, the substrate is connected to the power supply VSS, the source is connected to the signal v5, the gate is connected to the clock signal ckn, and the drain drives the signal ml_ax.

[0036] Preferably, the control signal generation circuit comprises:

[0037] Inverter X1, the input end is driven by the clock signal CK, and the output end drives the clock complementary signal ckn;

[0038] Inverter X2, the input end is driven by the clock complementary signal ckn, and the output end drives the signal cknn;

[0039] Inverter X3, the input end is driven by the enable signal SE, and the output end drives the complementary signal sen of the enable signal SE;

[0040] Inverter X4, the input end is driven by the signal cks2n, and the output end drives the signal cks3n;

[0041] Two-input NAND gate, the input ends are respectively driven by the enable complementary signal sen and the clock complementary signal ckn, and the output drives the signal cks2n.

[0042] Compared with the prior art, the advantages of the present application are:

[0043] Compared with the conventional D flip-flop STGFF with a scan structure, the control of the data input signal D of the flip-flop of the present application is more precise, not only controlled by the clock signal, but also controlled by the enable signal and the internal signal of the main trigger circuit, and at the same time, the output signal of the main trigger circuit is received by the slave trigger circuit using a double sampling structure, which greatly improves the delay characteristics of the flip-flop (the average delay is reduced by 8.74%, and the maximum delay is reduced by 24.9%), reduces the setup time of the flip-flop, and optimizes the CK2Q delay, which is very suitable for high-performance chip design such as high-frequency CPU, GPU, etc.

[0044] Compared with the conventional D flip-flop with a scan structure, the high-speed master-slave double sampling D flip-flop (SDTGFF) proposed in the present application has one less transmission gate circuit when the data is input, the setup time is shorter, the slave trigger circuit uses a double sampling structure, and the state of the main trigger circuit is transmitted to the output circuit only once when the clock signal rises, and the CK2Q delay is shorter.

[0045] Compared with the conventional D flip-flop, the high-speed master-slave double sampling D flip-flop proposed in the present application has a double sampling structure, and the state of the main trigger circuit is transmitted to the output circuit only once when the clock signal rises, and the CK2Q delay is shorter. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1This is a schematic diagram of a traditional D flip-flop circuit with a scanning structure; where D is the data input signal, CK is the clock input signal, SE is the enable signal, SI is the scan input signal, and Q is the output signal.

[0047] Figure 2 This is a circuit diagram of a traditional STGFF D flip-flop with a scanning structure.

[0048] Figure 3 This is the circuit structure diagram of a traditional D flip-flop TGFF.

[0049] Figure 4 This is a circuit diagram of the high-speed master-slave type dual-sampling D flip-flop SDTGFF according to Embodiment 1 of the present invention.

[0050] Figure 5 This is a circuit diagram of the high-speed master-slave type dual-sampling D flip-flop NSDTGFF according to Embodiment 2 of the present invention. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0052] Example 1:

[0053] like Figure 4 As shown, the high-speed master-slave dual-sampling D flip-flop with input approximation clock provided in this embodiment of the invention includes a slave trigger circuit, a master trigger circuit, and a control signal generation circuit; the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the clock signal CK is low, the master trigger circuit receives data input at the D terminal, while the slave trigger circuit is in a holding state; when the clock signal CK is high, the master trigger circuit is not affected by the input signal and is in a holding state, while the slave trigger circuit receives the stored state of the master trigger circuit, thereby updating the flip-flop state;

[0054] The trigger circuit includes:

[0055] Transmission gate TG1, data input terminal connected to signal ml_b, data output terminal connected to signal sl_ax, clock signal PMOS input terminal (G) connected to signal ckn, clock signal NMOS input terminal (G) connected to signal cknn;

[0056] Transmission gate TG2, data input terminal connected to signal ml_ax, data output terminal connected to signal sl_b, clock signal PMOS input terminal (G) connected to signal ckn, clock signal NMOS input terminal (G) connected to signal cknn;

[0057] Transmission gate TG3, data input terminal connected to sl_ax signal, data output terminal connected to sl_bn signal, clock signal PMOS input terminal (G) connected to signal cknn, clock signal NMOS input terminal (G) connected to signal ckn;

[0058] Inverter X6, the input end is driven by signal sl_ax, and the output end drives signal sl_b;

[0059] Inverter X7, the input end is driven by signal sl_b, and the output end drives output signal sl_bn;

[0060] Inverter X8, the input end is driven by signal sl_b, and the output end drives output signal Q.

[0061] The main trigger circuit comprises:

[0062] PMOS transistor MP1, the substrate is connected to power supply VDD, the source is connected to power supply VDD, the gate is connected to signal cks2n, and the drain drives signal v1;

[0063] PMOS transistor MP2, the substrate is connected to power supply VDD, the source is connected to signal v1, the gate is connected to clock complementary signal ckn, and the drain drives signal ml_ax;

[0064] PMOS transistor MP3, the substrate is connected to power supply VDD, the source is connected to power supply VDD, the gate is connected to signal ml_b, and the drain drives signal v1;

[0065] PMOS transistor MP4, the substrate is connected to power supply VDD, the source is connected to signal v1, the gate is connected to data input signal D, and the drain drives signal ml_ax;

[0066] PMOS transistor MP5, the substrate is connected to power supply VDD, the source is connected to power supply VDD, the gate is connected to signal sen, and the drain drives signal v3;

[0067] PMOS transistor MP6, the substrate is connected to power supply VDD, the source is connected to signal v3, the gate is connected to scanning signal SI, and the drain drives signal v4;

[0068] PMOS transistor MP7, the substrate is connected to power supply VDD, the source is connected to signal v4, the gate is connected to clock signal ckn, and the drain drives signal ml_ax;

[0069] NMOS transistor MN1, the substrate is connected to power supply VSS, the source is connected to power supply VSS, the gate is connected to control signal cks3n, and the drain drives signal v2;

[0070] NMOS transistor MN2, the substrate is connected to power supply VSS, the source is connected to signal v2, the gate is connected to clock signal ckn, and the drain drives signal ml_ax.

[0071] NMOS transistor MN3, the substrate is connected to power supply VSS, the source is connected to power supply VSS, the gate is connected to signal ml_b, and the drain drives signal v2;

[0072] NMOS transistor MN4, substrate connected to power supply VSS, source connected to signal v2, gate connected to data signal D, drain driving signal ml ax;

[0073] NMOS transistor MN5, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to enable signal SE, drain driving signal v6;

[0074] NMOS transistor MN6, substrate connected to power supply VSS, source connected to signal v6, gate scanning signal SI, drain driving signal v5;

[0075] NMOS transistor MN7, substrate connected to power supply VSS, source connected to signal v5, gate connected to clock signal ckn, drain driving signal ml ax;

[0076] Inverter X5, input driven by signal ml ax, output driving signal ml b.

[0077] The control signal generating circuit comprises:

[0078] Inverter X1, input driven by clock signal CK, output driving clock complementary signal ckn;

[0079] Inverter X2, input driven by clock complementary signal ckn, output driving signal ckn n;

[0080] Inverter X3, input driven by enable signal SE, output driving complementary signal sen of enable signal SE;

[0081] Inverter X4, input driven by signal cks2n, output driving control signal cks3n;

[0082] Two-input NAND gate, inputs driven by enable complementary signal sen and clock complementary signal ckn respectively, output driving control signal cks2n.

[0083] The above-mentioned input approximation high-speed master-slave type double sampling D flip-flop (Scan-Enabled Double transmission-gate flip-flop, abbreviated as SDTGFF), the slave trigger circuit uses a double sampling circuit structure, as shown in Figure 4 Under the control of the clock signal, the output signals ml ax and ml b of the master trigger circuit are transmitted to the slave trigger circuit through two internal transistors of the same size TG1 and TG2. As shown in Figure 2 In the conventional structure D flip-flop structure STGFF, under the control of the clock, the output signal of inverter X4 passes through transmission gate TG3, and then passes through inverters X6 and X8 to reach the output Q, and the signal passes through twice inversion; and as Figure 4The high-speed master-slave type double sampling D flip-flop (SDTGFF) of the application is shown. The output signal ml_ax of the master trigger circuit passes through the transmission gate TG2, and only needs to pass through the inverter X8 to reach the output Q after one inversion, reducing the number of signal inversions and improving the trigger delay characteristics. The clock to output delay (CK2Q) is reduced.

[0084] Figure 4 The working principle of the SDTGFF trigger circuit shown is as follows:

[0085] The signal ckn is the complement of the signal CK; at the same time, the signal ckn is the complement of the signal ckn, that is, when the clock signal CK is input as high level, ckn is low level and ckn is high level; otherwise, when CK is low, ckn is high and ckn is low. Similarly, SE and sen are complementary signals, SE is 1 and sen is 0; SE is 0 and sen is 1.

[0086] When the enable signal SE is 0, sen is 1, MP5 and MN5 are cut off, and no matter how the signal SI and the signal ckn change, the signal ml_ax will not change. At this time, the signal input is controlled by the data input end D, and is irrelevant to the scan signal end SI. At the same time, CK is 0, ckn is 1, the NAND output cks2n is 0, and MP1 is driven to be turned on. After the cks2n is inverted by the inverter X4, the signal cks3n is high level 1, driving MN1 to be turned on; at this time, when the data input signal D is 0, MP4 is turned on, the signal ml_ax is pulled up to 1, and after the inverter X2, the signal ml_b is pulled down to 0; otherwise, when D is 1, MN4 is turned on, the signal ml_ax is pulled down to 0, and the signal ml_b is pulled up to 1. Therefore, when the enable signal SE is 0 and the signal CK is 0, the control signal generation circuit inputs the signal D, the master trigger circuit samples the data input signal D and updates the state.

[0087] When the enable signal SE is set to 1, sen is 0, MP5 and MN5 are turned on, the NAND output cks2n is always 0, the signal cks3n is always 1 after driving the inverter X4, so MP1 and MN1 are cut off, at this time, no matter how the data input signal D changes, the signal ml_ax is related to SI; at this time, SE is 1, sen is 0 and CK is 1 (ckn is 0, cknn is 1 and ck3n is 0), MP5, MN5, MP7 and MN7 are all turned on, and when SI is 0, MP13 is also turned on and MN13 is cut off, the signal ml_ax is pulled up to 1, and the driving signal ml_b is pulled down to 0 after passing through the inverter X5, which is consistent with the signal SI; conversely, when SI is 1, the signal ml_ax is pulled down to 0 and the signal ml_b is pulled up to 1. Therefore, when the enable signal SE is set to 1 and the signal CK is set to 0, the control signal generation circuit inputs the scanning signal SI, and the main trigger circuit samples the scanning signal SI and updates the state.

[0088] When the clock input signal CK is set to 0, ckn is 1, cknn is 0 and ck3n is 1, the transmission gates TG1 and TG2 are cut off and TG3 is turned on; the inverter X7 and the inverter X6 constitute two first-order connected inverters to maintain the state of the slave trigger circuit and drive the inverter X8 to maintain the output signal Q.

[0089] When the clock input signal CK is set to 1, ckn is 0, cknn is 1 and ck3n is 1, the NAND output cks2n is always 0, the signal cks3n is always 1 after driving the inverter X4, so MP1 and MN1 are cut off; at this time, MP3, MN3 and the inverter X5 constitute two first-order connected inverters to maintain the state of the main trigger circuit; the transmission gate TG2 transmits the state of the signal ml_ax to the sl_b node, at this time, the state of the node ml_ax is the or scanning signal of the data input signal of the last beat, and then the data is updated through the inverter X8 to Q; the transmission gate TG1 transmits the state of the signal ml_b to the sl_ax node, and then the signal is transmitted to the node sl_b after passing through the inverter X6, at this time, the node sl_b is the state of the node ml_ax (i.e. the inverse of the signal sl_ax), and then the signal is consistent with the original signal of the sl_ax node after passing through the inverter again. Because the main trigger circuit is always in a maintenance state, the signals ml_ax and ml_b are not affected by the data input signal D and the scanning signal SI and remain stable, so the state update of the slave trigger circuit occurs at the moment when the signal CK changes from low level to high level, that is, the trigger of the application is a rising edge triggered D trigger with a scanning structure.

[0090] The high-speed main-slave type double-sampling D trigger SDTGFF proposed in the embodiment inputs an approximate clock, like Figure 4The SDTGFF has excellent delay characteristics of small setup time and small CK2Q delay. Compared with the conventional D flip-flop STGFF circuit with a scan structure, the circuit can be widely applied to high-performance high-frequency digital circuit design.

[0091] Embodiment Two

[0092] In the embodiment one, the output of the SDTGFF is inverted to obtain an inverted signal high-speed scan-enabled D flip-flop (Inverted Signal Scan-Enabled Double Transmission-Gate Flip-Flop (NSDTGFF)), as shown in Figure 5 to be applicable to common scenarios where the output signal needs to be inverted.

[0093] As shown in Figure 5 Compared with the flip-flop in embodiment one, the data output of the flip-flop in this embodiment is the inverted signal of the stored data of the main flip-flop. The flip-flop also includes a slave flip-flop circuit, a main flip-flop circuit, and a control signal generation circuit.

[0094] The slave flip-flop circuit includes:

[0095] The transmission gate TG1 has a data input end connected to the signal ml_b, a data output end connected to the signal sl_ax, a clock signal PMOS input end (G) connected to the signal ckn, and a clock signal NMOS input end (G) connected to the signal cknn.

[0096] The transmission gate TG2 has a data input end connected to the signal ml_ax, a data output end connected to the signal sl_b, a clock signal PMOS input end (G) connected to the signal ckn, and a clock signal NMOS input end (G) connected to the signal cknn.

[0097] The transmission gate TG3 has a data input end connected to the signal sl_ax, a data output end connected to the signal sl_bn, a clock signal PMOS input end (G) connected to the signal cknn, and a clock signal NMOS input end (G) connected to the signal ckn.

[0098] The inverter X6 has an input end driven by the signal sl_ax and an output end driving the signal sl_b.

[0099] The inverter X7 has an input end driven by the signal sl_b and an output end driving the output signal sl_bn.

[0100] The inverter X8 has an input end driven by the signal sl_b and an output end driving the output signal Q.

[0101] The inverter X9 has an input end driven by the signal sl_ax and an output end driving the signal QN.

[0102] The master trigger circuit comprises:

[0103] A PMOS transistor MP1, a substrate connected to a power supply VDD, a source connected to the power supply VDD, a gate connected to a signal cks2n, and a drain driving a signal v1;

[0104] A PMOS transistor MP2, a substrate connected to the power supply VDD, a source connected to the signal v1, a gate connected to a clock complementary signal ckn, and a drain driving a signal ml_ax;

[0105] A PMOS transistor MP3, a substrate connected to the power supply VDD, a source connected to the power supply VDD, a gate connected to a signal ml_b, and a drain driving the signal v1;

[0106] A PMOS transistor MP4, a substrate connected to the power supply VDD, a source connected to the signal v1, a gate connected to a data input signal D, and a drain driving the signal ml_ax;

[0107] A PMOS transistor MP5, a substrate connected to the power supply VDD, a source connected to the power supply VDD, a gate connected to a signal sen, and a drain driving a signal v3;

[0108] A PMOS transistor MP6, a substrate connected to the power supply VDD, a source connected to the signal v3, a gate connected to a scan signal SI, and a drain driving a signal v4;

[0109] A PMOS transistor MP7, a substrate connected to the power supply VDD, a source connected to the signal v4, a gate connected to a clock signal ckn, and a drain driving the signal ml_ax;

[0110] An NMOS transistor MN1, a substrate connected to a power supply VSS, a source connected to the power supply VSS, a gate connected to a control signal cks3n, and a drain driving a signal v2;

[0111] An NMOS transistor MN2, a substrate connected to the power supply VSS, a source connected to the signal v2, a gate connected to the clock signal ckn, and a drain driving the signal ml_ax.

[0112] An NMOS transistor MN3, a substrate connected to the power supply VSS, a source connected to the power supply VSS, a gate connected to the signal ml_b, and a drain driving the signal v2;

[0113] An NMOS transistor MN4, a substrate connected to the power supply VSS, a source connected to the signal v2, a gate connected to the data signal D, and a drain driving the signal ml_ax;

[0114] An NMOS transistor MN5, a substrate connected to the power supply VSS, a source connected to the power supply VSS, a gate connected to an enable signal SE, and a drain driving a signal v6;

[0115] An NMOS transistor MN6, a substrate connected to the power supply VSS, a source connected to the signal v6, a gate connected to the scan signal SI, and a drain driving a signal v5;

[0116] NMOS transistor MN7, the substrate is connected to power supply VSS, the source is connected to signal v5, the gate is connected to clock signal ckn, and the drain drives signal ml_ax;

[0117] Inverter X5, the input is driven by signal ml_ax, and the output drives signal ml_b.

[0118] Wherein MP5, MP6, MP7, MN5, MN6 and MN7 belong to a scanning structure;

[0119] The control signal generation circuit comprises:

[0120] Inverter X1, the input is driven by clock signal CK, and the output drives clock complementary signal ckn;

[0121] Inverter X2, the input is driven by clock complementary signal ckn, and the output drives signal ckn.

[0122] Inverter X3, the input is driven by enable signal SE, and the output drives complementary signal sen of the enable signal;

[0123] Inverter X4, the input is driven by signal cks2n, and the output drives signal cks3n;

[0124] Two-input NAND gate, the inputs are respectively driven by complementary signal sen and clock complementary signal ckn, and the output drives signal cks2n.

[0125] Figure 5 The working principle of the NSDTGFF trigger circuit shown is the same as that of the SDTGFF, but one inverter X9 is added to the sl_ax node, the input of X9 is connected to signal sl_ax, and the output drives QN.

[0126] Compared with the conventional D trigger STGFF with a scanning structure, the control of the data input signal D of the trigger SDTGFF is more precise, which is not only controlled by a clock signal, but also controlled by an enable signal and an internal signal of a main trigger circuit, and a double sampling circuit structure is used in the slave trigger circuit, so that the delay characteristics of the trigger are greatly improved (the average delay is reduced by 8.74%, and the maximum delay is reduced by 24.9%), the setup time of the trigger is reduced, and the CK2Q delay is optimized, and the trigger is very suitable for high-frequency CPU, GPU and other high-performance chip design.

[0127] Compared with the conventional D trigger STGFF with a scanning structure, the high-speed master-slave double sampling D trigger (SDTGFF) proposed in the application has one less transmission gate circuit when the data is input, and the setup time is shorter. Figure 2The output signal of the inverter X4 in the conventional D flip-flop STGFF with a scan structure is transmitted through the transmission gate TG3, and then transmitted through the inverters X6 and X8 to reach the output Q, which requires twice inversion; the slave trigger circuit of the SDTGFF uses a double sampling structure, and the output signal ml_ax of the master trigger circuit is transmitted through the transmission gate TG2, and then transmitted through the inverter X8 to reach the output Q, which requires once inversion, and the delay of CK2Q is shorter.

[0128] Compared with the conventional D flip-flop TGFF, the slave trigger circuit of the high-speed master-slave double sampling D flip-flop using an input approximate clock proposed in the application uses a double sampling structure, and the output signal ml_ax of the master trigger is transmitted through the transmission gate TG2, and then transmitted through the inverter X8 to reach the output Q, which requires once inversion, and the delay of CK2Q is shorter.

[0129] In order to compare the performance characteristics of the high-speed master-slave double sampling D flip-flop using an input approximate clock (SDTGFF) proposed in the application, the conventional D flip-flop with a scan structure (STGFF) and the high-speed master-slave double sampling D flip-flop using an input approximate clock (SDTGFF) proposed in the application are respectively characterized by using the LIBERATE17 tool under the same conditions, and then the lib library is compared and analyzed by using the qualib tool.

[0130] Table 1 is the comparison data of the related parameters of the flip-flop. Compared with the conventional D flip-flop with a scan structure STGFF, under the condition of the maximum timing arc, the rising edge CK2Q delay (rise_CK2Q) of the D flip-flop circuit (SDTGFF) proposed in the application is reduced by 2.2%, the falling edge CK2Q delay (fall_CK2Q) is reduced by 4.5%, the rising edge setup time (rise_setup) is reduced by 66.8%, the falling edge setup time (fall_setup) is reduced by 57.8%, and the overall maximum delay (max_total_delay) is reduced by 24.9%. Therefore, the standard cell of the high-speed master-slave double sampling D flip-flop using an input approximate clock (SDTGFF) implemented in the application has a wide application prospect in high-performance high-frequency digital integrated circuit design compared with the standard cell of the conventional D flip-flop with a scan structure (STGFF).

[0131] Table 1 is the comparison data of the related parameters of the flip-flop. Compared with the conventional D flip-flop with a scan structure STGFF, under the condition of the maximum timing arc, the rising edge CK2Q delay (rise_CK2Q) of the D flip-flop circuit (SDTGFF) proposed in the application is reduced by 2.2%, the falling edge CK2Q delay (fall_CK2Q) is reduced by 4.5%, the rising edge setup time (rise_setup) is reduced by 66.8%, the falling edge setup time (fall_setup) is reduced by 57.8%, and the overall maximum delay (max_total_delay) is reduced by 24.9%. Therefore, the standard cell of the high-speed master-slave double sampling D flip-flop using an input approximate clock (SDTGFF) implemented in the application has a wide application prospect in high-performance high-frequency digital integrated circuit design compared with the standard cell of the conventional D flip-flop with a scan structure (STGFF).

[0132]

[0133] The above are only preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiments. Any technical scheme falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled in the art, some improvements and refinements without departing from the principles of the present application shall be considered as the protection scope of the present application.

Claims

1. A high-speed master-slave double-sampling D flip-flop with input approximation clock, characterized in that, The master trigger circuit, the control signal generating circuit and the slave trigger circuit are connected in series. The master trigger circuit comprises: A PMOS transistor MP1, the substrate of which is connected to a power supply VDD, the source of which is connected to the power supply VDD, the gate of which is connected to a control signal cks2n, and the drain of which drives a signal v1; A PMOS transistor MP2, the substrate of which is connected to the power supply VDD, the source of which is connected to the signal v1, the gate of which is connected to a clock complementary signal ckn, and the drain of which drives a signal ml_ax; A PMOS transistor MP3, the substrate of which is connected to the power supply VDD, the source of which is connected to the power supply VDD, the gate of which is connected to a signal ml_b, and the drain of which drives the signal v1; A PMOS transistor MP4, the substrate of which is connected to the power supply VDD, the source of which is connected to the signal v1, the gate of which is connected to a data input signal D, and the drain of which drives the signal ml_ax; An NMOS transistor MN1, the substrate of which is connected to a power supply VSS, the source of which is connected to the power supply VSS, the gate of which is connected to a control signal cks3n, and the drain of which drives a signal v2; An NMOS transistor MN2, the substrate of which is connected to the power supply VSS, the source of which is connected to the signal v2, the gate of which is connected to a clock signal ckn, and the drain of which drives the signal ml_ax; An NMOS transistor MN3, the substrate of which is connected to the power supply VSS, the source of which is connected to the power supply VSS, the gate of which is connected to the signal ml_b, and the drain of which drives the signal v2; An NMOS transistor MN4, the substrate of which is connected to the power supply VSS, the source of which is connected to the signal v2, the gate of which is connected to a data signal D, and the drain of which drives the signal ml_ax; An inverter X5, the input of which is driven by the signal ml_ax, and the output of which drives a signal ml_b; A scan structure, the input of which is connected to a signal sen, a signal SI, a clock signal ckn, an enable signal SE and a clock signal ckn, and the output of which drives the signal ml_ax; The control signal generating circuit, the input of which is driven by a clock signal CK and an enable signal SE, and the output of which drives a clock complementary signal ckn, a signal ckn and a complementary signal sen of the enable signal SE; and the signal ckn and the signal sen generate a control signal cks2n and a control signal cks3n again; The input of the slave trigger circuit is connected to the signal ml_ax and a signal sl_ax, and the output of the slave trigger circuit drives an output signal Q; The slave trigger circuit comprises: A transmission gate TG1, the data input of which is connected to the signal ml_b, the data output of which is connected to the signal sl_ax, the clock signal PMOS input of which is connected to the signal ckn, and the clock signal NMOS input of which is connected to the signal ckn; A transmission gate TG2, the data input of which is connected to the signal ml_ax, the data output of which is connected to a signal sl_b, the clock signal PMOS input of which is connected to the signal ckn, and the clock signal NMOS input of which is connected to the signal ckn; A transmission gate TG3, the data input of which is connected to the signal sl_ax, the data output of which is connected to a signal sl_bn, the clock signal PMOS input of which is connected to the signal ckn, and the clock signal NMOS input of which is connected to the signal ckn; An inverter X6, the input of which is driven by the signal sl_ax, and the output of which drives the signal sl_b; An inverter X7, the input of which is driven by the signal sl_b, and the output of which drives the signal sl_bn; An inverter X8, the input of which is driven by the signal sl_b, and the output of which drives the output signal Q.

2. The high-speed master-slave double sampling D flip-flop inputting an approximation clock according to claim 1, wherein, The slave trigger circuit further comprises: Inverter X9, input end is driven by signal sl_ax, output end drives signal QN.

3. The high-speed master-slave double sampling D flip-flop inputting an approximation clock according to claim 1 or 2, characterized by, The scanning structure comprises: PMOS MP5, substrate connects power supply VDD, source connects power supply VDD, gate connects signal sen, drain drives signal v3; PMOS MP6, substrate connects power supply VDD, source connects signal v3, gate connects scanning signal SI, drain drives signal v4; PMOS MP7, substrate connects power supply VDD, source connects signal v4, gate connects clock signal ckn, drain drives signal ml_ax; NMOS MN5, substrate connects power supply VSS, source connects power supply VSS, gate connects enable signal SE, drain drives signal v6; NMOS MN6, substrate connects power supply VSS, source connects signal v6, gate connects scanning signal SI, drain drives signal v5; NMOS MN7, substrate connects power supply VSS, source connects signal v5, gate connects clock signal ckn, drain drives signal ml_ax.

4. The high-speed master-slave double sampling D flip-flop inputting an approximation clock according to claim 1 or 2, characterized by, The control signal generating circuit comprises: Inverter X1, input end is driven by clock signal CK, output end drives clock complementary signal ckn; Inverter X2, input end is driven by clock complementary signal ckn, output end drives signal ckn; Inverter X3, input end is driven by enable signal SE, output end drives complementary signal sen of enable signal SE; Inverter X4, input end is driven by signal cks2n, output end drives signal cks3n; Two-input NAND, input ends are respectively driven by complementary signal sen and clock complementary signal ckn, output drives signal cks2n.

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