Driving circuit, panel driving system and display device

Abstract

The invention discloses a driving circuit, a panel driving system and a display device. The driving circuit is applied to the display panel, the display panel comprises a plurality of pixel columns, the plurality of pixel columns are divided into m groups, the driving circuit comprises a plurality of output channels, the plurality of output channels are divided into m groups, and each group of output channels is connected with one group of pixel columns; wherein the m groups of output channels respond to a first clock signal and a second clock signal to sequentially output; wherein each at least two groups of output channels in the m groups of output channels respond to the first clock signal and the second clock signal to carry out one-time output, and the output delay time is output at any adjacent output interval. According to the invention, the space and the cost are saved, the high requirement of a PPCC function of a large-size panel is met, and the product yield is further improved.

Description

Technical Field

[0001] The embodiments disclosed in the present application relate to the field of display technology, and more specifically, to a driving circuit, a panel driving system and a display device. Background Art

[0002] With the continuous development of the display industry, various technologies and methods for improving display effects have emerged one after another. At present, due to market demand, product sizes are getting larger and larger, which has led to an increase in overall product power consumption and driver costs. At the same time, in order to improve the charging time and display effect of large-size panel products, higher requirements are also put forward for the PPCC function (Programmable Panel Charging Compensation Shift Function). Summary of the invention

[0003] According to the embodiments of the present application, the present application proposes a driving circuit, a panel driving system and a display device to solve the above problems.

[0004] The first aspect of the present application discloses a driving circuit applied to a display panel, wherein the display panel includes a plurality of pixel columns, wherein the plurality of pixel columns are divided into m groups, and include: a plurality of output channels, wherein the plurality of output channels are divided into the m groups, and each group of output channels is connected to a group of pixel columns; wherein the m groups of output channels output in sequence in response to a first clock signal and a second clock signal; wherein every at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and an output delay time is provided between any adjacent outputs.

[0005] In some embodiments, the first clock signal and the second clock signal have the same period, and the level timing of the first clock signal and the second clock signal are opposite and the level is consistent.

[0006] In some embodiments, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two groups of output channels among the m groups of output channels perform the current output; in response to the first clock signal being at a low level and the second clock signal being at a high level, the next two groups of output channels among the m groups of output channels perform the next output.

[0007] In some embodiments, the driving circuit further includes: a delay setting module connected to the external voltage-dividing circuit, and configured to set the output delay time according to the input voltage of the external voltage-dividing circuit.

[0008] In some embodiments, the output delay time is related to a period of the first clock signal or the second clock signal.

[0009] In some embodiments, the output delay time is set according to the input voltage of the external voltage divider circuit, including: in response to the input voltage being a first value, the output delay time is set to a first preset multiple of the period of the first clock signal or the second clock signal; in response to the input voltage being a second value, the output delay time is set to a second preset multiple of the period of the first clock signal or the second clock signal; wherein, if the first value is greater than the second value, the first preset multiple is less than the second preset multiple.

[0010] The second aspect of the present application discloses a panel driving system, comprising: at least one driving circuit connected to the display panel, wherein each of the driving circuits is a driving circuit as described in the first aspect; a timing control circuit connected to the at least one driving circuit, for generating the first clock signal and the second clock signal.

[0011] In some embodiments, the timing control circuit is also used to receive output grayscale data on the display panel corresponding to the corresponding driving circuit, and determine the target delay time corresponding to the corresponding driving circuit based on the output grayscale data; the at least one driving circuit is also used to adjust the output delay time of the corresponding driving circuit based on the target delay time.

[0012] In some embodiments, determining the target delay time corresponding to the corresponding driving circuit based on the output grayscale data includes: obtaining the impedance data of the corresponding driving circuit from a first preset table based on the output grayscale data; and obtaining the target delay time corresponding to the corresponding driving circuit from a second preset table based on the impedance data of the corresponding driving circuit.

[0013] The third aspect of the present application discloses a display device, comprising a display panel and the driving circuit described in the first aspect, or comprising the display panel and the panel driving system described in the second aspect.

[0014] The beneficial effects of the present application are as follows: a driving circuit is applied to a display panel, the driving circuit includes multiple output channels, the display panel includes multiple pixel columns, the multiple pixel columns and the multiple output channels are divided into m groups, the m groups of output channels output in sequence in response to a first clock signal and a second clock signal, wherein every at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and an output delay time is outputted at any adjacent output interval, and the output delay of the multiple output channels is controlled by the first clock signal and the second clock signal, which saves space and cost while meeting the high demand for the PPCC function of large-size panels, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present application will be further described below in conjunction with the accompanying drawings and implementation methods, in which:

[0016] Figure 1 It is a structural schematic diagram of a serial output line in the related art;

[0017] Figure 2 is a timing diagram of a clock signal in the related art;

[0018] Figure 3 is a schematic diagram of the structure of the driving circuit of an embodiment of the present application;

[0019] Figure 4 is a timing diagram of a clock signal of an embodiment of the present application;

[0020] Figure 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present application;

[0021] Figure 6 is a structural schematic diagram of a panel driving system according to an embodiment of the present application;

[0022] Figure 7 It is a schematic diagram of the structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of, for example, including at least one of A, B, and C, and can mean including any one or more elements selected from the set consisting of A, B, and C. In addition, the terms "first", "second", and "third" in this application are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0025] For ease of understanding, the driver output and PPCC functions are briefly described. Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of the serial output line in the related technology. Due to the size of the large-size display panel, the length of each drive output SOUT (Swap OUT, serial output line) cannot be completely consistent. In order to ensure that the impedance of the SOUT in the plane remains consistent when the architectural design remains unchanged, so that the charging effect of the data output by the driver to the plane remains consistent at the same time, the middle of the driver closer to the plane is routed in a curved "snake" shape, and the two ends are relatively straight broken lines to ensure that the routing length of the driver output to the SOUT in the middle and both ends of the plane is consistent. The SOUT output of the driver will be connected to the plane, but for the same driver, the number of SOUT outputs is large, such as 726ch, 966ch, 1366ch, etc.

[0026] If the SOUT data of multiple channels are output to the surface at the same time, the current drawn by the surface load to the driver will be very huge at the moment of output, which will cause the driver load to rise sharply instantly and put very high demands on the driver. The PPCC function can be used to solve this problem, that is, to control SOUT to not output at the same time at the moment of output, and group all the drive channels, such as Figure 2 As shown, Figure 2 It is a timing diagram of the clock signal in the related art. Taking the number of channels of a single driver as 966ch as an example, the channels are divided into 1 group of 12ch each, and then 81 groups are obtained. The 81 groups of channels can be controlled by 10 DCLKs (clock signals) respectively. For example, DCLK1 controls the output of the first group, DCLK2 controls the output of the second group..., and when it comes to the 11th group, it is controlled by the second high level of DCLK1 in a cycle, and each of the 81 groups is delayed by a fixed time interval.

[0027] Among them, the number of groups that the drive output SOUT can be divided into for output and the interval time between each group are fixed and cannot be adjusted. They are determined by the IC (Integrated Circuit) manufacturer at the beginning of the design and cannot be modified after the product is produced. They cannot be adjusted according to the actual impedance of the product or the difference between different products. In addition, using DCLK1-DCLK10 to control the group output requires 10 clock signals to be generated inside the IC. For the timing control circuit, it takes up a lot of space and cost.

[0028] To this end, the present application provides a driving circuit, a panel driving system and a display device to solve the above problems.

[0029] In order to enable those skilled in the art to better understand the technical solution of the present application, the technical solution of the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] See also Figure 3 , Figure 3 1 is a schematic diagram of a driving circuit according to an embodiment of the present application. The driving circuit 100 is applied to a display panel 200, and the display panel 200 includes a plurality of pixel columns 210, wherein the plurality of pixel columns 210 are divided into m groups.

[0031] The driving circuit 100 includes a plurality of output channels 110, and the plurality of output channels 110 are divided into m groups, such as Figure 3 As shown, the plurality of output channels 110 are divided into m groups, namely N1, N2, ... Nm. Each group of output channels is connected to a group of pixel columns, wherein the output channels 110 correspond to the pixel columns 210 one by one and are the same in number, and the output channels 110 can be used to provide output voltages to the pixel columns 210. For example, the display panel 200 includes 966 pixel columns 210, and 12 pixel columns 210 are divided into one group, so as to obtain 81 groups, namely m=81. Accordingly, the driving circuit 100 includes 966 output channels 110, which are divided into 81 groups.

[0032] The m groups of output channels output in sequence in response to the first clock signal and the second clock signal. Figure 4 As shown, Figure 4 is a timing diagram of the clock signal of the embodiment of the present application. For example, in response to the state changes of the first clock signal DCLK_a and the second clock signal DCLK_b, m groups of output channels output in sequence.

[0033] Among them, every at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and any adjacent output intervals have an output delay time. For example, the at least two groups of output channels may include 2 groups, 3 groups, 4 groups, etc.

[0034] like Figure 4As shown, m groups of output channels include output channels N1 , N2 . . . N10 , and output channels Nn (n=1, 2, . . . m) represent a group of output channels, wherein each group of output channels may include 12 output channels 110 . In some examples, every at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and an output delay time is separated from any adjacent outputs. For example, in response to the first clock signal DCLK_a being in the first timing state and the second clock signal DCLK_b being in the second timing state, the output channels N1-N2 output once, in response to the first clock signal DCLK_a being in the second timing state and the second clock signal DCLK_b being in the first timing state, the output channels N3-N4 output once, in response to the first clock signal DCLK_a being in the first timing state again and the second clock signal DCLK_b being in the second timing state again, the output channels N5-N6 output once…, the output interval time between the output channels N1-N2 and the output channels N3-N4 is T1, and the output interval time between the output channels N3-N4 and the output channels N5-N6 is T2, wherein T1 and T2 are the output delay times.

[0035] In this embodiment, the driving circuit 100 is applied to the display panel 200, the driving circuit 100 includes a plurality of output channels 110, the display panel 200 includes a plurality of pixel columns 210, the plurality of pixel columns 210 and the plurality of output channels 110 are divided into m groups, the m groups of output channels output in sequence in response to a first clock signal and a second clock signal, wherein at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and an output delay time is outputted at any adjacent output intervals, and the output delay of the plurality of output channels 110 is controlled by the first clock signal and the second clock signal, thereby saving space and cost while meeting the high demand for the PPCC function of large-size panels, thereby improving product yield.

[0036] In some embodiments, the first clock signal and the second clock signal have the same period, and the level timings of the first clock signal and the second clock signal are opposite and the levels are consistent.

[0037] like Figure 4 As shown, the first clock signal DCLK_a and the second clock signal DCLK_b have the same period T, and the level timing of the first clock signal DCLK_a and the second clock signal DCLK_b are opposite and the level is consistent. Among them, the period T of the first clock signal DCLK_a and the second clock signal DCLK_b can refer to the width time of the first clock signal DCLK_a / the second clock signal DCLK_b at a high level and a low level ( Figure 4 not shown).

[0038] In some embodiments, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two groups of output channels among the m groups of output channels perform the current output; in response to the first clock signal being at a low level and the second clock signal being at a high level, the next two groups of output channels among the m groups of output channels perform the next output.

[0039] Continue to use the above output channels N1, N2...N10 as an example for explanation. Figure 4 As shown, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two groups of output channels in the m groups of output channels perform the current output. For example, in response to the rising edge of the first clock signal DCLK_a and the second clock signal DCLK_b being at a low level, the channel signal 1 corresponding to the output channels N1-N2 is at a high level, and then the output channels N1-N2 perform the current output. At this time, the data of the remaining groups of output channels (for example, output channels N3-N10) are delayed in transmission.

[0040] Further, in response to the first clock signal being at a low level and the second clock signal being at a high level, the next two groups of output channels in the m groups of output channels perform the next output. For example, in the current period, the first clock signal DCLK_a is at a high level and the second clock signal DCLK_b is at a low level. In the next period, the first clock signal DCLK_a enters a low level and the second clock signal DCLK_b enters a high level. At this time, in response to the first clock signal DCLK_a being at a low level and the second clock signal DCLK_b being at a high level, the channel signal 2 corresponding to the output channel N3-N4 is at a high level, and the output channel N3-N4 performs the current output. At this time, the data of the remaining groups of output channels (for example, output channels N1-N2, output channels N5-N10) are delayed. It can be understood that the delayed output of the m groups of output channels can be controlled by the first clock signal DCLK_a and the second clock signal DCLK_b.

[0041] In this embodiment, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two groups of output channels among the m groups of output channels perform the current output, and in response to the first clock signal being at a low level and the second clock signal being at a high level, the next two groups of output channels among the m groups of output channels perform the next output, wherein the delayed output of the m groups of output channels is achieved through the first clock signal and the second clock signal, thereby saving space and cost of the driving circuit 100 and meeting the high requirements of the PPCC function of large-size panels.

[0042] In some embodiments, Figure 5 As shown, Figure 51 is a schematic diagram of the structure of a driving circuit according to an embodiment of the present application. The driving circuit 100 further includes a delay setting module 120, which is connected to the external voltage dividing circuit 300. The delay setting module 120 is used to set the output delay time according to the input voltage of the external voltage dividing circuit 300.

[0043] In some examples, the delay setting module 120 can be a register in the driving circuit 100, for example, any blank register in the driving circuit 100 is used to process and determine the output delay time. The delay setting module 120 is connected to the external voltage divider circuit 300, for example, the delay setting module 120 is connected to the resistor R1 and the resistor R2 in the external voltage divider circuit 300, and then the delay setting module 120 can set the output delay time according to the input voltage of the external voltage divider circuit 300, that is, the delay setting module 120 can control the voltage level input to the delay setting module 120 by means of the external voltage divider resistor to achieve the control of the output delay.

[0044] In some embodiments, the output delay time is related to a period of the first clock signal or the second clock signal.

[0045] For example, in response to the first clock signal DCLK_a being in the first timing state and the second clock signal DCLK_b being in the second timing state, the output channel N1-N2 performs an output, and in response to the first clock signal DCLK_a being in the second timing state and the second clock signal DCLK_b being in the first timing state, the output channel N3-N4 performs an output, the output interval time between the output channels N1-N2 and the output channels N3-N4 is T1, and the output interval time between the output channels N3-N4 and the output channels N5-N6 is T2, wherein T1 and T2 are output delay times, and T1 and T2 are related to the period T of the first clock signal DCLK_a or the second clock signal DCLK_b, for example, T1=T2=T / 2, that is, the output delay time can be half of the period length of the first clock signal or the second clock signal.

[0046] In some embodiments, the output delay time is set according to the input voltage of the external voltage divider circuit 300, including: in response to the input voltage being a first value, the output delay time is set to a first preset multiple of the period of the first clock signal or the second clock signal; in response to the input voltage being a second value, the output delay time is set to a second preset multiple of the period of the first clock signal or the second clock signal; wherein, if the first value is greater than the second value, the first preset multiple is less than the second preset multiple.

[0047] If the input voltage is the first value V1, the output delay time can be set to the first preset multiple x of the period T of the first clock signal or the second clock signal, and if the input voltage is the second value V2, the output delay time can be set to the second preset multiple y of the period T of the first clock signal or the second clock signal. If the first value is greater than the second value, the first preset multiple is less than the second preset multiple, for example, V1>V2, then x<y, that is, when the input voltage is the first value V1, the output delay time is set to x*T, and when the input voltage is the second value V2, the output delay time is set to y*T, x*T<y*T, and then the delayed output of the driving circuit 100 is controlled by changing the input voltage of the external voltage divider circuit 300.

[0048] In some examples, if the period T of the first clock signal DCLK_a or the second clock signal DCLK_b is 20ns, and the width time of the high level and the low level of the first clock signal DCLK_a or the second clock signal DCLK_b is 10ns respectively. When the input voltage is 3.3v, the output delay time can be set to a width time of 1 high level, that is, the output delay time is 10ns; when the input voltage is 1.8v, the output delay time can be set to a width time of 1.5 high levels, that is, the output delay time is 15ns; when the input voltage is 0.9v, the output delay time can be set to a width time of 2 high levels, that is, the output delay time is 20ns.

[0049] See also Figure 6 , Figure 6 6 is a schematic diagram of the structure of the panel driving system of the embodiment of the present application. The panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610, wherein the at least one driving circuit 100 is connected to the display panel 200, and the timing control circuit 610 is connected to the at least one driving circuit 100 to generate a first clock signal and a second clock signal.

[0050] In some examples, such as Figure 6 As shown, at least one driving circuit 100 includes a driving circuit 101, a driving circuit 102...a driving circuit 10n, wherein a timing control circuit 610 is connected to the driving circuit 101, the driving circuit 102...a driving circuit 10n, and can generate different first clock signals and second clock signals for different driving circuits 100.

[0051] In this embodiment, the panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610. The timing control circuit 610 is connected to the at least one driving circuit 100 to generate a first clock signal and a second clock signal corresponding to the at least one driving circuit 100, and then the output delay of multiple driving circuits 100 is controlled by the first clock signal and the second clock signal, thereby saving space and cost while meeting the high requirements of the PPCC function of large-size panels, thereby improving product yield.

[0052] In some embodiments, the timing control circuit 610 is also used to receive the output grayscale data on the display panel 200 corresponding to the corresponding driving circuit 100, and determine the target delay time corresponding to the corresponding driving circuit 100 based on the output grayscale data; at least one driving circuit 100 is also used to adjust the output delay time of the corresponding driving circuit 100 based on the target delay time.

[0053] In some examples, such as Figure 6 As shown, at least one driving circuit 100 includes a driving circuit 101, a driving circuit 102 ... a driving circuit 10n, wherein the impedances of the driving circuits 101, 102 ... driving circuits 10n are different, for example, R1, R2 ... Rn, respectively. The timing control circuit 610 receives grayscale data G, which may be actual output data of at least one driving circuit 100 corresponding to the display panel 200. The timing control circuit 610 may determine the target delay time corresponding to the corresponding driving circuit 100 according to the output grayscale data G of the driving circuits 101, 102 ... driving circuits 10n, and then at least one driving circuit 100 may adjust the corresponding output delay time according to the determined target delay time. The target delay time corresponding to the driving circuit 100 is the interval time between at least two groups of output channels in the m groups of output channels in the driving circuit 100 outputting once in response to the first clock signal and the second clock signal.

[0054] In this embodiment, the panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610. The timing control circuit 610 is connected to the at least one driving circuit 100 to generate a first clock signal and a second clock signal corresponding to the at least one driving circuit 100. The timing control circuit 610 is also used to receive the output grayscale data on the display panel corresponding to the corresponding driving circuit 100, and determine the target delay time corresponding to the corresponding driving circuit 100 based on the output grayscale data. Furthermore, at least one driving circuit 100 is also used to adjust the output delay time of the corresponding driving circuit 100 based on the target delay time, so as to avoid the influence of the differences between the driving circuits 100 on the output delay time of the driving circuits 100.

[0055] In some embodiments, a target delay time corresponding to a corresponding driving circuit 100 is determined based on the output grayscale data, including: obtaining impedance data of the corresponding driving circuit 100 from a first preset table based on the output grayscale data; and obtaining a target delay time corresponding to the corresponding driving circuit 100 from a second preset table based on the impedance data of the corresponding driving circuit 100.

[0056] The timing control circuit 610 is used to obtain the impedance data of the corresponding driving circuit 100 from the first preset table based on the received output grayscale data, and to obtain the target delay time corresponding to the corresponding driving circuit 100 from the second preset table based on the impedance data of the corresponding driving circuit 100, wherein the first preset table can be an impedance-grayscale data table (R / Gtable), and the second preset table can be an impedance-time data table (R / T table).

[0057] by Figure 6 Taking the driving circuit 10n in the example, for example, the timing control circuit 610 receives the output grayscale data Gn of the driving circuit 10n, and obtains the impedance data Rn of the driving circuit 10n from the R / G table according to the output grayscale data Gn. Further, according to the impedance data Rn of the driving circuit 101, the target delay time Tn corresponding to the driving circuit 101 can be obtained from the R / T table, that is, the interval Tn at which every at least two groups of output channels in the m groups of output channels in the driving circuit 10n output once in response to the first clock signal and the second clock signal.

[0058] In some examples, at least one driving circuit 100 includes driving circuit 101, driving circuit 102...driving circuit 10n, and the impedances of each driving circuit 100 are different, for example, R1, R2...Rn respectively. The output delay time of at least one driving circuit 100 can be set to T0. After the output of at least one driving circuit 100, the brightness under the current setting is tested using an optical measuring instrument, and the actual output grayscale G corresponding to the feedback measurement point pulled back from the position of at least one driving circuit 100 is tested at the same time, and then the output delay time of at least one driving circuit 100 is adjusted, and the actual display brightness is confirmed to be consistent with the preset brightness using an optical instrument, so that an impedance-grayscale data table and an impedance-time data table can be obtained.

[0059] Furthermore, the impedance-grayscale data table and the impedance-time data table can be compiled into the timing control circuit 610. When the in-plane architecture is designed, the output of different driving circuits 100 will be pulled back to the driving circuit 100 and synchronously fed back to the timing control circuit 610. The algorithm controller in the timing control circuit 610 receives the actual output grayscale G fed back at this time, and brings it into the impedance-grayscale data table to obtain the R of the corresponding driving circuit 100, and brings R into the impedance-time data table to obtain the target delay time T of the driving circuit 100. The timing control circuit 610 inputs the target delay time T into the delay setting module 120 of the driving circuit 100, and the delay setting module 120 adjusts the actual output delay time of the corresponding driving circuit 100 according to the input target delay time T, thereby achieving the adjustment of the PPCC actual output delay time of different driving circuits 100 to ensure that the output is completely free from the influence of different impedances.

[0060] See also Figure 7 , Figure 7 It is a schematic diagram of the structure of the display device of an embodiment of the present application. The display device 700 includes a display panel 200 and a driving circuit 100 as described above, or the display device 700 includes a display panel 200 and a panel driving system 600 as described above. Among them, the display panel 200 includes a plurality of pixel columns 210, wherein the plurality of pixel columns 210 are divided into m groups; the panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610; the driving circuit 100 includes a plurality of output channels 110, and the plurality of output channels 110 are divided into m groups. Among them, the m groups of output channels output in sequence in response to the first clock signal and the second clock signal, and every at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and any adjacent output intervals output a delay time.

[0061] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0062] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0063] In the several embodiments provided in the present application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the above-described related device implementations are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication disconnection shown or discussed can be through some interfaces, indirect coupling or communication disconnection of devices or units, which can be electrical, mechanical or other forms.

[0064] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0065] It is easy for a person skilled in the art to know that many modifications and changes can be made to the device and method while maintaining the teaching content of the present application. Therefore, the above disclosure should be considered as limited only by the scope of the appended claims.

Claims

1. A driving circuit, characterized in that: Applied to a display panel, the display panel comprises a plurality of pixel columns, the plurality of pixel columns are divided into m groups, including: A plurality of output channels, wherein the plurality of output channels are divided into the m groups, and each group of output channels is connected to a group of pixel columns; Wherein, the m groups of output channels output in sequence in response to the first clock signal and the second clock signal; Among the m groups of output channels, at least two groups of output channels perform output once in response to the first clock signal and the second clock signal, and an output delay time is provided between any adjacent outputs.

2. The driving circuit according to claim 1, characterized in that: The first clock signal and the second clock signal have the same period, and the level timing of the first clock signal and the second clock signal are opposite and the level is consistent.

3. The driving circuit according to claim 2, characterized in that: In response to the rising edge of the first clock signal and the second clock signal being at a low level, current two groups of output channels among the m groups of output channels perform current output; In response to the first clock signal being at a low level and the second clock signal being at a high level, the next two groups of output channels among the m groups of output channels perform the next output.

4. The driving circuit according to any one of claims 1 to 3, characterized in that: The driving circuit further includes: The delay setting module is connected to the external voltage-dividing circuit and is used to set the output delay time according to the input voltage of the external voltage-dividing circuit.

5. The driving circuit according to claim 4, characterized in that: The output delay time is related to a period of the first clock signal or the second clock signal.

6. The driving circuit according to claim 5, characterized in that: The step of setting the output delay time according to the input voltage of the external voltage divider circuit comprises: In response to the input voltage being a first value, setting the output delay time to a first preset multiple of a period of the first clock signal or the second clock signal; In response to the input voltage being a second value, setting the output delay time to a second preset multiple of a period of the first clock signal or the second clock signal; Among them, if the first value is greater than the second value, then the first preset multiple is less than the second preset multiple.

7. A panel driving system, characterized in that: include: at least one driving circuit connected to the display panel, wherein each of the driving circuits is a driving circuit as claimed in any one of claims 1 to 6; A timing control circuit is connected to the at least one driving circuit and is used to generate the first clock signal and the second clock signal.

8. The system according to claim 7, characterized in that The timing control circuit is also used to receive output grayscale data on the display panel corresponding to the corresponding driving circuit, and determine the target delay time corresponding to the corresponding driving circuit according to the output grayscale data; The at least one driving circuit is further configured to adjust an output delay time of the corresponding driving circuit according to the target delay time.

9. The system according to claim 8, characterized in that Determining the target delay time corresponding to the corresponding driving circuit according to the output grayscale data includes: According to the output grayscale data, obtaining impedance data of the corresponding driving circuit from a first preset table; According to the impedance data of the corresponding driving circuit, the target delay time corresponding to the corresponding driving circuit is obtained from the second preset table.

10. A display device, characterized in that: The invention comprises a display panel and a driving circuit as claimed in any one of claims 1 to 6, or comprises the display panel and a panel driving system as claimed in any one of claims 7 to 9.

Images