Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises a first drive circuit which comprises multiple stages of shift registers; the shift register comprises a shift control module and a shift output module which are used for controlling a first node, a second node and a shift output end and controlling the shift output end to output a shift signal; the first control module is used for controlling a signal of the fourth node; the second control module is used for adjusting a signal of the fourth node; the refresh output module is used for controlling the scanning output end to output a gate driving signal. According to the shift register, the second control module is additionally arranged, so that the potential stability of the fourth node of the shift register and the output stability of the gate driving signal can be improved, the output effectiveness, accuracy and stability of the shift register can be ensured, and the display quality of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of display technology, display screens based on multi-zone dynamic refresh technology have emerged. Displays using multi-zone dynamic refresh technology can perform different refresh rates in the dynamic picture area and static picture area of ​​the display area, or can present different refresh rates in the human eye observation area and non-human eye observation area of ​​the display area, thereby realizing partitioned display control of the display area. In this way, both refresh rate requirements and low power consumption requirements can be taken into account.

[0003] However, current display screens with a partition refresh function have problems such as poor stability, which affects the display effect. Summary of the invention

[0004] The present invention provides a display panel and a display device to solve the problems of poor stability of the current display screen with a partition refresh function.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising: a first driving circuit, the first driving circuit comprising a multi-stage shift register;

[0006] The shift register comprises:

[0007] a shift control module, electrically connected to the input terminal, the first clock terminal, the second clock terminal, the first power terminal, the second power terminal, the first node and the second node, and used to control a signal of the first node and a signal of the second node;

[0008] a shift output module, electrically connected to the first node, the second node, the first power supply terminal, the second power supply terminal and the shift output terminal, and used for controlling the shift output terminal to output a shift signal;

[0009] A first control module is electrically connected to the first node, the third node and the fourth node, and is used to control the signal of the fourth node; the third node is used to receive the first refresh control signal provided by the first refresh signal line;

[0010] a second control module, electrically connected to the third node and the fourth node, and used to adjust a signal of the fourth node; the second control module is also electrically connected to the first node, and / or the first control module is electrically connected to the fourth node through the second control module;

[0011] A refresh output module is electrically connected to the second node, the fourth node, the third power supply terminal, the fourth power supply terminal and the scan output terminal, and is used to control the scan output terminal to output a gate drive signal.

[0012] According to another aspect of the present invention, a display device is provided, comprising: the display panel as described above.

[0013] In the present invention, by adding a second control module in the shift register, the potential of the fourth node is not only affected by the first control module, but also by the second control module. Under the joint action of the first control module and the second control module, the added second control module can stabilize the potential of the fourth node. Specifically, if the potential of the fourth node is low, the second control module controls the potential of the fourth node to remain at a low level; if the potential of the fourth node is high, the second control module controls the potential of the fourth node to remain at a high level, especially when the first node is low and the first control module is turned off, the added second control module can control the potential of the fourth node to remain at a high level, reduce the leakage of the high level of the fourth node to the first node due to the interference of the first control module, and thus avoid the problem of the potential gradually decreasing and wrongly controlling the refresh output module caused by the leakage of the fourth node. Based on this, the second control module is added in the present invention, which can improve the potential stability of the fourth node of the shift register and the output stability of the gate drive signal, which is conducive to ensuring the output validity, accuracy and stability of the shift register, and thus is conducive to improving the display quality of the display panel.

[0014] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a shift register provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0020] Figure 5is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of a shift output unit provided by an embodiment of the present invention;

[0022] Figure 7 is a schematic diagram of another shift output unit provided by an embodiment of the present invention;

[0023] Figure 8 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0024] Fig. 9 yes Figure 8 The low frequency operation timing diagram of the shift register in the first display partition is shown;

[0025] Fig.10 yes Figure 8 The high frequency operation timing diagram of the shift register in the second display partition is shown;

[0026] Fig.11 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0027] Fig.12 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0028] Fig.13 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0029] Fig.14 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0030] Fig.15 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0031] Fig.16 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0032] Fig.17 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0033] Fig.18 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0034] Fig.19 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0035] Fig. 20 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0036] Fig.21 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0037] Fig. 22 yes Fig.21 The low frequency operation timing diagram of the shift register in the first display partition is shown;

[0038] Fig.23 yes Fig.21 The high frequency operation timing diagram of the shift register in the second display partition is shown;

[0039] Fig.24 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention, Figure 3 is a schematic diagram of a shift register provided by an embodiment of the present invention, Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention, Figure 5 is a schematic diagram of another shift register provided by an embodiment of the present invention. Figures 1 to 5As shown, the display panel 10 includes: a first driving circuit 11, the first driving circuit 11 includes a multi-stage shift register 12; the shift register 12 includes: a shift control module 110, electrically connected to an input terminal IN, a first clock terminal CK, a second clock terminal XCK, a first power supply terminal VG1, a second power supply terminal VG2, a first node N1 and a second node N2, for controlling a signal of the first node N1 and a signal of the second node N2; a shift output module 120, electrically connected to the first node N1, the second node N2, the first power supply terminal VG1, the second power supply terminal VG2 and a shift output terminal NEXT, for controlling the shift output terminal NEXT to output a shift signal; a first control module 130, electrically connected to the first node N1, the second node N2, the first power supply terminal VG1, the second power supply terminal VG2 and a shift output terminal NEXT, for controlling the shift output terminal NEXT to output a shift signal; The third node N3 and the fourth node N4 are used to control the signal of the fourth node N4; the third node N3 is used to receive the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1; the second control module 140 is electrically connected to the third node N3 and the fourth node N4, and is used to adjust the signal of the fourth node N4; the second control module 140 is also electrically connected to the first node N1, and / or the first control module 130 is electrically connected to the fourth node N4 through the second control module 140; the refresh output module 150 is electrically connected to the second node N2, the fourth node N4, the third power supply terminal VG3, the fourth power supply terminal VG4 and the scan output terminal OUT, and is used to control the scan output terminal OUT to output the gate drive signal Gout.

[0043] like Figure 3 As shown, the optional second control module 140 is also electrically connected to the first node N1, and the first control module 130 is electrically connected to the fourth node N4 through the second control module 140. Figure 4 As shown, the optional second control module 140 is also electrically connected to the first node N1, and the first control module 130 is directly electrically connected to the fourth node N4. Figure 5 As shown, the optional first control module 130 is electrically connected to the fourth node N4 through the second control module 140 .

[0044] In this embodiment, the shift control module 110 is electrically connected to the input terminal IN, the first clock terminal CK, the second clock terminal XCK, the first power terminal VG1, the second power terminal VG2, the first node N1 and the second node N2. Specifically, the input terminal IN provides an input signal, the first clock terminal CK provides a first clock signal, the second clock terminal XCK provides a second clock signal, the first power terminal VG1 provides a first power signal, and the second power terminal VG2 provides a second power signal. The first clock signal is different from the second clock signal, and the frequency of the first clock signal is the same as the frequency of the second clock signal and the phase of the first clock signal is different from the phase of the second clock signal. The first power signal is different from the second power signal, and one of the first power signal and the second power signal is a low level and the other is a high level. The shift control module 110 controls the signal of the first node N1 and the signal of the second node N2 according to the input signal, the first clock signal, the second clock signal, the first power signal and the second power signal.

[0045] The shift output module 120 controls the shift output terminal NEXT to output a shift signal according to the signal of the first node N1, the signal of the second node N2, the first power signal and the second power signal. The shift signal includes a valid level and an invalid level.

[0046] The first control module 130 controls the signal of the fourth node N4 according to the signal of the first node N1 and the signal of the third node N3. The first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 can be directly transmitted to the third node N3, that is, the signal of the third node N3 is the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1. In other embodiments, a switch structure may be optionally provided between the first refresh signal line SCL1 and the third node N3, and when the switch structure is turned on, the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 is transmitted to the third node N3.

[0047] refer to Figure 3 As shown, the second control module 140 controls the signal of the fourth node N4 according to the signal of the third node N3 , the signal of the first node N1 and the signal of the first control module 130 .

[0048] refer to Figure 4 As shown, the second control module 140 controls the signal of the fourth node N4 according to the signal of the third node N3 and the signal of the first node N1 . The signal of the fourth node N4 is affected by both the first control module 130 and the second control module 140 .

[0049] refer to Figure 5As shown, the second control module 140 controls the signal of the fourth node N4 according to the signal of the third node N3 and the signal of the first control module 130 . The signal of the fourth node N4 is affected by both the first control module 130 and the second control module 140 .

[0050] The refresh output module 150 controls the scan output terminal OUT to output the gate drive signal Gout according to the signal of the second node N2, the signal of the fourth node N4, the third power signal provided by the third power terminal VG3, and the fourth power signal provided by the fourth power terminal VG4. The gate drive signal Gout includes an effective level and an invalid level. The third power signal is different from the fourth power signal, and one of the third power signal and the fourth power signal is a low level and the other is a high level.

[0051] If there is no second control module 140 in the shift register 12, the fourth node N4 is directly electrically connected to the first control module 130, and the signal of the fourth node N4 is directly affected by the first control module 130. When the fourth node N4 is at a high level and the first node N1 is at a low level, if the first control module 130 is turned off, the high level of the fourth node N4 is easily interfered by the first control module 130 and leaks to the first node N1, and the potential of the corresponding fourth node N4 gradually decreases due to the leakage, which may cause the output of the shift register 12 to fail.

[0052] In the present invention, by adding the second control module 140 in the shift register 12, the potential of the fourth node N4 is not only affected by the first control module 130, but also by the second control module 140. Under the joint action of the first control module 130 and the second control module 140, the added second control module 140 can stabilize the potential of the fourth node N4. Specifically, if the potential of the fourth node N4 is at a low level, the second control module 140 controls the potential of the fourth node N4 to remain at a low level; if the potential of the fourth node N4 is at a high level, the second control module 140 controls the potential of the fourth node N4 to remain at a high level, especially when the first node N1 is at a low level and the first control module 130 is turned off, the added second control module 140 can control the potential of the fourth node N4 to remain at a high level, reduce the leakage of the high level of the fourth node N4 to the first node N1 due to the interference of the first control module 130, and thus avoid the problem that the potential of the fourth node N4 is gradually reduced due to the leakage and the wrong control of the refresh output module 150. Based on this, the second control module 140 is added in the present invention to improve the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout, which is beneficial to ensure the output validity, accuracy and stability of the shift register 12, and further beneficial to improve the display quality of the display panel.

[0053] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0054] Optional, reference Figure 1 to Figure 2 As shown, the display panel 10 may also include a plurality of signal lines 15 for providing signals to the first driving circuit 11. Exemplarily, the first refresh signal line SCL1 provides the first refresh control signal Ctrl1 to the shift register 12; the first clock signal line CKL1 and the second clock signal line CKL2 respectively provide the first clock signal to the first clock terminal CK of the shift register 12 and provide the second clock signal to the second clock terminal XCK of the shift register 12; the first power signal line VL1 provides the first power signal to the first power terminal VG1 of the shift register 12; the second power signal line VL2 provides the second power signal to the second power terminal VG2 of the shift register 12; the third power signal line VL3 provides the third power signal to the third power terminal VG3 of the shift register 12; the fourth power signal line VL4 provides the fourth power signal to the fourth power terminal VG4 of the shift register 12; the input signal line STV provides the input signal to the input terminal IN of at least one stage of the shift register 12; the display panel 10 may also include a plurality of other types of signal lines 15, which will not be described in detail here.

[0055] Understandable, reference Figure 1 As shown, the display panel 10 may include a plurality of pixels 16, and the pixel 16 may include a pixel circuit and a light-emitting element. The pixel circuit controls the provision of a driving current to the light-emitting element according to the gate driving signal Gout provided by the shift register 12, so as to drive the light-emitting element to emit light. The gate driving signal Gout output by the shift register 12 may be used to control the writing of data signals to the pixel circuit, or the gate driving signal Gout output by the shift register 12 may be used to control the duration of the pixel circuit providing the driving current to the light-emitting element, or the gate driving signal Gout output by the shift register 12 may be used to control the initialization of the pixel circuit, and so on, without limiting the role of the gate driving signal Gout output by the shift register 12. It should be noted that the structure of the pixel circuit of each pixel 16 in the display panel 10 may be designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0056] refer to Figures 3 to 5As shown, in the display panel 10, the shift register 12 includes a shift control module 110 and a shift output module 120, the shift control module 110 and the shift output module 120 constitute a shift output unit 13 of the shift register 12, the shift output unit 13 includes an input terminal IN and a shift output terminal NEXT, the shift output unit 13 is used to control the shift output terminal NEXT to output a shift signal, and the shift signal includes a valid level and an invalid level. The shift register 12 also includes a first control module 130, a second control module 140 and a refresh output module 150, the first control module 130, the second control module 140 and the refresh output module 150 constitute a scan output unit 14, the scan output unit 14 includes a scan output terminal OUT, the scan output unit 14 is also electrically connected to the first refresh signal line SCL1, the scan output unit 14 responds to the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 and controls the scan output terminal OUT to output a gate drive signal Gout, and the gate drive signal Gout includes a valid level and an invalid level.

[0057] refer to Figure 2 As shown, the shift output terminal NEXT of the i-th shift register 12 can be electrically connected to the input terminal IN of the (i+m)-th shift register 12, where m=1, and the shift signal output by the shift output unit 13 of the i-th shift register 12 is transmitted to the input terminal IN of the (i+1)-th shift register 12. In other embodiments, the shift output terminal NEXT of the i-th shift register can be electrically connected to the input terminal IN of the (i+m)-th shift register, where m can be an integer greater than 1, such as m=2, or m=3, or m=4, or m is equal to other positive integers, not limited to Figure 2 As shown, m=1.

[0058] In the display panel 10, the setting of the shift output unit 13 of the shift register 12 is diverse. Exemplarily, the shift output unit 13 can be "13T2C", or can be "13T3C", or can be "15T3C", or can be "16T3C", etc., wherein "T" represents a transistor and "C" represents a storage capacitor. The setting of the shift output unit 13 is not limited to this. In the following multiple embodiments, the shift output unit 13 uses "16T3C" as an example to illustrate the electrical connection relationship and working process of the shift register 12, and relevant practitioners can adaptively adjust the shift output unit 13 according to needs, which is not limited to "16T3C".

[0059] Figure 6 is a schematic diagram of a shift output unit provided by an embodiment of the present invention, such as Figure 6As shown, in the optional shift output unit 13, the shift control module 110 includes: a first shift submodule 111, electrically connected to the input terminal IN, the first clock terminal CK and the fifth node N5, for controlling the signal of the fifth node N5; a second shift submodule 112, electrically connected to the fifth node N5, the first clock terminal CK, the second clock terminal XCK, the first power supply terminal VG1, the second power supply terminal VG2 and the first node N1, for controlling the signal of the first node N1; a third shift submodule 113, electrically connected to the fifth node N5, the second clock terminal XCK, the first power supply terminal VG1, the second power supply terminal VG2 and the second node N2, for controlling the signal of the second node N2.

[0060] In this embodiment, the first shift submodule 111 is electrically connected to the input terminal IN, the first clock terminal CK and the fifth node N5, and is used to control the signal of the fifth node N5. Specifically, the input terminal IN of the first shift submodule 111 of the i-th stage shift register 12 is electrically connected to the shift output terminal NEXT of the (im)-th stage shift register 12, and m is an integer greater than or equal to 1. The input terminal IN of the first shift submodule 111 receives an input signal, and the first clock terminal CK of the first shift submodule 111 receives a first clock signal. The first shift submodule 111 controls the signal of the fifth node N5 in response to the input signal and the first clock signal, so that the potential of the fifth node N5 jumps between high and low levels.

[0061] The second shift submodule 112 is electrically connected to the fifth node N5, the first clock terminal CK, the second clock terminal XCK, the first power supply terminal VG1, the second power supply terminal VG2 and the first node N1. The first clock terminal CK of the second shift submodule 112 receives the first clock signal, the second clock terminal XCK of the second shift submodule 112 receives the second clock signal, and the first clock signal of the first clock terminal CK is different from the second clock signal of the second clock terminal XCK. The optional first clock signal and the second clock signal have the same frequency and different phases, but are not limited to this. The first power supply terminal VG1 of the second shift submodule 112 receives the first power supply signal, the second power supply terminal VG2 of the second shift submodule 112 receives the second power supply signal, the first power supply signal of the first power supply terminal VG1 is different from the second power supply signal of the second power supply terminal VG2, and one of the optional first power supply signal and the second power supply signal is low and the other is high. The second shift submodule 112 controls the signal of the first node N1 in response to the signal of the fifth node N5, the first clock signal, the second clock signal, the first power supply signal and the second power supply signal, so that the potential of the first node N1 jumps to a high or low level.

[0062] The third shift submodule 113 is electrically connected to the fifth node N5, the second clock terminal XCK, the first power terminal VG1, the second power terminal VG2, and the second node N2. The third shift submodule 113 controls the signal of the second node N2 in response to the signal of the fifth node N5, the second clock signal, the first power signal, and the second power signal, so that the potential of the second node N2 jumps between high and low levels.

[0063] Figure 7 is a schematic diagram of another shift output unit provided by an embodiment of the present invention, such as Figure 7 As shown, optional Figure 7 The middle shift output unit 13 is "16T3C".

[0064] The optional first shift submodule 111 includes a transistor Ma4 and a transistor Ma13. The gate of the transistor Ma4 is electrically connected to the first clock terminal CK, the first end of the transistor Ma4 is electrically connected to the input terminal IN, and the second end of the transistor Ma4 is electrically connected to the fifth node N5. The gate of the transistor Ma13 is electrically connected to the first clock terminal CK, the first end of the transistor Ma13 is electrically connected to the input terminal IN, and the second end of the transistor Ma13 is electrically connected to the node N5a. The first clock signal provided by the first clock terminal CK controls the transistor Ma4 and the transistor Ma13 to be turned on or off at the same time. When the transistor Ma4 and the transistor Ma13 are turned on at the same time, the input signal provided by the input terminal IN is written to the fifth node N5 and the node N5a. It can be understood that the signal of the node N5a is the same as the signal of the fifth node N5. In other embodiments, the optional first shift submodule includes one of the transistor Ma4 and the transistor Ma13.

[0065] The optional second shift submodule 112 includes a transistor Ma1, a transistor Ma2, a transistor Ma3, a transistor Ma5, a transistor Ma6, a transistor Ma7, a transistor Ma8 and a capacitor Ca2. The gate of the transistor Ma1 is electrically connected to the reset signal terminal RST, the first end of the transistor Ma1 is electrically connected to the second power supply terminal VG2, and the second end of the transistor Ma1 is electrically connected to the fifth node N5. The gate of the transistor Ma2 is electrically connected to the fifth node N5, the first end of the transistor Ma2 is electrically connected to the first clock terminal CK, and the second end of the transistor Ma2 is electrically connected to the node N6a. The gate of the transistor Ma3 is electrically connected to the node N6b, the first end of the transistor Ma3 is electrically connected to the second clock terminal XCK, and the second end of the transistor Ma3 is electrically connected to the node N6c. The gate of the transistor Ma5 is electrically connected to the first clock terminal CK, the first end of the transistor Ma5 is electrically connected to the first power supply terminal VG1, and the second end of the transistor Ma5 is electrically connected to the node N6a. The gate of the transistor Ma6 is electrically connected to the fifth node N5, the first end of the transistor Ma6 is electrically connected to the second power supply terminal VG2, and the second end of the transistor Ma6 is electrically connected to the first node N1. The gate of transistor Ma7 is electrically connected to the second clock terminal XCK, the first end of transistor Ma7 is electrically connected to node N6c, and the second end of transistor Ma7 is electrically connected to the first node N1. The gate of transistor Ma8 is electrically connected to the first power supply terminal VG1, the first end of transistor Ma8 is electrically connected to node N6a, and the second end of transistor Ma8 is electrically connected to node N6b. The first plate of capacitor Ca2 is electrically connected to node N6b, and the second plate of capacitor Ca2 is electrically connected to node N6c. In other embodiments, the type or number of transistors in the second shift submodule can be adaptively adjusted, and the corresponding connection relationship between each transistor and the signal terminal changes. The structure of the second shift submodule is not limited to Figure 7 shown.

[0066] The optional third shift submodule 113 includes a transistor Ma11, a transistor Ma12, a transistor Ma14, a transistor Ma15, a transistor Ma16 and a capacitor Ca3. The gate of the transistor Ma11 is electrically connected to the node N2b, the first end of the transistor Ma11 is electrically connected to the second clock terminal XCK, and the second end of the transistor Ma11 is electrically connected to the node N2a. The gate of the transistor Ma12 is electrically connected to the node N6a, the first end of the transistor Ma12 is electrically connected to the second power supply terminal VG2, and the second end of the transistor Ma12 is electrically connected to the node N2a. The gate of the transistor Ma14 is electrically connected to the node N2b, the first end of the transistor Ma14 is electrically connected to the node N2b, and the second end of the transistor Ma14 is electrically connected to the second node N2. The gate of the transistor Ma15 is electrically connected to the first power supply terminal VG1, the first end of the transistor Ma15 is electrically connected to the fifth node N5, and the second end of the transistor Ma15 is electrically connected to the second node N2. The gate of transistor Ma16 is electrically connected to the first power supply terminal VG1, the first terminal of transistor Ma16 is electrically connected to the fifth node N5 or node N5a, and the second terminal of transistor Ma16 is electrically connected to node N2b. The first plate of capacitor Ca3 is electrically connected to node N2a, and the second plate of capacitor Ca3 is electrically connected to node N2b. In other embodiments, the type or number of transistors in the third shift submodule can be adaptively adjusted, and the connection relationship between each transistor and the signal terminal changes accordingly. The structure of the third shift submodule is not limited to Figure 7 shown.

[0067] The shift output module 120 of the optional shift output unit 13 includes a transistor Ma9, a transistor M10 and a capacitor Ca1. The gate of the transistor Ma9 is electrically connected to the first node N1, the first end of the transistor Ma9 is electrically connected to the second power supply terminal VG2, and the second end of the transistor Ma9 is electrically connected to the shift output terminal NEXT. The gate of the transistor Ma10 is electrically connected to the second node N2, the first end of the transistor Ma10 is electrically connected to the first power supply terminal VG1, and the second end of the transistor Ma10 is electrically connected to the shift output terminal NEXT. The first plate of the capacitor Ca1 is electrically connected to the first node N1, and the second plate of the capacitor Ca1 is electrically connected to the second power supply terminal VG2.

[0068] Figure 7 In the optional shift output unit 13, transistors Ma1 to Ma16 are all P-type transistors; the corresponding optional first power supply terminal VG1 is a low level (marked as vgl1), and the second power supply terminal VG2 is a high level (marked as vgh1). In other embodiments, at least one transistor in the shift output unit can be an N-type transistor; the type or number of transistors in the shift output unit can be adaptively adjusted, and the corresponding connection relationship between each transistor and the signal terminal changes. The structure of the shift output unit is not limited to Figure 7 shown.

[0069] The shift control module 110 controls the signal of the first node N1 and the signal of the second node N2 in response to the input signal, the first clock signal, the second clock signal, the first power signal vgl1 and the second power signal vgh1, so that the signal of the first node N1 changes from high to low level, and the signal of the second node N2 changes from high to low level. The shift output module 120 controls one of the first power signal vgl1 and the second power signal vgh1 to be transmitted to the shift output terminal NEXT in response to the signal of the first node N1, the signal of the second node N2, the first power signal vgl1 and the second power signal vgh1. Take the effective level of the shift signal as the high level vgh1 as an example.

[0070] If the shift control module 110 controls the signal of the first node N1 to be low level, the transistor Ma9 in the shift output module 120 is turned on, the second power signal vgh1 provided by the second power terminal VG2 is transmitted to the shift output terminal NEXT, and the shift signal output by the shift output terminal NEXT is at a valid level.

[0071] If the shift control module 110 controls the signal of the first node N1 to be high level, the transistor Ma9 in the shift output module 120 is turned off, and the first power signal vgl1 provided by the first power terminal VG1 can be transmitted to the shift output terminal NEXT through the turned-on transistor Ma10, and the shift signal output by the shift output terminal NEXT is an invalid level.

[0072] Figure 8 is a schematic diagram of another shift register provided by an embodiment of the present invention, with reference to Figure 4 and Figure 8 As shown, the optional first control module 130 includes: a first transistor Mb1; the gate of the first transistor Mb1 is electrically connected to the third node N3, the first end of the first transistor Mb1 is electrically connected to the first node N1, and the second end of the first transistor Mb1 is electrically connected to the fourth node N4. The optional second control module 140a includes: a second transistor Mb2; the gate of the second transistor Mb2 is electrically connected to the first node N1, the first end of the second transistor Mb2 is electrically connected to the third node N3, and the second end of the second transistor Mb2 is electrically connected to the fourth node N4. In this embodiment, the second end of the optional first transistor Mb1 is directly electrically connected to the fourth node N4.

[0073] The optional refresh output module 150 includes: a first output submodule 151, electrically connected to the fourth node N4, the fourth power supply terminal VG4 and the scan output terminal OUT, and used to control the scan output terminal OUT to output the gate drive signal Gout; a second output submodule 152, electrically connected to the second node N2, the third power supply terminal VG3 and the scan output terminal OUT, and used to control the scan output terminal OUT to output the gate drive signal Gout. The optional first output submodule 151 includes: a sixth transistor Mb6; the gate of the sixth transistor Mb6 is electrically connected to the fourth node N4, the first end of the sixth transistor Mb6 is electrically connected to the fourth power supply terminal VG4, and the second end of the sixth transistor Mb6 is electrically connected to the scan output terminal OUT. The optional second output submodule 152 includes: a seventh transistor Mb7; the gate of the seventh transistor Mb7 is electrically connected to the second node N2, the first end of the seventh transistor Mb7 is electrically connected to the third power supply terminal VG3, and the second end of the seventh transistor Mb7 is electrically connected to the scan output terminal OUT.

[0074] The optional shift register 12 further includes: a fourth control module 160; the fourth control module 160 is electrically connected to the second control terminal B; the first refresh signal line SCL1 provides a first refresh control signal Ctrl1 to the third node N3 through the fourth control module 160; the second control terminal B is one of the fifth node N5, the second node N2 and the shift output terminal NEXT. The optional fourth control module 160 includes: a fifth transistor Mb5; the gate of the fifth transistor Mb5 is electrically connected to the second control terminal B, the first end of the fifth transistor Mb5 is electrically connected to the first refresh signal line SCL1, and the second end of the fifth transistor Mb5 is electrically connected to the third node N3.

[0075] In other embodiments, the fifth transistor Mb5 may be selected as a dual-gate transistor. Designing the fifth transistor Mb5 as a dual-gate transistor can reduce the leakage of the third node N3. Specifically, when the fifth transistor Mb5 is turned off and the third node N3 is at a high level, the fifth transistor Mb5 is designed as a dual-gate transistor, which can stabilize the potential of the third node N3 at a high level near the time node when the first refresh signal line SCL1 jumps from a high level to a low level, reduce the leakage of the high-level third node N3 to the low-level first refresh signal line SCL1, and improve the working stability of the shift register 12.

[0076] In this embodiment, the signal of the third node N3 controls the first transistor Mb1 to turn on or off. When the signal of the third node N3 controls the first transistor Mb1 to turn on, the signal of the first node N1 is transmitted to the fourth node N4 through the turned-on first transistor Mb1. The signal of the first node N1 controls the second transistor Mb2 to turn on or off. When the signal of the first node N1 controls the second transistor Mb2 to turn on, the signal of the third node N3 is transmitted to the fourth node N4 through the turned-on second transistor Mb2. It can be seen that the signal of the fourth node N4 is controlled by the first control module 130 and the second control module 140a, and the signal of the fourth node N4 jumps between high and low levels.

[0077] The signal of the fourth node N4 controls the sixth transistor Mb6 to turn on or off. When the signal of the fourth node N4 controls the sixth transistor Mb6 to turn on, the fourth power signal provided by the fourth power terminal VG4 is transmitted to the scan output terminal OUT. The signal of the second node N2 controls the seventh transistor Mb7 to turn on or off. When the signal of the second node N2 controls the seventh transistor Mb7 to turn on, the third power signal provided by the third power terminal VG3 is transmitted to the scan output terminal OUT. If the fourth power signal is a high level vgh2 and the third power signal is a low level vgl2, the gate drive signal Gout output by the shift register 12 is a high level vgh2 when the sixth transistor Mb6 is turned on, and the gate drive signal Gout output by the shift register 12 is a low level vgl2 when the seventh transistor Mb7 is turned on.

[0078] The signal of the second control terminal B controls the fifth transistor Mb5 to turn on or off. When the signal of the second control terminal B controls the fifth transistor Mb5 to turn on, the first refresh signal line SCL1 provides the first refresh control signal Ctrl1 to the third node N3 through the fifth transistor Mb5. The second control terminal B is one of the fifth node N5, the second node N2 and the shift output terminal NEXT. Figure 8 As shown, the signal of the node N5a is the same as the signal of the fifth node N5, and the signal of the node N2b is the same as the signal of the second node N2. Further, in the same shift register 12, the second control terminal B can be the fifth node N5, or the node N5a, or the second node N2, or the node N2b, or the shift output terminal NEXT. In other embodiments, the shift register 12 can also be selected not to include the fourth control module 160, then the first refresh signal line SCL1 is directly electrically connected to the third node N3, and the signal of the third node N3 is the first refresh control signal Ctrl1.

[0079] In this embodiment, the first transistor Mb1, the second transistor Mb2, the fifth transistor Mb5, the sixth transistor Mb6 and the seventh transistor Mb7 can be PMOS. However, it is not limited to this. Under the premise of ensuring the normal operation of the shift register 12, the working type of each transistor in the shift register 12 can be reasonably selected, either PMOS or NMOS. Correspondingly, the third power supply signal received by the optional third power supply terminal VG3 is a low level (marked as vgl2), and the fourth power supply signal received by the fourth power supply terminal VG4 is a high level (marked as vgh2). The effective level of the gate drive signal Gout provided by the optional scan output terminal OUT is a high level vgh2, and the invalid level of the gate drive signal Gout is a low level vgl2. The effective level of the shift signal provided by the optional shift output terminal NEXT is a high level vgh1, and the invalid level of the shift signal is a low level vgl1. In this embodiment, the second control terminal B in the shift register 12 is electrically connected to the shift output terminal NEXT as an example to illustrate the working principle of the shift register 12.

[0080] The level signal provided by the optional first power supply terminal VG1 is different from the level signal provided by the third power supply terminal VG3. The level signal provided by the optional first power supply terminal VG1 is less than or equal to the level signal provided by the third power supply terminal VG3. Figure 8 As shown, the first power signal provided by the optional first power terminal VG1 is a low level vgl1, and the third power signal provided by the third power terminal VG3 is a low level vgl2. The first power signal vgl1 and the third power signal vgl2 may be different. Specifically, the optional first power signal vgl1 may be less than or equal to the third power signal vgl2. If leakage occurs at the second node N2, the first power signal vgl1 is less than the third power signal vgl2, which can ensure that the transistor Ma10 and the seventh transistor Mb7 can be turned on and off normally, and avoid the situation where the second node N2 leaks and the transistor Ma10 and the seventh transistor Mb7 are mistakenly controlled. The normal and stable operation of the shift register 12 is ensured.

[0081] The optional display panel has a multi-frequency refresh mode; in the multi-frequency refresh mode, the display area of ​​the display panel includes at least a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

[0082] Optionally, in the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the first display partition is greater than the frequency of the gate drive signal; in the multi-frequency refresh mode, the frequency of the gate drive signal of the shift register in the first display partition is less than the frequency of the gate drive signal of the shift register in the second display partition. Therefore, the first display partition works at a low frequency, and the second display partition works at a high frequency. Optionally, in the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the second display partition can be equal to the frequency of the gate drive signal, but is not limited thereto.

[0083] Exemplarily, in the multi-frequency refresh mode, the first refresh frequency of the first display partition is 30 Hz, and the second refresh frequency of the second display partition is 120 Hz. For example, the refresh frequency of the display panel is 120 Hz. Then in the multi-frequency refresh mode, in the first display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 30 Hz; in the second display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 120 Hz.

[0084] Exemplarily, in the multi-frequency refresh mode, the first refresh frequency of the first display partition is 30 Hz, and the second refresh frequency of the second display partition is 60 Hz. For example, the refresh frequency of the display panel is 120 Hz. Then in the multi-frequency refresh mode, in the first display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 30 Hz; in the second display partition, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate drive signal is 60 Hz.

[0085] The working process of the optional shift register 12 includes a data writing stage and a data holding stage; in the data writing stage, the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 to the shift register 12 is a valid level; in the data holding stage, the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 to the shift register 12 is an invalid level.

[0086] It can be understood that a data holding phase is provided between two adjacent data writing phases of the shift register 12. In the multi-frequency refresh mode, the first refresh frequency of the first display partition is less than the second refresh frequency of the second display partition, so within one frame, the data holding phase duration of the shift register 12 in the first display partition is longer than the data holding phase duration of the shift register 12 in the second display partition.

[0087] In this embodiment, by adding the second control module 140a, the potential of the fourth node N4 can be stabilized, so that the output of any shift register 12 in the first display partition working at a low frequency is stable and effective, and the output of any shift register 12 in the second display partition working at a high frequency is stable and effective. Whether working at a low frequency or a high frequency, the shift register 12 will not have the problem of output failure or poor stability caused by the fourth node N4 leaking to other nodes and the potential being reduced.

[0088] In this embodiment, an example in which the effective level of the first refresh control signal Ctrl1 is a low level vgl and the ineffective level of the first refresh control signal Ctrl1 is a high level vgh is taken to illustrate the working principle of the shift register 12 .

[0089] Fig. 9 yes Figure 8 The low frequency operation timing diagram of the shift register 12 in the first display partition is shown. Figure 8 and Fig. 9 As shown, in the first display partition, the shift signal frequency of the shift register 12 is greater than the gate drive signal frequency. When the shift signal of the shift register 12 is at a valid level, there is a situation where the gate drive signal of the shift register 12 is at an invalid level, thereby achieving low-frequency operation. Fig. 9 The working condition of the shift register 12 in the first display partition is shown. In the stage from t11 to t13, the first refresh control signal Ctrl1 is at a high level vgh, i.e., an invalid level, so that the shift register 12 satisfies the situation that the shift signal is at a valid level and the gate drive signal is at an invalid level.

[0090] Fig.10 yes Figure 8 The high frequency operation timing diagram of the shift register 12 in the second display partition is shown. Figure 8 and Fig.10 As shown, in the optional second display partition, the shift signal frequency of the shift register 12 is equal to the gate drive signal frequency. Then, when the shift signal of the shift register 12 is at an effective level, the gate drive signal of the shift register 12 is at an effective level, thereby achieving high-frequency operation. Fig.10 The working condition of the shift register 12 in the second display partition is shown. In the stage from t21 to t23, the first refresh control signal Ctrl1 is at a low level vgl, i.e., a valid level, so that the shift register 12 satisfies the conditions that the shift signal is at a valid level and the gate drive signal is at a valid level.

[0091] In other embodiments, the shift register includes a data writing phase and a data holding phase, the phase t11 to t13 can also be independently regarded as the data holding phase of the shift register, and the phase t21 to t23 can also be independently regarded as the data writing phase of the shift register.

[0092] refer to Figure 8 and Fig. 9 As shown, the low-frequency operation process of the shift register 12 includes:

[0093] In the t11 phase, the first clock signal provided by the first clock terminal CK jumps from a low level to a high level, and the corresponding transistors Ma4 and Ma13 are synchronously turned on and then turned off. The input signal provided by the input terminal IN is a high level, then the fifth node N5 and the node N5a are both high levels, and the transistors Ma2 and Ma6 are both turned off; the transistors Ma15 and Ma16 are turned on, then the second node N2 and the node N2b are both high levels, and the transistor Ma10 is turned off; the low level vgl1 is sequentially transmitted to the node N6a and the node N6b through the transistors Ma5 and Ma8, and the transistor Ma3 is turned on; the second clock signal provided by the second clock terminal XCK is a high level, so that Transistor Ma7 is turned off, the first node N1 remains at the high level of the previous stage, and transistor Ma9 is turned off; the shift signal of the shift output terminal NEXT remains at the low level vgl1 of the previous stage, that is, the invalid level; transistor Mb5 is turned on, and the high level vgh of the first refresh control signal Ctrl1 is transmitted to the third node N3, then the third node N3 is the high level vgh, transistor Mb1 is turned off and transistor Mb2 is turned off, and under the coupling of the high level of the third node N3, the fourth node N4 can be stabilized as the high level vgh of the previous stage, so that transistor Mb6 is turned off; transistor Mb7 is turned off, and the gate drive signal Gout of the scan output terminal OUT remains at the low level vgl2.

[0094] From t12 to t13, it is also the effective level output stage of the shift signal of the shift register 12. The fifth node N5 and the node N5a are both kept at a high level, the second node N2 and the node N2b are both at a high level, and the transistor Ma10 is turned off; the node N6a and the node N6b are at a low level vgl1, so that the transistor Ma3 is turned on; when the second clock signal provided by the second clock terminal XCK is at a low level, the transistor Ma7 is turned on, and the low level of the second clock signal is transmitted to the node N6c and the first node N1, so that the first node N1 is at a low level, and when the second clock signal provided by the second clock terminal XCK is at a high level, the transistor Ma7 is turned off to keep the first node N1 at a low level; the transistor Ma9 is turned on, and the second power supply terminal The second power supply signal vgh1 provided by VG2 is transmitted to the shift output terminal NEXT, and the shift signal is a high level vgh1, i.e., an effective level; the transistor Mb5 is turned off, the third node N3 remains at the high level vgh of the previous stage, and the transistor Mb1 is turned off; the first node N1 is at a low level, so that the transistor Mb2 is turned on, and under the action of the third node N3, the fourth node N4 can be stabilized at a high level vgh, so that the leakage current from the fourth node N4 to the first node N1 can be reduced, and the problem of the fourth node N4 leaking to the first node N1 and the potential gradually decreasing is improved, so that the transistor Mb6 is turned off; the transistor Mb7 is turned off, and the gate drive signal Gout of the scan output terminal OUT remains at a low level vgl2, i.e., an invalid level. It can be seen that in this stage, the shift signal is at an effective level and the gate drive signal Gout is at an invalid level.

[0095] After stage t13, the fifth node N5 and the node N5a are at a low level, the corresponding second node N2 and the node N2b are at a low level, the transistor Ma10 is turned on, and the shift signal of the shift output terminal NEXT is at a low level vgl1; the transistor Ma6 is turned on, so that the first node N1 is at a high level vgh1, and the transistor Ma9 is turned off; the transistor Mb5 is turned on; if the signal Ctrl1 of the first refresh signal line SCL1 jumps high or low, the third node N3 jumps high or low to switch the on-off state of the transistor Mb1, and the first node N 1 is written into the fourth node N4 when the transistor Mb1 is turned on, so that the signal of the fourth node N4 is high level, and the control transistor Mb6 is turned off; alternatively, if the signal Ctrl1 of the first refresh signal line SCL1 is kept at a high level, the third node N3 is at a high level to turn off the transistor Mb1, and the transistor Mb2 is turned off. Under the coupling of the third node N3, the fourth node N4 can be stabilized at a high level vgh, so that the transistor Mb6 is turned off; the transistor Mb7 is turned on, and the gate drive signal Gout of the scan output terminal OUT is a low level vgl2.

[0096] As described above, when the shift register 12 operates in the low-frequency mode, the high-level signal provided by the first refresh signal line SCL1 can keep the third node N3 at a high level vgh, especially for the period from t12 to t13, the first node N1 is at a low level, and the transistor Mb1 is turned off, then the high level of the third node N3 can be written to the fourth node N4 through the newly added second control module 140a. The high level of the fourth node N4 is maintained, and the transistor Mb6 is controlled to be turned off, so as to prevent the fourth node N4 from leaking to the first node N1 and the potential gradually decreasing, causing the transistor Mb6 to be turned on by mistake, so that the gate drive signal Gout of the scan output terminal OUT is maintained at a low level vgl2. In this way, the circuit stability and effectiveness of the shift register 12 operating in the low-frequency mode are effectively enhanced.

[0097] refer to Figure 8 and Fig.10 As shown, the high-frequency operation process of the shift register 12 includes:

[0098] In the t21 stage, the first clock signal provided by the first clock terminal CK jumps from a low level to a high level, and the corresponding transistors Ma4 and Ma13 are synchronously turned on and then turned off. The input signal provided by the input terminal IN is a high level, then the fifth node N5 and the node N5a are both high levels, and the transistors Ma2 and Ma6 are both turned off; the transistors Ma15 and Ma16 are turned on, then the second node N2 and the node N2b are both high levels, and the transistor Ma10 is turned off; the low level vgl1 is sequentially transmitted to the node N6a and the node N6b through the transistors Ma5 and Ma8, and the transistor Ma3 is turned on; the second clock signal provided by the second clock terminal XCK is a high level, so that the transistors Ma4 and Ma13 are turned on and turned off; the transistors Ma2 and Ma6 are turned off and turned off; the transistors Ma15 and Ma16 are turned on, then the second node N2 and the node N2b are both high levels, and the transistor Ma10 is turned off; the low level vgl1 is sequentially transmitted to the node N6a and the node N6b through the transistors Ma5 and Ma8, and the transistor Ma3 is turned on; the second clock signal provided by the second clock terminal XCK is a high level, so that the transistors Ma2 and Ma6 are turned off and turned off; the transistors Ma15 and Ma16 are turned on and ... turned off; the transistors Ma15 and Ma16 are turned on and turned off; the transistors Ma15 and Ma16 are turned on and turned off; Transistor Ma7 is turned off, the first node N1 remains at the high level of the previous stage, and transistor Ma9 is turned off; the shift signal of the shift output terminal NEXT remains at the low level vgl1 of the previous stage, that is, the invalid level; transistor Mb5 is turned on, and the low level vgl of the first refresh control signal Ctrl1 is transmitted to the third node N3, then the third node N3 is the low level vgl, transistor Mb1 is turned on and transistor Mb2 is turned off, the high level of the first node N1 is transmitted to the fourth node N4, so that the fourth node N4 is stabilized at a high level, and transistor Mb6 is turned off; transistor Mb7 is turned off, and the gate drive signal Gout of the scan output terminal OUT remains at the low level vgl2 of the previous stage, that is, the invalid level.

[0099] The stage from t22 to t23 is also the effective level output stage of the shift signal of the shift register 12. The fifth node N5 and the node N5a are both kept at a high level, the second node N2 and the node N2b are both at a high level, and the transistor Ma10 is turned off; the node N6a and the node N6b are at a low level vgl1, so that the transistor Ma3 is turned on; when the second clock signal provided by the second clock terminal XCK is at a low level, the transistor Ma7 is turned on, and the low level of the second clock signal is transmitted to the node N6c and the first node N1, so that the first node N1 is at a low level, and when the second clock signal provided by the second clock terminal XCK is at a high level, the transistor Ma7 is turned on. 7 is turned off to keep the first node N1 at a low level; the transistor Ma9 is turned on, the second power signal vgh1 provided by the second power terminal VG2 is transmitted to the shift output terminal NEXT, and the shift signal is a high level vgh1, that is, an effective level; the transistor Mb5 is turned off, the third node N3 is kept at the low level vgl of the previous stage, the transistor Mb1 is turned on and the transistor Mb2 is turned on, then the fourth node N4 is a low level, the transistor Mb6 is turned on, the transistor Mb7 is turned off, the fourth power signal vgh2 provided by the fourth power terminal VG4 is transmitted to the scan output terminal OUT, and the gate drive signal Gout is a high level vgh2, that is, an effective level. It can be seen that in this stage, the shift signal is an effective level and the gate drive signal Gout is an effective level.

[0100] After stage t23, the fifth node N5 and the node N5a are at a low level, and the corresponding second node N2 and the node N2b are both at a low level, the transistor Ma10 is turned on, and the first power supply signal vgl1 provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT, and the shift signal of the shift output terminal NEXT is a low level vgl1, that is, an invalid level; the transistor Ma6 is turned on, so that the first node N1 is a high level vgh1, and the transistor Ma9 is turned off; the transistor Mb5 is turned on, and the transistor Mb2 is turned off; if the signal Ctrl1 of the first refresh signal line SCL1 remains at a low level, the third node N3 is at a low level to turn on the transistor Mb1, or, if the signal Ctrl1 of the first refresh signal line SCL1 changes from high to low, the third node N3 changes from high to low to switch the on-off state of the transistor Mb1; the high level of the first node N1 is written to the fourth node N4 when the transistor Mb1 is turned on, so that the signal of the fourth node N4 is at a high level, and the transistor Mb6 is controlled to be turned off; the transistor Mb7 is turned on, and the third power supply signal vgl2 provided by the third power supply terminal VG3 is transmitted to the scan output terminal OUT, and the gate drive signal Gout is at a low level vgl2, that is, an invalid level.

[0101] As described above, when the shift register 12 operates in the high frequency mode, the newly added second control module 140a does not affect the normal operation of the circuit, thereby ensuring the circuit stability and effectiveness of the shift register 12 operating in the high frequency mode.

[0102] In the present embodiment, a second control module 140a is added to the shift register 12. The second control module 140a can stabilize the potential of the fourth node N4, reduce the leakage of the high level of the fourth node N4 to the first node N1 due to the interference of the first control module 130, and thus avoid the problem of erroneous control of the refresh output module 150 caused by the leakage of the fourth node N4, thereby improving the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout, which is beneficial to ensuring the output validity, accuracy and stability of the shift register 12, and further beneficial to improving the display quality of the display panel.

[0103] Fig.11 is a schematic diagram of another shift register provided by an embodiment of the present invention, and Figure 8 The difference is that Fig.11 The third node N3 is directly electrically connected to the first refresh signal line SCL1.

[0104] Fig.11 The low frequency operation timing of the shift register 12 can be referred to Fig. 9 As shown. Specifically, the stage from t12 to t13 is used as an example for explanation. In the stage from t12 to t13, the first node N1 is at a low level, the second node N2 is at a high level, and the second power supply signal vgh1 provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT through the turned-on transistor Ma9, then the shift signal is at a high level vgh1, i.e., an effective level; the first refresh signal line SCL1 is directly electrically connected to the third node N3, then the third node N3 is at a high level of the first refresh control signal Ctrl1; the transistor Mb1 is turned off and the transistor Mb2 is turned on, and the high level of the third node N3 is transmitted to the fourth node N4, so that the transistor Mb6 is turned off; the gate drive signal Gout of the scan output terminal OUT remains at the low level vgl2 of the previous stage, i.e., an invalid level. It can be seen that the first refresh signal line SCL1 directly provides the first refresh control signal Ctrl1 to the third node N3, and when the shift signal output by the shift register 12 is at an effective level, the gate drive signal Gout can be an invalid level, thereby realizing low-frequency operation.

[0105] Fig.11 The high frequency operation timing of the shift register 12 can be referred to Fig.10As shown. Specifically, take the stage from t22 to t23 as an example to illustrate. In the stage from t22 to t23, the first node N1 is at a low level, the second node N2 is at a high level, the second power supply signal vgh1 is transmitted to the shift output terminal NEXT, and the shift signal is at a high level vgh1, i.e., an effective level; the low level of the first refresh control signal Ctrl1 is written to the third node N3; the transistor Mb1 is turned on and the transistor Mb2 is turned on, then the fourth node N4 is at a low level; the transistor Mb6 is turned on, the transistor Mb7 is turned off, the fourth power supply signal vgh2 is transmitted to the scan output terminal OUT, and the gate drive signal Gout is at a high level vgh2, i.e., an effective level. It can be seen that the first refresh signal line SCL1 directly provides the first refresh control signal Ctrl1 to the third node N3. When the shift signal output by the shift register 12 is at an effective level, the gate drive signal Gout can be at an effective level, thereby realizing high-frequency operation.

[0106] Fig.12 is a schematic diagram of another shift register provided by an embodiment of the present invention, with reference to Figure 5 and Fig.12 As shown, the optional second control module 140b includes: a third transistor Mb3; the gate of the third transistor Mb3 is electrically connected to the third node N3, the first end of the third transistor Mb3 is electrically connected to the first control module 130, and the second end of the third transistor Mb3 is electrically connected to the fourth node N4. Specifically, the second control module 140b is electrically connected between the first control module 130 and the fourth node N4. Fig.12 The second control module 140b shown in FIG. 1 is different from Figure 8 The second control module 140a is shown in FIG.

[0107] The third transistor Mb3 is of the same type as the first transistor Mb1, and both are PMOS. The signal of the third node N3 controls the third transistor Mb3 and the first transistor Mb1 to be turned on or off simultaneously. It can be understood that the first transistor Mb1 and the third transistor Mb3 can be regarded as a double-gate transistor.

[0108] Fig.12 The low frequency operation timing of the shift register 12 can be referred to Fig. 9As shown. Specifically, the stage from t12 to t13 is used as an example for explanation. In the stage from t12 to t13, the first node N1 is at a low level, the second node N2 is at a high level, and the shift signal output by the shift output terminal NEXT is the second power supply signal vgh1, i.e., the effective level; the high level of the first refresh control signal Ctrl1 is written into the third node N3, so that the dual-gate transistor (Mb1+Mb3) is turned off, and the fourth node N4 is in a floating state and remains at the high level of the previous stage; and the dual-gate transistor (Mb1+Mb3) is set between the fourth node N4 and the first node N1, which can reduce the leakage current from the fourth node N4 to the first node N1. Therefore, in this stage, by setting the second control module 140b, the leakage current from the fourth node N4 to the first node N1 is reduced, so that the fourth node N4 can also be stabilized at a high level to control the transistor Mb6 to turn off; the gate drive signal Gout of the scan output terminal OUT is kept at a low level vgl2, i.e., an invalid level. It can be seen that when the first node N1 is at a low level, the fourth node N4 is at a high level and the first transistor Mb1 is turned off, by setting a second control module 140b between the output end of the first transistor Mb1 and the fourth node N4, the leakage current from the fourth node N4 to the first node N1 can be reduced, thereby improving the output stability of the shift register 12.

[0109] Fig.12 The high frequency operation timing of the shift register 12 can be referred to Fig.10 As shown. Specifically, the stage from t22 to t23 is used as an example for explanation. In the stage from t22 to t23, the first node N1 is at a low level, the second power signal vgh1 is transmitted to the shift output terminal NEXT, and the shift signal is at a high level vgh1, i.e., an effective level; the low level of the first refresh control signal Ctrl1 is written to the third node N3, so that the dual-gate transistor (Mb1+Mb3) is turned on, then the fourth node N4 is at a low level, the fourth power signal vhg2 is transmitted to the scan output terminal OUT, and the gate drive signal Gout is at a high level vgh2, i.e., an effective level. It can be seen that by designing the dual-gate transistor (Mb1+Mb3), when the shift signal output by the shift register 12 is at an effective level, the gate drive signal Gout can be at an effective level, thereby realizing high-frequency operation.

[0110] Fig.13 is a schematic diagram of another shift register provided by an embodiment of the present invention, with reference to Figure 3 and Fig.13As shown, the optional shift register 12 includes a second control module 140a and a second control module 140b, wherein the second control module 140a includes a second transistor Mb2, and the second control module 140b includes a third transistor Mb3. The gate of the second transistor Mb2 is electrically connected to the first node N1, the first end of the second transistor Mb2 is electrically connected to the third node N3, and the second end of the second transistor Mb2 is electrically connected to the fourth node N4. The gate of the third transistor Mb3 is electrically connected to the third node N3, the first end of the third transistor Mb3 is electrically connected to the first control module 130, and the second end of the third transistor Mb3 is electrically connected to the fourth node N4.

[0111] The first transistor Mb1 and the third transistor Mb3 may be of the same type, and the second transistor Mb2 and the third transistor Mb3 may be of the same type or different types. Exemplarily, all three are PMOS, and the third node N3 controls the third transistor Mb3 and the first transistor Mb1 to be turned on or off at the same time. It can be understood that the first transistor Mb1 and the third transistor Mb3 can be regarded as a dual-gate transistor. However, it is not limited to this. Under the premise of ensuring the normal operation of the shift register 12, the working type of each transistor in the shift register 12 can be reasonably selected.

[0112] Fig.13 The low frequency operation timing of the shift register 12 can be referred to Fig. 9 As shown, Fig.13 The high frequency operation timing of the shift register 12 can be referred to Fig.10 shown.

[0113] Fig.13 In the case where the dual-gate transistor (Mb1+Mb3) is turned off, the first node N1 is at a low level and the fourth node N4 is at a high level, the dual-gate transistor (Mb1+Mb3) can reduce the leakage current from the fourth node N4 to the first node N1, and the high level of the third node N3 can also pull up the potential of the fourth node N4 through the second transistor Mb2, further reducing the leakage current from the fourth node N4 to the first node N1, so that the fourth node N4 can also be stabilized at a high level in low-frequency operation to control the transistor Mb6 to turn off, ensuring that the gate drive signal Gout of the scan output terminal OUT remains at a low level vgl2, i.e., an invalid level. By simultaneously setting the second control module 140a and the second control module 140b, the leakage current from the fourth node N4 to the first node N1 can be reduced, and the output stability of the shift register 12 can be improved.

[0114] In other embodiments, Fig.12 and Fig.13 A fourth control module 160 (see Figure 8As shown), the third node N3 is electrically connected to the first refresh signal line SCL1 through the fourth control module 160, so as to further improve the output stability of the shift register 12.

[0115] In this embodiment, the added second control module 140 can stabilize the potential of the fourth node N4, improve the problem of leakage of the high level of the fourth node N4 due to interference from the first control module 130, and thus avoid the problem of erroneous control of the refresh output module 150 caused by leakage of the fourth node N4, thereby improving the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout, which is beneficial to ensuring the output validity, accuracy and stability of the shift register 12, and further beneficial to improving the display quality of the display panel.

[0116] Fig.14 is a schematic diagram of another shift register provided by an embodiment of the present invention, such as Fig.14 As shown, the optional shift register 12 further includes: a third control module 170, electrically connected to the fifth power supply terminal VG5, the first control terminal A and the fourth node N4, for controlling the signal of the fourth node N4; the first control terminal A is one of the fifth node N5, the second node N2, the shift output terminal NEXT and the third node N3. The optional third control module 170 includes: a fourth transistor Mb4; the gate of the fourth transistor Mb4 is electrically connected to the first control terminal A, the first terminal of the fourth transistor Mb4 is electrically connected to the fifth power supply terminal VG5, and the second terminal of the fourth transistor Mb4 is electrically connected to the fourth node N4.

[0117] In this embodiment, the signal of the first control terminal A controls the fourth transistor Mb4 to turn on or off. When the signal of the first control terminal A controls the fourth transistor Mb4 to turn on, the fifth power supply signal provided by the fifth power supply terminal VG5 is transmitted to the fourth node N4 through the turned-on fourth transistor Mb4 to adjust the signal of the fourth node N4. Specifically, the signal of the node N5a is the same as the signal of the fifth node N5, and the signal of the node N2b is the same as the signal of the second node N2. Therefore, in the same shift register 12, the first control terminal A can be the fifth node N5, or the node N5a, or the second node N2, or the node N2b, or the shift output terminal NEXT, or the third node N3.

[0118] The fourth transistor Mb4 can be selected as a PMOS. The fifth power supply signal provided by the optional fifth power supply terminal VG5 is a high level vgh3. Accordingly, when the signal of the fourth node N4 is at a high level, whether the fourth transistor Mb4 is turned on or off, the fifth power supply signal vgh3 provided by the fifth power supply terminal VG5 can stabilize the potential of the fourth node N4, so that the fourth node N4 is maintained at a high level, and the leakage current of the fourth node N4 is reduced, and the problem of leakage current from the fourth node N4 to the fifth power supply terminal VG5 does not occur, and the sixth transistor Mb6 is ensured to be turned off. When the signal of the fourth node N4 is at a low level, the first control terminal A controls the fourth transistor Mb4 to be turned off, and the low level of the fourth node N4 controls the sixth transistor Mb6 to be turned on. In this way, the third control module 170 is added to the shift register 12, which does not affect the normal operation of the shift register 12, and can improve the output stability and effectiveness of the shift register 12. However, it is not limited to this. Under the premise of ensuring the normal operation of the shift register 12, the working type of each transistor in the shift register 12 and the signal of the signal terminal can be reasonably selected.

[0119] The level signal vgh3 provided by the optional fifth power supply terminal VG5 is different from the level signal vgh2 provided by the fourth power supply terminal VG4. The level signal vgh3 provided by the optional fifth power supply terminal VG5 is greater than or equal to the level signal vgh2 provided by the fourth power supply terminal VG4.

[0120] During the operation of the shift register 12, when the fourth node N4 is at a high level, the sixth transistor Mb6 is controlled to be turned off to ensure that the scan output terminal OUT outputs a low level. In this embodiment, the fourth power signal vgh2 provided by the fourth power terminal VG4 is designed to be smaller than the fifth power signal vgh3 provided by the fifth power terminal VG5. When the high level of the fourth node N4 is slightly decreased or disturbed due to leakage of the fourth node N4, external electric field interference, or other signal interference, the sixth transistor Mb6 can be ensured to remain turned off, thereby ensuring the output validity and stability of the shift register 12.

[0121] refer to Fig.14 As shown, at least two of the level signal provided by the optional second power supply terminal VG2, the level signal provided by the fourth power supply terminal VG4 and the level signal provided by the fifth power supply terminal VG5 are the same signal.

[0122] In this embodiment, the second power signal provided by the optional second power terminal VG2 is a high level vgh1, the fourth power signal provided by the fourth power terminal VG4 is a high level vgh2, and the fifth power signal provided by the fifth power terminal VG5 is a high level vgh3.

[0123] The same signal line can be used to provide power signals to the second power terminal VG2, the fourth power terminal VG4 and the fifth power terminal VG5 at the same time, and the second power signal vgh1 is equal to the fourth power signal vgh2 and equal to the fifth power signal vgh3. In other embodiments, two different signal lines can be used to provide power signals to the second power terminal VG2, the fourth power terminal VG4 and the fifth power terminal VG5 respectively; illustratively, one signal line is used to provide the same power signal to the second power terminal VG2 and the fourth power terminal VG4, and another signal line is used to provide the power signal to the fifth power terminal VG5. In this way, the number of signal lines in the non-display area can be reduced, which is conducive to achieving a narrow frame.

[0124] The optional shift register further includes: a first coupling module; a first end of the first coupling module is electrically connected to one of the second power supply end, the fourth power supply end and the fifth power supply end, and a second end of the first coupling module is electrically connected to the fourth node. The optional first coupling module includes: a first capacitor; a first plate of the first capacitor is the first end of the first coupling module, and a second plate of the first capacitor is electrically connected to the fourth node. Fig.14 As shown, the first coupling module 181 includes a first capacitor Cb1 , and the exemplary first capacitor Cb1 is electrically connected between the fourth power supply terminal VG4 and the fourth node N4 .

[0125] The optional shift register further includes: a second coupling module; the first end of the second coupling module is electrically connected to the sixth power supply terminal, and the second end of the second coupling module is electrically connected to the third node. The optional second coupling module includes: a second capacitor; the first plate of the second capacitor is electrically connected to the sixth power supply terminal, and the second plate of the second capacitor is electrically connected to the third node. Fig.14 As shown, the second coupling module 182 includes a second capacitor Cb2, and the exemplary second capacitor Cb2 is electrically connected between the sixth power supply terminal VG6 and the third node N3.

[0126] In this embodiment, the optional sixth power supply signal provided by the sixth power supply terminal VG6 is a low level vgl3. The optional first power supply signal provided by the first power supply terminal VG1 is a low level vgl1, and the third power supply signal provided by the third power supply terminal VG3 is a low level vgl2. Based on this, at least two of the level signal vgl1 provided by the optional first power supply terminal VG1, the level signal vgl2 provided by the third power supply terminal VG3, and the level signal vgl3 provided by the sixth power supply terminal VG6 are the same signal, that is, at least two of the first power supply terminal VG1, the third power supply terminal VG3, and the sixth power supply terminal VG6 are electrically connected to the same signal line. In this way, the number of signal lines in the non-display area can be reduced, which is conducive to achieving a narrow frame.

[0127] In other embodiments, the sixth power supply signal provided by the optional sixth power supply terminal is a high level. Based on this, the optional level signal provided by the sixth power supply terminal is the same signal as the level signal provided by the second power supply terminal; or, the level signal provided by the sixth power supply terminal is the same signal as the level signal provided by the fourth power supply terminal. Specifically, the same signal line is used to provide the same second power supply signal vgh1 to the sixth power supply terminal and the second power supply terminal; or, the same signal line is used to provide the same fourth power supply signal vgh2 to the sixth power supply terminal and the fourth power supply terminal. In this way, the number of signal lines in the non-display area can be reduced, which is conducive to achieving a narrow frame. In other embodiments, the optional level signal provided by the sixth power supply terminal is the same signal as the level signal provided by the fifth power supply terminal.

[0128] The optional shift register further includes: a third coupling module; a first end of the third coupling module is electrically connected to the scan output end, and a second end of the third coupling module is electrically connected to the second node. The optional third coupling module includes: a third capacitor; a first plate of the third capacitor is electrically connected to the scan output end, and a second plate of the third capacitor is electrically connected to the second node. Fig.14 As shown, the third coupling module 183 includes a third capacitor Cb3, and the exemplary third capacitor Cb3 is electrically connected between the scan output terminal OUT and the second node N2.

[0129] Fig.14 In the embodiment, the second control terminal B can be electrically connected to the shift output terminal NEXT, and the first control terminal A can be electrically connected to the second node N2.

[0130] Fig.14 The low frequency operation timing of the shift register 12 can be referred to Fig. 9 The specific description is made by taking the stage from t12 to t13 as an example.

[0131] In the stage t12 to t13 of low-frequency operation, the first node N1 is at a low level, the second node N2 is at a high level, and the second power supply signal vgh1 provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT through the turned-on transistor Ma9, then the shift signal is a high level vgh1, i.e., a valid level; the fifth transistor Mb5 is turned off, and the third node N3 maintains the high level of the previous stage, then the transistor Mb1 is turned off; the transistor Mb2 is turned on, the second node N2 is at a high level, so that the fourth transistor Mb4 is turned off, then the high level of the third node N3 is transmitted to the fourth node N4, so that the fourth node N4 maintains a high level; the transistor Mb6 is turned off, and the gate drive signal Gout of the scan output terminal OUT is maintained at a low level vgl2, i.e., an invalid level.

[0132] After the t13 stage of low-frequency operation, the first node N1 is at a high level, the second node N2 is at a low level, the first power signal vgl1 provided by the first power terminal VG1 is transmitted to the shift output terminal NEXT through the turned-on transistor Ma10, and the shift signal is a low level vgl1, that is, an invalid level; the fifth transistor Mb5 is turned on, and the high level of the first refresh control signal Ctrl1 is transmitted to the third node N3, and the transistor Mb1 is turned off; the transistor Mb2 is turned off, the second node N2 is at a low level to turn on the fourth transistor Mb4, and the fifth power signal vgh3 provided by the fifth power terminal VG5 is transmitted to the fourth node N4, so that the fourth node N4 is a high level; the transistor Mb6 is turned off and the transistor Mb7 is turned on, and the gate drive signal Gout of the scan output terminal OUT is a low level vgl2, that is, an invalid level.

[0133] Fig.14 The high frequency operation timing of the shift register 12 can be referred to Fig.10 As shown, the description will not be repeated here.

[0134] In this embodiment, by adding the second control module 140a and the third control module 170, the potential of the fourth node N4 can be stabilized, and the leakage of the high level of the fourth node N4 to the first node N1 due to the interference of the first control module 130 is reduced, thereby avoiding the problem of erroneous control of the refresh output module 150 caused by the leakage of the fourth node N4, thereby improving the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout, which is beneficial to ensuring the output validity, accuracy and stability of the shift register 12, and further beneficial to improving the display quality of the display panel.

[0135] In other embodiments, the types of transistors in the shift register may all be NMOS, or the types of transistors in the shift register may include at least one NMOS and at least one PMOS. Fig.15 is a schematic diagram of another shift register provided by an embodiment of the present invention, such as Fig.15As shown, the optional first control terminal A is the third node N3; the signal of the third node N3 controls the first control module 130 and the third control module 170 to be turned on in time-sharing. Specifically, the first transistor Mb1 in the optional first control module 130 is PMOS, and the fourth transistor Mb4 in the third control module 170 is NMOS, then the first control terminal A is the third node N3, and the signal of the third node N3 controls the first control module 130 and the third control module 170 to be turned on in time-sharing. When the signal of the third node N3 is at a high level, the first transistor Mb1 is controlled to be turned off and the fourth transistor Mb4 is turned on, and the fifth power supply signal vgh3 is written to the fourth node N4, so that the fourth node N4 is guaranteed to be at a high level, which can reduce the leakage current from the fourth node N4 to the first node N1. When the signal of the third node N3 is at a low level, the first transistor Mb1 is controlled to be turned on and the fourth transistor Mb4 is turned off, and the signal of the first node N1 is written to the fourth node N4. Fig.15 The low frequency operation timing of the shift register 12 can be referred to Fig. 9 As shown, Fig.15 The high frequency operation timing of the shift register 12 can be referred to Fig.10 As shown, the description will not be repeated here.

[0136] For the above-mentioned multiple embodiments, the shift register 12 includes a first control module 130 and a second control module 140. On this basis, the third control module 170, the fourth control module 160, the first coupling module 181, the second coupling module 182 and the third coupling module 183 are all optional options for the shift register 12, that is, the shift register 12 may not include the third control module 170, the fourth control module 160, the first coupling module 181, the second coupling module 182 and the third coupling module 183, or the shift register 12 may include at least one of the third control module 170, the fourth control module 160, the first coupling module 181, the second coupling module 182 and the third coupling module 183. Under the premise of ensuring the normal operation of the shift register 12, relevant practitioners can reasonably design the specific components and structures of the shift register 12 according to the product requirements. It is not limited to the above figures.

[0137] The inventor has found through research that the scan output unit 14 of the shift register 12 is not limited to the above structure, and the scan output unit 14 may not include the second control module 140, and by reasonably designing the structure of the scan output unit 14 in the shift register 12, it is ensured that the shift register 12 works normally and the output is stable and effective. The following multiple embodiments provide different multiple scan output units 14, wherein the scan output unit 14 may include the second control module 140 or not include the second control module 140.

[0138] Fig.16 is a schematic diagram of another shift register provided by an embodiment of the present invention, such as Fig.16 As shown, the scan output unit 14 of the optional shift register 12 does not include a second control module. The optional scan output unit 14 is a 5T3C structure, wherein the "5T" of the scan output unit 14 includes a first transistor Mb1, a fourth transistor Mb4, a fifth transistor Mb5, a sixth transistor Mb6 and a seventh transistor Mb7, and the "3C" of the scan output unit 14 includes a first capacitor Cb1, a second capacitor Cb2 and a third capacitor Cb3. The five transistors in the optional scan output unit 14 are all PMOS, but are not limited to this. The low-frequency operation timing of the shift register 12 can refer to Fig. 9 As shown, and its high frequency working timing can refer to Fig.10 As shown, no repetition is given here.

[0139] Fig.17 is a schematic diagram of another shift register provided by an embodiment of the present invention, and Fig.16 There is a difference. Specific, optional Fig.17 The scan output unit 14 is a 5T2C structure, wherein the first transistor Mb1 can be NMOS and the fourth transistor Mb4 can be PMOS, the gate of the fourth transistor Mb4 is electrically connected to the third node N3, and the scan output unit 14 can include only two capacitors, namely the second capacitor Cb2 and the third capacitor Cb3.

[0140] Fig.18 is a schematic diagram of another shift register provided by an embodiment of the present invention, and Fig.16 There is a difference. Specific, optional Fig.18 The middle scan output unit 14 is a 5T2C structure, wherein the first transistor Mb1 can be optionally an NMOS and the fourth transistor Mb4 can be a PMOS, the first end of the first transistor Mb1 receives a high level and the second end is electrically connected to the fourth node N4, the high level received by the first end of the first transistor Mb1 can come from the second power supply terminal VG2, or from the fourth power supply terminal VG4, or from the fifth power supply terminal VG5, the gate of the fourth transistor Mb4 is electrically connected to the third node N3, the first end of the fourth transistor Mb4 is electrically connected to the first node N1 and the second end is electrically connected to the fourth node N4, and the scan output unit 14 can include only two capacitors, namely the second capacitor Cb2 and the third capacitor Cb3.

[0141] Fig.19 is a schematic diagram of another shift register provided by an embodiment of the present invention, and Fig.16 There is a difference. Specific, optional Fig.19 The scan output unit 14 is a 4T2C structure, wherein the third node N3 of the shift register 12 can be directly electrically connected to the first refresh signal line SCL1 to receive the first refresh control signal Ctrl1, and the scan output unit 14 can include only two capacitors, namely the first capacitor Cb1 and the third capacitor Cb3.

[0142] Combination Fig. 9 and Fig.10 ,for Fig.19 In the shift register 12 shown in the figure, when the first refresh control signal Ctrl1 received by the third node N3 is at a high level, the first transistor Mb1 is turned off, and the shift register 12 is in a low refresh rate mode. On the contrary, when the first refresh control signal Ctrl1 received by the third node N3 of the shift register 12 is at a low level, the first transistor Mb1 is turned on, and the electrical signal of the first node N1 is written to the fourth node N4, and the shift register 12 is in a high refresh rate mode. Therefore, the high and low level jump position of the first refresh control signal Ctrl1 is the boundary between the low refresh rate display area and the high refresh rate display area.

[0143] In this embodiment, multiple refresh signal lines may be used, each refresh signal line is electrically connected to a continuous multi-stage shift register, and the jump of the refresh control signal of each refresh signal line will not affect the output validity of the shift register 12.

[0144] For the above embodiments, the structure of the scan output unit 14 can be adjusted under the premise of ensuring the normal operation of the shift register 12. The structure of the scan output unit 14 can be "5T3C", or "5T2C", or "4T2C", or other structures. Relevant practitioners can reasonably design the specific components and structures of the shift register 12 according to product requirements. It is not limited to the above figures.

[0145] Fig. 20 is a schematic diagram of another shift register provided by an embodiment of the present invention, Fig.21 is a schematic diagram of another shift register provided by an embodiment of the present invention, which is different from any of the above embodiments in that: Fig. 20 and Fig.21 The middle shift register 12 is electrically connected to two refresh signal lines.

[0146] like Fig. 20 and Fig.21 As shown, the optional shift register 12 also includes: a fifth control module 190; the fifth control module 190 is electrically connected to the second control terminal B, the second refresh signal line, the fifth power supply terminal VG5 and the fourth node N4, and is used to control the signal of the fourth node N4; the second control terminal B is one of the fifth node N5, the second node N2 and the shift output terminal NEXT.

[0147] In this embodiment, the display panel includes a second refresh signal line and a first refresh signal line, the first refresh signal line provides a first refresh control signal Ctrl1 to the shift register 12, and the second refresh signal line provides a second refresh control signal Ctrl2 to the shift register 12. The first refresh control signal Ctrl1 provided by the first refresh signal line can be transmitted to the third node N3 through the fourth control module 160; in other embodiments, the first refresh control signal Ctrl1 provided by the first refresh signal line can be directly transmitted to the third node N3.

[0148] Combination Figure 7 , Fig. 20 and Fig.21 As shown, it can be known that the second control terminal B can be the fifth node N5, or the node N5a, or the second node N2, or the node N2b, or the shift output terminal NEXT.

[0149] The optional fifth control module 190 includes: a first control submodule 191, electrically connected to the second control terminal B, the second refresh signal line and the first subnode N3a, for controlling the signal of the first subnode N3a; a second control submodule 192, electrically connected to the first subnode N3a, the fifth power supply terminal VG5 and the fourth node N4, for controlling the signal of the fourth node N4. The optional first control submodule 191 includes: an eighth transistor Mb8, the gate of the eighth transistor Mb8 is electrically connected to the second control terminal B, the first end of the eighth transistor Mb8 is electrically connected to the second refresh signal line, and the second end of the eighth transistor Mb8 is electrically connected to the first subnode N3a; the second control submodule 192 includes: a ninth transistor Mb9, the gate of the ninth transistor Mb9 is electrically connected to the first subnode N3a, the first end of the ninth transistor Mb9 is electrically connected to the fifth power supply terminal VG5, and the second end of the ninth transistor Mb9 is electrically connected to the fourth node N4.

[0150] In this embodiment, the first end of the eighth transistor Mb8 in the first control submodule 191 receives the second refresh control signal Ctrl2 provided by the second refresh signal line. The signal of the second control terminal B controls the on-off state of the first control submodule 191. Specifically, when the signal of the second control terminal B controls the eighth transistor Mb8 to turn on, the second refresh control signal Ctrl2 is transmitted to the first subnode N3a. When the signal of the second control terminal B controls the eighth transistor Mb8 to turn off, the first subnode N3a maintains the level of the previous stage.

[0151] The gate of the ninth transistor Mb9 in the second control submodule 192 is electrically connected to the first subnode N3a. The signal of the first subnode N3a controls the on-off state of the second control submodule 192. Specifically, when the signal of the first subnode N3a controls the ninth transistor Mb9 to turn on, the fifth power supply signal provided by the fifth power supply terminal VG5 is transmitted to the fourth node N4. When the signal of the first subnode N3a controls the ninth transistor Mb9 to turn off, the fourth node N4 maintains the level of the previous stage or is adjusted by the influence of other nodes.

[0152] like Fig.21 As shown, the optional fifth control module 190 further includes: a coupling submodule 193; a first end of the coupling submodule 193 is electrically connected to the sixth power supply terminal VG6, and a second end of the coupling submodule 193 is electrically connected to the first subnode N3a. The optional coupling submodule 193 includes: a fourth capacitor Cb4; a first plate of the fourth capacitor Cb4 is electrically connected to the sixth power supply terminal VG6, and a second plate of the fourth capacitor Cb4 is electrically connected to the first subnode N3a.

[0153] The control signal Ctrl2 provided by the optional second refresh signal line is different from the control signal Ctrl1 provided by the first refresh signal line. The control signal Ctrl2 provided by the optional second refresh signal line and the control signal Ctrl1 provided by the first refresh signal line are both high-low level transition signals, and the two are in opposite phases.

[0154] In this embodiment, the effective level of the first refresh control signal Ctrl1 is a low level vgl and the invalid level of the first refresh control signal Ctrl1 is a high level vgh as an example to illustrate the working principle of the shift register 12. Correspondingly, when the first refresh control signal Ctrl1 provided by the first refresh signal line is a low level vgl, the second refresh control signal Ctrl2 provided by the second refresh signal line is a high level vgh; conversely, when the first refresh control signal Ctrl1 is a high level vgh, the second refresh control signal Ctrl2 is a low level vgl. The first control terminal A can be electrically connected to the second node N2, and the second control terminal B can be electrically connected to the shift output terminal NEXT.

[0155] Here with Fig.21 For example, Fig. 22 yes Fig.21 The low frequency operation timing diagram of the shift register 12 in the first display partition is shown. Fig.21 and Fig. 22 As shown, in the first display partition, the shift signal frequency of the shift register 12 is greater than the gate drive signal frequency. Then, when the shift register 12 operates at a low frequency, the shift signal is at a valid level and the gate drive signal is at an invalid level, thereby achieving low-frequency operation.

[0156] Fig.23 yes Fig.21 The high frequency operation timing diagram of the shift register 12 in the second display partition is shown. Fig.21 and Fig.23 As shown, in the optional second display partition, the shift signal frequency of the shift register 12 is equal to the gate drive signal frequency. Then, when the shift register 12 operates at a high frequency, the shift signal is at a valid level and the gate drive signal is at a valid level, thereby achieving high frequency operation.

[0157] refer to Fig.21 and Fig. 22 As shown, the low-frequency operation process of the shift register 12 includes:

[0158] In stage t31, the second node N2 is at a high level, the first node N1 remains at a high level in the previous stage, and the shift signal of the shift output terminal NEXT remains at a low level vgl1, i.e., an invalid level, in the previous stage; transistors Mb5 and Mb8 are both turned on, the third node N3 is a high level vgh of the first refresh control signal Ctrl1, transistor Mb1 is turned off, the first subnode N3a is a low level vgl of the second refresh control signal Ctrl2, and transistor Mb9 is turned on; the fifth power supply signal vgh3 of the fifth power supply terminal VG5 is written into the fourth node N4, and the fourth node N4 is at a high level; transistor Mb6 is turned off and transistor Mb7 is turned off, and the gate drive signal Gout of the scan output terminal OUT remains at a low level vgl2.

[0159] The stage from t32 to t33 is also the effective level output stage of the shift signal of the shift register 12. The second node N2 is at a high level, the first node N1 is at a low level, the second power supply signal vgh1 provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT, and the shift signal is at a high level vgh1, i.e., an effective level; both the transistor Mb5 and the transistor Mb8 are turned off, the third node N3 remains at a high level vgh in the previous stage, and the fourth node N4 remains at a high level vgh3 in the previous stage; the transistor Mb6 is turned off and the transistor Mb7 is turned off, and the gate drive signal Gout of the scan output terminal OUT remains at a low level vgl2, i.e., an invalid level. It can be seen that in this stage, the shift signal is at an effective level and the gate drive signal Gout is at an invalid level.

[0160] After stage t33, the second node N2 is at a low level, the first node N1 is at a high level vgh1, and the shift signal of the shift output terminal NEXT is at a low level vgl1; transistor Mb5 and transistor Mb8 are both turned on, the third node N3 is at a high level vgh, the first subnode N3a is at a low level vgl to turn on transistor Mb9, the fifth power supply signal vgh3 is written to the fourth node N4, transistor Mb6 is turned off and transistor Mb7 is turned on, and the gate drive signal Gout of the scan output terminal OUT is at a low level vgl2.

[0161] refer to Fig.21 and Fig.23 As shown, the high-frequency operation process of the shift register 12 includes:

[0162] In stage t41, the second node N2 is at a high level, and the first node N1 remains at a high level in the previous stage, then the shift signal of the shift output terminal NEXT remains at a low level vgl1, i.e., an invalid level, in the previous stage; transistors Mb5 and Mb8 are both turned on, the third node N3 is a low level vgl of the first refresh control signal Ctrl1, transistor Mb1 is turned on, the first subnode N3a is a high level vgh of the second refresh control signal Ctrl2, and transistor Mb9 is turned off; the high level of the first node N1 is written into the fourth node N4, and the fourth node N4 is at a high level; transistor Mb6 is turned off and transistor Mb7 is turned off, and the gate drive signal Gout of the scan output terminal OUT remains at a low level vgl2.

[0163] From t42 to t43, the second node N2 is at a high level, the first node N1 is at a low level, the second power signal vgh1 is transmitted to the shift output terminal NEXT, and the shift signal is at a high level vgh1, i.e., an effective level; both transistors Mb5 and Mb8 are turned off, the third node N3 remains at a low level vgl in the previous stage, transistor Mb1 is turned on, and the low level vgl of the first node N1 is written to the fourth node N4; the first subnode N3a remains at a high level vgh in the previous stage, and transistor Mb9 is turned off; transistor Mb6 is turned on and transistor Mb7 is turned off, the fourth power signal vgh2 is written to the scan output terminal OUT, and the gate drive signal Gout is at a high level vgh2, i.e., an effective level. It can be seen that in this stage, the shift signal is at an effective level and the gate drive signal Gout is at an effective level.

[0164] After stage t43, the second node N2 is at a low level, the first node N1 is at a high level vgh1, the first power supply signal vgl1 is transmitted to the shift output terminal NEXT, and the shift signal is at a low level vgl1, that is, an invalid level; transistor Mb5 and transistor Mb8 are both turned on, the third node N3 is the low level vgl of the first refresh control signal Ctrl1, transistor Mb1 is turned on, the first subnode N3a is the high level vgh of the second refresh control signal Ctrl2, and transistor Mb9 is turned off; the high level of the first node N1 is written to the fourth node N4; transistor Mb6 is turned off and transistor Mb7 is turned on, the third power supply signal vgl2 is written to the scan output terminal OUT, and the gate drive signal Gout is a low level vgl2.

[0165] As described above, when the shift register 12 operates in the low-frequency mode or the high-frequency mode, the potential of the fourth node N4 is stable, and the fourth node N4 will not erroneously trigger the sixth transistor Mb6, thereby ensuring the circuit stability and effectiveness of the shift register 12. Based on this shift register structure, the display panel can achieve partition refresh at any position, save power consumption, and improve the output stability and effectiveness of the partition refresh, especially the output effectiveness of the low-refresh display area.

[0166] It should be noted that the structure of the shift register in the embodiment of the present invention is not limited to this. On this basis, the shift register with the structure of increasing or decreasing corresponding transistors is applicable to the embodiment of the present invention, and the embodiment of the present invention will not give examples one by one. Fig. 20 The transistor Mb4 is deleted on the basis of the above, and its working process is similar to other shift registers, which will not be described in detail. Obviously, the structure of the shift register in the embodiment of the present invention can be various, and is not limited to this.

[0167] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention. Therefore, the display device has the technical features of the display panel and the driving process provided by the embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by the embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0168] For example, Fig.24 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention, such as Fig.24 As shown, the display device 1 includes a display panel 10 provided in an embodiment of the present invention. The display device 1 provided in an embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0169] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0170] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: a first driving circuit, wherein the first driving circuit comprises a multi-stage shift register; The shift register comprises: a shift control module, electrically connected to the input terminal, the first clock terminal, the second clock terminal, the first power terminal, the second power terminal, the first node and the second node, and used to control a signal of the first node and a signal of the second node; a shift output module, electrically connected to the first node, the second node, the first power supply terminal, the second power supply terminal and the shift output terminal, and used for controlling the shift output terminal to output a shift signal; A first control module is electrically connected to the first node, the third node and the fourth node, and is used to control the signal of the fourth node; the third node is used to receive the first refresh control signal provided by the first refresh signal line; a second control module, electrically connected to the third node and the fourth node, and used to adjust a signal of the fourth node; the second control module is also electrically connected to the first node, and / or the first control module is electrically connected to the fourth node through the second control module; A refresh output module is electrically connected to the second node, the fourth node, the third power supply terminal, the fourth power supply terminal and the scan output terminal, and is used to control the scan output terminal to output a gate drive signal.

2. The display panel according to claim 1, characterized in that: The first control module includes: a first transistor; A gate of the first transistor is electrically connected to the third node, a first terminal of the first transistor is electrically connected to the first node, and a second terminal of the first transistor is electrically connected to the fourth node.

3. The display panel according to claim 1, characterized in that: The second control module includes: a second transistor; A gate of the second transistor is electrically connected to the first node, a first terminal of the second transistor is electrically connected to the third node, and a second terminal of the second transistor is electrically connected to the fourth node.

4. The display panel according to claim 1, characterized in that: The second control module includes: a third transistor; The gate of the third transistor is electrically connected to the third node, the first end of the third transistor is electrically connected to the first control module, and the second end of the third transistor is electrically connected to the fourth node.

5. The display panel according to claim 1, characterized in that: The shift control module comprises: a first shift submodule, electrically connected to the input terminal, the first clock terminal and the fifth node, and used to control a signal of the fifth node; a second shift submodule, electrically connecting the fifth node, the first clock terminal, the second clock terminal, the first power terminal, the second power terminal and the first node, and used for controlling a signal of the first node; The third shift submodule is electrically connected to the fifth node, the second clock terminal, the first power terminal, the second power terminal and the second node, and is used to control the signal of the second node.

6. The display panel according to claim 5, characterized in that: The shift register further includes: a third control module, electrically connected to the fifth power supply terminal, the first control terminal and the fourth node, and used to control a signal of the fourth node; The first control terminal is one of the fifth node, the second node, the shift output terminal, and the third node.

7. The display panel according to claim 6, characterized in that: The third control module includes: a fourth transistor; A gate of the fourth transistor is electrically connected to the first control terminal, a first terminal of the fourth transistor is electrically connected to the fifth power terminal, and a second terminal of the fourth transistor is electrically connected to the fourth node.

8. The display panel according to claim 6, characterized in that: The level signal provided by the fifth power supply terminal is different from the level signal provided by the fourth power supply terminal.

9. The display panel according to claim 6, characterized in that: The level signal provided by the fifth power supply terminal is greater than or equal to the level signal provided by the fourth power supply terminal.

10. The display panel according to claim 6, characterized in that: At least two of the level signal provided by the second power supply terminal, the level signal provided by the fourth power supply terminal, and the level signal provided by the fifth power supply terminal are the same signal.

11. The display panel according to claim 6, characterized in that: The first control end is the third node; The signal of the third node controls the first control module and the third control module to be turned on in a time-sharing manner.

12. The display panel according to claim 6, characterized in that: The shift register further includes: a first coupling module; A first end of the first coupling module is electrically connected to one of the second power supply end, the fourth power supply end, and the fifth power supply end, and a second end of the first coupling module is electrically connected to the fourth node.

13. The display panel according to claim 12, characterized in that: The first coupling module includes: a first capacitor; The first plate of the first capacitor is the first end of the first coupling module, and the second plate of the first capacitor is electrically connected to the fourth node.

14. The display panel according to claim 5, characterized in that: The shift register further includes: a fourth control module; The fourth control module is electrically connected to the second control terminal; The first refresh signal line provides the first refresh control signal to the third node through the fourth control module; The second control terminal is one of the fifth node, the second node and the shift output terminal.

15. The display panel according to claim 14, characterized in that: The fourth control module includes: a fifth transistor; A gate of the fifth transistor is electrically connected to the second control terminal, a first terminal of the fifth transistor is electrically connected to the first refresh signal line, and a second terminal of the fifth transistor is electrically connected to the third node.

16. The display panel according to claim 15, characterized in that: The fifth transistor is a dual-gate transistor.

17. The display panel according to claim 1, characterized in that: The shift register further includes: a second coupling module; A first end of the second coupling module is electrically connected to the sixth power supply end, and a second end of the second coupling module is electrically connected to the third node.

18. The display panel according to claim 17, characterized in that: The second coupling module includes: a second capacitor; The first plate of the second capacitor is electrically connected to the sixth power supply terminal, and the second plate of the second capacitor is electrically connected to the third node.

19. The display panel according to claim 17, characterized in that: At least two of the level signal provided by the first power supply terminal, the level signal provided by the third power supply terminal, and the level signal provided by the sixth power supply terminal are the same signal.

20. The display panel according to claim 17, characterized in that: The level signal provided by the sixth power supply terminal is the same as the level signal provided by the second power supply terminal; or, the level signal provided by the sixth power supply terminal is the same as the level signal provided by the fourth power supply terminal.

21. The display panel according to claim 1, characterized in that: The refresh output module comprises: A first output submodule, electrically connected to the fourth node, the fourth power supply terminal and the scan output terminal, and used for controlling the scan output terminal to output the gate driving signal; The second output submodule is electrically connected to the second node, the third power supply terminal and the scan output terminal, and is used to control the scan output terminal to output the gate driving signal.

22. The display panel according to claim 21, characterized in that: The first output submodule includes: a sixth transistor; A gate of the sixth transistor is electrically connected to the fourth node, a first terminal of the sixth transistor is electrically connected to the fourth power supply terminal, and a second terminal of the sixth transistor is electrically connected to the scan output terminal.

23. The display panel according to claim 21, characterized in that: The second output submodule comprises: a seventh transistor; A gate of the seventh transistor is electrically connected to the second node, a first terminal of the seventh transistor is electrically connected to the third power terminal, and a second terminal of the seventh transistor is electrically connected to the scan output terminal.

24. The display panel according to claim 1, characterized in that: The level signal provided by the first power supply terminal is different from the level signal provided by the third power supply terminal.

25. The display panel according to claim 1, characterized in that: The level signal provided by the first power supply end is less than or equal to the level signal provided by the third power supply end.

26. The display panel according to claim 1, characterized in that: The shift register further includes: a third coupling module; A first end of the third coupling module is electrically connected to the scan output end, and a second end of the third coupling module is electrically connected to the second node.

27. The display panel according to claim 26, characterized in that: The third coupling module includes: a third capacitor; The first plate of the third capacitor is electrically connected to the scan output terminal, and the second plate of the third capacitor is electrically connected to the second node.

28. The display panel according to claim 5, characterized in that: The shift register further includes: a fifth control module; The fifth control module is electrically connected to the second control terminal, the second refresh signal line, the fifth power terminal and the fourth node, and is used to control the signal of the fourth node; The second control terminal is one of the fifth node, the second node and the shift output terminal.

29. The display panel according to claim 28, characterized in that: The fifth control module comprises: A first control submodule, electrically connected to the second control terminal, the second refresh signal line and the first subnode, and used for controlling the signal of the first subnode; The second control submodule is electrically connected to the first subnode, the fifth power supply terminal and the fourth node, and is used to control the signal of the fourth node.

30. The display panel according to claim 29, characterized in that: The first control submodule comprises: an eighth transistor, a gate of the eighth transistor is electrically connected to the second control terminal, a first terminal of the eighth transistor is electrically connected to the second refresh signal line, and a second terminal of the eighth transistor is electrically connected to the first subnode; The second control submodule includes: a ninth transistor, a gate of the ninth transistor is electrically connected to the first subnode, a first end of the ninth transistor is electrically connected to the fifth power supply end, and a second end of the ninth transistor is electrically connected to the fourth node.

31. The display panel according to claim 29, characterized in that: The fifth control module further includes: a coupling submodule; The first end of the coupling submodule is electrically connected to the sixth power supply end, and the second end of the coupling submodule is electrically connected to the first sub-node.

32. The display panel according to claim 31, characterized in that: The coupling submodule includes: a fourth capacitor; The first plate of the fourth capacitor is electrically connected to the sixth power supply terminal, and the second plate of the fourth capacitor is electrically connected to the first sub-node.

33. The display panel according to claim 28, characterized in that: The control signal provided by the second refresh signal line is different from the control signal provided by the first refresh signal line.

34. The display panel according to claim 28, characterized in that: The control signal provided by the second refresh signal line and the control signal provided by the first refresh signal line are both high-low level transition signals, and the two are in opposite phases.

35. The display panel according to claim 1, characterized in that: The display panel has a multi-frequency refresh mode; In the multi-frequency refresh mode, the display area of ​​the display panel includes at least a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

36. The display panel according to claim 35, characterized in that: In the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the first display partition is greater than the frequency of the gate drive signal; In the multi-frequency refresh mode, the frequency of the gate driving signal of the shift register in the first display partition is lower than the frequency of the gate driving signal of the shift register in the second display partition.

37. A display device, characterized in that: include: A display panel as described in any one of claims 1 to 36.

Images