Display device and display method
By making pixels of odd and even rows share a pixel drive circuit in the display technology, the problem of large storage capacitor occupancy in the prior art is solved, and a higher display resolution and lower power consumption are achieved.
Patent Information
- Application Number
- CN202510427038.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-05-16
AI Technical Summary
In the display technology driven by silicon-based backplane, the existing designs require independent storage capacitors for each pixel, resulting in a large chip area. As the resolution and grayscale accuracy improve, the limitations of the design become more obvious, affecting the integration and display performance.
By making two pixels in odd and even rows and in the same column share a pixel driving circuit, the amount of storage capacitors and transistors used is reduced, thereby reducing the area occupied by the pixel driving circuit.
It realizes the integration of more pixels within a limited chip area, improves display resolution, reduces power consumption, and simplifies circuit design.
Smart Images
Figure CN120014956A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display technology, and in particular to a display device and a display method. Background Art
[0002] Currently, displays usually use a method of independently controlling each pixel to ensure high display accuracy and reliability. Although this design can provide excellent display effects, in the silicon-based backplane driving pixel circuit, each pixel requires an independent storage capacitor to maintain the pixel state, resulting in a large chip area. As display resolution and grayscale accuracy continue to improve, the limitations of this design become more and more obvious.
[0003] Under existing process conditions, the minimum size of storage capacitors is limited, especially in high-precision processes, and the capacitor area is difficult to further reduce, which not only affects the integration of pixel circuits, but also brings challenges to circuit layout, wiring complexity and manufacturing costs. In addition, the increase in storage capacitors causes the drive circuit to occupy a larger area, affecting the overall display performance optimization and may have an adverse effect on power consumption management.
[0004] Therefore, how to effectively reduce the capacitor area and improve the integration while ensuring display accuracy has become an urgent problem to be solved in silicon-based backplane driving display technology.
[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0006] The object of the present invention is to provide a display device which can reduce the occupied area of a pixel driving circuit and improve display resolution.
[0007] To achieve the above object, an embodiment of the present invention provides a display device, comprising:
[0008] A pixel array, comprising pixels in odd rows and pixels in even rows, each pixel corresponding to a light emitting element, at least adjacent pixels in odd rows and pixels in even rows, two pixels in the same column of the adjacent pixels in odd rows and pixels in even rows share a pixel driving circuit, the pixel driving circuit comprising a plurality of transistors and at least one storage capacitor, the pixel driving circuit being configured to drive the light emitting element to emit light based on data stored in the storage capacitor;
[0009] A data cache module, used to store external display data and display data corresponding to odd-numbered rows or even-numbered rows of pixels;
[0010] The timing control module is used to control at least the pixel driving circuit to reset in the reset phase based on the horizontal and vertical synchronization signals, control the data cache module to store the data corresponding to the odd-numbered or even-numbered rows of pixels in the corresponding storage capacitor in the data writing phase, and control the pixel driving circuit to drive the light-emitting elements corresponding to the odd-numbered or even-numbered rows of pixels to emit light in the light-emitting phase; wherein,
[0011] The pixels in odd-numbered rows and even-numbered rows are driven and displayed alternately.
[0012] In one or more embodiments of the present invention, the data cache module includes
[0013] A first buffer, used for storing external display data;
[0014] The second buffer is connected to the first buffer and is used to store pixel data of odd-numbered rows or even-numbered rows; wherein,
[0015] The first buffer transfers the data therein to the second buffer during a vertical blanking period, which is a low level phase of a horizontal synchronization signal.
[0016] In one or more embodiments of the present invention, after the first buffer transfers data to the second buffer, the timing control module notifies the storage capacitor corresponding to the pixel to receive new data through an interrupt, and the new data is temporarily stored in the local latch corresponding to the storage capacitor.
[0017] In one or more embodiments of the present invention, when the vertical synchronization signal is at a falling edge, the timing control module controls the local latch to be enabled, so as to store the data in the local latch into the storage capacitor.
[0018] In one or more embodiments of the present invention, the pixels in the odd-numbered rows and the pixels in the even-numbered rows are alternately driven to display the display including:
[0019] In each cycle of the horizontal and vertical synchronization signals, odd and even lines are switched during the horizontal blanking period.
[0020] In one or more embodiments of the present invention, the timing control module controls the pixels of odd rows to display in the current vertical synchronization cycle, and controls the pixels of even rows to display in the next vertical synchronization cycle, wherein the timing control module controls the data cache module to store the data corresponding to the pixels of odd rows or even rows into the corresponding storage capacitors in the first half of each cycle, and controls the corresponding pixel driving circuit to drive the light-emitting elements of the corresponding pixel rows to emit light in the second half of the cycle.
[0021] In one or more embodiments of the present invention, the data cache module starts redundant data retransmission in the next cycle of the vertical synchronization signal when a data check error is detected.
[0022] In one or more embodiments of the present invention, a clock error compensation module is further included, which monitors the phase difference between the main clock and the horizontal and vertical synchronization signals in real time through a phase-locked loop and dynamically adjusts the internal clock frequency based on the phase difference.
[0023] In one or more embodiments of the present invention, an odd-even row selection module is further included, which is configured to switch between an odd row state and an even row state, wherein:
[0024] In the odd row state, only odd-numbered rows of pixels are used to display the image;
[0025] In the even-row state, only the even-numbered rows of pixels are used to display the image;
[0026] An embodiment of the present invention provides a display method, comprising the following steps:
[0027] S1, in the reset stage, the timing control module controls the pixel driving circuit to reset;
[0028] S2, in the data writing stage, the timing control module controls the data cache module to write the data corresponding to the odd-row pixels into the storage capacitor of the pixel driving circuit;
[0029] S3, in the light-emitting stage, the timing control module generates a driving signal, and controls the light-emitting elements corresponding to the odd-row pixels to emit light based on the data corresponding to the odd-row pixels stored in the storage capacitor;
[0030] S4, in the reset stage, the timing control module controls the pixel driving circuit to reset;
[0031] S5, in the data writing stage, the timing control module controls the data cache module to write the data corresponding to the even-row pixels into the storage capacitor of the pixel driving circuit;.
[0032] S6, in the light-emitting stage, the timing control module generates a driving signal, and controls the light-emitting elements corresponding to the even-row pixels to emit light based on the data corresponding to the even-row pixels stored in the storage capacitor;
[0033] S7, repeat S1 to S6.
[0034] Compared with the prior art, the present invention enables two pixels in an odd row, an even row and in the same column to share a pixel driving circuit. Compared with two rows of pixels being driven separately by corresponding pixel driving circuits, the present invention can reduce the usage of pixel driving circuits, thereby reducing the usage of storage capacitors and reducing the area occupied by pixel driving circuits, so that more pixels can be integrated within a limited chip area, thereby improving display resolution. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1is a schematic structural diagram of a display device according to an embodiment of the present invention;
[0036] Figure 2 is a schematic diagram of a pixel driving circuit shared by even and odd row pixels according to an embodiment of the present invention;
[0037] Figure 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
[0038] Figure 4 is based on Figure 3 A schematic diagram of the display structure of the pixel driving circuit;
[0039] Figure 5 yes Figure 3 The timing diagram corresponding to the pixel driving circuit shown;
[0040] Figure 6 is a schematic diagram of the connection of different transistor types to light-emitting elements in a pixel driving circuit;
[0041] Figure 7 is a schematic diagram of the structure of a pixel driving circuit of Embodiment 2;
[0042] Figure 8 It is a working flow chart of the display device. DETAILED DESCRIPTION
[0043] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.
[0044] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.
[0045] like Figure 1 As shown, a display device according to a preferred embodiment of the present invention can reduce the use of storage capacitors by allowing pixels in odd rows and pixels in even rows to share a pixel driving circuit, thereby reducing the occupied area of the pixel driving circuit, which is beneficial to improving the pixel density (PPI) and meeting high-resolution display requirements.
[0046] Specifically, the display device includes a pixel array, a data buffer module and a timing control module.
[0047] The pixel array includes pixels in odd rows and pixels in even rows, and each pixel corresponds to a light-emitting element. In a specific implementation, each row of pixels can be numbered from 1 to N to determine the pixels in odd rows and the pixels in even rows. For example, a display screen with a resolution of 300×300 has 300 rows of pixels and 300 columns of pixels. The 300 rows of pixels can be numbered from 1 to 300, and finally the pixels in the first row can be determined as the pixels in the odd row, and the pixels in the second row can be determined as the pixels in the even row. By analogy, the pixels in the odd rows and the pixels in the even rows can be determined.
[0048] Among the pixels in odd rows and even rows, there are at least adjacent pixels in odd rows and even rows. For the adjacent pixels in odd rows and even rows, in the column direction, pixels in different rows and in the same column share a pixel driving circuit, where the pixel driving circuit includes a plurality of transistors and at least one storage capacitor, which is configured to drive the light-emitting element to emit light, so that the display device displays the corresponding image. The present invention combines the pixel driving circuits of the pixels in odd rows and even rows from being driven separately to being driven by one pixel driving circuit, that is, one pixel driving circuit can drive the light-emitting element corresponding to the pixels in odd rows to emit light, and can also drive the light-emitting element corresponding to the pixels in even rows to emit light, thereby reducing the use of the pixel driving circuit, thereby simplifying the circuit design, reducing the use of the storage capacitor, reducing the occupied area of the pixel driving circuit, and facilitating improving the integration.
[0049] The data buffer module is connected to the pixel driving circuit and is configured to store external display data and store display data corresponding to odd-numbered rows or even-numbered rows of pixels based on the external display data;
[0050] The timing control module is connected to the pixel driving circuit, and is configured to at least control the pixel driving circuit to reset in the reset phase based on the horizontal synchronization signal (HSYNC) and the vertical synchronization signal (VSYNC), control the data cache module to store the data corresponding to the odd-numbered rows or even-numbered rows of pixels in the corresponding storage capacitors in the data writing phase, and control the pixel driving circuit to drive the light-emitting elements corresponding to the odd-numbered rows or even-numbered rows of pixels to emit light in the light-emitting phase.
[0051] The display device also includes: an odd-even row switching module connected to the timing control module, and configured to switch between the odd row state and the even row state based on the control of the timing module, wherein when in the odd row state, it means that only pixels in odd rows display images, and when in the even row state, it means that only pixels in even rows display images.
[0052] When the display device of the present invention displays an image, for odd-numbered row pixels, in the reset stage, the timing control module generates a reset signal, controls the odd-even row selection module to switch to the odd-row state, and controls the storage capacitor in the pixel driving circuit to reset, such as clearing the storage capacitor in the pixel driving circuit, and controls the light-emitting element to reset, such as releasing the residual charge in the light-emitting element, etc. At the same time, in the reset stage, the timing control module controls the light-emitting element to turn off through the pixel driving circuit to ensure a clear display state.
[0053] In the data writing stage, for pixels in odd rows, the timing control module controls the data cache module to write the data corresponding to the odd row pixels into the storage capacitor of the pixel driving circuit. For pixels in even rows, the even row pixels are in an invalid state to ensure that the writing of data corresponding to the odd row pixels will not be interfered. Here, the even row pixels are in an invalid state means that the light-emitting elements corresponding to the even row pixels are in a closed state through the control of the timing control module, such as the timing control module controls the closing of the light-emitting elements by controlling the corresponding switch tubes.
[0054] In the light-emitting stage, the timing control module generates a driving signal to control the light-emitting elements corresponding to the odd-row pixels to emit light based on the data corresponding to the odd-row pixels stored in the storage capacitor.
[0055] For pixels in even rows, in the reset phase, the timing control module sends a reset signal to control the odd-even row selection module to switch the odd-even row selection module to the even row state, and reset the storage capacitor in the pixel driving circuit, such as clearing the storage capacitor in the pixel driving circuit, and reset the light-emitting element, such as releasing the residual charge in the light-emitting element, etc. At the same time, in the reset phase, the timing control module controls the light-emitting element to turn off through the pixel driving circuit to ensure a clear display state.
[0056] In the data writing stage, for pixels in even rows, the timing control module controls the data cache module to write the data corresponding to the pixels in the even rows into the storage capacitor of the pixel driving circuit. For pixels in odd rows, the pixels in the odd rows are in an invalid state to ensure that the writing of the data corresponding to the pixels in the even rows will not be interfered with. The odd row pixels being in an invalid state here means that the light-emitting elements corresponding to the odd row pixels are in a closed state through the control of the timing control module, such as the timing control module controls the closing of the light-emitting elements by controlling the corresponding switch tubes.
[0057] In the light-emitting stage, the timing control module generates a driving signal to control the light-emitting elements corresponding to the even-row pixels to emit light based on the data corresponding to the even-row pixels stored in the storage capacitor.
[0058] After the odd-row pixels and the even-row pixels are scanned row by row, a round of display update is completed, and the reset stage is further returned to re-clear the pixel driving circuit, etc., and prepare for the next round of display update. When the above display device is displaying, the odd-row pixels and the even-row pixels are alternately driven for display. In order to enable the odd-row pixels and the even-row pixels to obtain accurate driving signals, the odd-row and the even-row pixels are switched during the horizontal blanking period in each cycle of the horizontal and vertical synchronization signals.
[0059] In the present invention, by making two pixels in an odd row, an even row and in the same column share a pixel driving circuit, compared with two rows of pixels being driven by corresponding pixel driving circuits respectively, the usage of the pixel driving circuit can be reduced, thereby reducing the usage of the storage capacitor and reducing the occupied area of the pixel driving circuit, so that more pixels can be integrated within a limited chip area, thereby improving the display resolution.
[0060] In the present invention, the data buffer module includes a first buffer (Next Buffer) and a second buffer (ActiveBuffer), and a connection is established between the two. Among them, the first buffer is used to store external display data, that is, the image data to be displayed is first stored in the first buffer. The second buffer is connected to the storage capacitor in the pixel driving circuit, which is used to store the data corresponding to the odd-numbered rows or even-numbered rows of pixels based on the stored external data. In the specific implementation, the data in the first buffer transfers its internal data to the second buffer during the vertical blanking period. After the first buffer migrates the data to the second buffer, the timing control module notifies the storage capacitor corresponding to the pixel to accept the new data through an interrupt mode, and the new data is temporarily stored in the local latch corresponding to the storage capacitor, that is, the data in the second buffer is stored in the local latch corresponding to the storage capacitor. This method can ensure that the data migration is isolated from the pixel update and avoid display tearing. When the vertical synchronization signal is at the falling edge, the timing control module controls the local latch to enable, so as to store the data in the local latch into the storage capacitor, and ensure that the data update only occurs in the row scanning interval. The vertical blanking period here refers to the stage when the vertical synchronization signal is at a low level.
[0061] In the present invention, the data cache module adopts a double buffer architecture to distribute display data to the internal storage unit of the pixel (i.e., the storage capacitor in the pixel driving circuit corresponding to the pixel), which can reduce the access to the external memory and optimize the accuracy and response speed of the display control. During the display refresh process, the timing control module switches the management of the second buffer and the first buffer to ensure that the correct display data is loaded into the storage capacitor in the pixel driving circuit corresponding to each pixel. In addition, during data transmission and update, after the data is written to the first buffer, under the control of the timing control module, it can ensure that the data in the first buffer is transmitted to the second buffer as needed, and under the control of the timing module, the data in the second buffer can be written to the storage capacitor during the data writing phase to avoid display errors caused by data access delays or timing problems.
[0062] In this embodiment, the data cache module also includes a data flow management module, which is used to enable data to be efficiently and error-free transmitted from the first buffer to the second buffer, and coordinate the data update corresponding to each pixel through the timing control module. In the specific implementation, the data flow management module pre-processes the received data, including but not limited to format conversion, compression, CRC check, etc., such as external display data is input to the first buffer through a high-speed interface (such as LVDS or MIPI), and the data flow management module performs format conversion (such as RGB to grayscale mapping), compression (for repeated pixel blocks) and CRC check on the data to ensure data integrity and compatibility. Of course, the data flow management module can also perform priority scheduling for data, such as dynamically allocating storage space according to display requirements, giving priority to writing high-priority data (dynamic picture area), and delaying writing for low-priority data (static background area) to reduce bandwidth pressure. The data flow management module can also establish an error recovery mechanism. If a check error is detected (such as CRC failure), the module starts redundant data retransmission, that is, reloading data from the backup area of the first buffer, completing local repair within the next vertical synchronization signal cycle, and avoiding global refresh delays.
[0063] In the present invention, the timing control module ensures the accuracy and stability of display refresh through multi-level signal coordination and fault-tolerant design, such as the timing control module controls the writing of data and the driving of light-emitting elements based on horizontal synchronization signals and vertical synchronization signals. The horizontal synchronization signal here can at least be used to divide the frame boundary and trigger the switching of the second buffer and the first buffer; the vertical synchronization signal can at least be used to control the loading and driving of data line by line, such as each cycle of the vertical synchronization signal (VSYNC) corresponds to the writing and driving of a row of pixels. Specifically, for the writing of data, in the data cache module, when in the vertical blanking period, the data in the first buffer is transferred to the second buffer. After the migration is completed, the timing control module notifies the internal storage unit of the pixel (that is, the storage capacitor in the pixel driving circuit corresponding to the pixel) through a hardware interrupt to receive the new data, ensuring that the data migration is isolated from the pixel data update to avoid display tearing. The vertical blanking period here is the low level stage of the vertical synchronization signal.
[0064] Further, for odd-even row pixel display, in the first half of the previous vertical synchronization cycle of the vertical synchronization signal, the timing control module selects the odd row pixel for data display, and writes the data in the second buffer into the memory corresponding to the pixel, and in the second half of the cycle, the timing control module controls the pixel driving circuit corresponding to the odd row pixel to drive the light-emitting element to emit light. In the first half of the next vertical synchronization cycle of the vertical synchronization signal, the timing control module selects the even row pixel for data display, and writes the data in the second buffer into the memory corresponding to the pixel, and in the second half of the cycle, the timing control module controls the pixel driving circuit corresponding to the even row pixel to drive the light-emitting element to emit light. In this embodiment, the timing control module can select the odd and even rows through the odd and even row selection signal and the odd and even row drive signal, and control the pixel driving circuit to drive the light-emitting element to emit light. For example, when selecting the odd row pixel for display, the odd row selection signal can be set to a high level signal, and the even row selection signal can be set to a low level signal to select the odd row pixel. On the contrary, when selecting the even row pixel for display, the even selection signal can be set to a high level signal, and the odd row selection signal can be set to a low level signal. In the driving light-emitting stage, the odd-row driving signal can be activated, such as being set to a high-level signal, so that the pixel driver drives the light-emitting elements corresponding to the odd-row pixels to emit light, or the even-row driving signal can be activated, such as being set to a high-level signal, so that the pixel driver drives the light-emitting elements corresponding to the even-row pixels to emit light.
[0065] Furthermore, in order to improve the accuracy of display, compensation processing can be performed for timing errors. The timing control module sets a clock error compensation module. The clock error compensation module monitors the phase difference between the main clock and VSYNC and HSYNC in real time through a phase-locked loop (PLL) and dynamically adjusts the internal clock frequency. Of course, an elastic buffer can also be set, that is, a FIFO (first in first out) is set in the data path to absorb timing jitter and ensure strict alignment of data and drive signals.
[0066] The following takes two pixel driving circuits as an example to describe the display device of the present invention in detail. Of course, in other embodiments, pixel driving circuits of other structures can also be set according to actual needs, as long as they can drive the light-emitting elements corresponding to the odd-row pixels and the light-emitting elements corresponding to the even-row pixels to light up alternately.
[0067] Implementation
[0068] Combination Figure 2 to Figure 5As shown, the pixel driving circuit includes transistors T1 to T6, capacitors C1 to C2, and light-emitting elements L1 to L2. Among them, one electrode end of transistor T3 is connected to voltage Vccp through transistor T1, and the other electrode end is connected to the anode of light-emitting element L1 through transistor T5, and the cathode of light-emitting element L1 is connected to voltage Vcath. On the other hand, it is also connected to the anode of light-emitting element L2 through transistor T6, and the cathode of light-emitting element L2 is connected to voltage Vcath. The gate end is connected to the data signal through transistor T2; one end of capacitor C1 is connected to voltage Vccp, and the opposite end is connected to the gate end of transistor T3 through capacitor C2. Capacitor C1 is used to suppress the fluctuation of the source voltage of transistor T3, and set the gate-source voltage Vgs of transistor T3 to the threshold voltage of transistor T3. Vth, that is, C1 helps to keep the source voltage of transistor T2 stable when writing the signal voltage, and ensures that the gate-source voltage of transistor T2 can accurately reflect the threshold voltage Vth, which is crucial for correctly controlling the brightness of the organic EL element EL. The capacitor C2 is used to maintain the signal voltage Vsig written after sampling by the transistor T2, that is, C2 helps to maintain the voltage of the gate of the transistor T2 stable, and even after the signal is written, the voltage can be kept unchanged, so that the driving current remains stable, thereby controlling the brightness of the organic EL element EL; one electrode of the transistor T4 is connected between the transistor T3 and the transistor T5, and the other extreme point is connected to the voltage Vss. The gate end of transistor T1 is connected to a driving scan signal for controlling whether the light-emitting element emits light; the gate end of transistor T2 is connected to a writing scan signal for controlling whether data is written to the gate of transistor T3, and transistor T3 is used to control the current flowing through the light-emitting element according to the voltage received by the gate; the gate end of transistor T4 is connected to an automatic decay scan signal for controlling the anode of the light-emitting element to be reset to a predetermined potential based on the automatic decay signal, the gate end of transistor T5 is connected to an odd row scan signal CS0 for selecting the light-emitting element corresponding to the odd row pixel, and the gate end of transistor T6 is connected to an even row scan signal CS1 for selecting the light-emitting element corresponding to the even row pixel.
[0069] The data signal line described above is connected to the second buffer in the data buffer module. In the data writing stage, the data in the second buffer is written into the capacitor C2 corresponding to the corresponding pixel. The automatic decay scanning signal, odd row scanning signal and even row scanning signal described above are all generated by the timing control module. As shown in the figure, this is the timing control diagram corresponding to the pixel driving circuit.
[0070] In specific implementation, Figure 6As shown in the figure, the circuit structure for controlling the light-emitting element to emit light is different depending on the type of MOS tube selected. The circuit on the left uses a PMOS tube as a control switch tube for controlling the light-emitting element, and two control signals are required at this time. The circuit on the right uses a PMOS and an NMOS as control switch tubes for controlling the light-emitting element, and only one control signal is required at this time. Therefore, in the specific implementation, it can be configured according to actual needs.
[0071] The working principle of the above pixel driving circuit is further described in detail below based on the above timing control circuit diagram:
[0072] Combination Figure 8 As shown, in the initialization stage, i.e., the reset stage, all transistors are in the off state. The transistor T4 is turned on by the automatic zeroing scan signal, and at the same time, the transistors T5 and T6 are turned on by the odd-row scan signal and the even-row scan signal to release any charge remaining on the light-emitting element and ensure that the light-emitting element is in a zero potential state.
[0073] exist Qixing In the pixel data writing stage, the write scan signal controls the transistor T2 to turn on. At this time, the voltage data signal Vsig corresponding to the odd-row pixels in the second buffer can be input into the pixel driving circuit; when the data signal Vsig is written into the gate of the transistor T3 through the transistor T2, the capacitor C2 stores the voltage Vsig, and the source voltage of the transistor T2 is kept stable under the action of the capacitor C1 to ensure that the gate-source voltage Vgs of the transistor T3 is close to Vth.
[0074] In the odd-row pixel driving stage, the odd-row driving scanning signal controls the transistor T1 to turn on, during which the source potential of the transistor T3 becomes the power supply voltage Vccp. At this time, the capacitors C1 and C2 continue to maintain their original states, and the odd-row scanning signal further controls the transistor T5 to turn on, and then the light-emitting element L1 corresponding to the odd-row pixel emits light.
[0075] In the automatic zeroing stage, when the light emitting elements corresponding to the odd-row pixels emit light, the automatic zeroing scanning signal takes effect to reset, that is, when the light emitting elements corresponding to the odd-row pixels emit light, the automatic zeroing scanning signal turns on the transistor T4. At the same time, the odd-row scanning signal and the even-row scanning signal turn on the transistors T5 and T6 to release any charge remaining on the light emitting elements, ensuring that the light emitting elements are in a zero potential state, that is, the residual charge is released to the ground through Vss to avoid the influence of the residual charge.
[0076] In the even-row pixel data writing stage, the write scan signal controls the transistor T2 to turn on. At this time, the voltage data signal Vsig corresponding to the even-row pixels in the second buffer can be input into the pixel driving circuit; when the data signal Vsig is written into the gate of the transistor T3 through the transistor T2, the capacitor C2 stores the voltage Vsig, and the source voltage of the transistor T2 is kept stable under the action of the capacitor C1 to ensure that the gate-source voltage Vgs of the transistor T3 is close to Vth.
[0077] exist Odd line In the pixel driving stage, the even-row scanning signal controls the transistor T2 to turn on, during which the source potential of the transistor T3 becomes the power supply voltage Vccp. At this time, the capacitors C1 and C2 continue to maintain their original state, and the even-row scanning signal further controls the transistor T6 to turn on, and then the light-emitting element L2 corresponding to the even-row pixel emits light.
[0078] In the automatic zeroing stage, that is, the reset stage, when the light-emitting elements corresponding to the even-row pixels emit light, the automatic zeroing scan signal takes effect to reset. That is to say, when the light-emitting elements corresponding to the even-row pixels emit light, the automatic zeroing scan signal turns on the transistor T4, and at the same time, the odd-row scan signal and the even-row scan signal turn on the transistor T5 and the transistor T6 to release any charge remaining on the light-emitting element, ensuring that the light-emitting element is in a zero potential state, that is, the residual charge is released to the ground through Vss to avoid the influence of the residual charge.
[0079] Repeat the above process to fully display the image.
[0080] Embodiment 2
[0081] like Figure 7 As shown, the pixel driving circuit includes transistors T1-T8, capacitor C1, and light-emitting elements L1-L2. Among them, one electrode end of transistor T8 is connected to the anode end of light-emitting element L1 through transistor T5, the other electrode end is connected to the power supply VDD through transistor T4, and the gate end is connected to the data end Vint1 through transistor T1, wherein the gate end of transistor T8 forms node N1 when connected to transistor T1, one electrode end forms node N2 when connected to transistor T4, and the other electrode end forms node N3 when connected to transistor T5, node N1 is connected to power supply VDD through capacitor C1, node N1 is also connected to node N3 through transistor T2, node N2 is connected to data Vdata through transistor T3, node N3 is further connected to data segment Vint2 through transistor T6, and node N3 forms node N4 when connected to transistor T6, and node N4 is further connected to the anode end of light-emitting element L2 through transistor T7; cathode ends of light-emitting elements L1 and L2 are both connected to power supply Vee.
[0082] Among them, the gate end of transistor T1 is connected to the scan signal Scan1, the gate ends of transistors T2 and T3 are both connected to the scan signal Scan2, the gate end of transistor T4 is connected to the drive signal EM1, the gate end of transistor T5 is connected to the odd-row scan signal CS0, the gate end of transistor T6 is connected to the scan signal Scan3, and the gate end of transistor T7 is connected to the even-row scan signal CS1.
[0083] The working principle of the above pixel driving circuit is further described in detail below:
[0084] Combination Figure 8 As shown, in the reset stage, the scan signal Scan1 controls the transistor T1 to be turned on to reset the gate of the transistor T8, and the voltage of the node N1 is Vint1 at this time; the drive signal EM1 controls the transistor T4 to be turned on to reset the electrode end of the transistor T8, and the potential of the node N2 is VDD at this time; the scan signal Scan3 controls the transistor T6 to be turned on to reset the anodes of the light-emitting elements L1 and L2, and the potentials of the nodes N3 and N4 are Vint2 at this time; the transistor T3, the transistor T5, and the transistor T7 are all in the cut-off state, and the light-emitting elements L1 and L2 do not emit light.
[0085] In the odd-row pixel data writing stage, the scan signal Scan2 controls the transistors T2 and T3 to turn on. When the transistor T3 is turned on, the data signal can be written into the first electrode of the transistor T8. At this time, the potential of the node N2 is Vdata; when the transistor T2 is turned on, the potential of the node N1 is charged to Vdata-|Vth|. The sixth switch transistor T6 is turned on to reset the anode of the light-emitting element, and the potential of the third node N3 is Vint2. Under the control of the scan signal Scan1, the transistor T1 is turned off, and under the control of the drive signal EM1, the transistor T4 is turned off. At the same time, under the control of the scan signals CS0 and CS1, respectively, the transistors T5 and T7 are turned off, and the light-emitting element does not emit light.
[0086] In the odd-row pixel light-emitting stage, the driving signal EM1 controls the transistor T4 to turn on, so as to apply the voltage of the power supply VDD to the node N2. At this time, the potential of the node N2 is VDD. At this time, the gate-source voltage Vsg of the transistor is VDD-Vdata+|Vth|, and the driving current I of the transistor T8 is K(Vsg-|Vth|). 2 =K(VDD-Vdata) 2 Under the control of the odd-row scan signal CS0, the transistor T5 is turned on so that the driving current of the transistor drives the light-emitting element L1 to work and emit light.
[0087] In the reset stage, the scan signal Scan1 controls the transistor T1 to turn on to reset the gate of the transistor T8, and the voltage of the node N1 is Vint1 at this time; the drive signal EM1 controls the transistor T4 to turn on to reset the electrode end of the transistor T8, and the potential of the node N2 is VDD at this time; the scan signal Scan3 controls the transistor T6 to turn on to reset the anodes of the light-emitting elements L1 and L2, and the potentials of the nodes N3 and N4 are Vint2 at this time; the transistor diagram, the transistor T3, the transistor T5, and the transistor T7 are all in the cut-off state, and the light-emitting elements L1 and L2 do not emit light.
[0088] In the even-row pixel data writing stage, the scan signal Scan2 controls the transistors T2 and T3 to turn on. When the transistor T3 is turned on, the data signal can be written into the first electrode of the transistor T8. At this time, the potential of the node N2 is Vdata; when the transistor T2 is turned on, the potential of the node N1 is charged to Vdata-|Vth|. The sixth switch transistor T6 is turned on to reset the anode of the light-emitting element, and the potential of the third node N3 is Vint2. Under the control of the scan signal Scan1, the transistor T1 is turned off, and under the control of the drive signal EM1, the transistor T4 is turned off. At the same time, under the control of the scan signals CS0 and CS1, respectively, the transistors T5 and T7 are turned off, and the light-emitting element does not emit light.
[0089] In the even-row pixel light-emitting stage, the driving signal EM1 controls the transistor T4 to turn on, so as to apply the voltage of the power supply VDD to the node N2. At this time, the potential of the node N2 is VDD. At this time, the gate-source voltage Vsg of the transistor is VDD-Vdata+|Vth|, and the driving current I of the transistor T8 is K(Vsg-|Vth|). 2 =K(VDD-Vdata) 2 Under the control of the even line scanning signal CS1, the transistor T7 is turned on so that the driving current of the transistor drives the light emitting element L2 to work and emit light.
[0090] Combination Figure 8 As shown, the present invention also discloses a display method based on the above-mentioned display device. The method comprises the following steps:
[0091] When displaying an image, for odd-numbered row pixels, in the reset phase, the timing control module generates a reset signal, controls the odd-even row selection module to switch to the odd-row state, and controls the storage capacitor in the pixel driving circuit to reset, such as clearing the storage capacitor in the pixel driving circuit, and controls the light-emitting element to reset, such as releasing the residual charge in the light-emitting element, etc. At the same time, in the reset phase, the timing control module controls the light-emitting element to turn off through the pixel driving circuit to ensure a clear display state.
[0092] In the data writing stage, for pixels in odd rows, the timing control module controls the data cache module to write the data corresponding to the pixels in odd rows into the storage capacitor of the pixel driving circuit. For pixels in even rows, the pixels in even rows are in an invalid state to ensure that the writing of data corresponding to the pixels in odd rows will not be interfered.
[0093] In the light-emitting stage, the timing control module generates a driving signal to control the light-emitting elements corresponding to the odd-row pixels to emit light based on the data corresponding to the odd-row pixels stored in the storage capacitor.
[0094] For pixels in even rows, in the reset phase, the timing control module sends a reset signal to control the odd-even row selection module to switch the odd-even row selection module to the even row state, and reset the storage capacitor in the pixel driving circuit, such as clearing the storage capacitor in the pixel driving circuit, and reset the light-emitting element, such as releasing the residual charge in the light-emitting element, etc. At the same time, in the reset phase, the timing control module controls the light-emitting element to turn off through the pixel driving circuit to ensure a clear display state.
[0095] In the data writing stage, for pixels in even rows, the timing control module controls the data cache module to write the data corresponding to the pixels in even rows into the storage capacitor of the pixel driving circuit. For pixels in odd rows, the pixels in even rows are in an invalid state to ensure that the writing of data corresponding to the pixels in odd rows will not be interfered.
[0096] In the light-emitting stage, the timing control module generates a driving signal to control the light-emitting elements corresponding to the even-row pixels to emit light based on the data corresponding to the even-row pixels stored in the storage capacitor.
[0097] By repeating the above process, the image display device can realize image display.
[0098] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0099] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0100] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0102] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.
Claims
1. A display device, characterized in that: include: A pixel array, comprising pixels in odd rows and pixels in even rows, each pixel corresponding to a light emitting element, at least adjacent pixels in odd rows and pixels in even rows, two pixels in the same column of the adjacent pixels in odd rows and pixels in even rows share a pixel driving circuit, the pixel driving circuit comprising a plurality of transistors and at least one storage capacitor, the pixel driving circuit being configured to drive the light emitting element to emit light based on data stored in the storage capacitor; A data cache module, used to store external display data and display data corresponding to odd-numbered rows or even-numbered rows of pixels; The timing control module is used to control at least the pixel driving circuit to reset in the reset phase based on the horizontal and vertical synchronization signals, control the data cache module to store the data corresponding to the odd-numbered or even-numbered rows of pixels in the corresponding storage capacitor in the data writing phase, and control the pixel driving circuit to drive the light-emitting elements corresponding to the odd-numbered or even-numbered rows of pixels to emit light in the light-emitting phase; wherein, The pixels in odd-numbered rows and even-numbered rows are driven and displayed alternately.
2. The display device according to claim 1, wherein: The data cache module includes A first buffer, used for storing external display data; The second buffer is connected to the first buffer and is used to store pixel data of odd-numbered rows or even-numbered rows; wherein, The first buffer transfers the data therein to the second buffer during a vertical blanking period, which is a low level phase of a horizontal synchronization signal.
3. The display device according to claim 2, wherein: After the first buffer transfers the data to the second buffer, the timing control module notifies the storage capacitor corresponding to the pixel to receive new data through an interruption method, and the new data is temporarily stored in the local latch corresponding to the storage capacitor.
4. The display device according to claim 3, characterized in that When the vertical synchronization signal is at a falling edge, the timing control module controls the local latch to be enabled, so as to store the data in the local latch into the storage capacitor.
5. The display device according to claim 1, wherein: The pixels of the odd-numbered rows and the pixels of the even-numbered rows are alternately driven to display the display, including In each cycle of the horizontal and vertical synchronization signals, odd and even lines are switched during the horizontal blanking period.
6. The display device according to claim 1, wherein: The timing control module controls the display of pixels in odd rows in the current vertical synchronization cycle, and controls the display of pixels in even rows in the next vertical synchronization cycle, wherein the timing control module controls the data cache module to store the data corresponding to the pixels in odd rows or even rows in the corresponding storage capacitors in the first half of each cycle, and controls the corresponding pixel driving circuit to drive the light-emitting elements of the corresponding pixel rows to emit light in the second half of each cycle.
7. The display device according to claim 1, wherein: The data buffer module starts redundant data retransmission in the next cycle of the vertical synchronization signal when a data verification error is detected.
8. The display device according to claim 1, wherein: It also includes a clock error compensation module, which monitors the phase difference between the main clock and the horizontal and vertical synchronization signals in real time through a phase-locked loop and dynamically adjusts the internal clock frequency based on the phase difference.
9. The display device according to claim 1, wherein: It also includes an odd-even row selection module configured to switch between an odd row state and an even row state, wherein: In the odd row state, only odd-numbered rows of pixels are used to display the image; In the even row state, only the even-numbered rows of pixels are used to display the image.
10. A display method based on the display device according to any one of claims 1 to 8, characterized in that: The steps include: S1, in the reset stage, the timing control module controls the pixel driving circuit to reset; S2, in the data writing stage, the timing control module controls the data cache module to write the data corresponding to the odd-row pixels into the storage capacitor of the pixel driving circuit; S3, in the light-emitting stage, the timing control module generates a driving signal, and controls the light-emitting elements corresponding to the odd-row pixels to emit light based on the data corresponding to the odd-row pixels stored in the storage capacitor; S4, in the reset stage, the timing control module controls the pixel driving circuit to reset; S5, in the data writing stage, the timing control module controls the data cache module to write the data corresponding to the even-row pixels into the storage capacitor of the pixel driving circuit; S6, in the light-emitting stage, the timing control module generates a driving signal, and controls the light-emitting elements corresponding to the even-row pixels to emit light based on the data corresponding to the even-row pixels stored in the storage capacitor; S7, repeat S1 to S6.