Display device

Abstract

A display device is provided. The display device employs a first scan signal having an on-level that determines when a pixel receives a data voltage and a second scan signal having an on-level that determines a time for initializing an anode voltage of a light emitting element in the pixel. An active period in the frame period is from a time at which the pixel receives an initial first scan signal at an on level to a time at which the pixel receives a last first scan signal at the on level. The blanking period in the frame period is from a time when the pixel receives the last first scan signal at the on level to a time when the pixel receives the initial first scan signal at the on level during the next frame period. The blanking period is at least as long as a period in which each of the pixels receives the second scan signal at the on level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0158472 filed in the Korean Intellectual Property Office on November 15, 2023, Korean Patent Application No. 10-2023-0159290 filed in the Korean Intellectual Property Office on November 16, 2023, and Korean Patent Application No. 10-2024-0020514 filed in the Korean Intellectual Property Office on February 13, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] Display devices provide a connection medium between users and information, and have become increasingly important with the development of information technology. Some examples of display devices currently used include liquid crystal display devices and organic light emitting diode display devices. Such display devices can use multiple pixels to display images. These pixels can receive individual voltages depending on the image being displayed, and also receive a common voltage. The load of the element capacitively coupled to the common voltage in the pixel can change over time, which may cause the voltage level of the common voltage to change. When the voltage level of the common voltage applied to each pixel changes, the brightness of the pixel may be affected, and as a result, the image quality may be impaired. Summary of the invention

[0005] The present disclosure relates to a display device capable of maintaining uniform display quality.

[0006] A display device according to an embodiment of the present disclosure may have pixels, a first scan driver, and a second scan driver, the pixels including a light-emitting element that emits light with a brightness based on a received data voltage, the first scan driver providing a first scan signal at an on-level that determines the time when the pixel receives the data voltage, and the second scan driver providing a second scan signal at an on-level that determines the time for initializing the anode voltage of the light-emitting element, wherein each frame period includes an effective period and a blanking period, the effective period being a period from the time when the pixel receives an initial first scan signal at an on-level to the time when the pixel receives a last first scan signal at an on-level, the blanking period being a period from the time when the pixel receives the last first scan signal at an on-level to the time when the pixel receives an initial first scan signal at an on-level for a next frame period, and the length of the blanking period is greater than or equal to a period in which each of the pixels receives the second scan signal at an on-level.

[0007] The length of the blanking period may be an integer multiple of a period in which each of the pixels receives the second scan signal at an on level.

[0008] Each of the pixels may receive the first scan signal at an on level once during one frame period, each of the pixels may receive the second scan signal at an on level N times during one frame period, and N may be an integer greater than 3.

[0009] The length of the blank period may be (N-3) times of a period in which each of the pixels receives the second scan signal at an on level.

[0010] N may be 4, and the length of the blank period may be one time the period in which each of the pixels receives the second scan signal at the on level.

[0011] N may be 5, and the length of the blank period may be twice as long as a period in which each of the pixels receives the second scan signal at an on level.

[0012] The number of pixels simultaneously receiving the second scan signal at the on level may remain constant throughout the entire frame period.

[0013] A display device according to an embodiment of the present disclosure may include pixels, a first scan driver, and a second scan driver, the pixels including a light-emitting element that emits light with a brightness based on a received data voltage, the first scan driver providing a first scan signal at an on-level that determines the time when the pixel receives the data voltage, and the second scan driver providing a second scan signal at an on-level that determines the time for initializing an anode voltage of the light-emitting element, wherein each frame period includes an effective period and a blanking period, the effective period being a period from the time when the pixel receives an initial first scan signal at an on-level to the time when the pixel receives a last first scan signal at an on-level, the blanking period being a period from the time when the pixel receives the last first scan signal at an on-level to the time when the pixel receives an initial first scan signal at an on-level for a next frame period, and the length of the blanking period is greater than or equal to half of the corresponding frame period.

[0014] For each of the pixels, each of the frame periods may include an address scanning period and a self-scanning period, during which each of the pixels may receive a first scanning signal at an on-level and a second scanning signal at an on-level, and during the self-scanning period, each of the pixels may not receive the first scanning signal at the on-level and may receive the second scanning signal at the on-level.

[0015] The second scan signal at the on level received by the pixels located in the last pixel row among the pixels during the self-scan period may not overlap with the first scan signal at the on level received by the pixels located in the first pixel row among the pixels during the address scan period.

[0016] A display device according to an embodiment of the present disclosure may include pixels, a first scan driver, and a second scan driver, the pixels including a light-emitting element that emits light with a brightness based on a received data voltage, the first scan driver providing a first scan signal at an on-level that determines a time when the pixel receives the data voltage, and the second scan driver providing a second scan signal at an on-level that determines a time for initializing an anode voltage of the light-emitting element, wherein, for each of the pixels, each frame period includes an address scan period and a self-scan period, during the address scan period, each of the pixels receives the first scan signal at an on-level and the second scan signal at an on-level, and during the self-scan period, each of the pixels does not receive the first scan signal at an on-level and receives the second scan signal at an on-level, during each of the frame periods, the self-scan period of a first pixel row starts before the address scan period of a last pixel row ends, and during each of the frame periods, the second scan signal at an on-level supplied during the address scan period of the pixel does not overlap with the second scan signal at an on-level supplied during the self-scan period of the pixel.

[0017] During each of the frame periods, the second scan signals at the on level supplied during the address scan period of the pixels may overlap each other in units of M adjacent pixel rows, and M may be an integer greater than 1.

[0018] During each of the frame periods, the second scanning signals at the on level supplied during the self-scan period of the pixels may overlap with each other in units of M adjacent pixel rows.

[0019] The width of the second scan signal at the on level may be P horizontal periods, P may be an integer greater than 0, and M may be 2*P.

[0020] P can be 4, and M can be 8.

[0021] P can be 3 and M can be 6.

[0022] P can be 2, and M can be 4.

[0023] During each of the frame periods, each of the second scanning signals at the on-level supplied during the address scanning period of the pixel may include Q pulses, the first pulse among the Q pulses supplied to the first pixel row may overlap with the R pulses supplied to other pixel rows, and each of Q and R may be an integer greater than 0.

[0024] The second pulse among the Q pulses supplied to the first pixel row may overlap with the S pulses supplied to the other pixel rows, and S may be R+(R+1).

[0025] The third pulse among the Q pulses supplied to the first pixel row may overlap with the T pulses supplied to the other pixel rows, and T may be S+(R+1).

[0026] A display device according to some embodiments disclosed herein may maintain uniform display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0028] Figure 2 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0029] Figure 3A and Figure 3B Different display frequencies according to embodiments of the present disclosure are shown.

[0030] Figure 4 is a timing diagram illustrating an address scanning period according to an embodiment of the present disclosure.

[0031] Figure 5 is a timing diagram illustrating a self-scan period according to an embodiment of the present disclosure.

[0032] Figure 6 is a timing diagram illustrating a driving method of a display device according to an embodiment of the present disclosure.

[0033] Figure 7 Shows the use of Figure 6 The image displayed by the driving method.

[0034] Figure 8 is Figure 7 Timing diagram of selected signals used during display of an image.

[0035] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16is a timing diagram of a driving method according to an embodiment of the present disclosure.

[0036] Fig.17 is a block diagram of a display device according to an embodiment of the present disclosure.

[0037] Fig.18 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0038] Fig.19 is a timing diagram of an address scanning period according to an embodiment of the present disclosure.

[0039] Fig. 20 is a timing diagram of a self-scan period according to an embodiment of the present disclosure.

[0040] Fig.21 and Fig. 22 is a timing diagram of a driving method according to other embodiments of the present disclosure.

[0041] Fig.23 is a circuit diagram of a pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0043] In order to clearly illustrate various aspects of the present disclosure, elements that are not essential to the description may be omitted. Throughout the specification and the drawings, the same reference numerals may be used to indicate the same or similar constituent elements.

[0044] The size and thickness of the elements shown in the drawings may be adjusted for better understanding and convenience of description or illustration. Therefore, the present disclosure is not necessarily limited to the size or ratio shown in the drawings. In the drawings, the size of layers and regions may be exaggerated for clarity of illustration.

[0045] The expression "same" in the description may mean "substantially the same". That is, the elements referred to as the same may be the same to the extent that a person with ordinary knowledge would understand them to be the same or equivalent. In the case where a person of ordinary skill in the art understands this meaning, other expressions may similarly omit "substantially".

[0046] Figure 1 is a block diagram of a display device 10 according to an embodiment of the present disclosure.

[0047] Reference Figure 1 The display device 10 may include a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 , and an emission driver 15 .

[0048] The timing controller 11 may receive data indicating a grayscale value representing an input image (or input frame). The grayscale value of a pixel may include a first color grayscale value, a second color grayscale value, and a third color grayscale value. The first color grayscale value may indicate the intensity of the first color, the second color grayscale value may indicate the intensity of the second color, and the third color grayscale value may indicate the intensity of the third color.

[0049] The timing controller 11 may additionally receive one or more control signals for an image. These control signals may include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal. The vertical synchronization signal may include a plurality of pulses, and the time at which each pulse occurs may indicate when a frame period ends and when a new frame period begins. The interval between adjacent pulses in the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include a plurality of pulses, and the time at which each pulse occurs may indicate when a horizontal period ends and when a new horizontal period begins. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may have an enable level for certain horizontal periods and a disable level for other periods. The data enable signal at the enable level may indicate that a color grayscale value is supplied during the corresponding horizontal period.

[0050] The timing controller 11 may provide the grayscale value rendered or corrected to meet the specification of the display device 10 to the data driver 12. In addition, the timing controller 11 may provide a clock signal, a scan start signal, etc. to the scan driver 13. The timing controller 11 may provide a clock signal, a light emission stop signal, etc. to the emission driver 15.

[0051] The data driver 12 may generate data voltages to be provided to the data lines DL1, ..., DLj, ..., DLq using the grayscale values ​​and control signals from the timing controller 11, where q may be an integer greater than 1, and j may be an integer greater than 0 and less than q. For example, the data driver 12 may sample the grayscale values ​​using the clock signal, and may apply data voltages corresponding to the sampled grayscale values ​​to the data lines in units of pixel rows.

[0052] The scan driver 13 may include a first scan driver 13GW, a second scan driver 13GB, a third scan driver 13GI, and a fourth scan driver 13GC. The first scan driver 13GW may provide a first scan signal to the first scan lines GW1, ..., GWi, ..., and GWp. The second scan driver 13GB may provide a second scan signal to the second scan lines GB1, ..., GBi, ..., and GBp. The third scan driver 13GI may provide a third scan signal to the third scan lines GI1, ..., GIi, ..., and GIp. The fourth scan driver 13GC may provide a fourth scan signal to the fourth scan lines GC1, ..., GCi, ..., and GCp. In this article, p may be an integer greater than 1, and i may be an integer greater than 0 and less than p.

[0053] For example, the first scan driver 13GW may receive at least one scan clock signal and a scan start signal from the timing controller 11, and may generate a first scan signal to be provided to the first scan lines GW1 to GWp. The first scan driver 13GW may sequentially provide the first scan signal having an on-level pulse to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may be configured in the form of a shift register, and may generate the first scan signal in a manner of sequentially sending a scan start signal of an on-level pulse type to a next scan stage according to the scan clock signal.

[0054] Each of the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC may be configured similarly to the first scan driver 13GW, and thus repeated descriptions will be omitted. Depending on the implementation, at least some of the first scan driver 13GW, the second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC may be integrated or combined. For example, when the polarity and width of the pulses are the same for two or more scan drivers, the scan drivers may be integrated or combined. For example, referring to the further description below Figure 4 Since the polarity and width of the on-level pulse applied to the third scan line GIi at time t2a are the same as the polarity and width of the on-level pulse applied to the fourth scan line GCi at time t3a, the third scan driver 13GI and the fourth scan driver 13GC can be integrated or combined into one driver circuit.

[0055] The emission driver 15 may receive at least one light emission clock signal and a light emission stop signal from the timing controller 11 and may generate a light emission signal to be provided to the light emission lines EM1, ..., EMi, ..., and EMp. The emission driver 15 may sequentially provide a light emission signal having an off-level pulse to the light emission lines EM1 to EMp. For example, the emission driver 15 may be configured in the form of a shift register and may generate a light emission signal in a manner that sequentially sends a light emission stop signal as an off-level pulse type to the next light emission stage in accordance with the control of the light emission clock signal.

[0056] exist Figure 1 In the example of, the number of each of the first scan lines GW1 to GWp, the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the light emission lines EM1 to EMp may be p as shown. However, in an embodiment, the number of at least one of the second scan lines GB1 to GBp, the third scan lines GI1 to GIp, the fourth scan lines GC1 to GCp, and the light emission lines EM1 to EMp may be p / 2 or less. For example, two adjacent pixel rows may share one second scan line. Similarly, two adjacent pixel rows may share one third scan line, fourth scan line, or light emission line. The same pixel row refers to pixels connected to the same first scan line.

[0057] The pixel unit 14 includes a plurality of pixels PXij. Each pixel PXij may be connected to a corresponding data line DLj, scan lines GWi, GBi, GIi, and GCi, and a light emission line EMi. Each pixel PXij may include a light emitting element that emits light based on a received data voltage.

[0058] The pixel unit 14 may include a first pixel emitting light of a first color, a second pixel emitting light of a second color, and a third pixel emitting light of a third color. The first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue, the second color may be one color other than the first color among red, green, and blue, and the third color may be the remaining colors other than the first and second colors among red, green, and blue. Magenta, cyan, and yellow may be used as the first to third colors instead of red, green, and blue.

[0059] The pixel unit 14 may have various layouts, such as a diamond RGB stripe, S stripe, real RGB, normal wait.

[0060] Figure 2 is a circuit diagram of a pixel PXij according to an embodiment of the present disclosure.

[0061] Reference Figure 2 , the pixel PXij may include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC may include transistors T1, T2, T3, T4, T5, T6, T7 and T8 and a storage capacitor Cst.

[0062] The pixel PXij may be arranged in the i-th pixel row and the j-th pixel column of the pixel array or unit. The pixel PXij may be a first pixel for representing a first color. The second pixel for representing a second color and the third pixel for representing a third color may include the same circuit as the circuit in the first pixel.

[0063] The P-type transistor may be a polycrystalline silicon semiconductor transistor. In a polycrystalline silicon semiconductor transistor, the channel of the active layer may include a polycrystalline silicon semiconductor. For example, the polycrystalline silicon semiconductor transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor. The polycrystalline silicon semiconductor transistor has high electron mobility and therefore has fast driving characteristics.

[0064] The N-type transistor may be an oxide semiconductor transistor. In the oxide semiconductor transistor, the channel of the active layer may include an oxide semiconductor. For example, the oxide transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. The oxide semiconductor transistor generally has a charge mobility lower than that of a polycrystalline silicon semiconductor transistor. Therefore, the amount of leakage current generated in the off state of the oxide semiconductor transistor may be less than the amount of leakage current generated in the off state of the polycrystalline silicon semiconductor transistor.

[0065] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may be a P-type transistor. According to an embodiment, the first transistor T1 may include a sub-gate electrode (or a back gate electrode or a body electrode), and the sub-gate electrode may receive a first power supply voltage ELVDD.

[0066] The second transistor T2 may have a gate electrode connected to the first scan line GWi, a first electrode connected to the data line DLj, and a second electrode connected to the second node N2. The second transistor T2 may be a switching transistor. The second transistor T2 may be a P-type transistor.

[0067] The first scan driver 13GW may provide a first scan signal at an on level that determines when the pixel PXij receives the data voltage. For example, the second transistor T2 may receive the first scan signal at an on level and be turned on, so that the second transistor T2 applies the data voltage from the data line DLj to the second node N2.

[0068] The third transistor T3 may have a gate electrode connected to the fourth scan line GCi, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be a diode-connected transistor that makes the first transistor T1 diode-connected when turned on. The third transistor T3 may be an N-type transistor.

[0069] The fourth transistor T4 has a gate electrode connected to the third scan line GIi, a first electrode connected to the first node N1, and a second electrode receiving the first initialization voltage VINT. The fourth transistor T4 may be a gate initialization transistor. The fourth transistor T4 may be an N-type transistor.

[0070] The fifth transistor T5 may have a gate electrode connected to the light emission line EMi, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may be a first light emission control transistor. The fifth transistor T5 may be a P-type transistor.

[0071] The sixth transistor T6 may have a gate electrode connected to the light emission line EMi, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 may be a second light emission control transistor. The sixth transistor T6 may be a P-type transistor.

[0072] The seventh transistor T7 may have a gate electrode connected to the second scan line GBi, a first electrode receiving the second initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may be an anode initialization transistor. The seventh transistor T7 may be a P-type transistor.

[0073] The second scan driver 13GB may provide a second scan signal at an on-level that determines the time for initializing the anode voltage of the light emitting element LD. For example, the seventh transistor T7 may receive the second scan signal at an on-level and be turned on, so that the second initialization voltage VAINT is applied to the anode of the light emitting element LD. As a result, the anode voltage of the light emitting element LD may be initialized to the second initialization voltage VAINT.

[0074] The eighth transistor T8 may have a gate electrode connected to the second scan line GBi, a first electrode receiving the bias voltage VOBS, and a second electrode connected to the second node N2. The eighth transistor T8 may be a bias transistor. The eighth transistor T8 may be a P-type transistor.

[0075] The storage capacitor Cst may have a first electrode receiving the first power voltage ELVDD and a second electrode connected to the first node N1.

[0076] The anode of the light emitting element LD may be connected to the fourth node N4, and the cathode thereof may receive the second power supply voltage ELVSS. The light emitting element LD may emit light of one of the first color, the second color, and the third color. The light emitting element LD may be a light emitting diode. The light emitting element LD may include an organic light emitting diode, an inorganic light emitting diode, a quantum dot / well light emitting diode, or the like. In an embodiment, each pixel may include only one light emitting element LD, but in some other embodiments, each pixel may include a plurality of light emitting elements. The plurality of light emitting elements in a pixel may be connected in series, in parallel, in series-parallel, or the like.

[0077] Figure 3A and Figure 3B Different display frequencies that can be supported by a display device according to an embodiment of the present disclosure are shown.

[0078] The display device 10 may support a variable refresh rate (VRR). The refresh rate may be the frequency at which a data voltage is written to each pixel PXij, and may also be referred to as a screen scan rate or a screen refresh rate, and may indicate the number of video frames played per second.

[0079] For example, the pixel unit 14 of the display device 10 may display an image at a first frequency AHz in a first mode (see Figure 3A ), and can display images in a second mode at a second frequency BHz less than the first frequency AHz (see Figure 3B ). For example, in the first mode, for each pixel PXij, each frame period 1F may include one address scanning period AS and one self-scanning period SS. For example, in the second mode, for each pixel PXij, each frame period 1F may include one address scanning period AS and multiple self-scanning periods SS. As the second frequency BHz becomes smaller, the number of self-scanning periods SS included in one frame period 1F may increase. In another example, in the third mode, for each pixel PXij, each frame period 1F may include only one address scanning period AS without including a self-scanning period SS.

[0080] The address scanning period AS is a period for writing a data voltage into the pixel PXij. The address scanning period AS may be referred to as a data programming period in which the pixel PXij receives a data voltage from the data line DLj.

[0081] The self-scanning period SS is not a period for writing a data voltage into a pixel PXij. During the light emission period of the self-scanning period SS, the pixel PXij may emit light using a data voltage written in a previous address scanning period AS. The length or duration of the self-scanning period SS may be the same as the length or duration of the address scanning period AS.

[0082] Figure 4is a timing diagram showing signals applied during an address scan period according to an embodiment of the present disclosure. Figure 4 When, refer to Figure 2 Pixel PXij.

[0083] At time t1a, a light emission signal at an off level (high level) may be applied to the light emission line EMi so that the fifth transistor T5 and the sixth transistor T6 may be turned off, and the pixel PXij may be in a non-light emitting state.

[0084] At time t2a, a third scan signal at a turn-on level (high level) may be applied to the third scan line GIi, so that the fourth transistor T4 may be turned on. Therefore, a first initialization voltage VINT may be applied to the first node N1. The first initialization voltage VINT may be a sufficiently low voltage and may bias the first transistor T1 to turn on.

[0085] At time t3a, a fourth scan signal at a turn-on level (high level) may be applied to the fourth scan line GCi so that the third transistor T3 may be turned on. Therefore, the first transistor T1 may be in a diode connection state in which the drain electrode and the gate electrode of the first transistor T1 are connected.

[0086] At time t4a, a first scan signal at a turn-on level (low level) may be applied to the first scan line GWi, so that the second transistor T2 may be turned on. Therefore, the data voltage of the data line DLj may be applied to the first node N1 through the turned-on second transistor T2, the first transistor T1, and the third transistor T3. At this time, the voltage of the first node N1 may be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst may maintain the difference between the first power supply voltage ELVDD and the compensation voltage.

[0087] At time t5a, a second scan signal at a turn-on level (low level) may be applied to the second scan line GBi, so that the seventh transistor T7 and the eighth transistor T8 may be turned on. As the seventh transistor T7 is turned on, the second initialization voltage VAINT may be applied to the anode of the light emitting element LD, and the light emitting element LD may be initialized to a charge amount corresponding to a voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light emitting element LD may be promoted.

[0088] As the eighth transistor T8 is turned on at time t5a, the voltage of the second node N2 can be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1 instead of the data voltage of the previous frame period, hysteresis can be prevented and the on bias state can be guaranteed.

[0089] At time t6a, a light emission signal at a turn-on level (low level) may be applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned on. Therefore, the drive current may flow from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD. The amount of the drive current may depend on the voltage maintained in the storage capacitor Cst. The light emitting element LD may emit light having a brightness corresponding to the amount of the drive current. The light emitting element LD may emit light until the light emission signal at the turn-off level is applied to the light emission line EMi.

[0090] Figure 5 is a timing diagram showing a self-scan period according to an embodiment of the present disclosure. Figure 5 When, refer to Figure 2 Pixel PXij.

[0091] At time t7a, a light emission signal at an off level (high level) may be applied to the light emission line EMi so that the fifth transistor T5 and the sixth transistor T6 may be turned off, and the pixel PXij may be in a non-light emitting state.

[0092] During the period t7a to t8a, the scan signal at the off level may be maintained in the first scan line GWi, the third scan line GIi, and the fourth scan line GCi. Therefore, the voltage of the first node N1 does not vary.

[0093] At time t8a, a second scan signal at a turn-on level (low level) may be applied to the second scan line GBi, so that the seventh transistor T7 and the eighth transistor T8 may be turned on. As the seventh transistor T7 is turned on, the second initialization voltage VAINT may be applied to the anode of the light emitting element LD, and the light emitting element LD may be initialized to a charge amount corresponding to a voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. Therefore, low grayscale expression of the light emitting element LD may be promoted.

[0094] As the eighth transistor T8 is turned on, the voltage of the second node N2 may be set to the bias voltage VOBS. Therefore, since the bias voltage VOBS is applied to the source electrode of the first transistor T1, hysteresis may be prevented and a conduction bias state may be ensured.

[0095] At time t9a, a light emission signal at a conduction level (low level) may be applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 may be turned on. Therefore, the drive current flows from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6 and the light emitting element LD. The amount of the drive current may depend on the voltage maintained in the storage capacitor Cst. Since the voltage of the first node N1 recorded during the address scanning period AS is maintained during the self-scanning period SS, the brightness of the pixel PXij in the self-scanning period SS may be the same as the brightness of the pixel PXij in the address scanning period AS.

[0096] Figure 6 is a timing diagram of a method for driving a display device according to an embodiment of the present disclosure. Figure 7 Shown according to Figure 6 The driving method displays the image, and Figure 8 : is a timing chart showing the difference of the signal corresponding to the change of the second initialization voltage VAINT.

[0097] Reference Figure 6 Each frame period FRMP1, FRMP2, ... may include an effective period and a blanking period. For example, the first frame period FRMP1 may include an effective period ACTP1 and a blanking period BNKP1. The second frame period FRMP2 may include an effective period ACTP2 and a blanking period (not shown). The blanking period may be a retrace period.

[0098] The effective period ACTP1 or ACTP2 may be a period from when the pixel of the pixel unit 14 receives an initial first scan signal at an on level to when the pixel of the pixel unit 14 receives a final first scan signal at an on level.

[0099] Reference Figure 1 , the first scan driver 13GW may sequentially apply the first scan signal at the on level (low level) to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may apply the initial first scan signal at the on level to the first scan line GW1. For example, the first scan driver 13GW may apply the last first scan signal at the on level to the first scan line GWp. During the effective period ACTP1 or ACTP2, at the time corresponding to the first scan signal at the on level, the data driver 12 may apply the data voltage to the data lines DL1 to DLq in units of pixel rows.

[0100] like Figure 6The blanking period BNKP1 shown in may be a period from the time when the pixel of the pixel unit 14 receives the last first scan signal at the on-level to the time when the pixel of the pixel unit 14 receives the initial first scan signal at the on-level of the next frame period (e.g., the second frame period FRMP2). During the blanking period BNKP1, the data driver 12 may not apply the data voltage to the data lines DL1 to DLq. Depending on the embodiment, during the blanking period BNKP1, the data driver 12 may maintain the reference voltage at a specific level in the data lines DL1 to DLq, or the data driver 12 may not supply the voltage to the data lines DL1 to DLq.

[0101] The second scan driver 13GB may sequentially apply the second scan signal at the on level to the second scan lines GB1 to GBp. Figure 6 In an embodiment, the second scan signal at the on-level may be sequentially applied in units of two second scan lines. For example, the second scan driver 13GB may include a plurality of stages, and the first stage of the second scan driver 13GB may simultaneously apply the second scan signal at the on-level (low level) to the second scan lines GB1 and GB2. Next, the second stage of the second scan driver 13GB may simultaneously apply the second scan signal at the on-level to the second scan lines GB3 and GB4. Next, the third stage of the second scan driver 13GB may simultaneously apply the second scan signal at the on-level to the second scan lines GB5 and GB6. In another embodiment, the second scan signal at the on-level may be sequentially applied to one second scan line at a time (see Fig. 9 and Fig.10 ).

[0102] Each pixel may receive the first scanning signal at the on level once (i.e., only once) during one frame period (e.g., the first frame period FRMP1). Each pixel may receive the second scanning signal at the on level N times during one frame period (e.g., the first frame period FRMP1), where N may be an integer greater than 1. Figure 6 In the embodiment of the present invention, each pixel is shown to receive the second scanning signal at the on level four times during one frame period (e.g., the first frame period FRMP1). The second scanning driver 13GB can provide the second scanning signal at the on level to each pixel at a constant rate corresponding to a constant period or cycle GB1CYC. Figures 3A to 5 Description, in Figure 6In the embodiment, for each pixel PXij, one frame period (e.g., the first frame period FRMP1) may include one address scanning period AS and three self-scanning periods SS. The address scanning periods AS of pixels arranged in the same pixel row may be the same. Similarly, the self-scanning periods SS of pixels arranged in the same pixel row may be the same.

[0103] Figure 6 An example is shown in which the pulse width of the first scan signal at the on level corresponds to 1 horizontal period, and the pulse width of the second scan signal at the on level corresponds to 4 horizontal periods. In addition, the time interval between the second scan signals at the on level applied sequentially may be 2 horizontal periods. For example, after the second scan signal at the on level is simultaneously applied to the second scan lines GB1 and GB2, a time interval of two horizontal periods may pass before the second scan signal at the on level may be simultaneously applied to the second scan lines GB3 and GB4. In another embodiment, when the second scan signal at the on level is sequentially applied in units of one second scan line (see Fig. 9 and Fig.10 ), the time interval between the second scan signals at the on-level applied sequentially may be 1 horizontal period.

[0104] exist Figure 6 In an embodiment of the present invention, the length of the blanking period BNKP1 may be shorter than the period GB1CYC in which each pixel receives the second scanning signal at the on level. In this case, in each horizontal period of the specific periods swp1, swp2, and swp3, the number of second scanning lines to which the second scanning signal at the on level is applied may be 12. The pixels connected to these second scanning lines may be arranged in the second areas AR21, AR22, and AR23.

[0105] In this example, the number of second scan lines to which the second scan signal at the on level is applied in each horizontal period of the remaining periods except for the specific periods swp1, swp2, and swp3 may be 16. Pixels connected to the second scan lines may be arranged in the first areas AR11, AR12, AR13, and AR14.

[0106] However, in this example, during each of two horizontal periods arranged before / after the specific periods swp1, swp2, and swp3, the number of second scan lines to which the second scan signal at the on level is applied in each horizontal period may be 14.

[0107] Reference Figure 7, shows a photograph when a monochrome image frame is input to the pixel unit 14. Although the monochrome image frame is input to the pixel unit 14, darker stripes may be displayed in the second areas AR21, AR22, and AR23 compared to the first areas AR11, AR12, AR13, and AR14.

[0108] Reference Figure 8 , Figure 4 The light emission line EMi, the second scan line GBi, the fourth node voltage N4V, and the second initialization voltage VAINT in the address scan period AS described in are shown as an example.

[0109] At time t5a, the second scan signal at the on level may be applied to the second scan line GBi. At this time, the seventh transistor T7 may be turned on, and the second initialization voltage VAINT may be applied to the fourth node N4 (see Figure 2 ).

[0110] The second initialization voltage VAINT may be a common voltage commonly supplied to all pixels of the pixel unit 14. The second initialization voltage VAINT may be supplied as a DC voltage. However, the voltage level of the second initialization voltage VAINT may vary due to capacitive coupling to anodes of light emitting elements LD of different numbers of pixels through a plurality of turned-on seventh transistors T7.

[0111] As described above, for one horizontal period, the second initialization voltage VAINT can be capacitively coupled to 16 pixel rows in the first areas AR11, AR12, AR13, and AR14. For one horizontal period, the second initialization voltage VAINT can be capacitively coupled to 12 or 14 pixel rows in the second areas AR21, AR22, and AR23. Due to this load difference, the voltage level of the second initialization voltage VAINT supplied to the second areas AR21, AR22, and AR23 can be lower than the voltage level of the second initialization voltage VAINT supplied to the first areas AR11, AR12, AR13, and AR14.

[0112] Depending on the difference in the voltage level of the second initialization voltage VAINT, a difference in the fourth node voltage N4V of the fourth node N4 also occurs. Therefore, after time t6a, the light emitting elements LD of the second regions AR21, AR22, and AR23 may emit light having a lower brightness than the brightness of the light emitting elements LD of the first regions AR11, AR12, AR13, and AR14.

[0113] Figures 9 to 16 is a timing chart for illustrating a method of driving a display device according to another embodiment of the present disclosure.

[0114] Reference Fig. 9 and Fig.10 Each frame period FRMP1, FRMP2, ... may include an effective period and a blanking period. For example, the first frame period FRMP1 may include an effective period ACTP1 and a blanking period BNKP1. The second frame period FRMP2 may include an effective period ACTP2 and a blanking period (not shown).

[0115] The effective period ACTP1 or ACTP2 may be a period from when the pixel of the pixel unit 14 receives an initial first scan signal at an on level to when the pixel of the pixel unit 14 receives a final first scan signal at an on level.

[0116] The first scan driver 13GW may sequentially apply the first scan signal at the on level (low level) to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may apply the initial first scan signal at the on level to the first scan line GW1. For example, the first scan driver 13GW may apply the last first scan signal at the on level to the first scan line GWp. During the effective period ACTP1 or ACTP2, at the time corresponding to the first scan signal at the on level, the data driver 12 may apply the data voltage to the data lines DL1 to DLq in units of pixel rows.

[0117] The blanking period BNKP1 may be a period from when the pixel of the pixel unit 14 receives the last first scan signal at the on-level to when the pixel of the pixel unit 14 receives the initial first scan signal at the on-level of the next frame period (e.g., the second frame period FRMP2). During the blanking period BNKP1, the data driver 12 may not apply the data voltage to the data lines DL1 to DLq. Depending on the embodiment, during the blanking period BNKP1, the data driver 12 may maintain the reference voltage at a specific level in the data lines DL1 to DLq, or the data driver 12 may not supply the voltage to the data lines DL1 to DLq.

[0118] The second scan driver 13GB may sequentially apply the second scan signal at the on level to the second scan lines GB1 to GBp. Fig. 9In an embodiment, the second scan signal at the on-level may be sequentially applied as a unit of one second scan line. For example, the first stage of the second scan driver 13GB may apply the second scan signal at the on-level (low level) to the second scan line GB1. Next, the second stage of the second scan driver 13GB may apply the second scan signal at the on-level to the second scan line GB2. Next, the third stage of the second scan driver 13GB may apply the second scan signal at the on-level to the second scan line GB3. In another embodiment, two second scan lines (see Figure 6 ) is sequentially applied as a unit of the second scanning signal at the on level.

[0119] Each pixel may receive the first scanning signal at the on level once during one frame period (e.g., the first frame period FRMP1). Each pixel may receive the second scanning signal at the on level N times during one frame period (e.g., the first frame period FRMP1). N may be an integer greater than or equal to 1. Fig. 9 In the embodiment of , each pixel is shown to receive the second scanning signal at the on level four times during one frame period (eg, the first frame period FRMP1). Fig.10 In the embodiment of FIG. 5 , each pixel is shown to receive the second scan signal at the on-level five times during one frame period (eg, the first frame period FRMP1 ).

[0120] The second scan driver 13GB may provide a second scan signal at an on level to each pixel at a constant rate corresponding to a constant period or cycle GB1CYC. Figures 3A to 5 Description, in Fig. 9 In the embodiment of FIG. 5 , for each pixel PXij, one frame period (eg, the first frame period FRMP1 ) may include one address scanning period AS and three self-scanning periods SS. Fig.10 In the embodiment, for each pixel PXij, one frame period (e.g., the first frame period FRMP1) may include one address scanning period AS and four self-scanning periods SS. The address scanning periods AS of pixels arranged in the same pixel row may be the same. Similarly, the self-scanning periods SS of pixels arranged in the same pixel row may be the same.

[0121] Fig. 9 and Fig.10 An example is shown in which the pulse width of the first scan signal at the on level corresponds to 1 horizontal period, and the pulse width of the second scan signal at the on level corresponds to 3 horizontal periods. In addition, the time interval between the second scan signals at the on level sequentially applied to the consecutive scan lines may be one horizontal period.

[0122] exist Fig. 9 and Fig.10 In an embodiment of the present invention, the length of the blanking period BNKP1 may be greater than or equal to the period GB1CYC in which each pixel receives the second scanning signal at the on level. For example, the length of the blanking period BNKP1 may be an integer multiple of the period GB1CYC in which each pixel receives the second scanning signal at the on level. For example, the length of the blanking period BNKP1 may be (N-3) times the period GB1CYC in which each pixel receives the second scanning signal at the on level. For example, in Fig. 9 In the case of , since N corresponds to 4, the length of the blanking period BNKP1 may be one time the period GB1CYC in which each pixel receives the second scanning signal at the on level. Fig.10 In the case of , since N corresponds to 5, the length of the blank period BNKP1 may be twice as long as the period GB1CYC in which each pixel receives the second scan signal at a turn-on level.

[0123] according to Fig. 9 and Fig.10 In the embodiment, the number of pixels simultaneously receiving the second scanning signal at the on level may be the same throughout the frame periods FRMP1 and FRMP2. That is, the number of pixels simultaneously receiving the second scanning signal at the on level may be the same in each horizontal period of the frame periods FRMP1 and FRMP2.

[0124] Fig. 9 An example is shown in which the number of pixels receiving the second scan signal at the on-level at the continuous times t1b, t2b, t3b and t4b corresponding to four continuous horizontal periods may be the same. For example, at the continuous times t1b, t2b, t3b and t4b, the number of pixel rows receiving the second scan signal at the on-level may be 9, respectively. For example, at the time t1b, nine pixel rows including three pixel rows connected to the second scan lines GB(p-2), GB(p-1) and GBp may receive the second scan signal at the on-level. At the time t2b, nine pixel rows including three pixel rows connected to the second scan lines GB(p-1), GBp and GB1 may receive the second scan signal at the on-level. At the time t3b, nine pixel rows including three pixel rows connected to the second scan lines GBp, GB1 and GB2 may receive the second scan signal at the on-level. At time t4b, nine pixel rows including three pixel rows connected to the second scan lines GB1, GB2, and GB3 may receive the second scan signal at a turn-on level.

[0125] Fig.10An example is shown in which the number of pixels receiving the second scan signal at the on-level at the continuous times t1c, t2c, t3c and t4c corresponding to four continuous horizontal periods may be the same. For example, at the continuous times t1c, t2c, t3c and t4c, the number of pixel rows receiving the second scan signal at the on-level may be 9, respectively. For example, at the time t1c, nine pixel rows including three pixel rows connected to the second scan lines GB(p-2), GB(p-1) and GBp may receive the second scan signal at the on-level. At the time t2c, nine pixel rows including three pixel rows connected to the second scan lines GB(p-1), GBp and GB1 may receive the second scan signal at the on-level. At the time t3c, nine pixel rows including three pixel rows connected to the second scan lines GBp, GB1 and GB2 may receive the second scan signal at the on-level. At time t4c, nine pixel rows including three pixel rows connected to the second scan lines GB1, GB2, and GB3 may receive the second scan signal at a turn-on level.

[0126] Therefore, according to Fig. 9 and Fig.10 In the embodiment of the present invention, the voltage level of the second initialization voltage VAINT does not change due to the load difference. Therefore, the display device 10 can maintain uniform display quality without stripes or spots.

[0127] Figures 11 to 16 Each frame period FRMP1, FRMP2, ... may similarly include an effective period and a blanking period. For example, the first frame period FRMP1 may include an effective period ACTP1 and a blanking period BNKP1. The second frame period FRMP2 may include an effective period ACTP2 and a blanking period (not shown).

[0128] For each pixel, each frame period FRMP1, FRMP2, ... may include an address scanning period and a self-scanning period. Figures 11 to 13 In the embodiment, for each pixel, each of the frame periods FRMP1, FRMP2, ... includes an address scanning period and a self-scanning period. Figures 14 to 16 In the embodiment, for each pixel, each of the frame periods FRMP1, FRMP2, . . . includes one address scanning period and three self-scanning periods.

[0129] During the address scanning period, each pixel may receive a first scanning signal at an on level and a second scanning signal at an on level. During the self scanning period, each pixel may not receive the first scanning signal at an on level but may receive the second scanning signal at an on level.

[0130] During each frame period FRMP1, FRMP2, ..., the self-scan period of the first pixel row (i.e., the pixel row connected to the second scan line GB1) may start before the address scan period of the last pixel row (i.e., the pixel row connected to the second scan line GBp) ends. In addition, during each frame period FRMP1, FRMP2, ..., the second scan signal at the on-level supplied during the address scan period of the pixel may not overlap with the second scan signal at the on-level supplied during the self-scan period of the pixel.

[0131] exist Figures 11 to 13 In an embodiment, during each of the frame periods FRMP1, FRMP2, ..., the second scanning signal at the on level supplied during the address scanning period of the pixel may overlap in units of M adjacent pixel rows, where M may be an integer greater than 1. In addition, during each frame period FRMP1, FRMP2, ..., the second scanning signal at the on level supplied during the self-scanning period of the pixel may overlap in units of M adjacent pixel rows.

[0132] In one embodiment, the width of the second scanning signal at the on level may be P horizontal periods. P may be an integer greater than zero. In this case, M may be 2*P. Fig.11 In the case of , P may be 4, and M may be 8. Fig.12 In the case of , P can be 3, and M can be 6. Fig.13 In the case of , P can be 2 and M can be 4.

[0133] exist Figures 11 to 13 In each of the embodiments, during the frame periods FRMP1 and FRMP2, the number of pixels simultaneously receiving the second scanning signal at the on level may remain unchanged. That is, in each horizontal period of the frame periods FRMP1 and FRMP2, the number of pixels simultaneously receiving the second scanning signal at the on level may be the same. Fig.11 In an embodiment of the present invention, the number of pixel rows that simultaneously receive the second scanning signal at the on level in each horizontal period may be eight. Fig.12 In the embodiment of the present invention, the number of pixel rows that simultaneously receive the second scanning signal at the on level in each horizontal period may be six. Fig.13 In the embodiment of the present invention, the number of pixel rows that simultaneously receive the second scanning signal at the on level in each horizontal period may be four. Figures 11 to 13 In the embodiment of the present invention, the voltage level of the second initialization voltage VAINT does not change due to the load difference. Therefore, the display device 10 can maintain uniform display quality without stripes or spots.

[0134] exist Figures 14 to 16 In the embodiment of the present invention, during each frame period FRMP1 and FRMP2, each of the second scanning signals at the on level supplied during the address scanning period of the pixel may include Q pulses. Q may be an integer greater than 0. For example, Fig.14 In the case of Fig.15 In , Q can be 2, and Fig.16 , Q may be 1. In addition, during each of the frame periods FRMP1 and FRMP2 , each of the second scanning signals at the on level supplied during the self-scan period of the pixel may include Q pulses.

[0135] A first pulse among Q pulses supplied to a first pixel row (eg, pixels connected to the first scan line GW1 and the second scan line GB1 ) may overlap with R pulses supplied to other pixel rows, where R is an integer greater than 1. Fig.14 , Fig.15 and Fig.16 An example in which R is 3 is shown. Fig.14 , Fig.15 and Fig.16 , the first pulse among the Q pulses supplied to the second scan line GB1 overlaps with the pulses supplied to the second scan lines GB2, GB3 and GB4. Fig.14 and Fig.15 In the case of , four pulses supplied to the second scan line in the first area AR11 of the pixel unit 14 corresponding to the period swp1 may overlap with each other. Fig.14 and Fig.15 In the case of , four pulses supplied to the second scan line in the first area AR12 located at a position symmetrical to the first area AR11 from the center of the pixel unit 14 may overlap with each other. Fig.16 In this case, four pulses supplied to the second scan line may overlap with each other in the entire region of the pixel unit 14.

[0136] In addition, the second pulse among the Q pulses supplied to the first pixel row (eg, pixels connected to the first scan line GW1 and the second scan line GB1) may overlap with the S pulses supplied to other pixel rows, where S is R+(R+1). For example, S may be 7. Fig.14 and Fig.15 An example is shown in which the second pulse among the Q pulses supplied to the second scan line GB1 overlaps with the pulses supplied to the second scan lines GB2, GB3, GB4, GB5, GB6, . . . Fig.14 In the case of , eight pulses supplied to the second scan line in the second area AR21 of the pixel unit 14 corresponding to the period swp2 may overlap with each other. Fig.14In the case of , eight pulses supplied to the second scan line in the second area AR22 located at a position symmetrical to the second area AR21 from the center of the pixel unit 14 may overlap with each other. Fig.15 In this case, in the second area AR2 except the first areas AR11 and AR12, eight pulses supplied to the second scan line may overlap with each other.

[0137] In addition, the third pulse among the Q pulses supplied to the first pixel row (eg, pixels connected to the first scan line GW1 and the second scan line GB1) may overlap with the T pulses supplied to other pixel rows, where T may be S+(R+1). For example, T may be 11. Fig.14 An example is shown in which the third pulse among the Q pulses supplied to the second scan line GB1 overlaps with the pulses supplied to the second scan lines GB2, GB3, GB4, GB5, GB6, . . . Fig.14 In this case, in the third area AR3 except the first areas AR11 and AR12 and the second areas AR21 and AR22, 12 pulses supplied to the second scan line may overlap with each other.

[0138] Fig.16 An example is shown in which the entire area of ​​the pixel unit 14 can display a uniform display quality. Fig.15 In the embodiment of the present invention, the starting area AR11 and the ending area AR12 of the pixel unit 14 may show a lower brightness than expected, but the middle area AR2 of the pixel unit 14 may show a uniform display quality. Fig.14 In the embodiment, the starting areas AR11 and AR21 and the ending areas AR12 and AR22 of the pixel unit 14 may show lower brightness than expected, but the middle area AR3 of the pixel unit 14 may show uniform display quality. Fig.14 and Fig.15 In the case of the edge areas AR11, AR12, AR21 and AR22, the brightness reduction of the edge areas AR11, AR12, AR21 and AR22 may not be obviously visible to the user (and therefore not noticed by the user). In addition, by covering the edge areas AR11, AR12, AR21 and AR22 with a black matrix, the brightness reduction of the edge areas AR11, AR12, AR21 and AR22 can be prevented from being visible. According to an embodiment, the display device 10 can be configured to prevent the brightness reduction in the edge areas AR11, AR12, AR21 and AR12 by adding dummy pixel rows to the display device 10 before the first pixel row and after the last pixel row.

[0139] Fig.17 is a block diagram showing a display device 10 a according to another embodiment of the present disclosure.

[0140] Reference Fig.17 , the display device 10a may include a scan driver 13a and an emission driver 15a. Since other components of the display device 10a may be Figure 1 The components of the display device 10 are the same, so the description of the components described above may be omitted below.

[0141] The scan driver 13a may include a first scan driver 13GWa, a second scan driver 13GIa, and a third scan driver 13GRa. The first scan driver 13GWa may provide a first scan signal to the first scan lines GWa1, ..., GWai, ..., GWap, where p may be an integer greater than 1, and i may be an integer greater than 0 and less than p. The second scan driver 13GIa may provide a second scan signal to the second scan lines GIa1, ..., GIai, ..., GIap. The third scan driver 13GRa may provide a third scan signal to the third scan lines GRa1, ..., GRai, ..., GRap.

[0142] For example, the first scan driver 13GWa may generate a first scan signal to be provided to the first scan lines GWo1 to GWap using at least one scan clock signal and a scan start signal from the timing controller 11a. The first scan driver 13GWa may sequentially provide the first scan signal having an on-level pulse to the first scan lines GWo1 to GWap. For example, the first scan driver 13GWa may be configured in the form of a shift register, and may generate the first scan signal in a manner of sequentially sending a scan start signal as an on-level pulse type to the next scan stage according to the control of the scan clock signal. The second scan driver 13GIa and the third scan driver 13GRa may be configured to be substantially the same as the first scan driver 13GWa.

[0143] The emission driver 15a may include a first emission driver 15EMa and a second emission driver 15EMBa. The first emission driver 15EMa may provide a first light emission signal to the first light emission lines EMa1, ..., EMai, ..., EMap. The second emission driver 15EMBa may provide a second light emission signal to the second light emission lines EMBa1, ..., EMBai, ..., EMBap.

[0144] For example, the first emission driver 15EMa may generate a first light emission signal to be provided to the first light emission lines EMa1 to EMap using at least one light emission clock signal and a light emission stop signal from the timing controller 11a. The first emission driver 15EMa may sequentially provide the first light emission signal having an off-level pulse to the first light emission lines EMa1 to EMap. For example, the first emission driver 15EMa may be configured in the form of a shift register, and may generate the first light emission signal in a manner that sequentially sends a light emission stop signal as an off-level pulse type to the next light emission stage according to the control of the light emission clock signal. The second emission driver 15EMBa may be connected to the second light emission lines EMBa1 to EMBap, but may be configured and operated substantially the same as the first emission driver 15EMa in other respects.

[0145] The pixel unit 14a includes a plurality of pixels PXaij. Each pixel PXaij may be connected to a corresponding data line DLaj among the data lines DLa1 to DLaq, scan lines GWai, GIai and GRai, and light emission lines EMai and EMBai. Each pixel PXaij may include a light emitting element that emits light based on a data voltage received from the data line DLaj.

[0146] Fig.18 is a circuit diagram of a pixel PXaij according to an embodiment of the present disclosure.

[0147] according to Fig.18 The pixel PXaij of the embodiment of the present invention may include a pixel circuit PXCa and a light emitting element LDa. The pixel circuit PXCa may include transistors T1a, T2a, T3a, T4a, T5a and T6a, a first capacitor Csta and a second capacitor Choda.

[0148] In the following, the pixel circuit PXCa composed of N-type transistors is described as an example. However, a pixel circuit in which any one of the N-type transistors is replaced with a P-type transistor can be similarly operated by changing the polarity of the voltage applied to the gate terminal of the P-type transistor. Those skilled in the art will be able to design a circuit composed of a combination of a P-type transistor and an N-type transistor. A P-type transistor refers to a transistor in which the current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor refers to a transistor in which the current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. Each transistor can be composed of various forms such as a thin film transistor (TFT), a field effect transistor (FET), a bipolar junction transistor (BJT), etc.

[0149] In an embodiment, the transistors T1a, T2a, T3a, T4a, T5a and T6a may be N-type oxide thin film transistors. In another embodiment, the transistors T1a, T2a, T3a, T4a, T5a and T6a may be P-type silicon thin film transistors. In yet another embodiment, some of the transistors T1a, T2a, T3a, T4a, T5a and T6a may be N-type oxide thin film transistors, while others thereof may be P-type silicon thin film transistors.

[0150] The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which the active pattern (semiconductor layer) includes an oxide. However, this is an example, and the N-type transistor is not limited thereto. For example, the active pattern (i.e., semiconductor layer) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon) or an organic semiconductor. The silicon thin film transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor in which the active pattern (semiconductor layer) includes amorphous silicon, polycrystalline silicon, etc.

[0151] The first transistor T1a may have a first gate electrode connected to the first node N1a and a second gate electrode connected to the third node N3a. The second gate electrode of the first transistor T1a can be used to adjust the characteristics of the output current of the first transistor T1a compared to the input voltage. For example, the first transistor T1a can be mainly operated in a saturated state. Alternatively, if the second gate electrode of the first transistor T1a does not exist, the magnitude of the output current can also vary depending on the change of the drain-source voltage even if the gate-source voltage is the same. According to this embodiment, the characteristics of the first transistor T1a can be adjusted to be insensitive to the change of the drain-source voltage, so that the first transistor T1a can output substantially the same current for the same gate-source voltage. The first transistor T1a can control the amount of driving current flowing from the first power supply voltage ELVDDa to the second power supply voltage ELVSSa through the light emitting element LDa. Therefore, the first transistor T1a can be referred to as a driving transistor. The first electrode of the first transistor T1a can be connected to the second node N2a, and its second electrode can be connected to the third node N3a.

[0152] The second transistor T2a may have a gate electrode connected to the first scan line GWai, a first electrode connected to the data line DLaj, and a second electrode connected to the first node N1a. The second transistor T2a may receive a data voltage applied to the data line DLaj. Therefore, the second transistor T2a may be referred to as a data write transistor.

[0153] The first scan driver 13GWa may provide a first scan signal at a turn-on level that determines when the pixel PXaij receives the data voltage. For example, the second transistor T2a receiving the first scan signal at the turn-on level may be turned on and the second transistor T2a may apply the data voltage from the data line DLaj to the first node N1a.

[0154] The third transistor T3a may have a gate electrode connected to the third scan line GRai, a first electrode receiving a reference voltage VREFa, and a second electrode connected to the first node N1a. The reference voltage VREFa may be supplied from a reference voltage source. The third transistor T3a may apply the reference voltage VREFa to the first node N1a to initialize the voltage of the first node N1a to the reference voltage VREFa. Therefore, the third transistor T3a may be referred to as a first initialization transistor.

[0155] The fourth transistor T4a may have a gate electrode connected to the second scan line GIai, a first electrode receiving an initialization voltage VAINTa, and a second electrode connected to a fourth node N4a. The initialization voltage VAINTa may be supplied from an initialization voltage source. The fourth transistor T4a may apply the initialization voltage VAINTa to the fourth node N4a to initialize the voltage of the fourth node N4a to the initialization voltage VAINTa. Therefore, the fourth transistor T4a may be referred to as a second initialization transistor.

[0156] The second scan driver 13GIa may provide a second scan signal at a conduction level that determines the time for initializing the anode voltage of the light emitting element LDa. For example, the fourth transistor T4a receiving the second scan signal at the conduction level may be turned on, and the initialization voltage VAINTa may be applied to the anode of the light emitting element LDa, so that the anode voltage of the light emitting element LDa may be initialized to the initialization voltage VAINTa.

[0157] The fifth transistor T5a may have a gate electrode connected to the first light emission line EMai, a first electrode receiving the first power supply voltage ELVDDa, and a second electrode connected to the second node N2a. The fifth transistor T5a may control the opening and closing of the driving current along the path from the first power supply voltage ELVDDa to the second power supply voltage ELVSSa to the second node N2a. Therefore, the fifth transistor T5a may be referred to as a first light emission control transistor.

[0158] The sixth transistor T6a may have a gate electrode connected to the second light emission line EMBai, a first electrode connected to the third node N3a, and a second electrode connected to the fourth node N4a. The sixth transistor T6a may control the opening and closing of the driving current from the third node N3a along the path from the first power supply voltage ELVDDa to the second power supply voltage ELVSSa. Therefore, the sixth transistor T6a may be referred to as a second light emission control transistor.

[0159] The first capacitor Csta may connect the first node N1a and the third node N3a. A first electrode of the second capacitor Choda may receive the first power supply voltage ELVDDa, and a second electrode thereof may be connected to the third node N3a.

[0160] The anode of the light emitting element LDa may be connected to the fourth node N4a, and the cathode thereof may receive the second power supply voltage ELVSSa. The light emitting element LDa may be a light emitting diode. The light emitting element LDa may include an organic light emitting diode, an inorganic light emitting diode, a quantum dot / well light emitting diode, or the like. In the present embodiment, each pixel may include only one light emitting element LDa, but in other embodiments, each pixel may include a plurality of light emitting elements. The plurality of light emitting elements may be connected in series, in parallel, in series and in parallel, or similarly. The light emitting element LDa of each pixel PXaij may emit light having one of a first color, a second color, and a third color.

[0161] Fig.19 is a timing diagram illustrating an address scanning period according to an embodiment of the present disclosure.

[0162] Fig.19 The address scan period in Figure 3A and Figure 3B In the following, the address scanning period AS will be described based on the following example. Fig.17 and Fig.18 , the pixel rows connected to the first, second, and third scan lines GWai, GIai, and GRai and the first and second light emission lines EMai and EMBai shown in FIG.

[0163] First, at time t1d, a first light emission signal at an off level (eg, a low level) may be applied to the first light emission line EMai. Thus, the fifth transistor T5a may be turned off, and a light emission period based on a data voltage written in a previous frame period may end.

[0164] Next, at time t2d, a second scan signal at a conduction level (e.g., a high level) may be applied to the second scan line GIai, so that the fourth transistor T4a can be turned on. Therefore, the initialization voltage VAINTa may be applied to the fourth node N4a. Therefore, the anode voltage of the light emitting element LDa may be initialized. At this time, since the sixth transistor T6a is turned on, the initialization voltage VAINTa may also be applied to the third node N3a. Therefore, the voltage of the second electrode of the second capacitor Choda may be initialized.

[0165] Next, at time t3d, a third scan signal at an on level may be applied to the third scan line GRai, so that the third transistor T3a can be turned on. Therefore, the reference voltage VREFa may be applied to the first node N1a, and the voltage across the first capacitor Csta may be initialized.

[0166] Next, at time t4d, the second light emission signal at the off level may be applied to the second light emission line EMBai, so that the sixth transistor T6a can be turned off. Therefore, the third node N3a and the fourth node N4a may be electrically separated.

[0167] Next, at time t5d, the first light emission signal at the on level may be applied to the first light emission line EMai, so that the fifth transistor T5a can be turned on. As described above, the voltage at both ends of the first capacitor Csta has been initialized, and at time t5, the first capacitor Csta may maintain a voltage difference between the first gate electrode (first node N1a) and the source electrode (third node N3a) of the first transistor T1a that is higher than the threshold voltage of the first transistor T1a. Therefore, at time t5d, the first transistor T1a may be turned on. At this time, since the current is supplied from the first power supply voltage ELVDDa through the turned-on fifth transistor T5a and the first transistor T1a, the voltage of the third node N3a may gradually increase. When the voltage difference between the first gate electrode (first node N1a) and the source electrode (third node N3a) of the first transistor T1a reaches the threshold voltage of the first transistor T1a, the first transistor T1a may be turned off, and the voltage of the third node N3a may be maintained. Therefore, the first capacitor Csta may store a voltage corresponding to the threshold voltage of the first transistor T1a. A period during which a voltage corresponding to the threshold voltage of the first transistor T1a is stored in the first capacitor Csta may be referred to as a compensation period. At time t6d, when the first light emission signal at an off level is supplied to the first light emission line EMai, the compensation period may end.

[0168] Next, at time t7d, the first scan signal at the on level is applied to the first scan line GWai, so that the second transistor T2a can be turned on. At this time, the data voltage on the data line DLaj can be written to the first node N1a. The voltage of the third node N3a can vary depending on the capacitance ratio of the capacitors Csta and Choda and the voltage of the third node N3a previously stored during the compensation period.

[0169] Next, at time t8d, the second scan signal at the on level is applied to the second scan line GIai, so that the fourth transistor T4a can be turned on. Therefore, the anode voltage of the light emitting element LDa is initialized to the initialization voltage VAINTa, so that the light emitting element LDa can effectively represent a low gray level, such as black gray.

[0170] Next, at time t9d, the second light emission signal at the on level is applied to the second light emission line EMBai, so that the sixth transistor T6a can be turned on. Therefore, the first transistor T1a can be connected to the anode of the light emitting element LDa.

[0171] Next, at time t10d, the first light emission signal at the on level is applied to the first light emission line EMai, so that the fifth transistor T5a can be turned on. Therefore, a drive current path connected to the first power supply voltage ELVDDa, the fifth transistor T5a, the first transistor T1a, the sixth transistor T6a and the second power supply voltage ELVSSa can be created, and the light emitting element LDa can emit light having a brightness corresponding to the amount of drive current flowing along the drive current path.

[0172] Fig. 20 is a timing diagram illustrating a self-scan period according to an embodiment of the present disclosure.

[0173] Fig. 20 The self-scan period in can be Figure 3A and Figure 3B An example of a self-scan period SS in . Fig. 20 During the self-scan period, Fig.19 A signal of the same waveform as the waveform of the address scanning period may be applied to the first light emission line EMai, the second light emission line EMBai, and the second scanning line GIai. However, the scanning signal at the off level may be maintained in the first scanning line GWai and the third scanning line GRai. Therefore, the first node N1a may be in a floating state, and the voltage difference between the two ends of the first capacitor Csta may be maintained. Therefore, in Fig. 20 The brightness of the light emitting element LDa after the self-scanning period may be the same as the brightness of the light emitting element LDa after the previous address scanning period.

[0174] Fig.21and Fig. 22 is a timing diagram illustrating a method for driving a display device according to some other embodiments of the present disclosure.

[0175] Reference Fig.21 and Fig. 22 Each frame period FRMP1, FRMP2, ... may include an effective period and a blanking period. For example, the first frame period FRMP1 may include an effective period ACTP1 and a blanking period BNKP1. The second frame period FRMP2 may include an effective period ACTP2 and a blanking period (not shown).

[0176] The effective period ACTP1 or ACTP2 may be from the pixel unit 14a (see Fig.17 ) receives the initial first scan signal GWa1 at the on-level to the time when the pixel of the pixel unit 14a receives the final first scan signal GWap at the on-level.

[0177] The first scan driver 13GWa may sequentially apply a first scan signal at an on level (e.g., a high level) to the first scan lines GWa1 to GWap. For example, at the beginning of the effective period ACTP1, the first scan driver 13GWa may apply an initial first scan signal at an on level to the first scan line GWa1. At the end of the effective period ACTP1, the first scan driver 13GWa may apply a final first scan signal at an on level to the first scan line GWap. During each effective period ACTP1 or ACTP2, at a time corresponding to the first scan signal at an on level, the data driver 12a may apply data voltages for all pixels in one pixel row to the data lines DLa1 to DLaq.

[0178] The blanking period BNKP1 may be a period from the time when the pixels of the pixel unit 14a receive the last first scan signal at the on-level to the time when they receive the initial first scan signal at the on-level of the next frame period (e.g., the second frame period FRMP2). During the blanking period BNKP1, the data driver 12a may not apply the data voltage to the data lines DLa1 to DLaq. Depending on the embodiment, during the blanking period BNKP1, the data driver 12a may maintain the reference voltage at a specific level in the data lines DLa1 to DLaq, or the data driver 12a may not supply the voltage to the data lines DLa1 to DLaq.

[0179] The second scan driver 13GIa may sequentially apply the second scan signals at the on level to the second scan lines GIa1 to GIap. Here, each of the second scan signals at the on level may include one or more pulses. For example, referring to Fig.19, the first pulse of the second scan signal may appear at time t2d, and the second pulse of the second scan signal may appear at time t8d. In another example, the first pulse of the second scan signal may appear at time t1d. Fig.19 , and the second pulse of the second scan signal may not appear at time t8d. In this case, each of the second scan signals at the on level may include one pulse. The waveform of the second scan signal in the self-scan period may be the same as the waveform of the second scan signal in the address scan period (see Fig.19 and Fig. 20 ).

[0180] Reference Figures 3A to 5 Description, in Fig.21 and Fig. 22 In an embodiment, for each pixel PXaij, a frame period (e.g., a first frame period FRMP1) may include an address scanning period AS and a self-scanning period SS. The address scanning periods AS of pixels arranged in the same pixel row may be the same. Similarly, the self-scanning periods SS of pixels arranged in the same pixel row may be the same. During the address scanning period AS, each pixel may receive a first scanning signal at a conduction level and a second scanning signal at a conduction level. During the self-scanning period SS, each pixel may not receive the first scanning signal at a conduction level, but may receive the second scanning signal at a conduction level.

[0181] The pixel unit 14a may sequentially include a first area AR1a, a second area AR2a, a third area AR3a, and a fourth area AR4a. The first pixel row of the first area AR1a may be connected to the second scan line GIa1, and the last pixel row of the first area AR1a may be connected to the second scan line GIa(1+r), where r may be an integer greater than 0. One pixel row in the second area AR2a may be connected to the second scan line GIas, and another pixel row in the second area AR2a may be connected to the second scan line GIa(s+r), where s may be an integer greater than 1+r. One pixel row in the third area AR3a may be connected to the second scan line GIat, and another pixel row in the third area AR3a may be connected to the second scan line GIa(t+r), where t may be an integer greater than s+r. One pixel row in the fourth area AR4a may be connected to the second scan line GIa(pr), and another pixel row in the fourth area AR4a may be connected to the second scan line GIap, where pr may be an integer greater than t+r.

[0182] The data voltages applied to the data lines DLa1 to DLaq for displaying the portions of the images in the regions AR1a, AR2a, AR3a and AR4a are applied at different times. For example, the data voltage corresponding to the first region AR1a during the first frame period FRMP1 is applied during the period from time t1e to time t2e. When the first frame period FRMP1 is defined as the period from time t1e to time t5e, time t3e may be the middle time of the first frame period FRMP1. That is, the periods t1e to t3e may correspond to half of the first frame period FRMP1. In addition, the periods t3e to t5e may correspond to half of the first frame period FRMP1.

[0183] exist Fig.21 In the embodiment of the present invention, the duration of the blanking period BNKP1 as the period t4e to t5e may be less than half of the duration of the corresponding first frame period FRMP1. That is, the duration of the effective period ACTP1 may be longer than the duration of the blanking period BNKP1. In this case, in the third area AR3a, the second scan signal at the on level applied to the second scan lines GIat to GIa(t+r) may be applied before time t2e. That is, the anode voltage of the light emitting element LDa of the pixel connected to the second scan lines GIat to GIa(t+r) may be initialized to the initialization voltage VAINTa before time t2e.

[0184] Depending on the layout of the pixel PXaij, the anode of the light emitting element LDa may form a parasitic capacitance with the adjacent data lines DLa1 to DLaq. Therefore, if the data voltage changes at time t2e, the anode voltage N4a_AR3a of the light emitting element LDa of the third region AR3a may change according to the data voltage. On the other hand, in the pixel of the fourth region AR4a, the anode voltage of the light emitting element LDa may be initialized to the initialization voltage VAINTa after time t2e. Therefore, the anode voltage N4a_AR4a of the light emitting element LDa of the fourth region AR4a is not affected by the change of the data voltage at time t2e.

[0185] Therefore, in Fig.21 In the embodiment, even if a monochrome image pattern is input to the third area AR3a, a duplicate image pattern for a specific image pattern in the first area AR1a may appear, for example, as a ghost.

[0186] exist Fig. 22 In the embodiment of the present invention, the length of the blanking period BNKP1 as the period t2.5e to t5e may be greater than or equal to half of the corresponding first frame period FRMP1. Fig. 22, shows an example in which the length of the blanking period BNKP1 is greater than half of the corresponding first frame period FRMP1. In another embodiment, as described above, the first pulse of the second scanning signal may be Fig.19 , and the second pulse of the second scanning signal may not appear at time t8d. In this embodiment, the length of the blanking period BNKP1 may be equal to half of the corresponding first frame period FRMP1. That is, the end time of the first scanning signal at the on level of the first scanning line GWap may be time t3e.

[0187] exist Fig. 22 In an embodiment, the second scan signal at the on-level received by the pixels located in the last pixel row among the pixels (i.e., the pixels connected to the first scan line GWap and the second scan line GIap) during the self-scan period may not overlap with the first scan signal at the on-level received by the pixels located in the first pixel row among the pixels (i.e., the pixels connected to the first scan line GWa1 and the second scan line GIa1) during the address scan period. For example, the second scan signal at the on-level received by the pixels located in the last pixel row among the pixels (i.e., the pixels connected to the first scan line GWap and the second scan line GIap) during the self-scan period may end before time t1e. At this time, the first scan signal at the on-level received by the pixels located in the first pixel row among the pixels (i.e., the pixels connected to the first scan line GWa1 and the second scan line GIa1) during the address scan period may be received after time t1e. Even if the data voltage rises at time t1e and falls at time t2e', the rise and fall cancel each other out, so when using Fig. 22 When operating, such as Fig.21 The ghost pattern that may be caused as shown in FIG. 1 does not appear in the third area AR3a.

[0188] Fig.23 is a circuit diagram of a pixel PXbij according to another embodiment of the present disclosure.

[0189] Fig.23 The pixel PXbij in may have Fig.18 The pixel circuit PXCa of the pixel PXaij shown in FIG. 1 is similar to the pixel circuit PXCb. The pixel circuit PXCb is different from the pixel circuit PXCa in that the fifth transistor T5b and the sixth transistor T6b in the pixel circuit PXCb are P-type transistors. In this case, if the polarity of the light emission signal applied to the first light emission line EMbi and the second light emission line EMBbi is reversed, the same may be applied. Figures 17 to 22 implementation method.

[0190] The drawings and descriptions of the present disclosure are intended to be illustrative. Therefore, it will be appreciated by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the protection scope of this document should be determined by the technical scope of the attached claims.

Claims

1. A display device, comprising: a pixel including a light emitting element emitting light having a brightness based on a received data voltage; a first scan driver providing a first scan signal at an on level that determines a time when the pixel receives the data voltage; as well as a second scan driver that provides a second scan signal at an on level that determines a time for initializing an anode voltage of the light emitting element, Each frame period includes an effective period and a blanking period. The effective period is a period from the time when the pixel receives the initial first scanning signal at the conduction level to the time when the pixel receives the final first scanning signal at the conduction level, The blanking period is a period from the time when the pixel receives the last first scanning signal at the on-level to the time when the pixel receives the initial first scanning signal at the on-level of the next frame period, and The length of the blanking period is greater than or equal to a period in which each of the pixels receives the second scanning signal at the on-level.

2. The display device according to claim 1, wherein: The length of the blanking period is an integral multiple of the period during which each of the pixels receives the second scanning signal at the on-level.

3. The display device according to claim 1, wherein: Each of the pixels receives the first scanning signal at the on-level once during one frame period, Each of the pixels receives the second scanning signal at the on-level N times during the one frame period, and The N is an integer greater than 3.

4. The display device according to claim 3, wherein: The length of the blanking period is (N-3) times the period during which each of the pixels receives the second scanning signal at the on-level.

5. The display device according to claim 4, wherein: The N is 4, and The length of the blanking period is one time the period during which each of the pixels receives the second scanning signal at the on-level.

6. The display device according to claim 4, wherein: The N is 5, and The length of the blanking period is twice the period during which each of the pixels receives the second scanning signal at the on-level.

7. The display device according to claim 1, wherein: The number of pixels simultaneously receiving the second scanning signal at the on-level remains constant throughout the frame period.

8. A display device, comprising: a pixel including a light emitting element emitting light having a brightness based on a received data voltage; a first scan driver providing a first scan signal at an on level that determines a time when the pixel receives the data voltage; as well as a second scan driver that provides a second scan signal at an on level that determines a time for initializing an anode voltage of the light emitting element, Each frame period includes an effective period and a blanking period. The effective period is a period from the time when the pixel receives the initial first scanning signal at the conduction level to the time when the pixel receives the final first scanning signal at the conduction level, The blanking period is a period from the time when the pixel receives the last first scanning signal at the on-level to the time when the pixel receives the initial first scanning signal at the on-level of the next frame period, and The length of the blanking period is greater than or equal to half of the corresponding frame period.

9. The display device according to claim 8, wherein: For each of the pixels, each of the frame periods includes an address scanning period and a self scanning period, During the address scanning period, each of the pixels receives the first scanning signal at the on level and the second scanning signal at the on level, and During the self-scan period, each of the pixels does not receive the first scan signal at the on-level, and receives the second scan signal at the on-level.

10. The display device according to claim 9, wherein: The second scanning signal at the conduction level received by the pixels in the last pixel row among the pixels during the self-scan period does not overlap with the first scanning signal at the conduction level received by the pixels in the first pixel row among the pixels during the address scan period.

11. A display device, comprising: a pixel including a light emitting element emitting light having a brightness based on a received data voltage; a first scan driver providing a first scan signal at an on level that determines a time when the pixel receives the data voltage; as well as a second scan driver that provides a second scan signal at an on level that determines a time for initializing an anode voltage of the light emitting element, wherein, for each of the pixels, each frame period includes an address scanning period and a self-scanning period, During the address scanning period, each of the pixels receives the first scanning signal at the on level and the second scanning signal at the on level, and During the self-scan period, each of the pixels does not receive the first scan signal at the on-level and receives the second scan signal at the on-level, During each of the frame periods, the self-scan period of the first pixel row starts before the address scan period of the last pixel row ends, and During each of the frame periods, the second scanning signal at the on-level supplied during the address scanning period of the pixel does not overlap with the second scanning signal at the on-level supplied during the self scanning period of the pixel.

12. The display device according to claim 11, wherein: During each of the frame periods, the second scanning signals at the on-level supplied during the address scanning period of the pixels overlap each other in units of M adjacent pixel rows, and The M is an integer greater than 1.

13. The display device according to claim 12, wherein: During each of the frame periods, the second scanning signals at the on-level supplied during the self-scan period of the pixels overlap with each other in units of the M adjacent pixel rows.

14. The display device according to claim 13, wherein: The width of the second scanning signal at the on level is P horizontal periods, P is an integer greater than 0, and The M is 2*P.

15. The display device according to claim 14, wherein: The P is 4, and The M is 8.

16. The display device according to claim 14, wherein: The P is 3, and The M is 6.

17. The display device according to claim 14, wherein: The P is 2, and The M is 4.

18. The display device according to claim 11, wherein: During each of the frame periods, each of the second scanning signals at the on-level supplied during the address scanning period of the pixel includes Q pulses, A first pulse among the Q pulses supplied to the first pixel row overlaps with R pulses supplied to other pixel rows, and Each of the Q and the R is an integer greater than 0.

19. The display device according to claim 18, wherein: A second pulse among the Q pulses supplied to the first pixel row overlaps with S pulses supplied to other pixel rows, and The S is R+(R+1).

20. The display device according to claim 19, wherein: A third pulse among the Q pulses supplied to the first pixel row overlaps with T pulses supplied to other pixel rows, and The T is S+(R+1).

Images