Gate drive circuit, display panel and display device

Abstract

The embodiment of the invention provides a gate drive circuit, a display panel and a display device, and relates to the technical field of display. The gate drive circuit comprises a plurality of stages of shift register units; the 2N initial signal output modules are in one-to-one correspondence with the 2N display partitions; the control end of the ith initial signal output module is electrically connected with the corresponding first control signal end and second control signal end, and the output end of the ith initial signal output module is electrically connected with the input end of the jth-stage shifting register unit; the ith initial signal output module is configured to provide an effective initial signal for the input end of the jth-stage shift register unit under the condition that the level voltage signals of the first control signal end and the second control signal end meet the preset conditions; the first control signal ends and the second control signal ends corresponding to any two initial signal output modules are not completely consistent. According to the embodiment of the invention, partition refreshing of the display panel can be effectively realized.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a gate driving circuit, a display panel and a display device. Background Art

[0002] With the rapid development of display technology, new display panels such as organic light emitting diode (OLED) display panels and micro light emitting diode (micro LED) display panels are emerging in an endless stream, and full-screen display has become the development trend of mobile display devices such as mobile phones. With the continuous development of display technology and the increasing requirements of consumers for display panels, the functions integrated in display panels are increasing. However, at this stage, there is a problem that it is not convenient to refresh the display panels in different zones during operation. Summary of the invention

[0003] The embodiments of the present application provide a gate driving circuit, a display panel and a display device, which can effectively realize the partition refresh of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a gate driving circuit, which is applied to a display panel, wherein the display panel includes 2^N display partitions, where N is a positive integer; the gate driving circuit includes:

[0005] A multi-stage shift register unit, wherein an output end of the shift register unit is electrically connected to at least one row of sub-pixels in a corresponding display partition;

[0006] 2^N start signal output modules, the 2^N start signal output modules correspond to the 2^N display partitions one by one; the control end of the i-th start signal output module is electrically connected to the first control signal end and the second control signal end corresponding to it, and the output end of the i-th start signal output module is electrically connected to the input end of the j-th shift register unit;

[0007] The j-th shift register unit is the first shift register unit connected to the i-th display partition corresponding to the i-th start signal output module, i≤2^N, i and j are positive integers;

[0008] The i-th start signal output module is configured to provide a valid start signal to the input terminal of the j-th stage shift register unit when the level voltage signals provided by the first control signal terminal and the second control signal terminal both meet the preset conditions;

[0009] The first control signal terminal and the second control signal terminal corresponding to any two start signal output modules are not completely consistent.

[0010] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display panel, which includes the gate driving circuit as described in the embodiment of the first aspect above.

[0011] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, which includes the display panel as described in the embodiment of the second aspect above.

[0012] A gate drive circuit, a display panel and a display device provided by the embodiments of the present application are configured to respectively set corresponding start signal output modules at the input ends of the first-stage shift register units corresponding to different display partitions, thereby realizing gate drive of the corresponding partitions by controlling the on and off of the start signal output modules. The output level of the start signal output module is determined by the first control signal terminal and the second control signal terminal, and the first control signal terminal and the second control signal terminal corresponding to any two start signal output modules are not completely consistent, thereby realizing independent gate drive control corresponding to each of the above-mentioned display partitions respectively. Only when the level voltage signals provided by the first control signal terminal and the second control signal terminal corresponding to the start signal output module meet the preset conditions, the start signal output module will provide a valid start signal to the input end of the shift register unit, so that the shift register unit corresponding to the display partition performs cascade operation from the first stage downward.

[0013] A gate drive circuit, a display panel, and a display device according to an embodiment of the present application can control the start signal output modules corresponding to different display partitions in the gate drive circuit to be turned on or off according to the display refresh requirements of the actual display panel in actual display work. In this way, independent gate drive control of each display partition can be achieved, so that different refresh rate displays of any display partition of the display panel can be flexibly achieved. At the same time, the embodiment of the present application can effectively reduce the power consumption of the screen body and reduce the waste of shift register resources when the refresh rate partition display of the display panel is performed. When the refresh rate partition display is performed, the shift register part corresponding to the non-refresh row in the gate drive circuit does not need to be cascaded, and the refresh time of each frame is no longer affected by the cascade operation of the shift register unit of the entire row, so it is helpful to achieve a higher refresh rate display of the local partition, and also improve the power consumption waste problem existing in the display panel display process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0016] Figure 2 is a schematic structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0017] Figure 3 It is a schematic diagram of the structure of another gate driving circuit provided in an embodiment of the present application;

[0018] Figure 4 is a structural schematic diagram of a start signal output module provided in an embodiment of the present application;

[0019] Figure 5 is a structural schematic diagram of another start signal output module provided in an embodiment of the present application;

[0020] Figure 6 It is a structural schematic diagram of another start signal output module provided in an embodiment of the present application;

[0021] Figure 7 It is a structural schematic diagram of another start signal output module provided in an embodiment of the present application;

[0022] Figure 8 It is a structural schematic diagram of another start signal output module provided in an embodiment of the present application;

[0023] Fig. 9 It is a structural schematic diagram of another start signal output module provided in an embodiment of the present application;

[0024] Fig.10 is a structural schematic diagram of another gate driving circuit provided in an embodiment of the present application;

[0025] Fig.11 is a structural schematic diagram of another gate driving circuit provided in an embodiment of the present application;

[0026] Fig.12 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0027] Fig.13 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0030] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] It should be noted that the transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the on-level is a high level and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second poles thereof are connected, and when the gate of the N-type transistor is at a low level, the first and second poles thereof are disconnected. For a P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the control pole of the P-type transistor is at a low level, the first and second poles thereof are connected, and when the control terminal of the P-type transistor is at a high level, the first and second poles thereof are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors is used as its control pole, and, according to the signal of the gate of each transistor and its type, the first pole thereof can be used as the source and the second pole as the drain, or the first pole thereof can be used as the drain and the second pole as the source, and no distinction is made here. In addition, the on-level and the off-level in the embodiment of the present invention are both general terms, and the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0032] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0033] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not actual circuit units.

[0034] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0035] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0036] With the continuous development of display technology and the increasing market requirements for display technology, the low-frequency display and power-saving technologies of display panels are constantly iterating. At present, when realizing power saving, different refresh rates are often implemented for different positions of the display panel. For example, a high refresh rate is used for the video area, and a low refresh rate is used for the text area, so as to achieve the purpose of saving the display power consumption of the display panel.

[0037] However, the inventor of the present application has found that in the current working process of the display panel, there is a problem that a higher refresh rate cannot be achieved in any area of ​​the display panel. Specifically, the current mobile phone display screens are designed using the GOA (Gate driver OnArray, array substrate row drive) solution, but the GOA solution does not have the function of starting and stopping any node. In the GOA structure, the gate of the transistor can only be fixed to open row by row from the first row, and then closed row by row after the pixel charging is completed. In other words, at present, when the refresh rate is displayed in a partitioned manner, the shift register (Shift Register, VSR) part corresponding to the non-refresh row in the GOA structure also needs to be cascaded, resulting in the refresh time of each frame being closely affected by the cascade operation of the shift register, so that the display panel cannot achieve a higher refresh rate in any area.

[0038] In response to the above technical problems, the embodiments of the present application provide a gate driving circuit, a display panel and a display device, which can solve the problem in the related art that the display panel cannot achieve higher refresh rate in any area.

[0039] It should be noted that the embodiments provided in this application are not intended to limit the scope of the disclosure of this application.

[0040] The following first introduces the gate driving circuit provided in the embodiment of the present application.

[0041] Figure 1 A schematic diagram of the structure of a gate drive circuit 10 provided in an embodiment of the present application is shown. The gate drive circuit 10 is applied to a display panel, and the display panel includes 2^N display partitions, where N is a positive integer. Taking N=2 as an example, the display panel includes display partition AA1, display partition AA2, display partition AA3, and display partition AA4, and the display partition AA1, display partition AA2, display partition AA3, and display partition AA4 are arranged along the column direction, and different display partitions include at least one row of sub-pixels PX.

[0042] like Figure 1 As shown, the gate drive circuit 10 includes:

[0043] The multi-stage shift register unit 101 has an output terminal Gout electrically connected to at least one row of sub-pixels PX in a corresponding display partition.

[0044] 2^N start signal output modules 102, 2^N start signal output modules 102 correspond one to one with 2^N display partitions; the control end of the i-th start signal output module 102 is electrically connected to the corresponding first control signal end EN1 and the second control signal end EN2, and the output end of the i-th start signal output module 102 is electrically connected to the input end IN of the j-th shift register unit 101.

[0045] The j-th shift register unit 101 is the first shift register unit 101 connected to the i-th display partition corresponding to the i-th start signal output module 102, i≤2^N, i and j are positive integers;

[0046] It should be noted that, when the gate drive circuit 10 includes 2^N display partitions, i can be any value from 1 to 2^N, and the specific value of i is not limited in the embodiment of the present application. For example, when N=4, i is any value from 1 to 4, such as i=3. j is associated with the above parameter i and the number of sub-pixel rows in different display partitions, and this embodiment of the present application will not be described in detail.

[0047] The i-th start signal output module 102 is configured to provide a valid start signal to the input terminal IN of the j-th stage shift register unit 101 when the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 both meet preset conditions.

[0048] The above preset conditions, for example, the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both low level, which depends on the structural setting of the start signal output module 102 and the level of the effective start signal required by the shift register unit 101, and is not strictly limited here.

[0049] The first control signal terminal EN1 and the second control signal terminal EN2 corresponding to any two start signal output modules 102 are not completely consistent.

[0050] Therefore, in the embodiment of the present application, the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 corresponding to the i-th start signal output module 102 can be respectively controlled to meet the preset conditions, while the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 corresponding to the start signal output module 102 other than the i-th start signal output module 102 do not completely meet the preset conditions.

[0051] In this way, when the i-th start signal output module outputs a valid start signal, the start signal output modules except the i-th start signal output module among the 2^N start signal output modules provide ineffective start signals, thereby achieving separate gate drive control for each display partition.

[0052] In a specific application example, combined with Figure 1As shown, illustratively, taking i=3 as an example, the display partition AA3 is a high refresh display area, and the other display partitions are low refresh display areas. The start signal output module 102 of the display partition AA3, under the control of the first control signal terminal EN1 and the second control signal terminal EN2 corresponding to the display partition AA3, provides a valid start signal to the input terminal IN of the first-stage shift register unit 101 corresponding to the display partition AA3, so that the sub-pixels in the display partition AA3 are scanned at a high frequency under the shift register cascade operation, meeting the pixel scanning requirements under a high refresh rate.

[0053] For the remaining display partitions with low refresh rates in the display panel, such as display partition AA1, the corresponding shift register units can be kept working at low frequency under the control of their corresponding start signal output modules 102, thereby meeting the pixel scanning requirements of display partition AA1 at low refresh rates.

[0054] A gate drive circuit 10 provided in an embodiment of the present application is configured to respectively set corresponding start signal output modules 102 at the input terminals IN of the first-stage shift register units 101 corresponding to different display partitions, thereby realizing gate drive of the corresponding partitions by controlling the on and off of the start signal output modules 102. The output level of the start signal output module 102 is determined by the first control signal terminal EN1 and the second control signal terminal EN2, and the first control signal terminals EN1 and the second control signal terminals EN2 corresponding to any two start signal output modules 102 are not completely consistent, thereby realizing independent gate drive control corresponding to each of the above-mentioned display partitions. Only when the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 corresponding to the start signal output module 102 meet the preset conditions, the start signal output module 102 will provide a valid start signal to the input terminal IN of the shift register unit 101, so that the shift register unit 101 corresponding to the display partition performs cascade operation from the first stage downward.

[0055] A gate drive circuit 10 of an embodiment of the present application can be used to control the start signal output module 102 corresponding to different display partitions in the gate drive circuit 10 to be turned on or off according to the display refresh requirements of the actual display panel in actual display work. In this way, independent gate drive control of each display partition can be achieved, so that different refresh rate displays of any display partition of the display panel can be flexibly achieved. At the same time, the embodiment of the present application can effectively reduce the power consumption of the screen body and reduce the waste of shift register resources when the display panel refresh rate partition display is displayed, and also improve the power consumption waste problem existing in the display panel display process.

[0056] In an embodiment of the present application, the gate drive circuit 10 can select any area in the display panel to directly perform gate drive work under local high refresh rate. When the refresh rate is partitioned, the shift register part corresponding to the non-refresh row in the gate drive circuit 10 does not need to perform cascade operation, and the refresh time of each frame is no longer affected by the cascade operation of the shift register unit 101 of the whole row, so as to save time, thereby fully improving the higher refresh rate display of the local area.

[0057] See below Figure 2 , Figure 2 is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Figure 2 As shown, according to some embodiments of the present application, optionally, the gate driving circuit 10 further includes N pairs of control signal lines. The N pairs of control signal lines can be specifically led out by the display driver chip, and the display driver chip performs output level and timing control.

[0058] When one of the pair of control signal lines provides a high level to its corresponding control signal terminal, the other control signal line provides a low level to its corresponding control signal terminal.

[0059] The first control signal terminal EN1 connected to the i-th start signal output module 102 is electrically connected to any control signal line in the corresponding m-th pair of control signal lines, and the second control signal terminal EN2 connected to the i-th start signal output module 102 is electrically connected to any control signal line in the corresponding n-th pair of control signal lines, 1≤m, n≤N, m≠n.

[0060] Among the 2^N start signal output modules 102 , any two start signal output modules 102 correspond to two different control signal lines.

[0061] In this embodiment, N pairs of control signal lines with opposite potentials are provided to realize level output control of different start signal output modules 102, thereby indirectly realizing flexible control of refresh rates of different display partitions in the display panel.

[0062] Among the N pairs of control signal lines, the control signal lines of the same pair are a group, the first control signal terminal EN1 of the same start signal output module 102 is connected to the control signal line in the mth group, and the second control signal line EN2 is connected to the control signal line in the nth group, m≠n, thereby ensuring that the first control signal terminal EN1 and the second control signal line EN2 are not electrically connected to the control signal lines in the same group.

[0063] For example, Figure 2As shown, taking N=2, the display panel includes 4 display partitions AA1, AA2, AA3 and AA4 as an example. The gate drive circuit 10 includes 2 pairs of control signal lines A / A-, -B / B, the first control signal terminal EN1 and the second control signal terminal EN2 connected to the same start signal output module 102 are electrically connected to different pairs of control signal lines, and any two start signal output modules 102 correspond to different control signal lines.

[0064] For example, during the specific connection, the start signal output module 102 corresponding to the display partition AA1 is electrically connected to the control signal lines A and B, the start signal output module 102 corresponding to the display partition AA2 is electrically connected to the control signal lines A and -B, the start signal output module 102 corresponding to the display partition AA3 is electrically connected to the control signal lines A- and B, and the start signal output module 102 corresponding to the display partition AA4 is electrically connected to the control signal lines A- and B-.

[0065] In this way, taking the preset condition that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both low levels as an example, if the control signal lines A- and B corresponding to the display partition AA3 simultaneously provide low levels to the corresponding first control signal terminal EN1 and the second control signal terminal EN2, in this case, the third start signal output module 102 provides a valid start signal to the first-stage shift register unit 101 corresponding to the display partition AA3.

[0066] When the control signal lines A- and B both provide low levels, since the levels of the control signal lines A and B- are opposite, the level voltage signals output by the first control signal terminal EN1 and the second control signal terminal EN2 corresponding to the display partitions AA1, AA2, and AA4 do not completely meet the aforementioned preset conditions, and the shift register units corresponding to the display partitions AA1, AA2, and AA4 will not start working, thereby avoiding the waste of shift register resources and substantially saving refresh time.

[0067] It should be noted that after the control signal lines A- and B corresponding to the display partition AA3 provide a low level to the first control signal terminal EN1 and the second control signal terminal EN2 connected to the corresponding j-th shift register unit 101, the control signal lines A- and B can remain in a floating state to prevent the j-th shift register unit 101 corresponding to the display partition from continuously receiving a valid start signal. Accordingly, the control signal lines A and B- also remain floating until the first-stage shift register unit 101 corresponding to the next display partition to be refreshed needs to be started.

[0068] It is also necessary to add that Figure 2The figure shows a 4-partition scheme of the display panel. In actual display applications, if more display partitions are required, 2^N partitions of the display panel can be realized by setting 2N signal lines with opposite levels, for example, N=3, N=4.

[0069] See below Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Figure 3 As shown, according to some embodiments of the present application, optionally, the gate drive circuit 10 further includes N control signal lines and N inverters, and the input ends of the N inverters are correspondingly connected to the N control signal lines.

[0070] The first control signal terminal EN1 connected to the i-th start signal output module 102 is electrically connected to the corresponding m-th control signal line, or is electrically connected to the output terminal of the corresponding m-th inverter.

[0071] The second control signal terminal EN2 connected to the start signal output module 102 is electrically connected to the corresponding n-th control signal line, or is electrically connected to the output terminal of the corresponding n-th inverter.

[0072] The input end of the mth inverter is electrically connected to the mth control signal line, and the input end of the nth inverter is electrically connected to the nth control signal line, 1≤m, n≤N, m≠n.

[0073] Among the 2^N start signal output modules 102, when the control signal lines corresponding to any two start signal output modules 102 are the same, only one of the first control signal terminals EN1 connected to the two start signal output modules 102 is connected to the corresponding control signal line through an inverter, and / or, only one of the second control signal terminals EN2 connected to the two start signal output modules 102 is connected to the corresponding control signal line through an inverter.

[0074] In this embodiment, in order to reduce the number of control signal lines, thereby saving signal line wiring space, this embodiment adopts a combination of control signal lines and inverters to achieve control of the start signal output module 102. Among the N control signal lines and N inverters, the inverters connected to the control signal lines form a group, the first control signal terminal EN1 of the same start signal output module 102 is connected to the control signal line or inverter in the mth group, and the second control signal line EN2 is connected to the control signal line or inverter in the nth group, m≠n, thereby ensuring that the first control signal terminal EN1 and the second control signal line EN2 are not electrically connected to the control signal lines and inverters in the same group.

[0075] In order to fully ensure that the first control signal terminal EN1 and the second control signal terminal EN2 connected to different start signal output modules 102 are not completely the same, among the 2^N start signal output modules 102, when the control signal lines corresponding to any two start signal output modules 102 are the same, only the first control signal terminal EN1 connected to the two start signal output modules 102 is connected to the corresponding control signal line through an inverter, and / or, only the second control signal terminal EN2 connected to the two start signal output modules 102 is connected to the corresponding control signal line through an inverter.

[0076] For example, Figure 3 As shown, N=2, the display panel includes 4 display partitions, the gate drive circuit 10 includes 2 control signal lines A, B, and corresponding 2 inverters, and the input ends of the 2 inverters are electrically connected to the 2 control signal lines A, B in a one-to-one correspondence.

[0077] The start signal output module 102 corresponding to the display partition AA1 is electrically connected to the control signal lines A and B; the start signal output module 102 corresponding to the display partition AA2 is electrically connected to the control signal line A through an inverter, and is directly electrically connected to the control signal line B; the start signal output module 102 corresponding to the display partition AA3 is electrically connected to the control signal line A, and is electrically connected to the control signal line B through an inverter; the start signal output module 102 corresponding to the display partition AA4 is electrically connected to the control signal lines A and B through an inverter.

[0078] When the shift register unit corresponding to the display partition AA1 needs to be started, the level voltage signals provided by the control signal lines A and B both meet the preset conditions, for example, both are low levels, so that the input terminal IN of the first-stage shift register unit 101 corresponding to the display partition AA1 receives a valid start signal. However, due to the level inversion effect of the inverter, the start signal output module 102 corresponding to the display partitions AA2, AA3, and AA4 outputs an ineffective start signal. When the shift register unit corresponding to the display partition AA2 needs to be started, the level voltage signal of the control signal line A after passing through the inverter and the level voltage signal provided by the control signal line B both meet the preset conditions, and the shift register units corresponding to the remaining display partitions do not work. By analogy, the gate drive control between each display partition is finally independent.

[0079] It should be noted that in this example, although the control signal lines corresponding to the start signal output module 102 corresponding to the display partition AA1 are the same as those of the display partition AA2, both are control signal lines A and B. However, the start signal output module 102 corresponding to the display partition AA2 is electrically connected to the control signal line A through an inverter, so that the signal control of the start signal output modules 102 corresponding to the display partitions AA1 and AA2 is not exactly the same.

[0080] In this way, through the N control signal lines and the N inverters, the number of signal lines can be reduced and the wiring space can be saved, while the independent gate drive control of the 2^N display partitions can be realized respectively.

[0081] It should be added that, in this embodiment, the first control signal terminal EN1 is connected to the control signal line A, and the second control signal terminal EN2 is connected to the control signal line B. The two situations where the first control signal terminal EN1 is connected to the control signal line B and the second control signal terminal EN2 is connected to the control signal line A can be regarded as the same situation, that is, the control signal lines corresponding to the start signal output module 102 are A and B. In other words, the two situations where the first control signal terminal EN1 and the second control signal terminal EN2 are connected interchangeably can be regarded as one situation.

[0082] See below Figure 4 , Su Figure 4 Schematic diagram of the structure of a start signal output module provided in an embodiment of the present application. Figure 4 As shown, in order to more fully implement the output control of the valid start signal by the above-mentioned start signal output module 102, according to some embodiments of the present application, optionally, the start signal output module 102 includes a first switch unit 110 and a second switch unit 120.

[0083] The control terminal of the first switch unit 110 is electrically connected to the corresponding first control signal terminal EN1 and the second control signal terminal EN2 . The first switch unit 110 is connected between the first level voltage signal terminal Vref1 and the target node N.

[0084] The control terminal of the first switch unit 110 is electrically connected to the corresponding first control signal terminal EN1 and second control signal terminal EN2 , and the second switch unit 120 is connected between the target node N and the second level voltage signal terminal Vref2 .

[0085] The target node N is electrically connected to the input terminal IN of the j-th stage shift register unit 101 .

[0086] When the level voltage signal provided by either the first control signal terminal EN1 or the second control signal terminal EN2 does not meet the preset condition, the first switch unit 110 is turned on and the second switch unit 120 is turned off to transmit the first level voltage signal provided by the first level voltage signal terminal Vref1 to the target node N.

[0087] When the first control signal terminal EN1 and the level voltage signal provided by the first control signal terminal EN2 both meet the preset conditions, the first switch unit 110 is turned off and the second switch unit 120 is turned on to transmit the second level voltage signal provided by the second level voltage signal terminal Vref2 to the target node N.

[0088] like Figure 4 As shown, in this embodiment, the internal circuit structure of the start signal output module 102 is described in detail. The first switch unit 110 and the second switch unit 120 can respectively use one or more switch tubes to implement their functions, and the specific number and type of switch tubes can be determined according to actual control requirements.

[0089] For example, the first switch unit 110 may use multiple switch tubes in a parallel structure to achieve that when the level voltage signal provided by either the first control signal terminal EN1 or the second control signal terminal EN2 does not meet the preset conditions, the first switch unit 110 is turned on, and is in the off state in other cases.

[0090] Accordingly, the second switch unit 120 may adopt multiple switch tubes in a series structure to realize that when the first control signal terminal EN1 and the level voltage signal provided by the first control signal terminal EN1 both meet the preset conditions, the second switch unit 120 is turned on, and is in the off state in other cases.

[0091] It should be noted that the target node N can be directly electrically connected to the input terminal IN of the j-th shift register unit 101, or can be indirectly electrically connected through other functional modules. For example, the target node N is indirectly electrically connected to the input terminal IN of the j-th shift register unit 101 through the level flip module described later, which is not strictly limited here.

[0092] More specifically, in order to fully guarantee the independent gate drive control of each display partition, it is necessary to control that when the start signal output module 102 of one display partition outputs a valid start signal, the start signal output modules 102 of the remaining display partitions can output an ineffective start signal. Therefore, if the target node N is directly electrically connected to the input terminal IN of the j-th stage shift register unit 101, the j-th stage shift register unit 101 receives the second level voltage signal as a valid start signal.

[0093] The j-th stage shift register unit 101 receives the first level voltage signal as a non-valid start signal.

[0094] Specifically, the second level voltage signal provided by the second level voltage signal terminal Vref2 is used as a valid start signal. When the level voltage signals provided by the first control signal terminal EN1 and the first control signal terminal EN2 both meet the preset conditions, the first switch unit 110 is turned off and the second switch unit 120 is turned on, thereby transmitting the second level voltage signal as a valid start signal to the input terminal IN of the j-th stage shift register unit 101.

[0095] When the level voltage signal provided by either the first control signal terminal EN1 or the second control signal terminal EN2 does not meet the preset conditions, the first switch unit 110 is turned on and the second switch unit 120 is turned off, thereby transmitting the first level voltage signal as a non-valid start signal to the input terminal IN of the j-th stage shift register unit 101.

[0096] See also Figure 5 , Figure 5 Schematic diagram of another structure of a start signal output module provided in an embodiment of the present application. Figure 5 As shown, in order to fully guarantee effective gate drive control of each display partition and to guarantee accurate output of a valid start signal by the start signal output module 102 , according to some embodiments of the present application, the start signal output module 102 optionally further includes a level flipping unit 130 .

[0097] The control end of the level flip unit 130 is electrically connected to the target node N, the first end of the level flip unit 130 is electrically connected to the first level voltage signal end Vref1, the second end of the level flip unit 130 is electrically connected to the second level voltage signal end Vref2, and the output end of the level flip unit 130 is electrically connected to the input end IN of the j-th stage shift register unit 101.

[0098] The level flip unit 130 is configured to transmit the first level voltage signal provided by the first level voltage signal terminal Vref1 to the input terminal IN of the j-th shift register unit 101 when receiving the second level voltage signal provided by the target node N. The j-th shift register unit 101 receives the first level voltage signal as a valid start signal.

[0099] When receiving the first level voltage signal provided by the target node N, the second level voltage signal provided by the second level voltage signal terminal Vref2 is transmitted to the input terminal IN of the jth stage shift register unit 101. The jth stage shift register unit 101 receives the second level voltage signal as a non-valid start signal.

[0100] In this embodiment, the level flip unit 130 flips the level voltage signal received from the target node N and outputs it to the input terminal IN of the j-th shift register unit 101. In this way, when the first level voltage signal is a valid start signal, the independent gate drive control of each display partition can still be guaranteed.

[0101] Specifically, when the first control signal terminal EN1 and the level voltage signal provided by the first control signal terminal EN2 both meet the preset conditions, the first switch unit 110 is turned off, the second switch unit 120 is turned on, and the second level voltage signal provided by the second level voltage signal terminal Vref2 is transmitted to the target node N.

[0102] Under the control of the first control signal terminal EN1 and the second control signal terminal EN2, the second level voltage signal at the target node N can be processed by the level flip unit 130 to obtain a first level voltage signal with opposite level, and the first level voltage signal is transmitted to the input terminal IN of the j-th stage shift register unit 101 as a valid start signal.

[0103] When the level voltage signal provided by either the first control signal terminal EN1 or the second control signal terminal EN2 does not meet the preset condition, the first switch unit 110 is turned on, the second switch unit 120 is turned off, and the first level voltage signal provided by the first level voltage signal terminal Vref1 is transmitted to the target node N.

[0104] Under the control of the first control signal terminal EN1 and the second control signal terminal EN2, the first level voltage signal at the target node N can be processed by the level flip unit 130 to obtain a second level voltage signal, and the second level voltage signal is transmitted to the input terminal IN of the j-th stage shift register unit 101 as a non-valid start signal.

[0105] See also Figure 6 , Figure 6 Schematic diagram of another structure of a start signal output module provided in an embodiment of the present application. Figure 6 As shown, in order to fully realize the switch control function of the first switch unit 110 and the second switch unit 120 on the start signal, the specific structures of the first switch unit 110 and the second switch unit 120 are expanded below. According to some embodiments of the present application, optionally, the first switch unit 110 includes a first switch tube M1 and a second switch tube M2 connected in parallel between the first level voltage signal terminal Vref1 and the target node N.

[0106] The control end of the first switch tube M1 is electrically connected to the corresponding first control signal end EN1 , and the control end of the second switch tube M2 is electrically connected to the corresponding second control signal end EN2 .

[0107] The second switch unit 120 includes a third switch tube M3 and a fourth switch tube M4 which are connected in series between the target node N and the second level voltage signal terminal Vref2 .

[0108] The control end of the third switch tube M3 is electrically connected to the corresponding first control end, and the control end of the fourth switch tube M4 is electrically connected to the corresponding second control signal end EN2.

[0109] More specifically, the channel types of the first switch transistor M1 and the second switch transistor M2 are both the first channel type, and the channel types of the third switch transistor M3 and the fourth switch transistor M4 are both the second channel type. The first channel type is opposite to the second channel type.

[0110] In an example, the channel types of the first switch transistor M1 and the second switch transistor M2 are P-channel types, and the channel types of the third switch transistor M3 and the fourth switch transistor M4 are N-channel types.

[0111] In another example, the channel types of the first switch tube M1 and the second switch tube M2 are N-channel types, and the channel types of the third switch tube M3 and the fourth switch tube M4 are P-channel types.

[0112] In this way, under the control of N pairs of control signal lines with opposite levels in the aforementioned embodiment, the switch tubes can fully ensure effective gate drive control of different display partitions.

[0113] According to some embodiments of the present application, optionally, the j-th stage shift register unit 101 receives a second level voltage signal as a valid start signal.

[0114] When the shift register unit 101 is low level effective, the first level voltage signal is high level, the second level voltage signal is low level, the first channel type is P type, the second channel type is N type, and the preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both high level.

[0115] When the shift register unit 101 is high level valid, the first level voltage signal is low level, the second level voltage signal is high level, the first channel type is N type, the second channel type is P type, and the preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both low level.

[0116] In this embodiment, considering that, for example, when the shift register unit 101 is specifically an SP circuit, the shift register unit 101 is low level effective. That is, when the level output by the start signal output module 102 is low level, the output terminal Gout of the shift register unit 101 provides a gate drive signal to the pixels connected in the display partition.

[0117] In this case, if Figure 6 As shown, the first level voltage signal is set to a high level, the second level voltage signal is set to a low level, the channel types of the first switch tube M1 and the second switch tube M2 are P-type, and the channel types of the third switch tube M3 and the fourth switch tube M4 are N-type. The preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both high levels.

[0118] Thus, when both the first control signal terminal EN1 and the second control signal terminal EN2 are at a high level, M1 and M2 are turned off, M3 and M4 are turned on, and the second level voltage signal VGL is transmitted as a valid start signal to the input terminal IN of the corresponding shift register unit 101. When either the first control signal terminal EN1 or the second control signal terminal EN2 is at a low level, M1 or M2 is turned on, M3 and M4 are turned off, and the first level voltage signal VGH of the first level voltage signal terminal Vref1 is transmitted as a non-valid start signal to the input terminal IN of the corresponding shift register unit 101.

[0119] And as Figure 7 As shown, considering that, for example, when the shift register unit 101 is specifically an SN circuit, the shift register unit 101 is high level effective. Therefore, in this case, the first level voltage signal is set to be low level, the second level voltage signal is set to be high level, the channel type of the first switch tube M1 and the second switch tube M2 is N type, the channel type of the third switch tube M3 and the fourth switch tube M4 is P type, and the preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both low level.

[0120] Thus, when the first control signal terminal EN1 and the second control signal terminal EN2 are both at low levels, M1 and M2 are turned off, M3 and M4 are turned on, and the second level voltage signal VGH is transmitted as a valid start signal to the input terminal IN of the corresponding shift register unit 101. When either the first control signal terminal EN1 or the second control signal terminal EN2 is at a low level, M1 or M2 is turned on, M3 and M4 are turned off, and the first level voltage signal VGL of the first level voltage signal terminal Vref1 is transmitted as a non-valid start signal to the input terminal IN of the corresponding shift register unit 101.

[0121] According to some embodiments of the present application, optionally, Figure 8As shown, when the first level voltage signal is a valid start signal, the start signal output module 102 further includes a level flip unit 130. The level flip unit 130 includes a fifth switch tube M5 and a sixth switch tube M6.

[0122] The control end of the fifth switch tube M5 is electrically connected to the target node N, the first end of the fifth switch tube M5 is electrically connected to the first level voltage signal end Vref1 , and the second end of the fifth switch tube M5 is electrically connected to the input end IN of the j-th stage shift register unit 101 .

[0123] The control end of the sixth switch tube M6 is electrically connected to the target node N, the first end of the fifth switch tube M5 is electrically connected to the second level voltage signal end Vref2 , and the second end of the fifth switch tube M5 is electrically connected to the input end IN of the j-th stage shift register unit 101 .

[0124] The channel type of the fifth switch tube M5 is the first channel type, and the channel type of the sixth switch tube M6 is the second channel type.

[0125] More specifically, in combination with an actual gate driving scenario, optionally, the j-th stage shift register unit 101 receives a first level voltage signal as a valid start signal.

[0126] When the shift register unit 101 is low level valid, the first level voltage signal is low level, the second level voltage signal is high level, the first channel type is N type, the second channel type is P type, and the preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both low level.

[0127] When the shift register unit 101 is high level valid, the first level voltage signal is high level, the second level voltage signal is low level, the first channel type is P type, the second channel type is N type, and the preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both high level.

[0128] Specifically, if Figure 8 As shown, considering that, for example, when the shift register unit 101 is specifically an SP circuit, the shift register unit 101 is low level effective. In this case, the first level voltage signal is set to a low level, the second level voltage signal is set to a high level, the channel type of the first switch tube M1, the second switch tube M2 and the fifth switch tube M5 is N type, and the channel type of the third switch tube M3, the fourth switch tube M4 and the sixth switch tube M6 is P type. The preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both low level.

[0129] Thus, when the first control signal terminal EN1 and the second control signal terminal EN2 are both at low levels, M1 and M2 are turned off, M3 and M4 are turned on, and the second level voltage signal VGH is transmitted to the target node N. Under the control of the target node N, M5 is turned on, M6 is turned off, and the first level voltage signal VGL of the first level voltage signal terminal Vref1 is transmitted to the input terminal IN of the corresponding shift register unit 101 as a valid start signal.

[0130] When either the first control signal terminal EN1 or the second control signal terminal EN2 is at a high level, M1 or M2 is turned on, M3 and M4 are turned off, and the second level voltage signal VGH is transmitted to the target node N. Under the control of the target node N, M5 is turned off, M6 is turned on, and the second level voltage signal VGH of the second level voltage signal terminal Vref2 is transmitted to the input terminal IN of the corresponding shift register unit 101 as a non-valid start signal.

[0131] And as Fig. 9 As shown, considering that, for example, when the shift register unit 101 is specifically an SN circuit, the shift register unit 101 is high level effective. Therefore, in this case, the first level voltage signal is set to a high level, the second level voltage signal is set to a low level, the channel type of the first switch tube M1, the second switch tube M2 and the fifth switch tube M5 is a P type, the channel type of the third switch tube M3, the fourth switch tube M4 and the sixth switch tube M6 is an N type, and the preset condition is that the level voltage signals provided by the first control signal terminal EN1 and the second control signal terminal EN2 are both high level.

[0132] Thus, when the first control signal terminal EN1 and the second control signal terminal EN2 are both at high levels, M1 and M2 are turned off, M3 and M4 are turned on, and the second level voltage signal VGL is transmitted to the target node N. Under the control of the target node N, M5 is turned on, M6 is turned off, and the first level voltage signal VGH of the first level voltage signal terminal is transmitted to the input terminal IN of the corresponding shift register unit 101 as a valid start signal.

[0133] When either the first control signal terminal EN1 or the second control signal terminal EN2 is at a low level, M1 or M2 is turned on, M3 and M4 are turned off, and the first level voltage signal VGH is transmitted to the target node N. Under the control of the target node N, M5 is turned off, M6 is turned on, and the second level voltage signal VGL of the second level voltage signal terminal Vref2 is transmitted to the input terminal IN of the corresponding shift register unit 101 as a non-valid start signal.

[0134] See below Fig.10 , Fig.10 is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Fig.10As shown, according to some embodiments of the present application, optionally, in order to fully guarantee the separate gate drive control of each display partition in the 2^N display partitions, the input terminal IN of the j-th shift register unit 101 and the output terminal Gout of the j-1-th shift register unit 101 are not cascaded, j>1.

[0135] The sub-pixels in the i-th display partition are electrically connected to M-stage shift register units 101 , which are cascade-connected. The j-th stage shift register unit 101 is the first stage shift register unit 101 among the M-stage shift register units 101 , and M is a positive integer.

[0136] In this way, by controlling the shift register units 101 corresponding to each partition not to be cascaded, the shift register units corresponding to different partitions can be controlled, thereby avoiding the influence of the cascaded shift register units corresponding to different partitions on the partition gate driving control.

[0137] See below Fig.11 , Fig.11 is a schematic diagram of the structure of another gate drive circuit provided in an embodiment of the present application. Fig.11 As shown, according to some embodiments of the present application, optionally, the display panel includes 2^N display partitions and a target display partition, and the gate driving circuit 10 further includes a start signal line STV.

[0138] The target display partition includes L-stage shift register units 101 , the input terminal IN of the k-th stage shift register unit 101 is electrically connected to the start signal line STV, and the k-th stage shift register unit 101 is the first stage shift register unit 101 in the L-stage shift register units 101 .

[0139] The output terminal Gout of the k+L-1th shift register unit 101 is not cascaded with the input terminal IN of the k+Lth shift register unit 101. The k+L-1th shift register unit 101 is the last shift register unit 101 in the L-stage shift register unit 101. k and L are positive integers.

[0140] In this embodiment, in combination with the conventional scheme using the start signal line STV, it is proposed that the display panel includes a target display partition in addition to the aforementioned 2^N display partitions. The start signal line STV is responsible for providing a valid start signal to the first-stage shift register unit 101 corresponding to the target display partition.

[0141] The corresponding shift register units 101 in the target display partition are cascaded, which helps to realize the gate drive control corresponding to the target display partition. However, the last stage shift register unit 101 corresponding to the target display partition is not cascaded with the next stage shift register unit 101, thereby effectively avoiding the influence of the cascade on the individual gate drive control of other display partitions.

[0142] According to some embodiments of the present application, optionally, the 2^N display partitions include a first display partition AA1 and a second display partition AA2, and a refresh frequency of the first display partition AA1 is higher than a refresh frequency of the second display partition AA2.

[0143] In one picture display cycle, the first gate driving frequency corresponding to the first display partition AA1 is higher than the second gate driving frequency corresponding to the second display partition AA2. The first gate driving frequency is equal to the frequency at which the start signal output module 102 corresponding to the first display partition outputs a valid start signal, and the second gate driving frequency is equal to the frequency at which the start signal output module 102 corresponding to the second display partition outputs a valid start signal.

[0144] In this way, by controlling the first gate drive frequency corresponding to the first display partition AA1 to be higher than the second gate drive frequency corresponding to the second display partition AA2, the scanning frequency of the pixels in the first display partition AA1 can be higher than that in the second display partition AA2, thereby achieving a refresh frequency of the first display partition AA1 higher than that of the second display partition AA2.

[0145] It should be added that the first gate driving frequency and the second gate driving frequency can be specifically set according to the refresh frequency required by the corresponding display partition, and their parameter values ​​are not strictly limited here.

[0146] It can be understood that the gate drive circuit 10 includes a light emitting control drive circuit and / or a scan drive circuit. The light emitting control drive circuit can be used to provide a light emitting control signal to a sub-pixel to facilitate light emitting control of the light emitting device in the sub-pixel. The scan drive circuit, such as an SN circuit or an SP circuit, can be used to provide a scan signal to a sub-pixel to facilitate initialization of a transistor in the sub-pixel and threshold compensation, etc., which is not strictly limited in this embodiment.

[0147] It can be understood that, considering the wide application of light-emitting control driving circuits and scanning driving circuit structures in the panel field, for the sake of brevity, the specific circuit structures and specific working processes in the light-emitting control driving circuits and scanning driving circuits are not described in detail in this embodiment.

[0148] Based on the gate driving circuit provided in any of the above embodiments, the present application also provides a display panel, including the gate driving circuit provided in any of the above embodiments. Fig.12 , Fig.12 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Fig.12 As shown, the display panel 100 provided in the embodiment of the present application may include the gate driving circuit 10 described in any of the above embodiments. Fig.12 The display panel shown may be an organic light-emitting diode (OLED) display panel.

[0149] Those skilled in the art should understand that in other implementations of the present application, the display panel may also be a micro light emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0150] The display panel provided in the embodiment of the present application has the beneficial effects of the gate driving circuit 10 provided in the embodiment of the present application. For details, please refer to the specific description of the gate driving circuit 10 in the above embodiments, which will not be repeated in this embodiment.

[0151] Based on the display panel provided in the above embodiment, the present application also provides a display device, including the display panel provided in the present application. Fig.13 , Fig.13 A schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.13 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig.13 In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not impose specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application. For details, reference can be made to the specific description of the display panel 100 in the above embodiments, and this embodiment will not be repeated here.

[0152] It should be understood that the specific structure of the circuit and the cross-sectional structure of the display panel provided in the drawings of the embodiments of the present application are only some examples and are not used to limit the present application. In addition, the above embodiments provided by the present application can be combined with each other if there is no contradiction.

[0153] It should be clear that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in this application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that technicians in the relevant technical field can make good use of the application and the modified use based on the application. The application is only limited by the claims and their full scope and equivalents.

[0154] Those skilled in the art should understand that the above embodiments are exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on the study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to indicate names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A gate drive circuit, characterized in that: Applied to a display panel, the display panel includes 2^N display partitions, N is a positive integer; the gate driving circuit includes: A multi-stage shift register unit, wherein an output end of the shift register unit is electrically connected to at least one row of sub-pixels in the corresponding display partition; 2^N start signal output modules, the 2^N start signal output modules correspond one to one to the 2^N display partitions; the control end of the i-th start signal output module is electrically connected to the first control signal end and the second control signal end corresponding to it, and the output end of the i-th start signal output module is electrically connected to the input end of the j-th shift register unit; The j-th shift register unit is the first shift register unit connected to the i-th display partition corresponding to the i-th start signal output module, i≤2^N, i and j are positive integers; The i-th start signal output module is configured to provide a valid start signal to the input terminal of the j-th stage shift register unit when the level voltage signals provided by the first control signal terminal and the second control signal terminal both meet preset conditions; The first control signal terminal and the second control signal terminal corresponding to any two start signal output modules are not completely consistent.

2. The gate driving circuit according to claim 1, characterized in that: The gate drive circuit further includes N pairs of control signal lines; when one of the control signal lines of a pair of control signal lines provides a high level to its corresponding control signal terminal, the other control signal line provides a low level to its corresponding control signal terminal; The first control signal terminal connected to the i-th start signal output module is electrically connected to any control signal line in the corresponding m-th pair of control signal lines, and the second control signal terminal connected to the i-th start signal output module is electrically connected to any control signal line in the corresponding n-th pair of control signal lines, 1≤m, n≤N, m≠n; Among the 2^N start signal output modules, any two start signal output modules correspond to two different control signal lines.

3. The gate driving circuit according to claim 1, characterized in that: The gate drive circuit further includes N control signal lines and N inverters, and input ends of the N inverters are correspondingly connected to the N control signal lines; The first control signal terminal connected to the i-th start signal output module is electrically connected to the corresponding m-th control signal line, or is electrically connected to the output terminal of the corresponding m-th inverter; The second control signal terminal connected to the start signal output module is electrically connected to the corresponding n-th control signal line, or is electrically connected to the output terminal of the corresponding n-th inverter; The input end of the m-th inverter is electrically connected to the m-th control signal line, and the input end of the n-th inverter is electrically connected to the n-th control signal line, 1≤m, n≤N, m≠n; Among the 2^N start signal output modules, when the control signal lines corresponding to any two start signal output modules are the same, only the first control signal terminal connected to one of the two start signal output modules is connected to the corresponding control signal line through an inverter, and / or, only the second control signal terminal connected to one of the two start signal output modules is connected to the corresponding control signal line through an inverter.

4. The gate driving circuit according to claim 1, characterized in that: The start signal output module includes a first switch unit and a second switch unit; The control end of the first switch unit is electrically connected to the corresponding first control signal end and the second control signal end, and the first switch unit is connected between the first level voltage signal end and the target node; The control end of the first switch unit is electrically connected to the corresponding first control signal end and the second control signal end, and the second switch unit is connected between the target node and the second level voltage signal end; Wherein, the target node is electrically connected to the input end of the j-th stage shift register unit; When the level voltage signal provided by either the first control signal terminal or the second control signal terminal does not meet the preset condition, the first switch unit is turned on, the second switch unit is turned off, and the first level voltage signal provided by the first level voltage signal terminal is transmitted to the target node; When the first control signal terminal and the level voltage signal provided by the second control signal terminal both meet the preset conditions, the first switch unit is turned off and the second switch unit is turned on to transmit the second level voltage signal provided by the second level voltage signal terminal to the target node.

5. The gate driving circuit according to claim 4, characterized in that: The target node is directly electrically connected to the input terminal of the j-th shift register unit, and the j-th shift register unit receives the second level voltage signal as the valid start signal; The j-th stage shift register unit receives the first level voltage signal as a non-valid start signal.

6. The gate driving circuit according to claim 4, characterized in that: The start signal output module also includes a level flip unit; The control end of the level flip unit is electrically connected to the target node, the first end of the level flip unit is electrically connected to the first level voltage signal end, the second end of the level flip unit is electrically connected to the second level voltage signal end, and the output end of the level flip unit is electrically connected to the input end of the j-th stage shift register unit; The level flip unit is configured to transmit the first level voltage signal provided by the first level voltage signal terminal to the input terminal of the j-th stage shift register unit when receiving the second level voltage signal provided by the target node; the j-th stage shift register unit receives the first level voltage signal as the valid start signal; When the first level voltage signal provided by the target node is received, the second level voltage signal provided by the second level voltage signal terminal is transmitted to the input terminal of the j-th shift register unit; the j-th shift register unit receives the second level voltage signal as a non-valid start signal.

7. The gate driving circuit according to claim 4, characterized in that: The first switch unit includes a first switch tube and a second switch tube connected in parallel between the first level voltage signal terminal and the target node; The control end of the first switch tube is electrically connected to the corresponding first control signal end, and the control end of the second switch tube is electrically connected to the corresponding second control signal end; The second switch unit includes a third switch tube and a fourth switch tube connected in series between the target node and the second level voltage signal terminal; The control end of the third switch tube is electrically connected to the corresponding first control end, and the control end of the fourth switch tube is electrically connected to the corresponding second control signal end.

8. The gate driving circuit according to claim 7, characterized in that: The channel types of the first switch tube and the second switch tube are both the first channel type, and the channel types of the third switch tube and the fourth switch tube are both the second channel type; The first channel type is opposite to the second channel type.

9. The gate driving circuit according to claim 8, characterized in that: The j-th stage shift register unit receives the second level voltage signal as the valid start signal; In the case where the shift register unit is low level effective, the first level voltage signal is high level, the second level voltage signal is low level, the first channel type is P type, the second channel type is N type, and the preset condition is that the level voltage signals provided by the first control signal terminal and the second control signal terminal are both high level; When the shift register unit is high level valid, the first level voltage signal is low level, the second level voltage signal is high level, the first channel type is N type, the second channel type is P type, and the preset condition is that the level voltage signals provided by the first control signal terminal and the second control signal terminal are both low level.

10. The gate driving circuit according to claim 8, characterized in that: In the case where the first level voltage signal is the valid start signal, the start signal output module further includes a level flip unit; the level flip unit includes a fifth switch tube and a sixth switch tube; The control end of the fifth switch tube is electrically connected to the target node, the first end of the fifth switch tube is electrically connected to the first level voltage signal end, and the second end of the fifth switch tube is electrically connected to the input end of the j-th stage shift register unit; The control end of the sixth switch tube is electrically connected to the target node, the first end of the fifth switch tube is electrically connected to the second level voltage signal end, and the second end of the fifth switch tube is electrically connected to the input end of the j-th stage shift register unit; The channel type of the fifth switch tube is the first channel type, and the channel type of the sixth switch tube is the second channel type.

11. The gate driving circuit according to claim 10, characterized in that: The j-th stage shift register unit receives the first level voltage signal as the valid start signal; In the case where the shift register unit is low level effective, the first level voltage signal is low level, the second level voltage signal is high level, the first channel type is N type, the second channel type is P type, and the preset condition is that the level voltage signals provided by the first control signal terminal and the second control signal terminal are both low level; When the shift register unit is high level valid, the first level voltage signal is high level, the second level voltage signal is low level, the first channel type is N type, the second channel type is P type, and the preset condition is that the level voltage signals provided by the first control signal terminal and the second control signal terminal are both high level.

12. The gate driving circuit according to claim 1, characterized in that: The input end of the j-th shift register unit is not cascaded with the output end of the j-1-th shift register unit, j>1; The sub-pixels in the i-th display partition are electrically connected to M-stage shift register units, the M-stage shift register units are cascade-connected, the j-th stage shift register unit is the first stage shift register unit among the M-stage shift register units, and M is a positive integer.

13. The gate driving circuit according to claim 1, characterized in that: The display panel includes the 2^N display partitions and the target display partition, and the gate drive circuit further includes a start signal line; The target display partition includes L-stage shift register units, an input end of the k-th stage shift register unit is electrically connected to the start signal line, and the k-th stage shift register unit is a first-stage shift register unit in the L-stage shift register units; The output end of the k+L-1th shift register unit is not cascaded with the input end of the k+Lth shift register unit, the k+L-1th shift register unit is the last shift register unit in the L-stage shift register units, and k and L are positive integers.

14. The gate driving circuit according to claim 1, characterized in that: The 2^N display partitions include a first display partition and a second display partition, and a refresh frequency of the first display partition is higher than a refresh frequency of the second display partition; In a picture display cycle, the first gate drive frequency corresponding to the first display partition is higher than the second gate drive frequency corresponding to the second display partition; wherein the first gate drive frequency is equal to the frequency at which the start signal output module corresponding to the first display partition outputs the valid start signal, and the second gate drive frequency is equal to the frequency at which the start signal output module corresponding to the second display partition outputs the valid start signal.

15. A display panel, characterized in that: The display panel comprises the gate driving circuit as described in any one of claims 1-14.

16. A display device, characterized in that: The display device comprises the display panel as claimed in claim 15 .

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