Display panel, driving method thereof and display device

Abstract

The invention discloses a display panel and a driving method thereof and a display device.The display panel of one embodiment comprises a display area and a non-display area, a first area of the non-display area comprises a binding area, and the display area comprises at least two sub-display areas which are sequentially arranged in the direction away from the binding area; the third area comprises at least one group of first shift register circuits which are sequentially cascaded in the first direction, the sub-display area, close to the second area, in the sub-display areas is a second sub-display area, and the other sub-display areas form a first sub-display area; among the first shift register circuits corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the clock signal received by the first shift register circuit close to the first area and marking a falling edge. According to the embodiment of the invention, the charging time of the near-end clock signal and the far-end clock signal is prolonged, and the display uniformity is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] AMOLED (Active-matrix organic light-emitting diode) displays rely on organic light-emitting diodes to emit light autonomously, and have excellent display effects. In order to improve the competitiveness of the screen, the frame uses an array process to prepare a shift register (GOA) to drive the lighting of the AMOLED. However, the timing of the GOA is provided by the display driver chip. The timing signal varies at different distances from the display driver chip, resulting in uneven screen display. Summary of the invention

[0003] In order to solve at least one of the above problems, a first aspect of the present disclosure provides a display panel, comprising: a display area and a non-display area, the non-display area comprising a first area and a second area arranged opposite to each other, and a third area arranged between the first area and the second area, the first area comprising a binding area, the display area comprising at least two sub-display areas arranged in sequence along a first direction, the first direction being a direction away from the binding area,

[0004] The third area includes at least one group of first shift register circuits arranged in cascade sequence along the first direction, each first shift register circuit provides a scanning signal to at least one corresponding row of pixel units in the display area,

[0005] The display area includes a first sub-display area and a second sub-display area, wherein the sub-display area close to the second area in the sub-display area is the second sub-display area, and the other sub-display areas constitute the first sub-display area, and the rising edge of the clock signal received by the first shift register circuit far away from the first area in the first shift register circuit corresponding to the first sub-display area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

[0006] Optionally, there is a bending area between the sub-display areas.

[0007] For each group of cascaded first shift register circuits, the non-display area further includes: a first clock signal line and a second clock signal line arranged in the third area and extending along the first direction, and a first compensation signal line and a second compensation signal line extending along the first direction,

[0008] One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit is electrically connected to a first clock signal line, and the other is electrically connected to a second clock signal line, the first clock signal line receives a first clock signal, and the second clock signal line receives a second clock signal,

[0009] The first compensation signal line is electrically connected to the first outer folded end of the first clock signal line and receives the first compensation signal, the second compensation signal line is electrically connected to the second outer folded end of the second clock signal line and receives the second compensation signal, the first outer folded end and the second outer folded end are located in an extended area of ​​the third area in the bending area away from the binding area,

[0010] The first compensation signal is at an invalid level during a scanning period of each row of pixel units in the second sub-display area, and the first clock signal provided during a scanning period of each row of pixel units in the first sub-display area is the same as the first clock signal provided during the scanning period.

[0011] The second compensation signal is at an invalid level during the scanning period of each row of pixel units in the second sub display area, and the second clock signal provided during the scanning period of each row of pixel units in the first sub display area is the same.

[0012] Optionally, a bending area is between the first sub-display area and the second sub-display area.

[0013] For each group of cascaded first shift register circuits, the non-display area further includes: a first clock signal line, a second clock signal line and a first initial compensation signal line which are arranged in the third area and extend along the first direction,

[0014] The display area includes: a first display mode in which the first sub-display area displays a picture and the second sub-display area does not display a picture,

[0015] One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line, and the first initial compensation signal line is electrically connected to the first shift register circuit farthest from the first area among the first shift register circuits corresponding to the first sub-display area.

[0016] In the first display mode, the first clock signal line is at an invalid level during a scanning time period of each row of pixel units corresponding to the second sub-display area, and provides a first clock signal during a scanning time period of each row of pixel units corresponding to the first sub-display area, the second clock signal line is at an invalid level during a scanning time period of each row of pixel units corresponding to the second sub-display area, and provides a second clock signal during a scanning time period of each row of pixel units corresponding to the first sub-display area, and the first initial compensation signal line provides an initial signal to the first shift register circuit in the first sub-display area that is farthest from the first area.

[0017] Optionally, for each group of cascaded first shift register circuits, the non-display area further includes: at least two clock signal line groups arranged in the third area and extending along the first direction, the clock signal line groups are arranged in a one-to-one correspondence with the sub-display areas, and each clock signal line group includes a first clock signal line and a second clock signal line.

[0018] One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit in each sub-display area is electrically connected to the first clock signal line of a corresponding group of clock signal line groups, and the other is electrically connected to the second clock signal line of the group of clock signal line groups, and,

[0019] In the clock signal line group, the first clock signal line provides a first clock signal during the scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods. The first clock signal line provides a second clock signal during the scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods.

[0020] Optionally, the first clock signal and the second clock signal are both periodic signals in which high level and low level are alternately arranged.

[0021] During the period when the first clock signal is at a valid level, the second clock signal is at an invalid level for at least part of the period; during the period when the second clock signal is at a valid level, the first clock signal line is at an invalid level for at least part of the period.

[0022] Optionally, the first clock signal and the second clock signal are inverted signals.

[0023] Optionally, the first clock signal terminal and the second clock signal terminal of the first shift register circuit generate a scanning signal of the corresponding row of pixel units based on the received clock signal.

[0024] Optionally, the display area includes three sub-display areas.

[0025] A second aspect of the present disclosure provides a display device, comprising the display panel described above.

[0026] A third aspect of the present disclosure provides a display driving method applied to the display panel described above, the method comprising:

[0027] In the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a schematic structural diagram of a display panel driven by GOA;

[0030] Figure 2 is a timing diagram of shift register clock signals corresponding to the far end and the near end of the display area in the related art;

[0031] Figure 3 It is a timing superposition comparison diagram of the shift register clock signals corresponding to the far end and the near end of the display area in the related art;

[0032] Figure 4 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0033] Figure 5 Based on Figure 4 A clock signal timing diagram of a first shift register circuit of a display panel of the embodiment shown;

[0034] Figure 6 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0035] Figure 7 Based on Figure 6 A clock signal timing diagram of a first shift register circuit of a display panel of the embodiment shown;

[0036] Figure 8 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0037] Fig. 9 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0038] Fig.10 Based on Fig. 9 The clock signal timing diagram of the first shift register circuit of the display panel of the embodiment shown is shown.

[0039] The beneficial effects of the present disclosure are as follows:

[0040] In response to the existing problems, the present disclosure develops a display panel, a driving method thereof, and a display device, and improves the consistency of charging time of clock signals received by the near-end and far-end first shift register circuits by setting the rising edge of the clock signal received by the first shift register circuit close to the first area in the first shift register circuit corresponding to the first sub-display area to be close to the rising edge of the clock signal received by the first shift register circuit far away from the first area and the falling edge to be close to the falling edge of the clock signal received by the first shift register circuit far away from the first area, thereby improving display uniformity, and having broad application prospects. DETAILED DESCRIPTION

[0041] In order to more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present disclosure.

[0042] It should be noted that the ordinal numbers such as "first", "second", "third", etc. in this document are not intended to limit the order of the various units, nodes, elements or components, but are only intended to distinguish the various units, nodes, elements or components. The meanings of "including", "comprising", and "having" in this document are open-ended. For example, when describing including units, nodes, elements or components, in addition to these included units, nodes, elements or components, other units, nodes, elements or components may also be included.

[0043] Reference Figure 1 As shown, the display panel that uses GOA to provide scanning signals for the pixel units in the display area requires a display driver chip to provide a signal for driving each shift register circuit in the GOA, and the display driver chip is located on the display panel or on a flexible circuit board bound to the display panel. In this example, the display driver chip is located in the non-display area below the display panel. Figure 1 It can be seen from the partial enlarged view in that a plurality of signal lines are arranged in the non-display area on the left side of the display area, and one end of these signal lines is electrically connected to the display driver chip to provide the signal provided by the display driver chip to each shift register circuit. There is a difference in the length of the line close to the display driver chip and the position far from the driver chip, which leads to a difference in RC loading at the near end and the far end of the display area.

[0044] Reference Figure 2 and Figure 3 As shown, Figure 2The three signals on the top represent the signals connected to the input terminal STV, the first clock signal terminal CK, and the second clock signal terminal CB of the shift register circuit located at the near end of the display area. The three signals on the bottom represent the signals connected to the input terminal STV, the first clock signal terminal CK, and the second clock signal terminal CB of the shift register circuit located at the far end of the display area. Figure 3 Show Figure 2 The superposition comparison diagram of the two groups of signals in . The initial signal provided by the initial signal line STV is only connected to the input end of the shift register circuit at the first stage of GOA, and the input end of the shift register circuit at other stages is connected to the cascade signal of the previous stage in turn, which does not cause the RC load difference. However, the first clock signal end CK and the second clock signal end CB of all the cascaded shift register circuits are respectively connected to the same first clock signal line CK and the second clock signal. Due to the different wiring lengths, the RC load difference is caused, and then due to the RC load difference, the charging time at the near end and the far end is significantly different, because the closer to the display driver chip, the stronger the signal driving ability, and the farther from the display driver chip, the greater the RC value caused by the resistance of the signal line itself, the longer the charging time, the rising edge time Tr and the falling edge time Tf of the clock signal end of the near-end shift register circuit are shorter, and the rising edge time Tr and the falling edge time Tf of the clock signal end of the far-end shift register circuit are longer, resulting in uneven display at the far end and the near end of the display product. In particular, for folding display products with multiple display areas, the display screen is larger, and the display area away from the display driver chip is farther away than the near end, resulting in more significant display unevenness and more obvious visual display uniformity differences.

[0045] In view of this, the display panel of the embodiment of the present disclosure includes: a display area and a non-display area, the non-display area includes a first area and a second area arranged opposite to each other, and a third area arranged between the first area and the second area, the first area includes a binding area, the display area includes at least two sub-display areas arranged in sequence along a first direction, the first direction is a direction away from the binding area,

[0046] The third area includes at least one group of first shift register circuits arranged in cascade sequence along the first direction, each first shift register circuit provides a scanning signal to at least one corresponding row of pixel units in the display area,

[0047] The display area includes a first sub-display area and a second sub-display area. The sub-display area close to the second area in the sub-display area is the second sub-display area, and the other sub-display areas constitute the first sub-display area. In the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area is close to the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge is close to the falling edge of the clock signal received by the first shift register circuit close to the first area.

[0048] In this embodiment, in the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area is close to the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge is close to the falling edge of the clock signal received by the first shift register circuit close to the first area, thereby improving the charging time consistency of the clock signals received by the near-end and far-end first shift register circuits, thereby improving display uniformity.

[0049] In a specific embodiment, referring to Figure 4 As shown, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes first areas NA1 and NA2 arranged opposite to each other, and a third area NA3 arranged between the first area NA1 and the second area NA2. In this example, the third area NA3 refers to an area of ​​the non-display area located between the first area NA1 located at the upper part and the second area NA2 located at the lower part in the figure, and located on the left and right sides of the display area AA.

[0050] The first area NA1 includes a binding area 11. If the display driver chip is located on the display panel, the binding area 11 may be a binding area for binding the display driver chip. If the display driver chip is not located on the display panel but is located on a flexible circuit board or other circuit boards, the binding area 11 may be a binding area for binding the flexible circuit board. In other words, the signal for providing the first shift register circuit in the GOA is derived from the first area NA1, that is, for the display area AA, the end close to the first area NA1 is the proximal end, and the end away from the first area NA1 is the distal end.

[0051] Continue to refer to Figure 4 As shown, the display area AA includes three sub-display areas AA-1, AA-2 and AA2 arranged in sequence along the first direction, and the first direction is the direction away from the first area NA1, that is, the Y direction in the figure. Among the three sub-display areas AA-1, AA-2 and AA2, the sub-display area away from the first area NA1 is the second sub-display area, which is indicated by the label "AA2", and the other sub-display areas AA-1 and AA-2 constitute the first sub-display area, which is indicated by the label "AA1".

[0052] like Figure 4 As shown, in this example, the sub-display areas are bending areas, the bending area between the sub-display area AA-1 and the sub-display area AA-2 is the bending area 121, and the bending area between the first sub-display area AA1 and the second sub-display area AA2 is the bending area 122. The bending area 122 is arranged away from the first area NA1 relative to the bending area 121, for example: the bending area 122 can be called an "outer bending area", and the bending area 121 can be called an "inner folding area".

[0053] Figure 4 It is shown that the third area NA3 located on the left side of the display area AA includes a group of first shift register circuits cascaded in sequence along the first direction, and each first shift register circuit provides a scan signal to a corresponding row of pixel units in the display area AA.

[0054] Specifically, the cascaded first shift register circuits scan pixel units step by step with a row of pixel units away from the first area NA1 as the first row, thereby driving the display area AA to display a picture. Therefore, the first shift register circuit G_1 away from the end of the first area NA1 is the first stage first shift register circuit.

[0055] Reference Figure 4 As shown, the first-stage first shift register circuit G_1 to the A-stage first shift register circuit G_A in the group of cascaded first shift register circuits correspond to the A-row pixel units of the second sub-display area AA2; the A+1-stage first shift register circuit G_A+1 to the B-stage first shift register circuit G_B correspond to the B-(A)-row pixel units of the sub-display area AA-2 far away from the first area NA1 in the second sub-display area AA2; the B+1-stage first shift register circuit G_B+1 to the N-stage first shift register circuit G_N correspond to the N-(B)-row pixel units of the sub-display area AA-1 close to the first area NA1 in the second sub-display area AA2, and each stage of the first shift register circuit provides a scanning signal to a row of pixel units corresponding thereto, and A, B and N are positive integers greater than 1. When no distinction is required, the first shift register circuits are collectively referred to as first shift register circuits G.

[0056] It should be noted that, in the present disclosure, the cascaded first shift register circuit outputs scanning signals stage by stage, but it is not intended to limit the cascaded first shift register circuit to scan adjacent rows of pixel units in the display area row by row. In other words, illustratively, each level of the first shift register circuit in a group of first shift register circuits can only correspond to odd-numbered rows of pixel units in the display area AA, and scan these rows in sequence stage by stage. Of course, each level in a group of first shift register circuits can also only scan even-numbered rows of pixel units or other alternate rows of pixel units. In addition, a first shift register circuit can also scan multiple rows of pixel units at the same time, which is not elaborated in this article.

[0057] It should also be noted that although Figure 4The example of FIG. 1 shows a circuit structure of a group of cascaded first shift register circuits, but the present disclosure does not intend to limit the number of groups of cascaded first shift register circuits in the third area NA3 and the position of each group of first shift register circuits. For example, the third area NA3 may include multiple groups of first shift register circuits, and one or more groups are arranged in the third area NA3 on the left, and one or more groups are arranged in the third area NA3 on the right, which will not be described in detail herein.

[0058] Continue to refer to Figure 4 As shown, the non-display area NA further includes: a first clock signal line CK and a second clock signal line CB arranged in the third area NA3 and extending along the first direction Y, and a first compensation signal line CK1 and a second compensation signal line CB1 extending along the first direction Y, wherein the first shift register circuit G can respond to the signal control of the first clock signal line CK and the second clock signal line CB to output the scan signal and shift step by step. The first clock signal line CK is electrically connected to the first clock signal terminal of each first shift register circuit G and receives the first clock signal, and the second clock signal line CB is electrically connected to the second clock signal terminal of each first shift register circuit G and receives the second clock signal.

[0059] One of the first clock signal terminal ck and the second clock signal terminal cb of each first shift register circuit G is electrically connected to the first clock signal line CK, and the other is electrically connected to the second clock signal line CB. Figure 5 As shown, the first clock signal line CK is connected to the first clock signal, and the second clock signal line CB is connected to the second clock signal.

[0060] Of course, in order to simplify the view, the figure does not reflect the initial signal line STV that provides the initial signal, and the input end in the first shift register circuit of each stage. It should be understood that the input end of the first shift register circuit of the first stage is connected to the initial signal line, and the first shift register circuits of each stage are cascaded with the cascade end of the previous stage through the input end.

[0061] Combination Figure 4 and Figure 5 As shown, the first compensation signal line CK1 is electrically connected to the first outer folded end N1 of the first clock signal line CK and receives the first compensation signal, the second compensation signal line CB1 is electrically connected to the second outer folded end N2 of the second clock signal line CB and receives the second compensation signal, and the first outer folded end N1 and the second outer folded end N2 are located in the extension area of ​​the bending area 122 away from the binding area 11 in the third area NA3 (the area defined by the dotted extension line of the bending area boundary in the figure). For clarity, the symbols of the corresponding clock signal lines are used in the figure to represent the signals received by the clock signal lines.

[0062] Optionally, the length of the first compensation signal line CK1 is shorter than the length of the first clock signal line CK, and the length of the second compensation signal line CB1 is shorter than the length of the second clock signal line CB.

[0063] With this configuration, at the compensation position, the signal line resistance of the first compensation signal line CK1 is smaller than that of the first clock signal line CK, and the signal line resistance of the second compensation signal line CB1 is smaller than that of the second clock signal line CB.

[0064] In addition, the first compensation signal line CK1 may be disposed on a side of the first clock signal line CK away from the display area AA, and the second compensation signal line CB1 may be disposed on a side of the second clock signal line CB away from the display area AA.

[0065] Reference Figure 5 As shown, the first compensation signal is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and is the same as the first clock signal provided during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1; the second compensation signal is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and is the same as the second clock signal provided during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1.

[0066] Through this setting, considering that the farther the signal line is from the first area NA1, the greater the signal line load RC is, the more significant the impact on the charging time of the rising edge and the falling edge of the signal loaded on the first signal terminal ck and the second signal terminal cb is, and the first clock signal of the first clock signal line CK and the second clock signal of the second clock signal line CB are scanned from the farthest end of the display area as the first row to the near end in sequence. In order to supplement the first compensation signal and the second compensation signal as the starting point at the first outer fold end N1 and the second outer fold end N2 to enhance the far-end driving capability, it is necessary to consider the actual arrival time at the compensation end, that is, the first compensation signal and the second compensation signal at the second sub The time period corresponding to the display area AA2 is an invalid level (the invalid level is a high level in this example), and the scanning period of each row of pixel units in the first sub-display area AA1 is the same as the first clock signal and the second clock signal, respectively, thereby ensuring that the rising edge of the clock signal connected to the shift register circuit far away from the first area NA1 is consistent with the rising edge of the clock signal connected to the shift register circuit closer to the first area NA1, and at the same time ensuring that the falling edge of the clock signal connected to the shift register circuit far away from the first area NA1 is consistent with the falling edge of the clock signal connected to the shift register circuit in the first area NA1, thereby improving display uniformity.

[0067] It should be noted that for the shift register circuit G_1 to G_A corresponding period, the first compensation signal CK1 and the second compensation signal CB2 input invalid level signals, which is equivalent to not making compensation at the position corresponding to the period, and the compensation position is at the position of the shift register circuit G_A+1. In addition, although the invalid level is a high level in this example, it is not limited to this. Depending on the structure and driving principle of the shift register circuit, the invalid level can also be a low level, which will not be elaborated in this article.

[0068] Optionally, the first clock signal and the second clock signal are both periodic signals with high level and low level alternately arranged. During the period ② when the first clock signal is at a valid level, at least part of the period ① when the second clock signal is at an invalid level, and during the period when the second clock signal is at a valid level, at least part of the period when the first clock signal line is at an invalid level.

[0069] Reference Figure 5 As shown, in this example, the high level is an invalid level, the low level is a valid level, in the period ② when the first clock signal is at a low level, the period ① of the second clock signal is at a high level, in the period ③ when the second clock signal is at a low level, the period ④ of the first clock signal is at a high level.

[0070] Of course, those skilled in the art should understand that the first clock signal and the second clock signal are not limited thereto, and the first clock signal and the second clock signal may be inverted signals of each other.

[0071] In some other optional embodiments, refer to Figure 6 and Figure 7 As shown, another structure of a display panel is shown in the figure. Figure 4 The difference between the display panels shown is that, in this embodiment, the first clock signal line and the second clock signal line are not electrically connected to the compensation signal line, but when the display area is set to the first display mode in which the first sub-display area AA1 displays the picture and the second sub-display area AA2 does not display the picture, the first clock signal line CK is at an invalid level during the scanning time period of the corresponding rows of pixel units in the second sub-display area AA2, and provides the first clock signal during the scanning time period of the corresponding rows of pixel units in the first sub-display area AA1, and the second clock signal line CB is at an invalid level during the scanning time period of the corresponding rows of pixel units in the second sub-display area AA2, and provides the second clock signal during the scanning time period of the corresponding rows of pixel units in the first sub-display area AA1.

[0072] Exemplarily, in the first display mode, the first clock signal terminal ck and the second clock signal terminal cb of the first shift register circuit corresponding to the second sub-display area AA2 do not generate a scan signal due to receiving an invalid level, thereby not scanning and refreshing the pixel unit, and the first shift register circuit corresponding to the first sub-display area AA1 normally outputs a scan signal under the drive of the first clock signal and the second clock signal, thereby enabling the second sub-display area AA2 to display the picture.

[0073] In addition, because the first stage of the first shift register circuit is located at the remote end, and the initial signal should be fed into the first shift register circuit located at the first stage via the initial signal line STV during normal display, in order to enable the initial signal to be normally transmitted to the first shift register circuit corresponding to the first sub-display area AA1 when the second sub-display area AA2 does not generate a normal output, refer to Figure 7 As shown, the non-display area NA further includes a first initial compensation signal line STV1, and the first initial compensation signal line STV1 is electrically connected to the first shift register circuit G_A+1 farthest from the first area NA1 among the first shift register circuits G_A+1-G_N corresponding to the first sub-display area AA1. In the first display mode, the first initial compensation signal line STV1 provides an initial signal to the first shift register circuit G_A+1 farthest from the first area NA1 among the first shift register circuits of the first sub-display area AA1. Specifically, if the input terminal of the first shift register circuit G_A+1 is stv, the first initial compensation signal line STV1 is electrically connected to the input terminal stv.

[0074] The connection relationship between the first shift register circuit G and the first clock signal lines CK and CB in cascade is the same as Figure 4 The example shown is similar and will not be described in detail here. The first clock signal terminal ck and the second clock signal terminal cb of the first shift register circuit G generate a scanning signal of the corresponding row of pixel units based on the received clock signal.

[0075] Through the above settings, when the second sub-display area AA2 does not need to display a picture, for example, if the bending area 122 is used as an outer folding area and the second sub-display area AA2 is folded outward to the back of the first sub-display area AA1 so that the second sub-display area AA2 does not serve as a display screen facing the user, by setting the first clock signal line CK and the second clock signal line CB to the invalid level of the high level during the scanning period of the corresponding display units of each row of the second sub-display area AA2, that is, the period in which the first shift register G_1 to G_A needs to be driven to work, so that there is no charging and discharging period of clock high-low conversion during this period, which is equivalent to the end of the first sub-display area AA1 away from the first area NA1 starting as the starting end of the first clock signal and the second clock signal, thereby eliminating the load influence of the first clock signal line and the second clock signal line in the second sub-display area AA2, thereby improving the consistency of the rising edge and falling edge of the signal received by the first clock signal terminal ck and the second clock signal terminal cb of the first shift register circuit G at the near end and the far end in the first sub-display area AA1, and improving the display uniformity. At the same time, through this setting, the display driving power consumption of the display driver chip in the first display mode can also be reduced.

[0076] In some other optional embodiments, refer to Figure 8 As shown, in Figure 4 On the basis of the display panel shown, the display area may also include a first display mode in which the first sub-display area AA1 displays a picture and the second sub-display area AA2 does not display a picture. Figure 6 The area filled with the middle fill pattern represents a black screen where no image is displayed.

[0077] In the first display mode, the first clock signal line CK is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and provides the first clock signal during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1, and the second clock signal line CB is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and provides the second clock signal during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1. At the same time, the first compensation signal line CK1 and the second clock signal line CK2 are not connected to a valid signal. In the present disclosure, the first compensation signal line CK1 and the second clock signal line CK2 are not connected to a valid signal, which means that neither of them is connected to a signal or both are only connected to an invalid level signal.

[0078] Reference Figure 8As shown, the non-display area NA further includes a first initial compensation signal line STV1, and the first initial compensation signal line STV1 is electrically connected to the first shift register circuit G_A+1 farthest from the first area NA1 among the first shift register circuits G_A+1-G_N corresponding to the first sub-display area AA1. In the first display mode, the first initial compensation signal line STV1 provides an initial signal to the first shift register circuit G_A+1 farthest from the first area NA1 among the first shift register circuits of the first sub-display area AA1. Specifically, if the input terminal of the first shift register circuit G_A+1 is stv, the first initial compensation signal line STV1 is electrically connected to the input terminal stv.

[0079] Through this arrangement, when the second sub-display area AA2 does not need to display the picture, it is equivalent to that the end of the first sub-display area AA1 away from the first area NA1 becomes the starting end of the first clock signal and the second clock signal, thereby eliminating the load influence of the first clock signal line and the second clock signal line in this part of the second sub-display area AA2, thereby improving the consistency of the rising edge and falling edge of the signal received by the first clock signal terminal ck and the second clock signal terminal cb of the first shift register circuit G at the near end and the far end in the first sub-display area AA1, thereby improving the display uniformity.

[0080] At the same time, the setting can make full use of the display characteristics to ensure that when both the first sub-display area AA1 and the second sub-display area AA2 need to be displayed, the timing consistency of the near-end and far-end clock signal ends is improved, the display uniformity is improved, and the display uniformity can be achieved in the first display mode. In addition, in the first display mode, the driving difficulty of the display driver chip can be reduced, and when the first compensation signal line and the second compensation signal line are not connected to the signal, the driving power consumption of the display drive signal can be reduced.

[0081] In some other optional embodiments, this embodiment provides a display panel of another structure, which differs from the above-mentioned display panel in that, for a group of cascaded first shift register circuits G, the non-display area NA includes: at least two clock signal line groups arranged in the third area NA3 and extending along the first direction Y, the clock signal line groups are arranged one-to-one corresponding to the sub-display areas, and each of the clock signal line groups includes a first clock signal line and a second clock signal line.

[0082] Specific to Fig. 9In the example shown, the display area AA includes three sub-display areas AA-1, AA-2 and AA2. For the group of cascaded first shift register circuits G, the sub-display area AA2 corresponds to the clock signal line group consisting of the first clock signal line CK1 and the second clock signal line CB1, the sub-display area AA-2 corresponds to the clock signal line group consisting of the first clock signal line CK2 and the second clock signal line CB2, and the sub-display area AA-1 corresponds to the clock signal line group consisting of the first clock signal line CK3 and the first clock signal line CB3.

[0083] One of the first clock signal terminal and the second clock signal terminal of each first shift register circuit in each sub-display area is electrically connected to the first clock signal line of a corresponding group of clock signal line groups, and the other is electrically connected to the second clock signal line of the group of clock signal line groups.

[0084] Specific to Fig. 9 As shown, one of the first clock signal terminals ck and the second clock signal terminals cb of the first shift register circuits G_1 to G_A corresponding to the sub-display area AA2 is electrically connected to the first clock signal line CK1, and the other is electrically connected to the second clock signal line CB1. One of the first clock signal terminals ck and the second clock signal terminals cb of the first shift register circuits G_A+1 to G_B corresponding to the sub-display area AA-2 is electrically connected to the first clock signal line CK2, and the other is electrically connected to the second clock signal line CB2. One of the first clock signal terminals ck and the second clock signal terminals cb of the first shift register circuits G_B+1 to G_N corresponding to the sub-display area AA-2 is electrically connected to the first clock signal line CK3, and the other is electrically connected to the second clock signal line CB3.

[0085] In the clock signal line group, the first clock signal line provides a first clock signal during the scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods. The first clock signal line provides a second clock signal during the scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods.

[0086] Combination Fig. 9 and Fig.10As shown, the first level of the cascaded first shift register circuit G far away from the first area NA1 is the first level, and from this level onwards, the first clock signal terminal ck and the second clock signal terminal cb of the first shift register circuit G of each level are sequentially connected to the corresponding clock signal to generate the scanning signal in sequence. Then the first clock signal line CK1 and the second clock signal line CB1 electrically connected to the first shift register circuits G_1 to G_A corresponding to the sub-display area AA2 are only connected to the first clock signal and the second clock signal during the scanning time period of each row of pixel units corresponding to these first shift register circuits, and the other time periods are invalid levels. Correspondingly, the first clock signal line CK2 and the second clock signal line CB2 electrically connected to the first shift register circuits G_A+1 to G_B corresponding to the sub-display area AA-2 are only connected to the first clock signal and the second clock signal during the scanning time period of each row of pixel units corresponding to these first shift register circuits, and the other time periods are invalid levels. The first clock signal line CK3 and the second clock signal line CB3 electrically connected to the first shift register circuits G_B+1 to G_N corresponding to the sub-display area AA-1 are only connected to the first clock signal and the second clock signal during the scanning time period of each row of pixel units corresponding to these first shift register circuits, and are invalid levels in other time periods.

[0087] Through this setting, it can be ensured that the first clock signal line and the second clock signal line of the first shift register circuit corresponding to each sub-display area are driven starting from the corresponding sub-display area, so that the length of the signal line that actually affects the RC load is cut into multiple sections, which is equivalent to greatly shortening the length of the signal line, thereby reducing the attenuation caused by the RC load of the signal line corresponding to each sub-display area. Thereby, the consistency of the rising edge of the clock signal of the first shift register circuit at the end of the first sub-display area AA1 close to the first area NA1 and the rising edge of the clock signal of the first shift register circuit far from the first area NA1 is greatly improved, and the consistency of the falling edge of the clock signal of the first shift register circuit at the end of the first sub-display area AA1 close to the first area NA1 and the falling edge of the clock signal of the first shift register circuit far from the first area NA1 is improved, thereby improving display uniformity.

[0088] Optionally, the length of the first clock signal line CK1 is greater than the length of the first clock signal line CK2, the length of the first clock signal line CK2 is greater than the length of the first clock signal line CK3, and the length of the second clock signal line CB1 is greater than the length of the second clock signal line CB2, the length of the second clock signal line CB2 is greater than the length of the second clock signal line CB3.

[0089] Through this setting, the signal line length is adjusted according to the area driven by each group of first clock signal lines and second clock signal lines, so as to reduce the signal line length corresponding to the sub-display area close to the first area NA1, and minimize the influence of the signal line coupling capacitance and signal line resistance on the RC load.

[0090] It should be noted that other structural features of the display panel of this embodiment are the same as those described above. Figure 4 The structures of the embodiments shown are similar and will not be described in detail here.

[0091] Based on the same inventive concept, an embodiment of the present disclosure also provides a driving method applied to the display panel described in the above embodiment, including: in the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

[0092] Optionally, refer to Figure 5 As shown, for Figure 4 In the structure shown, when display driving is performed, the first clock signal line CK is connected to the first clock signal, the second clock signal line CB is connected to the second clock signal, the first compensation signal CK1 is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and is the same as the first clock signal provided during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1, the second compensation signal CB1 is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and is the same as the second clock signal provided during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1.

[0093] Optionally, refer to Figure 7 As shown, for Figure 6 In the structure shown, when display driving is performed, in the first display mode, the first clock signal line CK is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and provides the first clock signal during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1, and the second clock signal line CB is at an invalid level during the scanning time period of each row of pixel units corresponding to the second sub-display area AA2, and provides the second clock signal during the scanning time period of each row of pixel units corresponding to the first sub-display area AA1.

[0094] Alternatively, for Figure 8 The structure shown in the figure is in the first display mode, except that the first clock signal line CK and the second clock signal line CB are connected to Figure 6Outside the timing shown, the first compensation signal line CK1 and the second compensation signal line CB1 are not connected to a signal or are connected to an invalid level.

[0095] Optionally, refer to Fig.10 As shown, for Fig. 9 In the structure shown, when the display is driven, in each clock signal line group, the first clock signal line provides a first clock signal during a scanning time period of each row of pixel units in a corresponding sub-display area, and is at an invalid level in other time periods; the first clock signal line provides a second clock signal during a scanning time period of each row of pixel units in a corresponding sub-display area, and is at an invalid level in other time periods.

[0096] Through the above arrangement, the charging time consistency of the clock signals received by the near-end and far-end first shift register circuits can be improved, thereby improving display uniformity.

[0097] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, comprising the display panel described in the above embodiment.

[0098] Since the display panel included in the display device provided in the embodiment of the present disclosure corresponds to the display panel provided in the above embodiment, the previous implementation is also applicable to this embodiment and will not be described in detail in this embodiment.

[0099] In this embodiment, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a car display, a digital photo frame or a navigator, especially a large foldable product with multiple bending ends. By loading the above display panel, the display device can have a uniform display effect and has broad application prospects.

[0100] It is obvious from the present disclosure that the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area, the non-display area including a first area and a second area arranged opposite to each other, and a third area arranged between the first area and the second area, the first area including a binding area, the display area including at least two sub-display areas arranged in sequence along a first direction, the first direction being a direction away from the binding area, The third area includes at least one group of first shift register circuits sequentially cascaded along the first direction, each of the first shift register circuits provides a scanning signal to at least one corresponding row of pixel units in the display area, The display area includes a first sub-display area and a second sub-display area, wherein the sub-display area close to the second area is the second sub-display area, and the other sub-display areas constitute the first sub-display area. In the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area is close to the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge is close to the falling edge of the clock signal received by the first shift register circuit close to the first area.

2. The display panel according to claim 1, characterized in that: The bending area is between the sub-display areas. For each group of cascaded first shift register circuits, the non-display area further includes: a first clock signal line and a second clock signal line arranged in the third area and extending along the first direction, and a first compensation signal line and a second compensation signal line extending along the first direction, One of the first clock signal terminal and the second clock signal terminal of each of the first shift register circuits is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line, the first clock signal line receives a first clock signal, and the second clock signal line receives a second clock signal, The first compensation signal line is electrically connected to a first outer folded end of the first clock signal line and receives a first compensation signal, the second compensation signal line is electrically connected to a second outer folded end of the second clock signal line and receives a second compensation signal, the first outer folded end and the second outer folded end are located in an extension area of ​​the bending area away from the binding area in the third area, The first compensation signal is at an invalid level during a scanning period of each row of pixel units corresponding to the second sub display area, and the first clock signal provided during a scanning period of each row of pixel units corresponding to the first sub display area is the same. The second compensation signal is at an invalid level during a scanning period of each row of pixel units in the second sub-display area, and the second clock signal provided during a scanning period of each row of pixel units in the first sub-display area is the same.

3. The display panel according to claim 1, characterized in that: A bending area is between the first sub-display area and the second sub-display area. For each group of cascaded first shift register circuits, the non-display area further includes: a first clock signal line, a second clock signal line and a first initial compensation signal line arranged in the third area and extending along the first direction, The display area includes a first display mode in which the first sub-display area displays a picture and the second sub-display area does not display a picture, One of the first clock signal terminal and the second clock signal terminal of each of the first shift register circuits is electrically connected to the first clock signal line, and the other is electrically connected to the second clock signal line, and the first initial compensation signal line is electrically connected to the first shift register circuit farthest from the first area among the first shift register circuits corresponding to the first sub-display area. In the first display mode, the first clock signal line is at an invalid level during a scanning time period of each row of pixel units corresponding to the second sub-display area, and provides a first clock signal during a scanning time period of each row of pixel units corresponding to the first sub-display area, the second clock signal line is at an invalid level during a scanning time period of each row of pixel units corresponding to the second sub-display area, and provides a second clock signal during a scanning time period of each row of pixel units corresponding to the first sub-display area, and the first initial compensation signal line provides an initial signal to the first shift register circuit in the first sub-display area that is farthest from the first area.

4. The display panel according to claim 1, characterized in that: For each group of cascaded first shift register circuits, the non-display area further includes: at least two clock signal line groups arranged in the third area and extending along the first direction, the clock signal line groups are arranged in a one-to-one correspondence with the sub-display areas, and each of the clock signal line groups includes a first clock signal line and a second clock signal line, One of the first clock signal terminal and the second clock signal terminal of each of the first shift register circuits in each sub-display area is electrically connected to the first clock signal line of a corresponding group of clock signal line groups, and the other is electrically connected to the second clock signal line of the group of clock signal line groups, and, In the clock signal line group, the first clock signal line provides a first clock signal during a scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods; the first clock signal line provides a second clock signal during a scanning time period of each row of pixel units corresponding to the corresponding sub-display area, and is an invalid level in other time periods.

5. The display panel according to any one of claims 2 to 4, characterized in that: The first clock signal and the second clock signal are both periodic signals in which high level and low level are alternately arranged. During the period when the first clock signal is at a valid level, the second clock signal is at an invalid level for at least part of the period; during the period when the second clock signal is at a valid level, the first clock signal line is at an invalid level for at least part of the period.

6. The display panel according to claim 5, characterized in that: The first clock signal and the second clock signal are inverted signals.

7. The display panel according to any one of claims 2 to 4, characterized in that: The first clock signal terminal and the second clock signal terminal of the first shift register circuit generate a scanning signal of a corresponding row of pixel units based on the received clock signal.

8. The display panel according to any one of claims 2 to 4, characterized in that: The display area includes three sub-display areas.

9. A display device, characterized in that: A display panel comprising any one of claims 1-8.

10. A display driving method applied to a display panel according to any one of claims 1 to 8, characterized in that: include: In the first shift register circuit corresponding to the first sub-display area, the rising edge of the clock signal received by the first shift register circuit far away from the first area approaches the rising edge of the clock signal received by the first shift register circuit close to the first area, and the falling edge approaches the falling edge of the clock signal received by the first shift register circuit close to the first area.

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