Driving circuit, driving chip, display panel and display device

Abstract

The invention is suitable for the technical field of driving display, and provides a driving circuit, a driving chip, a display panel and a display device. The driving circuit comprises an operational amplification module and a current generation module, and the current generation module is electrically connected with the operational amplification module. When the operational amplification module is started, the current generation module is used for outputting a first current to a first tail current end of the operational amplification module according to the first voltage and the third voltage and outputting a second current to a second tail current end of the operational amplification module. A third current is output to a third tail current end of the operational amplifier module according to the second voltage and the third voltage, and a fourth current is output to a fourth tail current end of the operational amplifier module; and when the operational amplification module enters a normal working state, the current generation module stops outputting the first current, the second current, the third current and the fourth current. Under the condition that the power consumption is not increased, the establishment time of the operational amplification module is shortened, and the requirement of the driving display field for low power consumption is met.

Description

Technical Field

[0001] The present application belongs to the field of drive display technology, and in particular, relates to a drive circuit, a drive chip, a display panel and a display device. Background Art

[0002] At present, in display fields such as LCD (Liquid Crystal Display), AMOLED (Active Matrix Organic Light Emitting Diode), and AMLED (Active Matrix Light Emitting Diode), in order to enhance the driving capability of the driver chip, a driver buffer is usually set at the channel output end. When the grayscale voltage is above 11 bits, most of them use a dual-input operational amplifier with an interpolation DAC (Digital to Analog Convertor) as a driver buffer, and because the display array of the display panel has a capacitive load, the driver buffer is required to have a certain load capacity.

[0003] However, due to the strict power consumption requirements in the display field, when one wants to control power consumption, a smaller operational amplifier quiescent current is designed. This will prolong the setup time of the driver buffer (the time from startup to entering normal working state), affecting the normal display of the display. If one wants to shorten the setup time, one needs to increase the slew rate, but this will increase the quiescent current of the entire operational amplifier, thereby increasing power consumption, which is in conflict with the demand for low power consumption. Summary of the invention

[0004] The embodiments of the present application provide a driving circuit, a driving chip, a display panel and a display device, which can solve the problem of the contradiction between the setup time and power consumption of the existing driving buffer.

[0005] In a first aspect, an embodiment of the present application provides a driving circuit, including:

[0006] Operational amplifier module;

[0007] A current generating module, the current generating module is electrically connected to the operational amplification module;

[0008] When the operational amplifier module is started, the current generating module is used to output a first current to the first tail current terminal of the operational amplifier module according to the first voltage and the third voltage, output a second current to the second tail current terminal of the operational amplifier module, and output a third current to the third tail current terminal of the operational amplifier module according to the second voltage and the third voltage, and output a fourth current to the fourth tail current terminal of the operational amplifier module; wherein the first voltage is the voltage on the first positive input terminal of the operational amplifier module, the second voltage is the voltage on the second positive input terminal of the operational amplifier module, and the third voltage is the voltage on the feedback node of the operational amplifier module, and the feedback node is a node to which the first reverse input terminal, the second reverse input terminal and the output terminal of the operational amplifier module are commonly connected;

[0009] When the operational amplifier module enters a normal working state, the current generating module stops outputting the first current, the second current, the third current and the fourth current.

[0010] Specifically, when the operational amplifier module of the present application is started, the current generating module uses the voltage on the reverse input terminal of the operational amplifier module to be 0, and the voltage on the forward input terminal is greater than the voltage on the reverse input terminal, and outputs a dynamic peak current to the tail current terminal of the operational amplifier module to increase the tail current of the operational amplifier module. Since the slew rate of the operational amplifier module is proportional to the tail current, after the tail current of the operational amplifier module is increased, the slew rate of the operational amplifier module will also increase, which will shorten the establishment time of the operational amplifier module. When the operational amplifier module enters a normal working state, the current generating module stops outputting current to the tail current terminal of the operational amplifier module, that is, it will not increase the static current of the operational amplifier module when it is in a normal state. Therefore, the driving circuit provided in the embodiment of the present application shortens the establishment time of the operational amplifier module without increasing power consumption, meeting the demand for low power consumption in the driving display field.

[0011] In a second aspect, an embodiment of the present application provides a driver chip, comprising the driver circuit described in any one of the first aspects.

[0012] In a third aspect, an embodiment of the present application provides a display panel, comprising a plurality of pixel circuits and at least one driver chip as described in the second aspect, each of the driver chips being electrically connected to the plurality of pixel circuits.

[0013] In a fourth aspect, an embodiment of the present application provides a display device, comprising the display panel described in the third aspect.

[0014] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0015] The embodiment of the present application provides a driving circuit, including an operational amplifier module and a current generating module, wherein the current generating module is electrically connected to the operational amplifier module. When the operational amplifier module is started, the current generating module is used to output a first current to a first tail current terminal of the operational amplifier module according to a first voltage and a third voltage, output a second current to a second tail current terminal of the operational amplifier module, output a third current to a third tail current terminal of the operational amplifier module according to the second voltage and the third voltage, and output a fourth current to a fourth tail current terminal of the operational amplifier module; wherein the first voltage is a voltage on a first positive input terminal of the operational amplifier module, the second voltage is a voltage on a second positive input terminal of the operational amplifier module, and the third voltage is a voltage on a feedback node of the operational amplifier module, and the feedback node is a node to which the first reverse input terminal, the second reverse input terminal, and the output terminal of the operational amplifier module are commonly connected.

[0016] When the operational amplifier module enters a normal working state, the current generating module stops outputting the first current, the second current, the third current and the fourth current.

[0017] In the present application, when the operational amplifier module is started, the current generating module uses the voltage on the reverse input terminal of the operational amplifier module to be 0, and the voltage on the forward input terminal is greater than the voltage on the reverse input terminal, and outputs a dynamic peak current to the tail current terminal of the operational amplifier module to increase the tail current of the operational amplifier module. Since the slew rate of the operational amplifier module is proportional to the tail current, after the tail current of the operational amplifier module is increased, the slew rate of the operational amplifier module will also increase, which will shorten the establishment time of the operational amplifier module. When the operational amplifier module enters a normal working state, the current generating module stops outputting current to the tail current terminal of the operational amplifier module, that is, it will not increase the static current of the operational amplifier module when it is in a normal working state. Therefore, the driving circuit provided in the embodiment of the present application shortens the establishment time of the operational amplifier module without increasing power consumption, and meets the demand for low power consumption in the driving display field.

[0018] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 is a schematic block diagram of an existing dual-input operational amplifier;

[0021] Figure 2 is a principle block diagram of a driving circuit provided in an embodiment of the present application;

[0022] Figure 3 is a principle block diagram of a driving circuit provided in another embodiment of the present application;

[0023] Figure 4 is a principle block diagram of a driving circuit provided in another embodiment of the present application;

[0024] Figure 5 yes Figure 3 A circuit connection diagram of a first current generating unit in the driving circuit shown;

[0025] Figure 6 yes Figure 3 A circuit connection diagram of a second current generating unit in the driving circuit shown;

[0026] Figure 7 Schematic diagram of a simulation of a driving circuit provided in an embodiment of the present application.

[0027] In the figure: 10, operational amplifier module; 11, first current mirror; 12, second current mirror; 13, first current difference adjustment unit; 14, second current difference adjustment unit; 15, first translinear loop; 16, second translinear loop; 20, current generating module; 21, first current generating unit; 211, first current mirror unit; 212, first enabling subunit; 213, first switch subunit; 214, second current mirror unit; 215, second enabling subunit; 22, second current generating unit; 221, third enabling subunit; 222, third current mirror unit; 223, second switch subunit; 224, fourth enabling subunit; 225, fourth current mirror unit. DETAILED DESCRIPTION

[0028] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0029] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0030] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0031] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0032] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0034] In the display fields such as LCD, AMOLED and AMLED, multiple driver chips are usually used to drive the display array so that the display array can display images and content. Among them, the number of driver chips is usually related to the size of the display array and the number of its own channels. The number of channels of the driver chip can be 16 channels, 48 ​​channels, 64 channels, 96 channels, etc. When using, the driver chip of the corresponding channel can be selected according to actual needs. The following takes one channel in the driver chip as an example to explain the working principle of the driver chip.

[0035] The driver chip includes a timing control circuit, a data latch, a level conversion circuit, and a DAC (Digital-to-Analog Converter). In order to improve the driving capability of the driver chip, a driving buffer is also provided in the driver chip. Among them, the timing control circuit is used to generate timing signals and control signals. The timing signals include row scan signals and column scan signals. The row scan signal is used to control the refresh order of each row of pixels in the display array, and the column scan signal is used to select the pixel column to be refreshed. The data latch is used to store and hold the pixel data to be displayed so as to pass it to the lower circuit at the appropriate time. The level conversion circuit is used to convert the digital signal into a level or voltage suitable for the driving buffer. The DAC circuit is used to convert the digital pixel data processed by the data latch and the level conversion circuit into an analog voltage signal suitable for controlling the display array. The driving buffer is used to improve the driving capability of the analog voltage signal.

[0036] When the grayscale voltage of the display array is above 11 bits, a dual-input operational amplifier with a differential DAC is often used as a driver buffer. Figure 1 Figure 1 shows a schematic block diagram of a dual-input operational amplifier. Figure 1 As shown, the dual-input operational amplifier mainly includes a bias current generating circuit, a differential input circuit, an output circuit, a first current difference adjusting unit 13, a second current difference adjusting unit 14, a first current mirror 11, a second current mirror 12, a first translinear loop 15 and a second translinear loop 16.

[0037] Wherein, the bias current generating circuit includes a fifth PMOS tube MP5, a sixth PMOS tube MP6, a sixth NMOS tube MN6 and a fifth NMOS tube MN5. The differential input circuit includes two pairs of PMOS tubes and two pairs of NMOS tubes. One pair of PMOS tubes includes a first PMOS tube MP1 and a second PMOS tube MP2, the source of the first PMOS tube MP1 is electrically connected to the source of the second PMOS tube MP2, the drain of the sixth PMOS tube MP6 and the first current difference adjustment unit 13, and the common end connected to them is the first tail current end of the operational amplifier, represented by PS_H. The other pair of PMOS tubes includes a third PMOS tube MP3 and a fourth PMOS tube MP4, the source of the third PMOS tube MP3 is electrically connected to the source of the fourth PMOS tube MP4 and the first current difference adjustment unit 13, and the common end connected to them is the third tail current end of the operational amplifier, represented by PS_L. One pair of NMOS tubes includes a first NMOS tube MN1 and a second NMOS tube MN2, the source of the first NMOS tube MN1 is electrically connected to the source of the second NMOS tube MN2, the drain of the sixth NMOS tube MN6 and the second current difference adjustment unit 14, and the common end connected to them is the second tail current end of the operational amplifier, which is represented by NS_H. Another pair of NMOS tubes includes a third NMOS tube MN3 and a fourth NMOS tube MN4, the source of the third NMOS tube MN3 is electrically connected to the source of the fourth NMOS tube MN4 and the second current difference adjustment unit 14, and the common end connected to them is the fourth tail current end of the operational amplifier, which is represented by NS_L. The output circuit adopts a class AB structure, including a seventh PMOS tube MP7 and a seventh NMOS tube MN7, the drain of the seventh PMOS tube MP7 is electrically connected to the drain of the seventh NMOS tube MN7, and the common end connected to them is the output end of the operational amplifier.

[0038] The gate of the first PMOS tube MP1 and the gate of the first NMOS tube MN1 serve as the first reverse input terminal of the operational amplifier, the gate of the fourth PMOS tube MP4 and the gate of the fourth NMOS tube MN4 serve as the second reverse input terminal of the operational amplifier, the first reverse input terminal of the operational amplifier is electrically connected to the second reverse input terminal of the operational amplifier and the output terminal of the operational amplifier, the node connected between them serves as a feedback node, and the voltage on the feedback node is the third voltage VN. The gate of the second PMOS tube MP2 and the gate of the second NMOS tube MN2 serve as the first positive input terminal of the operational amplifier, the voltage on the first positive input terminal is the first voltage VH, the gate of the third PMOS tube MP3 and the gate of the third NMOS tube MN3 serve as the second positive input terminal of the operational amplifier, and the voltage on the second positive input terminal is the second voltage VL.

[0039] The first current mirror 11 and the second current mirror 12 adopt a common source and common gate structure. The number of bits of the first current difference adjustment unit 13 and the second current difference adjustment unit 14 is related to the number of bits of the DAC circuit connected to the front stage of the operational amplifier. When in use, the number of bits of the first current difference adjustment unit 13 and the second current difference adjustment unit 14 can be set according to actual conditions.

[0040] The circuit structure of the driver buffer is described above. From its circuit structure, it can be determined that the role of the driver buffer is to improve the driving ability of the driver chip. In order to improve the driving ability of the driver chip, the driver buffer is required to have a certain load capacity. However, due to the strict power consumption requirements in the display field, when you want to control power consumption, you will design a smaller operational amplifier quiescent current, which will make the driver buffer setup time longer and affect the normal display of the display. If you want to shorten the setup time, you need to increase the slew rate, which will increase the quiescent current of the entire operational amplifier, thereby increasing power consumption, which is in conflict with the demand for low power consumption.

[0041] In view of the above problems, the present application provides a driving circuit, such as Figure 2 As shown, the driving circuit includes an operational amplifier module 10 and a current generating module 20. The current generating module 20 is electrically connected to the operational amplifier module 10. Figure 2 It can be seen that the input end of the current generating module 20 is electrically connected to the first positive input end, the second positive input end and the feedback node FB of the operational amplifier module 10, and the output end of the current generating module 20 is electrically connected to the first tail current end PS_H, the second tail current end NS_H, the third tail current end PS_L and the fourth tail current end NS_L of the operational amplifier module 10. Among them, the circuit structure of the operational amplifier module 10 is exactly the same as the circuit structure of the dual-input operational amplifier, which will not be repeated here.

[0042] In the embodiment of the present application, when the operational amplifier module 10 is started, the current generating module 20 is used to output a first current to the first tail current terminal PS_H of the operational amplifier module 10 according to the first voltage VH and the third voltage VN, and output a second current to the second tail current terminal NS_H of the operational amplifier module 10, the first current is equal to the second current, and the first current and the second current are both dynamic peak currents; and output a third current to the third tail current terminal PS_L of the operational amplifier module 10 according to the second voltage VL and the third voltage VN, and output a fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10, the third current is equal to the fourth current, and the third current and the fourth current are both dynamic peak currents. Wherein, the first voltage VH is the voltage on the first positive input terminal of the operational amplifier module 10, the second voltage VL is the voltage on the second positive input terminal of the operational amplifier module 10, and the third voltage VN is the voltage on the feedback node FB of the operational amplifier module 10, and the feedback node FB is a node where the first reverse input terminal, the second reverse input terminal and the output terminal of the operational amplifier module 10 are connected together.

[0043] When the operational amplifier module 10 enters the normal working state, the current generating module 20 stops outputting the first current, the second current, the third current and the fourth current.

[0044] In the present application, when the operational amplifier module 10 is started, the current generating module 20 uses the voltage VN on the reverse input terminal of the operational amplifier module 10 to be 0, and the voltages VH and VL on the forward input terminal are both greater than the voltage VN on the reverse input terminal, to output a dynamic peak current to the tail current terminal of the operational amplifier module 10, so as to increase the tail current of the operational amplifier module 10. Since the slew rate of the operational amplifier module 10 is proportional to the tail current, after the tail current of the operational amplifier module 10 is increased, the slew rate of the operational amplifier module 10 will also increase, which will shorten the establishment time of the operational amplifier module 10. When the operational amplifier module 10 enters a normal working state, the current generating module 20 stops outputting current to the tail current terminal of the operational amplifier module 10, that is, it will not increase the static current of the operational amplifier module 10 when it is in a normal working state. Therefore, the driving circuit provided in the embodiment of the present application shortens the establishment time of the operational amplifier module 10 without increasing power consumption, and meets the demand for low power consumption in the driving display field.

[0045] like Figure 3 As shown, the current generating module 20 includes a first current generating unit 21 and a second current generating unit 22. The first current generating unit 21 is electrically connected to the feedback node FB, the first positive input terminal, the first tail current terminal PS_H and the second tail current terminal NS_H of the operational amplifier module 10. The second current generating unit 22 is electrically connected to the feedback node FB, the second positive input terminal, the third tail current terminal PS_L and the fourth tail current terminal NS_L of the operational amplifier module 10. Figure 3 It can be seen that the input end of the first current generating unit 21 is electrically connected to the first positive input end and the feedback node FB of the operational amplifier module 10, and the output end of the first current generating unit 21 is electrically connected to the first tail current end PS_H and the second tail current end NS_H of the operational amplifier module 10. The input end of the second current generating unit 22 is electrically connected to the second positive input end and the feedback node FB of the operational amplifier module 10, and the output end of the second current generating unit 22 is electrically connected to the third tail current end PS_L and the fourth tail current end NS_L of the operational amplifier module 10.

[0046] In the embodiment of the present application, when the operational amplifier module 10 is started, the first current generating unit 21 is used to output a first current to the first tail current terminal PS_H of the operational amplifier module 10 according to the first voltage VH and the third voltage VN, and output a second current to the second tail current terminal NS_H of the operational amplifier module 10, wherein the first current is equal to the second current. The second current generating unit 22 is used to output a third current to the third tail current terminal PS_L of the operational amplifier module 10 according to the second voltage VL and the third voltage VN, and output a fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10.

[0047] When the operational amplifier module 10 enters the normal working state, the first current generating unit 21 stops outputting the first current and the second current, and the second current generating unit 22 stops outputting the third current and the fourth current.

[0048] In the present application, when the operational amplifier module 10 is started, the first current generating unit 21 uses the voltage VN on the reverse input terminal of the operational amplifier module 10 to be 0, and the voltage VH on the first forward input terminal is greater than the voltage VN on the reverse input terminal, to output a dynamic peak current to the first tail current terminal PS_H and the second tail current terminal NS_H of the operational amplifier module 10; the second current generating unit 22 uses the voltage VN on the reverse input terminal of the operational amplifier module 10 to be 0, and the voltage VL on the second forward input terminal is greater than the voltage VN on the reverse input terminal, to output a dynamic peak current to the third tail current terminal PS_L and the fourth tail current terminal NS_L of the operational amplifier module 10, so as to increase the tail current of the operational amplifier module 10. Since the slew rate of the operational amplifier module 10 is proportional to the tail current, after the tail current of the operational amplifier module 10 is increased, the slew rate of the operational amplifier module 10 will also increase, thereby shortening the settling time of the operational amplifier module 10.

[0049] When the operational amplifier module 10 enters a normal working state, the first current generating unit 21 stops outputting the first current to the first tail current terminal PS_H of the operational amplifier module 10 and the second current to the second tail current terminal NS_H of the operational amplifier module 10, and the second current generating unit 22 stops outputting the third current to the third tail current terminal PS_L of the operational amplifier module 10 and the fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10, that is, the static current of the operational amplifier module 10 when it is in a normal state will not be increased. Therefore, the driving circuit provided in the embodiment of the present application shortens the setup time of the operational amplifier module 10 without increasing power consumption, and meets the demand for low power consumption in the driving display field.

[0050] It should be noted that when the operational amplifier module 10 is started, the first current generating unit 21 and the second current generating unit 22 simultaneously output current to the operational amplifier module 10. When the operational amplifier module 10 enters a normal working state, the first current generating unit 21 and the second current generating unit 22 simultaneously stop outputting current to the operational amplifier module 10.

[0051] like Figure 4 As shown, the first current generating unit 21 includes a first current mirror unit 211, a first enabling subunit 212, a second current mirror unit 214, a first switch subunit 213, and a second enabling subunit 215. The first switch subunit 213 is electrically connected to the feedback node FB, the first positive input terminal, the first current mirror unit 211, the first enabling subunit 212, the second current mirror unit 214, and the second enabling subunit 215 of the operational amplifier module 10, respectively; the first current mirror unit 211 is electrically connected to the first tail current terminal PS_H of the operational amplifier module 10; the second current mirror unit 214 is electrically connected to the second tail current terminal NS_H of the operational amplifier module 10; the first current mirror unit 211 and the first enabling subunit 212 are both used to be electrically connected to the first power supply AVDD; and the second current mirror unit 214 and the second enabling subunit 215 are both used to be grounded.

[0052] In the embodiment of the present application, when the operational amplifier module 10 is not started, the first enabling subunit 212 is used to be turned on according to the first enabling signal, and output the first clamping voltage to the first current mirror unit 211, so that the first current mirror unit 211 does not work, and the second enabling subunit 215 is used to be turned on according to the second enabling signal, and output the second clamping voltage to the second current mirror unit 214, so that the second current mirror unit 214 does not work. The first enabling subunit 212 and the second enabling subunit 215 function to ensure that the first current mirror unit 211 and the second current mirror unit 214 do not work when the operational amplifier module 10 is not started, so that the first current generating unit 21 does not generate current consumption. It should be noted that the first enabling signal is a low level signal, and the second enabling signal is a high level signal.

[0053] When the operational amplifier module 10 is started, the first enabling sub-unit 212 is used to disconnect according to the first enabling signal, so that the first current mirror unit 211 starts working, the second enabling sub-unit 215 is used to disconnect according to the second enabling signal, so that the second current mirror unit 214 starts working, and the first switch sub-unit 213 is used to be turned on according to the first voltage VH and the third voltage VN, so that the first current mirror unit 211 outputs the first current to the first tail current terminal PS_H of the operational amplifier module 10, and the second current mirror unit 214 outputs the second current to the second tail current terminal NS_H of the operational amplifier module 10.

[0054] When the operational amplifier module 10 enters a normal working state, the third voltage VN is no longer equal to 0, but becomes greater than 0 and tends to be stable. The first switch subunit 213 is used to disconnect the first voltage VH and the third voltage VN, so that the first current mirror unit 211 stops outputting the first current and the second current mirror unit 214 stops outputting the second current.

[0055] like Figure 5 As shown, the first current mirror unit 211 includes a first MOS tube M1 and a second MOS tube M2, the source of the first MOS tube M1 and the source of the second MOS tube M2 are both used to be electrically connected to the first power supply AVVDD, the gate of the first MOS tube M1 is electrically connected to the drain of the first MOS tube M1, the gate of the second MOS tube M2, the first enabling sub-unit 212 and the first switch sub-unit 213 respectively, and the drain of the second MOS tube M2 is electrically connected to the first tail current terminal PS_H of the operational amplifier module 10.

[0056] In the embodiment of the present application, when the first enabling subunit 212 is turned on, the first clamping voltage is output to the gate of the first MOS tube M1. Since the connection mode of the first MOS tube M1 is equivalent to a diode, the first MOS tube M1 is turned off, so that the first current mirror unit 211 does not work. When the first enabling subunit 212 is turned off, it means that the operational amplifier module 10 starts to start. At this time, the first switch subunit 213 is turned on. Since the connection mode of the first MOS tube M1 is equivalent to a diode, a current is generated on the first MOS tube M1, and then through the mirroring effect of the current mirror, a current is also generated on the second MOS tube M2, that is, the first current. When the operational amplifier module 10 enters the normal working state, the first switch subunit 213 is turned off, and then there is no current on the first MOS tube M1, that is, the output of the first current stops.

[0057] Exemplarily, both the first MOS tube M1 and the second MOS tube M2 are PMOS (positive channel Metal Oxide Semiconductor) tubes.

[0058] It should be noted that the first current mirror unit 211 may also be replaced by other units that realize its functions, and is not limited thereto.

[0059] like Figure 5 As shown, the first enabling subunit 212 includes a third MOS tube M3, the gate of the third MOS tube M3 is used to receive the first enabling signal EN, the source of the third MOS tube M3 is used to be electrically connected to the first power supply AVDD, and the drain of the third MOS tube M3 is electrically connected to the first current mirror unit 211 and the first switch subunit 213, respectively, wherein the first enabling signal EN is a low level signal when the operational amplifier module 10 is not turned on, and the first enabling signal EN becomes a high level signal after the operational amplifier module 10 is turned on. According to Figure 5 It can be known that the drain of the third MOS tube M3 is electrically connected to the gate of the first MOS tube M1 , the drain of the first MOS tube M1 , the gate of the second MOS tube M2 and the first switch sub-unit 213 respectively.

[0060] Exemplarily, the third MOS tube M3 is a PMOS tube.

[0061] In the embodiment of the present application, when the operational amplifier module 10 is not turned on, the first enable signal EN is a low level signal, the third MOS tube M3 is turned on, and the first clamping voltage AVDD is output to the first current mirror unit 211. When the operational amplifier module 10 is turned on, the first enable signal EN becomes a high level signal, and the third MOS tube M3 is turned off.

[0062] It should be noted that the first enabling subunit 212 may also be replaced by other units that implement its functions, and is not limited thereto.

[0063] like Figure 5 As shown, the first switch subunit 213 includes a fourth MOS tube M4 and a fifth MOS tube M5, the gate of the fourth MOS tube M4 is used to receive the first voltage VH, the gate of the fifth MOS tube M5 is used to receive the third voltage VN, the drain of the fourth MOS tube M4 is electrically connected to the first current mirror unit 211 and the first enabling subunit 212, the source of the fourth MOS tube M4 is electrically connected to the source of the fifth MOS tube M5, and the drain of the fifth MOS tube M5 is electrically connected to the second current mirror unit 214 and the second enabling subunit 215. Figure 5 It can be known that the drain of the fourth MOS tube M4 is electrically connected to the gate of the first MOS tube M1, the drain of the first MOS tube M1, the gate of the second MOS tube M2 and the drain of the third MOS tube respectively.

[0064] Exemplarily, the fourth MOS tube M4 is an NMOS (N-Metal-Oxide-Semiconductor) tube, and the fifth MOS tube M5 is a PMOS tube.

[0065] In the embodiment of the present application, when the operational amplifier module 10 is just turned on, the third voltage VN is equal to 0, then the fifth MOS tube M5 is turned on, and the first voltage VH is greater than 0, then the fourth MOS tube M4 is turned on, then the branch where the fourth MOS tube M4 and the fifth MOS tube M5 are located will generate current, and then through the mirroring effect of the first current mirror unit 211 and the second current mirror unit 214, the first current will be output to the first tail current terminal PS_H of the operational amplifier module 10, and the second current will be output to the second tail current terminal NS_H of the operational amplifier module 10, thereby increasing the tail current of the operational amplifier module 10, thereby shortening the setup time of the operational amplifier module 10.

[0066] When the operational amplifier module 10 enters a normal working state, the third voltage VN becomes greater than 0, and the fifth MOS tube M5 is disconnected, and the first current is stopped from being output to the first tail current terminal PS_H of the operational amplifier module 10, and the second current is stopped from being output to the second tail current terminal NS_H of the operational amplifier module 10, that is, the static current of the operational amplifier module 10 entering a normal state will not be increased. The present application shortens the setup time of the operational amplifier module 10 without increasing power consumption.

[0067] It should be noted that the first switch sub-unit 213 may also be replaced by other units that realize its functions, and is not limited thereto.

[0068] like Figure 5As shown, the second current mirror unit 214 includes a sixth MOS tube M6 and a seventh MOS tube M7, the gate of the sixth MOS tube M6 is electrically connected to the drain of the sixth MOS tube M6, the gate of the seventh MOS tube M7, the first switch subunit 213 and the second enabling subunit 215, the source of the sixth MOS tube M6 and the source of the seventh MOS tube M7 are both used for grounding, and the drain of the seventh MOS tube M7 is electrically connected to the second tail current terminal NS_H of the operational amplifier module 10. According to Figure 5 It can be known that the gate of the sixth MOS transistor M6 is electrically connected to the drain of the sixth MOS transistor M6 , the gate of the seventh MOS transistor M7 , the drain of the fifth MOS transistor M5 , and the second enabling sub-unit 215 , respectively.

[0069] In the embodiment of the present application, when the second enabling subunit 215 is turned on, the second clamping voltage will be output to the gate of the sixth MOS tube M6. Since the connection mode of the sixth MOS tube M6 is equivalent to a diode, the sixth MOS tube M6 is turned off, so that the second current mirror unit 214 does not work. When the second enabling subunit 215 is turned off, it means that the operational amplifier module 10 starts to start. At this time, the first switch subunit 213 is turned on. Since the connection mode of the sixth MOS tube M6 is equivalent to a diode, a current will be generated on the sixth MOS tube M6, and then through the mirroring effect of the current mirror, a current, that is, the second current, is also generated on the seventh MOS tube M7. When the operational amplifier module 10 enters a normal working state, the first switch subunit 213 is turned off, and then there is no current on the sixth MOS tube M6, that is, the second current is stopped.

[0070] Exemplarily, the sixth MOS transistor M6 and the seventh MOS transistor M7 are both NMOS transistors.

[0071] It should be noted that the second current mirror unit 214 may also be replaced by other units that realize its functions, and is not limited thereto.

[0072] like Figure 5 As shown, the second enabling subunit 215 includes an eighth MOS tube M8, the gate of the eighth MOS tube M8 is used to receive the second enabling signal ENB, the source of the eighth MOS tube M8 is used to be grounded AGND, and the drain of the eighth MOS tube M8 is electrically connected to the second current mirror unit 214 and the first switch subunit 213, respectively, wherein the second enabling signal ENB is a high level signal when the operational amplifier module 10 is not turned on, and the second enabling signal ENB becomes a low level signal after the operational amplifier module 10 is turned on. According to Figure 5 It can be known that the drain of the eighth MOS tube M8 is electrically connected to the gate of the sixth MOS tube M6, the drain of the sixth MOS tube, the gate of the seventh MOS tube M7 and the drain of the fifth MOS tube M5 respectively.

[0073] Exemplarily, the eighth MOS tube M8 is an NMOS tube.

[0074] In the implementation of the present application, when the operational amplifier module 10 is not turned on, the second enable signal ENB is a high level signal, the eighth MOS tube M8 is turned on, and the second clamping voltage AGND is output to the second current mirror unit 214. When the operational amplifier module 10 is turned on, the second enable signal ENB becomes a low level signal, and the eighth MOS tube M8 is turned off.

[0075] It should be noted that the second enabling subunit 215 may also be replaced by other units that implement its functions, and is not limited thereto.

[0076] like Figure 4 As shown, the second current generating unit 22 includes a third enabling subunit 221, a third current mirror unit 222, a second switch subunit 223, a fourth enabling subunit 224 and a fourth current mirror unit 225. The second switch subunit 223 is electrically connected to the feedback node FB, the second positive input terminal, the third enabling subunit 221, the third current mirror unit 222, the fourth current mirror unit 225 and the fourth enabling subunit 224 of the operational amplifier module 10 respectively. The third current mirror unit 222 is connected to the third tail current terminal PS_L of the operational amplifier module 10. The fourth current mirror unit 225 is electrically connected to the fourth tail current terminal NS_L of the operational amplifier module 10. The third enabling subunit 221 and the third current mirror unit 222 are both used to be electrically connected to the first power supply AVDD. The fourth enabling subunit 224 and the fourth current mirror unit 225 are both used to be grounded AGND.

[0077] In the embodiment of the present application, when the operational amplifier module 10 is not started, the third enabling subunit 221 is used to be turned on according to the first enabling signal, and output the third clamping voltage to the third current mirror unit 222, so that the third current mirror unit 222 does not work, and the fourth enabling subunit 224 is used to be turned on according to the second enabling signal, and output the fourth clamping voltage to the fourth current mirror unit 225, so that the fourth current mirror unit 225 does not work. The function of the third enabling subunit 221 and the fourth enabling subunit 224 is to ensure that the third current mirror unit 222 and the fourth current mirror unit 225 do not work when the operational amplifier module 10 is not started, so that the second current generating unit 22 does not generate current consumption.

[0078] When the operational amplifier module 10 is started, the third enabling sub-unit 221 is used to disconnect according to the first enabling signal, so that the third current mirror unit 222 starts working, the fourth enabling sub-unit 224 is used to disconnect according to the second enabling signal, so that the fourth current mirror unit 225 starts working, and the second switch sub-unit 223 is used to be turned on according to the second voltage VL and the third voltage VN, so that the third current mirror unit 222 outputs the third current to the third tail current terminal PS_L of the operational amplifier module 10, and the fourth current mirror unit 225 outputs the fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10.

[0079] When the operational amplifier module 10 enters a normal working state, the third voltage VN is no longer equal to 0, but becomes greater than 0 and tends to be stable. The second switch subunit 223 is used to disconnect the second voltage VL and the third voltage VN, so that the third current mirror unit 222 stops outputting the third current and the fourth current mirror unit 225 stops outputting the fourth current.

[0080] like Figure 6 As shown, the third enabling sub-unit 221 includes a ninth MOS tube M9, a gate of the ninth MOS tube M9 is used to receive the first enabling signal EN, a source of the ninth MOS tube M9 is used to be electrically connected to the first power supply AVDD, and a drain of the ninth MOS tube M9 is electrically connected to the third current mirror unit 222 and the second switch sub-unit 223 respectively.

[0081] Exemplarily, the ninth MOS tube M9 is a PMOS tube.

[0082] In the embodiment of the present application, when the operational amplifier module 10 is not turned on, the first enable signal EN is a low level signal, the ninth MOS tube M9 is turned on, and the third clamping voltage AVDD is output to the third current mirror unit 222. When the operational amplifier module 10 is turned on, the first enable signal EN becomes a high level signal, and the ninth MOS tube M9 is turned off.

[0083] It should be noted that the third enabling subunit 221 may also be replaced by other units that realize its functions, and is not limited thereto.

[0084] like Figure 6 As shown, the third current mirror unit 222 includes a tenth MOS tube M10 and an eleventh MOS tube M11, the gate of the tenth MOS tube M10 is electrically connected to the drain of the tenth MOS tube M10, the gate of the eleventh MOS tube M11, the third enabling subunit 221 and the second switch subunit 223 respectively, the source of the tenth MOS tube M10 and the source of the eleventh MOS tube M11 are both used to be electrically connected to the first power supply AVDD, and the drain of the eleventh MOS tube M11 is electrically connected to the third tail current terminal PS_L of the operational amplifier module 10. According to Figure 6It can be known that the gate of the tenth MOS tube M10 is electrically connected to the drain of the tenth MOS tube M10 , the gate of the eleventh MOS tube M11 , the drain of the ninth MOS tube M9 , and the second switch sub-unit 223 , respectively.

[0085] In the embodiment of the present application, when the third enabling subunit 221 is turned on (i.e., the ninth MOS tube M9 is turned on), the third clamping voltage AVDD is output to the gate of the tenth MOS tube M10. Since the connection mode of the tenth MOS tube M10 is equivalent to a diode, the tenth MOS tube M10 is turned off, so that the third current mirror unit 222 does not work. When the third enabling subunit 221 is turned off (i.e., the ninth MOS tube M9 is turned off), it means that the operational amplifier module 10 starts to start. At this time, the second switch subunit 223 is turned on. Since the connection mode of the tenth MOS tube M10 is equivalent to a diode, a current is generated on the tenth MOS tube M10, and then through the mirroring effect of the current mirror, a current is also generated on the eleventh MOS tube M11, i.e., the third current. When the operational amplifier module 10 enters a normal working state, the second switch subunit 223 is turned off, and then there is no current on the tenth MOS tube M10, i.e., the output of the third current stops.

[0086] Exemplarily, the tenth MOS transistor M10 and the eleventh MOS transistor M11 are both PMOS transistors.

[0087] It should be noted that the third current mirror unit 222 may also be replaced by other units that realize its functions, and is not limited thereto.

[0088] like Figure 6 As shown, the second switch subunit 223 includes a twelfth MOS tube M12 and a thirteenth MOS tube M13, the gate of the twelfth MOS tube M12 is used to receive the third voltage VN, the gate of the thirteenth MOS tube M13 is used to receive the second voltage VL, the drain of the twelfth MOS tube M12 is electrically connected to the third enabling subunit 221 and the third current mirror unit 222, the source of the twelfth MOS tube M12 is electrically connected to the source of the thirteenth MOS tube M13, and the drain of the thirteenth MOS tube M13 is electrically connected to the fourth enabling subunit 224 and the fourth current mirror unit 225. Figure 6 It can be known that the drain of the twelfth MOS tube M12 is electrically connected to the drain of the ninth MOS tube M9 , the drain of the tenth MOS tube M10 , the gate of the tenth MOS tube M10 and the gate of the eleventh MOS tube M11 respectively.

[0089] Exemplarily, the twelfth MOS tube M12 is an NMOS tube, and the thirteenth MOS tube M13 is a PMOS tube.

[0090] In the embodiment of the present application, when the operational amplifier module 10 is just turned on, the third voltage VN is equal to 0, then the thirteenth MOS tube M13 is turned on, and the second voltage VL is greater than 0, then the twelfth MOS tube M12 is turned on, then the branch where the twelfth MOS tube M12 and the thirteenth MOS tube M13 are located will generate current, and then through the mirroring effect of the third current mirror unit 222 and the fourth current mirror unit 225, the third current will be output to the third tail current terminal PS_L of the operational amplifier module 10, and the fourth current will be output to the second tail current terminal NS_L of the operational amplifier module 10, thereby increasing the tail current of the operational amplifier module 10, which will shorten the setup time of the operational amplifier module 10.

[0091] When the operational amplifier module 10 enters a normal working state, the third voltage VN becomes greater than 0, and the thirteenth MOS tube M13 is disconnected, and the third current is stopped from being output to the third tail current terminal PS_L of the operational amplifier module 10 and the fourth current is stopped from being output to the fourth tail current terminal NS_L of the operational amplifier module 10, that is, the static current of the operational amplifier module 10 entering a normal state will not be increased. The present application shortens the setup time of the operational amplifier module 10 without increasing power consumption.

[0092] It should be noted that the second switch subunit 223 may also be replaced by other units that realize its functions, and is not limited thereto.

[0093] like Figure 6 As shown, the fourth enabling subunit 224 includes a fourteenth MOS tube M14, the gate of the fourteenth MOS tube M14 is used to receive the second enabling signal ENB, the source of the fourteenth MOS tube M14 is used to be grounded AGND, and the drain of the fourteenth MOS tube M14 is electrically connected to the second switch subunit 223 and the fourth current mirror unit 225. Figure 6 It can be known that the drain of the fourteenth MOS tube M14 is electrically connected to the drain of the thirteenth MOS tube M13 and the fourth current mirror unit 225 respectively.

[0094] Exemplarily, the fourteenth MOS tube M14 is an NMOS tube.

[0095] In the embodiment of the present application, when the operational amplifier module 10 is not turned on, the second enable signal ENB is a high level signal, the fourteenth MOS tube M14 is turned on, and outputs the fourth clamping voltage AGND to the fourth current mirror unit 225. When the operational amplifier module 10 is turned on, the second enable signal ENB becomes a low level signal, and the fourteenth MOS tube M14 is turned off.

[0096] It should be noted that the fourth enabling subunit 224 may also be replaced by other units that implement its functions, and is not limited thereto.

[0097] like Figure 6As shown, the fourth current mirror unit 225 includes a fifteenth MOS tube M15 and a sixteenth MOS tube M16, the gate of the fifteenth MOS tube M15 is electrically connected to the drain of the fifteenth MOS tube M15, the gate of the sixteenth MOS tube M16, the fourth enabling subunit 224 and the second switch subunit 223, respectively, the source of the fifteenth MOS tube M15 and the source of the sixteenth MOS tube M16 are both used for grounding AGND, and the drain of the sixteenth MOS tube M16 is connected to the fourth tail current terminal NS_L of the operational amplifier module 10. According to Figure 6 It can be known that the gate of the fifteenth MOS tube M15 is electrically connected to the drain of the fifteenth MOS tube M15, the gate of the sixteenth MOS tube M16, the drain of the fourteenth MOS tube M14 and the drain of the thirteenth MOS tube M13 respectively.

[0098] In the embodiment of the present application, when the fourth enabling subunit 224 is turned on (i.e., the fourteenth MOS tube M14 is turned on), the fourth clamping voltage AGND is output to the gate of the fifteenth MOS tube M15. Since the connection mode of the fifteenth MOS tube M15 is equivalent to a diode, the fifteenth MOS tube M15 is turned off, so that the fourth current mirror unit 225 does not work. When the fourth enabling subunit 224 is turned off (i.e., the fourteenth MOS tube M14 is turned off), it means that the operational amplifier module 10 starts to start. At this time, the second switch subunit 223 is turned on. Since the connection mode of the fifteenth MOS tube M15 is equivalent to a diode, a current is generated on the fifteenth MOS tube M15, and then through the mirroring effect of the current mirror, a current is also generated on the seventeenth MOS tube M17, i.e., the fourth current. When the operational amplifier module 10 enters a normal working state, the second switch subunit 223 is turned off, and then there is no more current on the fifteenth MOS tube M15, i.e., the output of the fourth current stops.

[0099] Exemplarily, the fifteenth MOS tube M15 and the sixteenth MOS tube M16 are both NMOS tubes.

[0100] It should be noted that the fourth current mirror unit 225 may also be replaced by other units that realize its functions, and is not limited thereto.

[0101] Combine the following Figure 1 , Figure 5 and Figure 6 The working principle of the driving circuit provided in the embodiment of the present application is introduced.

[0102] like Figure 1As shown, the voltages on the first inverting input terminal, the second inverting input terminal and the output terminal of the operational amplifier module 10 are the third voltage VN, the first voltage VH on the first positive input terminal, and the second voltage VL on the second positive input terminal. When the operational amplifier module 10 is started, the third voltage VN is 0V, and the first voltage VH and the second voltage VN are both greater than 0V. By using this feature, the first voltage VH and the third voltage VN are used as the control signal of the first current generating unit 21, and the first current generating unit 21 is connected to the first current generating unit 21. Figure 5 It can be known that the fourth MOS tube M4 in the first current generating unit 21 is turned on under the control of the first voltage VH, and the fifth MOS tube M5 in the first current generating unit 21 is turned on under the control of the third voltage VN. Since the connection mode of the first MOS tube M1 and the sixth MOS tube M6 is equivalent to a diode, when the fourth MOS tube M4 and the fifth MOS tube are turned on, a current is generated on the branch where the first MOS tube M1 is located, and then through the mirror effect of the current mirror, a current is also generated on the second MOS tube M2 and the seventh MOS tube M7, and then the first current is output to the first tail current terminal PS_H of the operational amplifier module 10, and the second current is output to the second tail current terminal NS_H of the operational amplifier module 10.

[0103] At the same time, the second voltage VL and the third voltage VN are used as control signals of the second current generating unit 22. Figure 6 It can be known that the twelfth MOS tube M12 in the second current generating unit 22 is turned on under the control of the second voltage VN, and the thirteenth MOS tube M13 in the second current generating unit 22 is turned on under the control of the third voltage VN. Since the connection mode of the tenth MOS tube M10 and the fifteenth MOS tube M15 is equivalent to a diode, when the twelfth MOS tube M12 and the thirteenth MOS tube M13 are turned on, a current is generated on the branch where the tenth MOS tube M10 is located, and then through the mirror effect of the current mirror, a current is also generated on the eleventh MOS tube M11 and the sixteenth MOS tube M16, and then the third current is output to the third tail current terminal PS_L of the operational amplifier module 10, and the fourth current is output to the fourth tail current terminal NS_L of the operational amplifier module 10. During the startup process of the operational amplifier module 10, the current output by the first current generating unit 21 and the second current generating unit 22 to the tail current terminal of the operational amplifier module 10 is a dynamic peak current, which will increase the tail current of the operational amplifier module 10. Since the slew rate of the operational amplifier module 10 is proportional to the tail current, after the tail current of the operational amplifier module 10 is increased, the slew rate of the operational amplifier module 10 will also increase, which will shorten the setup time of the operational amplifier module 10.

[0104] When the operational amplifier module 10 enters a normal working state, the third voltage VN is greater than 0V and tends to be stable, then the fifth MOS tube in the first current generating unit 21 will be disconnected, and the thirteenth MOS tube in the second current generating unit 22 will be disconnected, then the first current generating unit 21 stops outputting the first current and the second current, and the second current generating unit 22 stops outputting the third current and the fourth current. When the operational amplifier module 10 enters a normal working state, the first current generating unit 21 and the second current generating unit 22 stop outputting current to the tail current terminal of the operational amplifier module 10, that is, the static current of the operational amplifier module 10 when it is in a normal working state will not be increased. Therefore, the driving circuit provided in the embodiment of the present application shortens the setup time of the operational amplifier module 10 without increasing power consumption, and meets the demand for low power consumption in the driving display field.

[0105] Figure 7 FIG. 1 shows a simulation schematic diagram of a driving circuit provided in an embodiment of the present application. Figure 7 It can be seen that the driving circuit provided in the embodiment of the present application can shorten the voltage establishment time by 867ns after adding the current generating module 20, which is particularly important in the field of driving displays.

[0106] The embodiment of the present application also provides a driving chip, including a timing control circuit, a data latch, a level conversion circuit, a DAC circuit and a plurality of the driving circuits described above. The data latch is electrically connected to the timing control circuit and the level conversion circuit respectively, and the DAC circuit is electrically connected to the level conversion circuit and the plurality of driving circuits described above respectively, that is, the output of the timing control circuit is connected to the input of the data latch, the output of the data latch is connected to the input of the level conversion circuit, the output of the level conversion circuit is connected to the input of the DAC circuit, and the output of the DAC circuit is connected to the operational amplifier module in the driving circuit of the aforementioned embodiment. It should be noted that the number of channels of the driving chip in this embodiment is related to the operational amplifier module in the aforementioned driving circuit, that is, the channel end of the driving chip and the input end of the operational amplifier module in the driving circuit are connected correspondingly. Please refer to the above for the working principle of each module in the driving chip, which will not be repeated here.

[0107] The driver chip provided in the embodiment of the present application can shorten its setup time while meeting the low power consumption requirements. For the specific working principle, please refer to the description of the working principle of the driving circuit described above, which will not be repeated here.

[0108] The embodiment of the present application further provides a display panel, comprising a plurality of pixel circuits and at least one of the above-mentioned driving chips. Each driving chip is electrically connected to the plurality of pixel circuits and is used to drive the light emitting diodes in the plurality of pixel circuits to emit light.

[0109] An embodiment of the present application further provides a display device, comprising the display panel described above.

[0110] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A driving circuit, characterized in that: include: Operational amplifier module; A current generating module, the current generating module is electrically connected to the operational amplification module; When the operational amplifier module is started, the current generating module is used to output a first current to the first tail current terminal of the operational amplifier module according to the first voltage and the third voltage, output a second current to the second tail current terminal of the operational amplifier module, and output a third current to the third tail current terminal of the operational amplifier module according to the second voltage and the third voltage, and output a fourth current to the fourth tail current terminal of the operational amplifier module; wherein the first voltage is the voltage on the first positive input terminal of the operational amplifier module, the second voltage is the voltage on the second positive input terminal of the operational amplifier module, and the third voltage is the voltage on the feedback node of the operational amplifier module, and the feedback node is a node to which the first reverse input terminal, the second reverse input terminal and the output terminal of the operational amplifier module are commonly connected; When the operational amplifier module enters a normal working state, the current generating module stops outputting the first current, the second current, the third current and the fourth current.

2. The driving circuit according to claim 1, characterized in that: The current generating module comprises: A first current generating unit, wherein the first current generating unit is electrically connected to a feedback node, a first positive input terminal, a first tail current terminal, and a second tail current terminal of the operational amplifier module respectively; A second current generating unit, the second current generating unit being electrically connected to the feedback node, the second positive input terminal, the third tail current terminal and the fourth tail current terminal of the operational amplifier module respectively; When the operational amplifier module is started, the first current generating unit is used to output the first current to the first tail current terminal of the operational amplifier module according to the first voltage and the third voltage, and output the second current to the second tail current terminal of the operational amplifier module; the second current generating unit is used to output the third current to the third tail current terminal of the operational amplifier module according to the second voltage and the third voltage, and output the fourth current to the fourth tail current terminal of the operational amplifier module; When the operational amplifier module enters a normal working state, the first current generating unit stops outputting the first current and the second current, and the second current generating unit stops outputting the third current and the fourth current.

3. The driving circuit according to claim 2, characterized in that: The first current generating unit comprises a first current mirror unit, a first enabling subunit, a second current mirror unit, a first switch subunit and a second enabling subunit, the first switch subunit is electrically connected to the feedback node, the first positive input terminal, the first current mirror unit, the first enabling subunit, the second current mirror unit and the second enabling subunit of the operational amplifier module respectively, the first current mirror unit is electrically connected to the first tail current terminal of the operational amplifier module, the second current mirror unit is electrically connected to the second tail current terminal of the operational amplifier module, the first current mirror unit and the first enabling subunit are both used to be electrically connected to a first power supply, and the second current mirror unit and the second enabling subunit are both used to be grounded; When the operational amplifier module is not started, the first enabling subunit is used to be turned on according to a first enabling signal, and output a first clamping voltage to the first current mirror unit, so that the first current mirror unit does not work, and the second enabling subunit is used to be turned on according to a second enabling signal, and output a second clamping voltage to the second current mirror unit, so that the second current mirror unit does not work; When the operational amplifier module is started, the first enabling subunit is used to disconnect according to the first enabling signal, so that the first current mirror unit is started to work, the second enabling subunit is used to disconnect according to the second enabling signal, so that the second current mirror unit is started to work, and the first switch subunit is used to conduct according to the first voltage and the third voltage, so that the first current mirror unit outputs the first current to the first tail current terminal of the operational amplifier module, and the second current mirror unit outputs the second current to the second tail current terminal of the operational amplifier module; When the operational amplifier module enters a normal working state, the first switch subunit is used to disconnect according to the first voltage and the third voltage, so that the first current mirror unit stops outputting the first current and the second current mirror unit stops outputting the second current.

4. The driving circuit according to claim 3, characterized in that: The first current mirror unit includes a first MOS tube and a second MOS tube, the source of the first MOS tube and the source of the second MOS tube are both used to be electrically connected to the first power supply, the gate of the first MOS tube is electrically connected to the drain of the first MOS tube, the gate of the second MOS tube, the first enabling sub-unit and the first switch sub-unit respectively, and the drain of the second MOS tube is electrically connected to the first tail current terminal of the operational amplifier module.

5. The driving circuit according to claim 3, characterized in that: The first enabling subunit includes a third MOS tube, a gate of the third MOS tube is used to receive the first enabling signal, a source of the third MOS tube is used to be electrically connected to the first power supply, and a drain of the third MOS tube is electrically connected to the first current mirror unit and the first switch subunit respectively.

6. The driving circuit according to claim 3, characterized in that: The first switch subunit includes a fourth MOS tube and a fifth MOS tube, the gate of the fourth MOS tube is used to receive the first voltage, the gate of the fifth MOS tube is used to receive the third voltage, the drain of the fourth MOS tube is electrically connected to the first current mirror unit and the first enabling subunit respectively, the source of the fourth MOS tube is electrically connected to the source of the fifth MOS tube, and the drain of the fifth MOS tube is electrically connected to the second current mirror unit and the second enabling subunit respectively.

7. The driving circuit according to claim 3, characterized in that: The second current mirror unit includes a sixth MOS tube and a seventh MOS tube, the gate of the sixth MOS tube is electrically connected to the drain of the sixth MOS tube, the gate of the seventh MOS tube, the first switch sub-unit and the second enabling sub-unit respectively, the source of the sixth MOS tube and the source of the seventh MOS tube are both used for grounding, and the drain of the seventh MOS tube is electrically connected to the second tail current terminal of the operational amplifier module.

8. The driving circuit according to claim 3, characterized in that: The second enabling subunit includes an eighth MOS tube, a gate of the eighth MOS tube is used to receive the second enabling signal, a source of the eighth MOS tube is used to be grounded, and a drain of the eighth MOS tube is electrically connected to the second current mirror unit and the first switch subunit respectively.

9. The driving circuit according to claim 2, characterized in that: The second current generating unit includes a third enabling subunit, a third current mirror unit, a second switch subunit, a fourth enabling subunit and a fourth current mirror unit, the second switch subunit is electrically connected to the feedback node, the second positive input terminal, the third enabling subunit, the third current mirror unit, the fourth current mirror unit and the fourth enabling subunit of the operational amplifier module respectively, the third current mirror unit is electrically connected to the third tail current terminal of the operational amplifier module, the fourth current mirror unit is electrically connected to the fourth tail current terminal of the operational amplifier module, the third enabling subunit and the third current mirror unit are both used to be electrically connected to the first power supply, and the fourth enabling subunit and the fourth current mirror unit are both used to be grounded; When the operational amplifier module is not started, the third enabling subunit is used to be turned on according to the first enabling signal, and output a third clamping voltage to the third current mirror unit, so that the third current mirror unit does not work, and the fourth enabling subunit is used to be turned on according to the second enabling signal, and output a fourth clamping voltage to the fourth current mirror unit, so that the fourth current mirror unit does not work; When the operational amplifier module is started, the third enabling subunit is used to disconnect according to the first enabling signal, so that the third current mirror unit is started to work, the fourth enabling subunit is used to disconnect according to the second enabling signal, so that the fourth current mirror unit is started to work, and the second switch subunit is used to conduct according to the second voltage and the third voltage, so that the third current mirror unit outputs the third current to the third tail current terminal of the operational amplifier module, and the fourth current mirror unit outputs the fourth current to the fourth tail current terminal of the operational amplifier module; When the operational amplifier module enters a normal working state, the second switch subunit is used to disconnect according to the second voltage and the third voltage, so that the third current mirror unit stops outputting the third current and the fourth current mirror unit stops outputting the fourth current.

10. A driver chip, characterized in that: The driving circuit comprises the driving circuit according to any one of claims 1 to 9.

11. A display panel, characterized in that: The invention comprises a plurality of pixel circuits and at least one driving chip according to claim 10, wherein each of the driving chips is electrically connected to the plurality of pixel circuits.

12. A display device, characterized in that: Includes the display panel as claimed in claim 11.

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