Semiconductor device

Abstract

A semiconductor device according to the present disclosure includes a logic cell and a memory array including a plurality of memory cells. The memory cells and the logic cells are arranged in a row, the first plurality of memory cells being closer to the logic cells than the second plurality of memory cells. A front-side interconnect structure is disposed over the memory cells and includes a front-side bit line. A front side bit line is coupled to each memory cell arranged in a row. A backside interconnect structure is disposed under the memory cells and includes a backside bit line. A backside bit line is coupled to at least the first plurality of memory cells. The front side bit line is coupled to the back side bit line through a source / drain feature of one of the first plurality of memory cells through the gate transistor.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more specifically, to semiconductor devices. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] This scaling down of integrated circuit technology not only complicates the manufacturing process, but also poses specific challenges in the design and functionality of memory arrays within memory devices. For example, the operation of memory cells at different locations in a memory array requires tailored structural designs for signal lines (e.g., bit lines) coupled to the memory cells. The traditional approach of using a bit line with a uniform width on all cells in the same row on the front side of the memory cell is increasingly inappropriate due to the inability to address the different performance requirements of these memory cells in an optimized manner. Relying solely on front-side bit lines with uniform width deployed in a memory array may result in suboptimal performance, where the specific requirements of memory cells at different locations in the memory array are not fully met. This difference highlights the need for a differentiated approach in bit line architecture to improve the overall efficiency and performance of memory devices, especially in the context of advanced semiconductor technologies. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a logic cell; a memory array comprising a plurality of memory cells, wherein the memory cells and the logic cells are arranged in rows, and wherein a first plurality of memory cells are closer to the logic cells than a second plurality of memory cells; a front-side interconnect structure, disposed above the memory cells and comprising a front-side bit line, wherein the front-side bit line is coupled to each memory cell arranged in the row; and a back-side interconnect structure, disposed below the memory cells and comprising a back-side bit line, wherein the back-side bit line is coupled to at least the first plurality of memory cells, and wherein the front-side bit line is coupled to the back-side bit line through a source / drain component of a pass-gate transistor of one of the first plurality of memory cells.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a memory array comprising a plurality of memory cells arranged in rows; a front-side interconnect structure disposed above the memory cells and comprising front-side bit lines, wherein the front-side bit lines are coupled to at least some of the memory cells arranged in the row; and a back-side interconnect structure disposed below the memory cells and comprising back-side bit lines, wherein the back-side bit lines are coupled to at least some of the memory cells arranged in the row, wherein, in a top view of the semiconductor device, the front-side bit lines partially overlap with the back-side bit lines, and wherein, in a cross-sectional view of the semiconductor device, both the front-side bit lines and the back-side bit lines are coupled to a source / drain component of a pass-gate transistor in one of the memory cells.

[0006] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a memory array comprising memory cells arranged in M ​​rows and N columns, M and N being both integers; a logic area adjacent to the memory array and coupled to the memory cells; and an interconnect structure arranged above the memory array and the logic area, wherein the interconnect structure comprises a front-side signal line suspended directly above a row of the M rows of memory cells and a back-side signal line arranged directly below a row of the M rows of memory cells, and wherein: the front-side signal line is coupled to each memory cell of a row of the M rows, the back-side signal line comprises a first segment and a second segment, the first segment is coupled to the memory cells in the first column to the (Q-1)th column of a row of the M rows, the second segment is coupled to the memory cells in the Qth column to the Nth column of a row of the M rows, Q is an integer greater than 1 and less than N, the first column is closer to the logic area than the Nth column, and the first segment has a first width, and the second segment has a second width less than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a block diagram of a semiconductor device having a memory macro according to various aspects of the present disclosure.

[0009] Figure 2 is a block diagram of a memory macro having a memory array according to various aspects of the present disclosure.

[0010] Figure 3 is a circuit schematic of a single-port static random access memory (SRAM) cell according to various aspects of the present disclosure.

[0011] Figure 4Cross-sectional views of various layers of a memory device according to various aspects of the present disclosure are shown.

[0012] Figure 5 and Figure 6 The following are respectively shown according to various aspects of the present disclosure. Figure 3 The layout of a single-port SRAM cell including device and metal layers is shown.

[0013] Figure 7 A layout of device and metal layers including a 2×2 SRAM array according to various aspects of the present disclosure is shown.

[0014] Figure 8 According to various aspects of the present disclosure, Figure 7 Cross-sectional view of the semiconductor device along cutting line AA in FIG.

[0015] Fig. 9 An alternative layout of device and metal layers including a 2×2 SRAM array according to various aspects of the present disclosure is shown.

[0016] Fig.10 According to various aspects of the present disclosure, Fig. 9 Cross-sectional view of the semiconductor device along cutting line AA in FIG.

[0017] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 A layout including front-side bit lines and back-side bit lines in a memory macro according to various aspects of the present disclosure is shown.

[0018] Fig.17 is a circuit schematic of a dual-port static random access memory (SRAM) cell according to various aspects of the present disclosure.

[0019] Fig.18 and Fig.19 The following are respectively shown according to various aspects of the present disclosure. Fig.17 The layout of the dual-port SRAM cell including the device layer and the metal layer is shown.

[0020] Fig. 20 A layout including front-side bit lines and back-side bit lines in a memory macro according to various aspects of the present disclosure is shown.

[0021] Fig.21 According to various aspects of the present disclosure, Fig. 20 sectional view of the semiconductor device along the cutting line BB in FIG.

[0022] Fig. 22 , Fig.23 and Fig.24 An alternative layout including frontside bit lines and backside bit lines in a memory macro according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0024] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0025] In addition, when "about," "approximately," etc. are used to describe a number or a series of numbers, the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features associated with the number, the number or range includes a reasonable range that includes the described number, such as within + / - 10% of the described number. For example, a material layer with a thickness of "about 5 nm" may include a size range of 4.5 nm to 5.5 nm, where manufacturing tolerances associated with deposited material layers are known to those of ordinary skill in the art to be + / - 10%. When describing aspects of transistors, the source / drain regions may be referred to individually or collectively as the source or drain, depending on the context.

[0026] Static random access memory (SRAM) is a semiconductor memory that retains data statically as long as power is applied. Unlike dynamic RAM (DRAM), SRAM is faster, more reliable, and does not need to be constantly refreshed. The SRAM macro includes memory cells and logic cells. Memory cells are also called bit cells and are configured to store memory bits. When forming an array, the memory cells can be arranged in rows and columns. The logic cell can be a standard cell (STD cell), such as an inverter (INV), AND, OR, NAND, NOR, Flip Flip, SCAN, etc. The logic cell is arranged around the memory cell and is configured to implement various logic functions.

[0027] Between the memory cell and the logic cell, the multi-layer interconnect structure provides metal tracks (metal lines) for interconnecting power lines and signal lines. Memory cells at different locations may have different structural design requirements to achieve optimal performance. For example, a memory cell located near a logic cell may need to have a structural design for its bit line to minimize resistance, because other memory cells in the same row also have to "consider" series resistance. Bit lines with low resistance provide greater voltage margin. In contrast, memory cells located far away from the logic cell may need a structural design for their bit line that minimizes delay by reducing parasitic capacitance, because such memory cells are generally affected by reduced circuit speed. At the same time, as the size of SRAM cells decreases, the available layout area on the front side of the SRAM array becomes limited. Therefore, the bit line is often designed to have a reduced size and is more tightly packed. This inevitably leads to an increase in resistance and parasitic capacitance. Therefore, relying solely on the bit line set on the front side of the SRAM array to have a uniform bit line width between different memory cells may result in suboptimal performance because it does not meet the unique requirements of each memory cell.

[0028] The present disclosure introduces a bit line structure, which provides a bit line (referred to as a front side bit line) disposed on the front side of an SRAM array and a bit line (referred to as a back side bit line) disposed on the back side of the SRAM array. The widths of the front side and back side bit lines may be different. In addition, each of the front side and back side bit lines may have an uneven width. In one embodiment, an SRAM array may have a front side bit line with a uniform width, and a back side bit line with two or more widths for use in memory cells at different distances from the input / output (I / O) periphery, thereby improving circuit performance.

[0029] Reference now Figure 1 . Figure 11 is a simplified block diagram of a semiconductor device (or IC) 10 according to some embodiments of the present disclosure. The semiconductor device 10 may be, for example, a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), or a portion thereof, including various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs (Fin Field Effect Transistors), full-all-around gate (GAA) transistors (such as nanosheet FETs or nanowire FETs), other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. The exact functionality of the semiconductor device 10 is not limited to the subject matter provided.

[0030] Semiconductor device 10 includes a memory macro (hereinafter referred to as macro) 20. In some embodiments, macro 20 is a static random access memory (SRAM) macro, such as a single-port SRAM macro, a dual-port SRAM macro, or another type of SRAM macro. However, the present disclosure contemplates embodiments in which macro 20 is another type of memory, such as a dynamic random access memory (DRAM), a non-volatile random access memory (NVRAM), flash memory, or another suitable memory. For clarity, Figure 1 It is simplified to better understand the inventive concepts of the present disclosure. Additional features may be added in macro 20, and some of the features described below may be replaced, modified, or eliminated in other embodiments of macro 20.

[0031] In some embodiments, the macro 20 includes a memory cell and a peripheral circuit. The memory cell is also referred to as a bit cell and is configured to store a memory bit. The peripheral cell is also referred to as a logic cell, which is arranged around the bit cell and is configured to implement various logic functions. The logic functions of the logic cell include, for example, write decoding and / or read decoding, word line selection, bit line selection, data driving, and memory self-test. For the purpose of explanation, the logic functions of the above-mentioned logic cells are given. Various logic functions of the logic cell are within the intended scope of the present disclosure. In the illustrated embodiment, the macro 20 includes a circuit area 22, in which at least one memory array 24 and at least one peripheral circuit 26 are positioned very close to each other. The memory array 24 includes many memory cells arranged in rows and columns. The peripheral circuit 26 includes a logic cell. Typically, the peripheral circuit 26 may include many logic cells to provide read operations and / or write operations to the memory cells in the memory array 24. The macro 20 may include more than one memory array 24 and more than one peripheral circuit 26. The transistors in one or more memory arrays 24 and one or more peripheral circuits 26 can be implemented with various PFETs and NFETs, such as planar transistors or non-planar transistors, including various FinFET transistors, GAA transistors, or combinations thereof. A GAA transistor refers to a transistor having a gate electrode surrounding a transistor channel, such as a vertically stacked gate surrounding a horizontal nanowire or nanosheet MOSFET device. The following disclosure will continue with one or more GAA examples to illustrate various embodiments of the present disclosure. However, it should be understood that the application should not be limited to a specific type of device unless specifically required. For example, aspects of the present disclosure may also be applied to implementations based on FinFETs or planar FETs.

[0032] Figure 2 A portion of a macro 30 is shown, which includes a memory array 32, input / output (I / O) circuits 34, word line drivers 36, and control circuits 38. In some embodiments, macro 30 may be implemented as Figure 1 The memory array 32 may be implemented as Figure 1 and the input / output (I / O) circuit 34, the word line driver 36 and the control circuit 38 may be implemented together as Figure 1 For the sake of clarity, Figure 2 It is simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to macro 30, and some of the features described below may be replaced, modified, or eliminated in other embodiments of macro 30.

[0033] The memory array 32 includes memory cells arranged in rows and columns. In the illustrated embodiment, each memory cell is arranged from the 1st row to the Mth row extending along a first direction (here, in the X direction), and each memory cell is arranged from the 1st column to the Nth column extending along a second direction (here, in the Y direction), where M and N are positive integers. Typically, N is a power of 2, such as 64, 128, 256, 512, etc. The present disclosure contemplates that N is any other integer. For simplicity of description, Figure 2 Only a few rows and columns and the corresponding memory cells are shown. Each memory cell stores one bit of data. Therefore, according to the position of the memory cell in the memory array 32, the memory cell is also called a bit cell or represented as a BC. mn , where m represents the row and n represents the column. For example, BC 11 BC represents the memory cell located in the first row (row 1) and the first column (column 1), which is the memory cell closest to the I / O circuit 34 in the first row (row 1); 12 BC represents a memory cell located in the first row (row 1) and the second column (column 2), which is the memory cell in the first row (row 1) that is the second closest to the I / O circuit 34; 1N BC represents the memory cell located in the first row (row 1) and the last column (column N), which is the memory cell farthest from the I / O circuit 34 in the first row (row 1); MN Denotes the memory cell located in the last row (row M) and the last column (column N). For simplicity, memory cell BC mn It can be called BC.

[0034] Rows 1 to M each include a bit line pair extending in the X direction, such as a bit line (BL) and an inverted bit line (BLB) (also referred to as a complementary bit line), which facilitates reading data from and / or writing data to each memory cell BC in true and complementary form row by row. Columns 1 to M each include a word line (WL) that facilitates accessing each memory cell BC column by column. Each memory cell BC is electrically connected to a corresponding BL, a corresponding BLB, and a corresponding WL.

[0035] I / O circuit 34 is coupled to memory array 32 through bit line pair BL and BLB. In some embodiments, I / O circuit 34 is configured to select one of the rows in memory array 32 and provide a bit line signal on one of the bit line pairs arranged on the selected row. The bit line signal is transmitted to the corresponding memory cell BC through the selected bit line pair BL and BLB for writing bit data into the corresponding memory cell BC or reading bit data from the corresponding memory cell BC.

[0036] The word line driver 36 is coupled to the memory array 32 through the word lines WL. In some embodiments, the word line driver 36 is configured to select one of the columns in the memory array 32 and provide a word line signal on one of the word lines WL arranged on the selected column. The word line signal is transmitted to the corresponding memory cell BC through the selected word line WL for writing or reading bit data into or from the corresponding memory cell BC.

[0037] The control circuit 38 is coupled to the I / O circuit 34 and the word line driver 36 and is disposed near the I / O circuit 34 and the word line driver 36. The control circuit 38 configures the I / O circuit 34 and the word line driver 36 to generate one or more signals to select at least one WL and at least one bit line pair (here BL and BLB) to access at least one of the memory cells BC for a read operation and / or a write operation. The control circuit 38 includes any circuit suitable for facilitating a read operation from the memory cell BC / a write operation to the memory cell BC, including but not limited to a column decoder circuit, a row decoder circuit, a column selection circuit, a row selection circuit, a read / write circuit (e.g., configured to read data from and / or write data to the memory cell BC corresponding to the selected bit line pair (in other words, the selected column)), other suitable circuits or combinations thereof. In some embodiments, the control circuit 38 is implemented by a processor. In some other embodiments, the control circuit 38 is integrated with the processor. The processor is implemented by a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0038] In a write operation or a read operation, the I / O circuit 34 and the word line driver 36 select at least one bit line pair and at least one word line WL, respectively. When a word line WL on a corresponding column is selected, a bit line signal is transmitted from the I / O circuit 34 to a corresponding memory cell BC, or the bit line signal is transmitted from the memory cell BC to the I / O circuit 34. Memory cells far from the I / O circuit 34, such as the memory cell BC 1N , which is more sensitive to the delay affected by parasitic capacitance. However, the transmission path along the signal line in the bit line pair (here, BL and BLB extending through column 1 to column N) to such a memory cell is relatively long and is prone to introducing large parasitic capacitance. Therefore, memory cells far from the I / O circuit 34 may want to "consider" narrower signal lines to reduce parasitic capacitance. In contrast, for memory cells located near the I / O circuit 34, such as memory cell BC 11, the transmission path along the signal line in the bit line pair (here, the BL and BLB extending through column 1 to column N) is relatively short, and the memory cell is less sensitive to parasitic capacitance. Therefore, the memory cell located near the I / O circuit 34 may want to "take into account" the wider signal line, thereby expanding the voltage margin. Therefore, in order to further optimize performance, the memory cells located in different columns of the memory array have different requirements for the size of the signal line (e.g., the width of the BL and BLB in the bit line pair).

[0039] Figure 3 is a circuit diagram of an exemplary SRAM cell 50, which may be implemented as Figure 2 The memory cell BC in Figure 1 In the semiconductor device 10 of FIG. 1 , the SRAM cell 50 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, the SRAM cell 50 may be other types of memory cells, such as a dual-port memory cell or a memory cell having more than six transistors. For clarity, Figure 3 It is simplified for better understanding of the inventive concepts of the present disclosure. Additional features may be added in the single-port SRAM cell 50 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the single-port SRAM cell 50 .

[0040] The exemplary SRAM cell 50 is a single-port SRAM cell that includes six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistor PG-1 and the pass-gate transistor PG-2 provide access to a storage portion of the SRAM cell 50, which includes a cross-coupled pair of inverters, inverter 52 and inverter 54. Inverter 52 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and inverter 54 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. In some embodiments, the pull-up transistors PU-1 and PU-2 are configured as p-type FinFET transistors or p-type GAA transistors, and the pull-down transistors PD-1 and PD-2 are configured as n-type FinFET transistors or n-type GAA transistors.

[0041] The gate of the pull-up transistor PU-1 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the first common drain (CD1), and the gate of the pull-down transistor PD-1 is inserted between the source (electrically coupled to the power supply voltage (VSS), which may be electrically grounded) and the first common drain. The gate of the pull-up transistor PU-2 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the second common drain (CD2), and the gate of the pull-down transistor PD-2 is inserted between the source (electrically coupled to its power supply voltage (VSS)) and the third common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) storing data in a true form, and the second common drain (CD2) is a storage node (SNB) storing data in a complementary form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are coupled to the second common drain (CD2), and the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 are coupled to the first common drain (CD1). The gate of the pass-gate transistor PG-1 is inserted between the source (electrically coupled to the bit line BL) and the drain electrically coupled to the first common drain (CD1). The gate of the pass-gate transistor PG-2 is inserted between the source (electrically coupled to the complementary bit line BLB) and the drain electrically coupled to the second common drain (CD2). The gates of the pass-gate transistors PG-1 and PG-2 are electrically coupled to the word line WL. In some embodiments, the pass-gate transistors PG-1 and PG-2 provide access to the storage nodes SN and SNB during a read operation and / or a write operation. For example, the pass-gate transistors PG-1 and PG-2 couple the storage nodes SN and SNB to the bit lines BL and BLB, respectively, in response to the voltage applied to the gates of the pass-gate transistors PG-1 and PG-2 by the word line WL.

[0042] Figure 4 1 is a partial schematic cross-sectional view of a semiconductor device 100 according to various aspects of the present disclosure, the semiconductor device 100 including a portion of a memory device (eg, Figure 2 Memory macro 30) and / or a portion of an SRAM cell (such as Figure 3 The various layers (levels) of the SRAM cell 50). Figure 4As shown, each layer includes a device layer DL, a front multilayer interconnect structure (FMLI) disposed on the device layer DL, and a back multilayer interconnect structure (BMLI) disposed below the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation component 64, and a transistor T. Each gate structure 68 has a metal gate stack formed by a gate electrode 74 disposed on a gate dielectric 76 and a gate spacer 78 disposed along the sidewall of the metal gate stack.

[0043] The multi-layer interconnect structures FMLI and BMLI electrically couple various devices and / or components of the device layer DL so that the various devices and / or components can operate according to the design requirements of the memory device. Each of the multi-layer interconnect structures FMLI and BMLI may include one or more interconnect layers.

[0044] In the depicted embodiment, the FMLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero layer (M0 level), a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The present disclosure contemplates FMLIs with more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the FMLI is 2 to 10. Each layer of the FMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features of the same level of the FMLI (e.g., the M0 level) are formed simultaneously. In some embodiments, conductive features of the same level of the FMLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. The CO level includes source / drain contacts (MD) disposed in the dielectric layer 66; the V0 level includes gate vias VG, source / drain contact vias VD, and butt contacts disposed in the dielectric layer 66. The M0 level includes an M0 metal line disposed in the dielectric layer 66, wherein the gate vias VG connect the gate structure to the M0 metal line, the source / drain vias V0 connect the source / drain to the M0 metal line, and the butt contacts connect the gate structure and the source / drain together and to the M0 metal line. The V1 level includes a V1 via disposed in the dielectric layer 66, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 layer includes an M1 metal line disposed in the dielectric layer 66. The V2 level includes a V2 via disposed in the dielectric layer 66, wherein the V2 via connects the M1 line to the M2 line. The M2 level includes an M2 metal line disposed in the dielectric layer 66. The V3 level includes V3 vias disposed in dielectric layer 66 , wherein the V3 vias connect the M2 lines to the M3 lines.

[0045] In the depicted embodiment, the BMLI includes a backside via zero layer (BV0 level), a backside metal zero layer (BM0 level), a backside via one layer (BV1 level), and a backside metal one layer (BM1 level). The present disclosure contemplates a BMLI having more or fewer layers and / or layers, for example, the total number of metal layers (levels) of the BMLI is 2 to 10. Each layer of the BMLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features of the same level of the BMLI (such as the BM0 level) are formed simultaneously. In some embodiments, conductive features at the same level of the BMLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. The BV0 level includes a via BV0 formed below the device layer DL. For example, the via BV0 may include one or more backside source / drain vias formed directly below the source / drain features 72 of the device layer DL and coupled to these source / drain features 72 through the silicide layer. The via BV0 may include one or more backside gate vias formed directly below and in direct contact with the gate structure 68 of the device layer DL. The BM0 level includes a BM0 metal line formed below the BV0 level and disposed in the backside dielectric structure 66'. The backside gate via connects the gate structure 68 to the BM0 metal line, and the backside source / drain via connects the source / drain features 72 to the BM0 metal line. The BV1 level includes a BV1 via disposed in the backside dielectric structure 66', wherein the BV1 via connects the BM0 metal line to the BM1 metal line. The BM1 layer includes a BM1 metal line formed below the BV1 layer.

[0046] In order to better understand the inventive concept of the present disclosure, the Figure 4 Additional features may be added in various layers of the memory, and some of the features described may be replaced, modified, or eliminated in other embodiments of the memory. Figure 4 This is merely an example and may not reflect an actual cross-sectional view of the memory macro 30 and / or the SRAM cell 50 discussed in further detail below.

[0047] Figure 5 and Figure 6 It shows that Figure 3 An exemplary layout 200 of an SRAM cell 50 is shown, wherein Figure 5 The DL level, CO level and V0 level of the layout 200 are shown. Figure 6 The V0 level and the M0 level of the layout 200 are shown. To facilitate the description of the positional relationship, Figure 6 It also shows that Figure 5The SRAM cell 50 has active regions (such as active regions 205A, 205B, 205C, and 205D) as shown. Figure 5 and Figure 6 The dashed line in the figure represents the cell boundary 202. The cell boundary 202 is a rectangular box that is longer in the Y direction than in the X direction (e.g., about 3.5 times to about 6 times longer). A first dimension of the cell boundary 202 in the X direction is represented as a cell width W, and a second dimension of the cell edge 202 in the Y direction is represented as a memory cell height H. When the SRAM cell 50 is repeated in the memory array (e.g., Figure 7 ), the cell width W may represent and be referred to as the memory cell spacing in the memory array along the X direction, and the cell height H may represent and be referred to as the memory cell spacing in the memory array along the Y direction. In the illustrated embodiment, the cell width W is twice the polysilicon pitch. The polysilicon pitch refers to the minimum center-to-center distance between two adjacent gate structures along the X direction.

[0048] The SRAM cell 50 includes an active region 205 (including 205A, 205B, 205C, and 205D) oriented longitudinally along the X direction, and a gate structure 240 (including 240A, 240B, 240C, and 240D) oriented longitudinally along the Y direction perpendicular to the X direction. The active regions 205B and 205C are disposed above an n-type well (or n-well) 204N. The active regions 205A and 205D are disposed above a p-type well 204P located on both sides of the n-well 204N along the Y direction. The gate structure 240 joins the channel region of the corresponding active region 205 to form a transistor. In this regard, gate structure 240A joins the channel region of active region 205A to form an n-type transistor as a pass-gate transistor PG-1; gate structure 240B joins the channel region of active region 205A to form an n-type transistor as a pull-down transistor PD-1, and joins the channel region of active region 205B to form a p-type transistor as a pull-up transistor PU-1; gate structure 240C joins the channel region of active region 205D to form an n-type transistor as a pull-down transistor PD-2, and joins the channel region of active region 205C to form a p-type transistor as a pull-up transistor PU-2; gate structure 240D joins the channel region of active region 205D to form an n-type transistor as a pass-gate transistor PG-2. In this embodiment, each channel region is in the form of a vertically stacked nanostructure, and each transistor PU-1, PU-2, PD-1, PD-2, PG-1 and PG-2 is a GAA transistor. Alternatively, each channel region is in the form of a fin, and each of the transistors PU- 1 , PU- 2 , PD- 1 , PD- 2 , PG- 1 , and PG- 2 is a FinFET transistor.

[0049] Different active areas in different transistors of the SRAM cell 50 may have different widths (e.g., dimensions measured in the Y direction) to optimize device performance. In more detail, the active area 205A of the pull-down transistor PD-1 and the pass-gate transistor PG-1 has a width W1, the active area 205B of the pull-up transistor PU-1 has a width W2, the active area 205C of the pull-up transistor PU-2 has a width W2, and the active area 205D of the pass-gate transistor PG-2 and the pull-down transistor PD-2 has a width W1. The widths W1 and W2 may also be measured in portions of the active area corresponding to the channel region. In other words, these portions of the active area (from which the widths W1 and W2 are measured) are the channel regions of the transistors (e.g., the vertically stacked nanostructures of the GAA device). In order to optimize SRAM performance, in some embodiments, the width W1 is configured to be greater than the width W2 (W1>W2) to balance the speed between the n-type transistor and the p-type transistor. In some embodiments, the ratio of W1 / W2 may be in the range of about 1.1 to about 3.

[0050] Width W1 being greater than width W2 increases the strength of the n-type transistor in SRAM cell 50, which results in a higher current handling capability of SRAM cell 50. This configuration of active regions is suitable for high current applications (such SRAM cells are referred to as high current SRAM cells). In some other embodiments, widths W1 and W2 may be the same (W1=W2). Reduced width W1 allows SRAM cell 50 to have a smaller cell height H. This configuration of active regions is suitable for high density applications (such SRAM cells are referred to as high density SRAM cells). Figure 1 Taking the macro 20 in FIG. 1 as an example, in one embodiment, the memory macro 20 may include a memory array 24 made entirely of high-current SRAM cells; in another embodiment, the memory macro 20 may include a memory array 24 made entirely of high-density SRAM cells; and in another embodiment, the memory macro 20 may include some memory arrays 24 made of high-current SRAM cells and some other memory arrays 24 composed of high-density SRAM cells.

[0051] The SRAM cell 50 also includes conductive components at the CO level, the V0 level, the M0 level, and even higher metal levels (e.g., the M1 level, the M2 level, etc.). The gate contact 260A electrically connects the gate of the through-gate transistor PG-1 (formed by the gate structure 240A) to the first word line WL landing pad 280A. The first WL landing pad 280A is electrically coupled to the word line WL at a higher metal level. The gate contact 260L electrically connects the gate of the through-gate transistor PG-2 (formed by the gate structure 240D) to the second word line WL landing pad 280L. The second WL landing pad 280L is electrically coupled to the word line WL at a higher metal level. Source / drain (S / D) contact 260K electrically connects the drain region of pull-down transistor PD-1 (formed on active region 205A (which may include n-type epitaxial source / drain components)) and the drain region of pull-up transistor PU-1 (formed on active region 205B (which may include p-type epitaxial source / drain components)) so that the common drain of pull-down transistors PD-1 / PU-1 forms storage node SN. Gate contact 260B electrically connects the gate of pull-up transistor PU-2 (formed by gate structure 240C) and the gate of pull-down transistor PD-2 (also formed by gate structure 240C) to storage node SN. Gate contact 260B may be a butt contact adjacent to S / D contact 260K. S S / D contact 260C electrically connects the drain region of pull-down transistor PD-2 (formed on active region 205D (which may include n-type epitaxial source / drain components)) and the drain region of pull-up transistor PU-2 (formed on active region 205C (which may include p-type epitaxial source region / drain components)) such that the common drain of pull-down transistor PD-2 and pull-up transistor PU-2 forms a complementary storage node SNB. Gate contact 260D electrically connects the gate of pull-up transistor PU-1 (formed by gate structure 240B) and the gate of pull-down transistor PD-1 (also formed by gate structure 240B) to complementary storage node SNB. Gate contact 260D may be a butt contact adjacent to S / D contact 260C.

[0052] The S / D contact 260E and the S / D contact via 270E landed thereon electrically connect the source region of the pull-up transistor PU-1 (formed on the active area 205B (which may include a p-type epitaxial source / drain component)) to the VDD line 280E. The VDD line 280E is electrically coupled to the power supply voltage VDD. The S / D contact 260F and the S / D contact via 270F landed thereon electrically connect the source region of the pull-up transistor PU-2 (formed on the active area 205C (which may include a p-type epitaxial source / drain component)) to the VDD line 280E. The S / D contact 260G and the S / D contact via 270G landed thereon electrically connect the source region of the pull-down transistor PD-1 (formed on the active area 205A (which may include an n-type epitaxial source / drain component)) to the first VSS landing pad 280G. The first VSS landing pad 280G is electrically coupled to the electrical ground VSS. The S / D contact 260H and the S / D contact via 270H landing thereon electrically connect the source region of the pull-down transistor PD-2 (formed on the active area 205D (which may include an n-type epitaxial source / drain component)) to the second VSS landing pad 280H. The second VSS landing pad 280H is electrically coupled to the electrical ground VSS. The S / D contact 260G and the S / D contact 260H may be device-level contacts shared by adjacent SRAM cells 50 (e.g., four SRAM cells 50 adjacent at the same corner may share one S / D contact 260H). The S / D contact 260I and the S / D contact via 270I landing thereon electrically connect the source region of the pass-gate transistor PG-1 (formed on the active area 205A (which may include an n-type epitaxial source / drain component)) to the bit line BL 280I. S / D contact 260J and S / D contact via 270J landed thereon electrically connect the source region of pass-gate transistor PG-2 formed on active region 205D (which may include n-type epitaxial source / drain features) to complementary bit line (barred bit line) BLB 280J.

[0053] Conductive components in the CO level, M0 level, and higher metal levels (e.g., M1 level, M2 level, etc.) are routed along a first routing direction or a second routing direction different from the first routing direction. For example, the first routing direction is the X direction (and is substantially parallel to the longitudinal direction of the active regions 205A-205D), and the second routing direction is the Y direction (and is substantially parallel to the longitudinal direction of the gate structures 240A-240D). In the depicted embodiment, the source / drain contacts (260C, 260E, 260F, 260G, 260H, 260I, 260J, 260K) have a longitudinal (longitudinal) direction substantially along the Y direction (i.e., the second routing direction), and the butt contacts (260B, 260D) have a longitudinal direction substantially along the X direction (i.e., the first routing direction). The metal lines of the even-numbered metal levels (i.e., the M0 level and the M2 level) are wired along the X direction (i.e., the first wiring direction), and the metal lines of the odd-numbered metal levels (i.e., the M1 level and the M3 level) are wired along the Y direction (i.e., the second wiring direction). Figure 6 In the M0 level shown, the bit line 280I, the inverted bit line 280J, the VDD line 280E, the VSS landing pad 280G, the VSS landing pad 280H, the word line landing pad 280A, and the word line landing pad 280L have a longitudinal direction substantially along the X direction. In addition, since the metal lines in the same metal level (e.g., the M0 level) have the same longitudinal direction, the metal lines can be located in a metal track arranged in parallel. The metal track can include one or more metal lines. For example, the metal track can include a single metal line extending through the entire SRAM cell, or the metal track can include one or more local metal lines that do not extend through the entire SRAM cell.

[0054] The metal lines shown are generally rectangular (i.e., each metal line is longer than its width), but the present disclosure contemplates metal lines having different shapes and / or combinations of shapes to optimize and / or improve performance (e.g., reduce resistance) and / or layout footprint (e.g., reduce density). For example, VDD line 280E may optionally have a shape such as Figure 6 The added protrusion portion (or simply as a protrusion portion) is shown. A protrusion refers to the junction where two portions of different widths intersect. The protrusion portion of VDD line 280E has a greater width than other portions of VDD line 280E. The protrusion can add about 1% to about 50% additional width to VDD line 280E. A protrusion is added to the interconnection region (region) of VDD line 280E to increase the cross-sectional area of ​​the interconnection region. Increasing the cross-sectional area of ​​the interconnection region of VDD line 280E allows the cross-sectional area of ​​S / D contact vias 270E and 270F in the V0 level to be increased, which reduces the wiring resistance between the connection of VDD line 280E and the corresponding source / drain contact (thereby reducing the wiring resistance to the source / drain region below).

[0055] A "landing pad" generally refers to a metal line in a metal layer that provides an intermediate local interconnect for an SRAM cell, such as an intermediate local interconnect between (1) a device level component (e.g., a gate or source / drain) and a bit line, an inverted bit line, a word line, a voltage line, or (2) an intermediate local interconnect between a bit line, a word line, or a voltage line. For example, VSS landing pad 280G is connected to source / drain contact 260G of transistor PD-1 and further connected to a VSS line at a higher metal level, VSS landing pad 280H is connected to source / drain contact 260H of transistor PD-2 and further connected to a VSS line at a higher metal level, WL landing pad 280A is connected to the gate of transistor PG-1 and further connected to word line WL at a higher metal level, and WL landing pad 280L is connected to the gate of transistor PG-2 and further connected to word line WL at a higher metal level. The landing pad has a sufficiently large longitudinal dimension to provide sufficient pad area for its overlying via (thereby minimizing coverage issues and providing greater patterning flexibility). In the depicted embodiment, the longitudinal dimension of the landing pad is smaller than the longitudinal dimension of the SRAM cell 50, such as a dimension along the X direction that is smaller than the cell width W and a dimension along the Y direction that is smaller than the cell height H. Compared to the landing pad, the bit line 280I, the inverted bit line 280J, and the VDD line 280E have a longitudinal dimension along the X direction that is larger than the cell width W of the SRAM cell 50. When the bit line 280I, the inverted bit line 280J, and the VDD line 280E at the M0 level pass through the entire SRAM cell 50 along the X direction, the bit line 280I, the inverted bit line 280J, and the VDD line 280E are also referred to as global metal lines, while the other lines are referred to as local metal lines (including pads). In some embodiments, the length of each of the bit line 2801, the bar bit line 280J, and the VDD line 280E is sufficient to allow multiple SRAM cells in a column (or row) to be electrically connected to a corresponding global metal line.

[0056] The metal lines (global metal lines and local metal lines) at the M0 level in the SRAM cell 50 may have different widths. For example, the main portion of the VDD line 280E has a width of W VDD , the bit line 280I and the inverted bit line 280J both have a uniform width W BL In some embodiments, the width W BL Greater than width W VDD (W BL >W VDD ). The maximum width reserved for bit line 280I and inverted bit line 280J allows the signal line in the bit line pair to generally benefit from a reduction in resistance, thereby reducing the voltage drop along the signal line. In some embodiments, the width W BL With width WVDD The ratio (i.e. W BL / W VDD ) is about 1.1 to about 2. In the illustrated embodiment, the edges (and center lines) of the bit line 280I and the inverted bit line 280J are offset relative to the edges (and center lines) of the underlying active regions 205A and 205D, respectively. The offset increases the cross-sectional area of ​​the interconnection region between the bit line 280I and the inverted bit line 280J and the corresponding underlying S / D contact vias 270I and 270J. In addition, the width W of the bit line 280I and the inverted bit line 280J is BL The width W1 of the active regions 205A and 205D may be greater than the width W1 of the active regions 205A and 205D. BL The ratio of the width W1 (i.e. W BL / W1) is from about 1.1 to about 1.5.

[0057] Figure 7 A portion of an SRAM array according to the present disclosure (eg Figure 2 300 - 1 is a layout of various layers of the memory array 32 of the SRAM array (part of the memory array 32 in FIG. 300 ). Specifically, the layout 300 - 1 includes the active regions and gate structures of the DL level, the V0 level, and the M0 level as part of the FMLI of the SRAM array, and the BV0 level and the BM0 level as part of the BMLI of the SRAM array. For visual clarity and better understanding of the inventive concepts of the present disclosure, Figure 7 The layout 300-1 is simplified. For example, some features including the well region, S / D contacts, and docking contacts are omitted. In the illustrated portion of the layout 300-1, four SRAM cells are arranged along the X direction and the Y direction to form a 2×2 sub-array within the SRAM array. Each SRAM cell can be used as shown in FIG. Figure 5 and Figure 6 The layout 200 of the SRAM cell 50 shown in FIG. 2 shows that two adjacent SRAM cells in the X direction are symmetrical with respect to the common boundary line between them, and two adjacent SRAM cells in the Y direction are symmetrical with respect to the common boundary line between them. Figure 2 Columns are referred to as being in the Y direction of the array and rows are referred to as being in the X direction of the array. Figure 8 The following diagram shows some embodiments of the present disclosure. Figure 7 A cross-sectional view of the SRAM array taken along line AA in FIG.

[0058] Because adjacent cells in the array are mirror images along a common boundary between adjacent cells, some active areas in an SRAM cell may extend across multiple SRAM cells in a row. Figure 7, the active area 205A of transistors PG-1 and PD-1 in one SRAM cell extends into an adjacent SRAM cell, serving as the active area of ​​transistors PD-1 and PG-1 in the adjacent SRAM cell. The active area 205C of transistor PU-2 in one SRAM cell extends into an adjacent SRAM cell, serving as the active area of ​​transistor PU-2 in the adjacent SRAM cell. The active area 205D of transistors PG-2 and PD-2 in one SRAM cell extends into an adjacent SRAM cell, serving as the active area of ​​transistors PD-2 and PG-2 in the adjacent SRAM cell. Similarly, some gate structures can be shared by multiple SRAM cells in a column. For example, the gate structure of transistor PG-1 in one SRAM cell extends into an adjacent SRAM cell, serving as the gate structure of transistor PG-1 in the adjacent SRAM cell. The gate structure of transistor PG-2 in one SRAM cell extends into an adjacent SRAM cell, serving as the gate structure of transistor PG-2 in the adjacent SRAM cell. The spacing between active regions along the Y direction and the spacing between gate structures along the X direction can be uniform. This configuration can improve the uniformity of the array layout. Figure 7 Also depicted are metal lines of the M0 level, such as bit line 280I, inverted bit line 280J, VDD line 280E as global metal lines extending across multiple SRAM rows, and word line landing pads 280A / 280L, VSS landing pads 280G / 280H as local metal lines.

[0059] Common Reference Figure 7 and Figure 8In the SRAM device design, the power rails and signal lines are not necessarily all formed on the front side of the integrated circuit structure, but can be distributed on the front and back sides of the integrated circuit. For example, the integrated circuit structure may include FMLI and BMLI that are respectively arranged on the front and back sides of the integrated circuit structure and configured to connect various components of the pull-up device, the pull-down device, and the through-gate device to form an SRAM cell. The design of this configuration takes into account various factors and parameters, including the size of various conductive components, packaging density, resistance of conductive components, parasitic capacitance between adjacent conductive components, overlap offset, and process margin. In the illustrated embodiment, some signal lines, especially the bit line BL and the inverted bit line (complementary bit line) BLB in the bit line pair, are also formed on the back side of the SRAM array. In this context, if not separately indicated, the bit line BL and the inverted bit line BLB may also be collectively referred to as a bit line. Therefore, the bit lines and inverted bit lines formed on the front side of the SRAM array may be collectively referred to as front side bit lines (BL and BLB), and the bit lines formed on the back side of the SRAM array may be collectively referred to as back side bit lines (B-BL and B-BLB). The front side and back side bit lines may be collectively referred to as double side bit lines, or just bit lines. Double side bit lines may reduce resistance along the bit line control signal path by about 30% to about 50% compared to the front side bit lines alone.

[0060] On the back side of the SRAM array, the shown portion of the BMLI includes the BV0 level and the BM0 level. The BV0 level includes backside vias (or backside source / drain contacts) B-270I and B-270J. The backside vias B-270I and B-270J can be regarded as the corresponding portions of the frontside source / drain contacts and contact vias. Similar to the function of the frontside source / drain contacts and contact vias that electrically couple the source regions of the pass-gate transistors PG-1 and PG-2 to the frontside bit line (BL) 280I and the frontside anti-bit line (BLB) 280J, respectively, the backside vias B-270I and B-270J electrically couple the source regions of the pass-gate transistors PG-1 and PG-2 to the backside bit line (B-BL) B-280I and the backside anti-bit line (B-BLB) B-280J, respectively. The backside vias B-270I and B-270J may have the same size as the active areas 205A and 205D along the Y direction, respectively. This is due to an exemplary backside manufacturing process, in which the backside vias are formed by etching the fin-shaped substrate in the active area from the back side to form a backside trench and filling the backside trench with a conductive material. Therefore, the backside via inherits the width of the active area. In other words, the backside vias B-270I and B-270J may each have the same width W1 as the active areas 205A and 205D.

[0061] The BM0 level includes a backside bit line B-280I and a backside inverted bit line B-280J as global metal lines that extend longitudinally through the array in the X direction and are shared by multiple SRAM cells in the same row. The backside bit line B-280I is directly below the corresponding frontside bit line 280I and is electrically coupled to the corresponding frontside bit line 280I through an electrical path including a backside via B-270I, a source / drain feature of a through-gate transistor PG-1, a source / drain contact 260I, and a source / drain contact through-hole 270I. Similarly, the backside inverted bit line B-280J is directly below the corresponding frontside inverted bit line 280J and is electrically coupled to the corresponding frontside inverted bit line 280J through an electrical path including a backside via B-270J, a source / drain feature of a through-gate transistor PG-2, a source / drain contact 260J, and a source / drain contact through-hole 270J.

[0062] The back side bit line B-280I and the back side bar bit line B-280J each have a width W B-BL Since the thickness of the metal lines formed in the backside manufacturing process is generally greater than that of the metal lines formed in the frontside manufacturing process, the width of the backside signal lines can be smaller than that of the frontside signal lines while maintaining similar resistance due to the greater thickness. Figure 8 As shown, the thickness T of the back side bit line B-280I and the back side bar bit line B-280J is B-BL Greater than or equal to the thickness T of the front bit line 280I and the bar bit line 280J BL (T B-BL ≥T BL ), width W B-BL Less than or equal to width W BL (W B-BL ≤W BL ). In some embodiments, the width W B-BL With width W BL The ratio (i.e. W B-BL / W BL ) is about 0.2 to about 1 (0.2≤W B-BL / W BL ≤1). This range is not arbitrary or trivial. Having narrower backside signal lines helps to increase the line spacing (e.g. Figure 7 The distance S between the opposite edges of two adjacent dorsal antiphase lines B-280J B1 At the same time, if the ratio is less than about 0.2, the resistance of the backside signal line may become too large and adversely affect the signal swing margin due to the large voltage drop along the signal line.

[0063] In order to further expand the spacing between adjacent backside signal lines to further reduce parasitic capacitance, the backside signal lines can only overlap with the corresponding backside vias to save more line spacing. overlap can be smaller than the length (L overlap <W1). For example, Figure 7 and Figure 8 As shown, the center line of the backside bit line B-280I can deviate from the center line of the corresponding active area 205A, thereby deviating from the center line of the backside through hole B-270I, resulting in a partial overlap between the backside bit line B-280I and the backside through hole B-270I. The edge of the backside bit line B-280I can also deviate from the edge of the corresponding active area 205A. Figure 7 As shown, in the top view, one edge of the back side bit line B-280I can be aligned with the corresponding edge of the front side bit line 280I. In some embodiments, both edges of the back side bit line B-280I can be aligned with both side edges of the front side bit line 280I (thus W B-BL =W BL ). Alternatively, the two edges of the back side bit line B-280I may also deviate from the two side edges of the front side bit line 280I. Similarly, the center line of the back side anti-bit line B-280J may deviate from the center line of the corresponding active area 205D, thereby deviating from the center line of the back side through hole B-270J, resulting in a partial overlap between the back side anti-bit line B-280J and the back side through hole B-270J. The edge of the back side anti-bit line B-280I may also deviate from the edge of the corresponding active area 205D. Figure 7 As shown, in the top view, one edge of the back-side anti-bit line B-280J can be aligned with the corresponding edge of the front-side anti-bit line 280J. In some embodiments, the two edges of the back-side anti-bit line B-280J can be aligned with the two side edges of the front-side anti-bit line 280J (so that W B-BL =W BL Alternatively, the two edges of the back-side anti-phase line B-280J may also deviate from the two side edges of the front-side anti-phase line 280J. overlap The ratio of the length of the backside through hole (which is also the length of the corresponding active area in the illustrated embodiment) W1 is about 0.3 to about 1 (0.3 <L overlap / W1<1). This range is not arbitrary or trivial. Having a ratio equal to or greater than 1 can reduce the inter-line spacing between adjacent backside signal lines, thereby increasing parasitic capacitance. At the same time, if the ratio is less than 0.3, the contact resistance between the backside signal line and the backside via may become too large, adversely affecting the signal swing margin due to the large voltage drop along the signal line. In some embodiments, the width W B-BL The ratio of the width W1 is about 0.3 to about 2 (0.3 <WB-BL / W1<2). This range is not arbitrary or trivial. Keeping the ratio within this range maintains a balance between the active area width for current drive capability in high performance and / or high current transistor designs and the parasitic resistance and capacitance requirements of the backside signal lines.

[0064] Fig. 9 shows an alternative layout 300 - 2 of layers of a portion of an SRAM array according to some embodiments of the present disclosure, Fig.10 Shown along Fig. 9 The cross-sectional view of the SRAM array taken along line AA in FIG. Fig. 9 and Fig.10 The layout 300-2 and its cross-sectional view are similar to those shown in FIG. Figure 7 and Figure 8 Arrangement 300-1 and its cross-sectional view are shown. Layout 300-2, however, provides increased inter-line spacing in the backside signal lines, which results in a reduction in parasitic capacitance.

[0065] One difference between layouts 300-1 and 300-2 is that Fig. 9 The shapes of the backside bit line B-280I and the backside bar bit line B-280J are similar to those shown in FIG. Figure 7 More specifically, in addition to having a uniform width W B-BL In addition to the rectangular shape, Fig. 9 The backside bit line B-280I and the backside bar bit line B-280J are shown to have non-uniform widths. Fig. 9 As shown, the back side bit line B-280I and the back side bar bit line B-280J each include a width W extending longitudinally along the X direction. B-BL1 The protrusion itself has a width W measured along the Y direction. jog and the length L measured along the X direction jog That is, the backside bit line B-280I and the backside bar bit line B-280J have a width W measured at the protruding portion. B-BL2 , that is, W B-BL2 =W B-BL1 +W jog The protrusion provides sufficient contact area between the backside signal line and the backside through hole, allowing the main part of the backside signal line to shrink, thereby reducing the line spacing S B1 Two additional cam widths were added to achieve S B2 (i.e. S B2 =S B1 +2×W jog ).

[0066] In the embodiment shown, the length L of the projection is jog= is equal to the polysilicon pitch. In the illustrated embodiment, the gate structures are uniformly distributed along the X direction, and the distance between two adjacent gate structures is uniform. The uniform distance is denoted as the gate pitch or polysilicon pitch ("PP"). In various embodiments, the length L of the protruding portion is jog The ratio of the polysilicon pitch is about 0.5 to about 1.5 (0.5 <L jog / PP<1.5). In various embodiments, the width W of the protruding portion jog The width W measured at the protruding part B-BL2 The ratio is about 0.3 to about 0.7 (0.3≤W jog / W B-BL2 ≤0.7). This range is not arbitrary or trivial. Keeping the ratio within this range can maintain a balance between the parasitic resistance and capacitance requirements of the backside signal line and improve device performance. In some embodiments, the width W B-BL1 The ratio of the width W1 of the active region 205A is about 0.3 to about 2 (0.3 <W B-BL1 / W1<2). This range is not arbitrary or trivial. Keeping the ratio within this range maintains a balance between the active area width for current drive capability in high performance and / or high current transistor designs and the parasitic resistance and capacitance requirements of the backside signal lines.

[0067] like Figure 8 and Fig.10 One difference between the cross-sectional views shown is that Figure 8 As shown, the backside bit line B-280I and the backside bar bit line B-280J have the same width W B-BL , but if Fig.10 As described above, the widths of the backside bit line B-280I and the backside inverted bit line B-280J are different. This difference is caused by the fact that along Fig.10 The cross-sectional view of line AA in FIG. 1 passes through a region with a smaller width W. B-BL1 The main part of the back side bit line B-280I and the larger width W B-BL2 The protruding part of the dorsal anti-phase line B-280J.

[0068] Now refer to Fig.11 and Fig.12 . Fig.11 Memory macro 30 ( Figure 2 ), which includes the first two rows (rows 1-2) of the memory array 32 and a portion of the logic cells in the I / O circuit (or I / O region) 34. For clarity, Fig.11 It is simplified to better understand the inventive concepts of the present disclosure. For example, Fig.11Some features including well regions, active regions, gate structures, S / D contacts, butt contacts, and through holes are omitted. Meanwhile, in order to better illustrate the embodiment, the first two columns and the first two rows (i.e., BC 11 , B.C. 12 , B.C. 21 , B.C. 22 )’s SRAM cell at the V0 level and backside vias at the BV0 level. Fig.12 An alternative layout 400 - 2 is shown in accordance with some embodiments of the present disclosure. Fig.11 and 12 The layouts 400-1 and 400-2 shown in FIG. 4 are similar. One difference is that Fig.11 The backside signal lines shown are Figure 7 The uniform width (W B-BL ), Fig.12 The backside signal lines shown are configured with Fig. 9 The non-uniform width (W) of the protrusion shown B-BL1 and W B-BL2 ).

[0069] As described above, the gate structures intersect the corresponding active regions when forming transistors. The transistors formed at the intersections of the active regions and gate structures within the memory array 32 are dedicated to forming SRAM cells. The transistors formed at the intersections of the active regions and gate structures within the I / O region 34 are dedicated to forming logic cells. In the illustrated embodiment, the transistors in the SRAM array 32 form a plurality of SRAM cells, such as SRAM cells BC. 11 , B.C. 12 , B.C. 21 , B.C. 22 (collectively referred to as SRAM cells BC). Each SRAM cell in the array can be used as Figure 5 200 of the SRAM cell 50 shown in FIG. 200 . In some embodiments, two adjacent SRAM cells in the X direction are line symmetric with respect to the common boundary between them, and two adjacent SRAM cells in the Y direction are also line symmetric with respect to the common boundary between them. That is, a 2x2 subarray formed by four SRAM cells can be used as shown in FIG. Figure 7 or Fig. 9 The layout 300 shown. Specifically, the SRAM cell BC 12 It is SRAM cell BC 11 A replica of the cell, but flipped on the Y axis; SRAM cell BC 22 It is SRAM cell BC 12 A replica of the cell, but flipped on the X axis; SRAM cell BC 21 It is SRAM cell BC 11A copy of the cell, but flipped on the X axis.

[0070] In the illustrated embodiment, the transistors in the I / O region 34 form a plurality of logic cells. The logic cells may be standard cells, such as inverters (INV), AND gates, OR gates, NAND gates, NOR gates, flip-flops, scanners, etc. The logic cells implement various logic functions for the SRAM cells BC. The logic functions of the logic cells include, for example, write decoding and / or read decoding, word line selection, bit line selection, data driving, and memory self-test. As shown, each logic cell has a logic cell height CH, which is half the height H of the SRAM cell (H=2×CH). Therefore, the two logic cells have a border, whose opposite edges are aligned with the opposite edges of the border of one SRAM cell, the edges are spaced apart in the Y direction, and each edge extends in the X direction.

[0071] Between the opposing boundary lines of the SRAM cells in the memory array 32 and the logic cells in the I / O region 34 is an active area transition region 40, or simply a transition region. The transition region 40 provides isolation between transistors formed in the memory array 32 and transistors formed in the I / O region 34. Metal lines in the FMLI and / or BMLI extend through the transition region 40 to provide electrical connections between the memory array 32 and the I / O region 34.

[0072] In the illustrated embodiment, the I / O region 34 of the M0 level includes a plurality of metal tracks arranged in parallel. Specifically, in the layout 400-1 or 400-2, two adjacent logic cells include eleven metal tracks arranged in sequence from the first (M0 track 1) to the eleventh (M0 track 11) along the Y direction. The center line of the metal track is represented by a horizontal dotted line.

[0073] The metal lines at the M0 level in the SRAM cell are aligned with the metal tracks in the I / O region 34, allowing the metal lines in the logic cell to extend into the SRAM cell. Therefore, no edge cells are required to provide metal transitions between the SRAM cell and the logic cell. In the M0 track 1, the VSS line extends to the SRAM cell BC 11and merged with the VSS landing pad. In M0 track 2, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 3, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 4, the metal line as the bit line BL in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the bit line BL of multiple SRAM cells in the same row. In M0 track 5, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 6, the metal line as the VDD line in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the VDD line of multiple SRAM cells in the same row. In M0 track 7, the metal line as the signal line in the logic cell is maintained in the boundary of the corresponding logic cell. In M0 track 8, the metal line as the inverted bit line BLB in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the inverted bit line BLB of multiple SRAM cells in the same row. In M0 track 9, the metal lines as signal lines in the logic cells are kept in the boundaries of the corresponding logic cells. In M0 track 10, the metal lines as signal lines in the logic cells are kept in the boundaries of the corresponding logic cells. In M0 track 11, the metal lines as VSS lines in the logic cells can extend through the boundaries of the respective logic cells but do not contact the word line WL landing pads.

[0074] The boundary of the SRAM cell may be adjacent to the boundary of one or two logic cells. One or two logic cells provide 2*N+1 metal tracks, where N is an integer. The metal line in the center metal track (the N+1th metal track) extends into the SRAM cell as a common VDD line for the SRAM cell and one or two logic cells. For the SRAM cell and one or two logic cells, two metal lines in two metal tracks that are equidistant from the center metal track extend into the SRAM cell as a bit line BL and an inverted bit line BLB, respectively. The two metal lines in the first and (2*N+1)th metal tracks extend across the boundary of one or two logic cells and are connected to one of the VSS landing pads in the SRAM cell.

[0075] In the illustrated embodiment, the metal lines in metal tracks 4 and 8 extend from the logic cell and pass through the SRAM cell located in the same row as the bit line BL and the inverted bit line BLB, respectively. Alternatively, depending on the layout, it may be the metal lines in metal tracks 2 and 10, or the metal lines in metal tracks 3 and 9, or the metal lines in metal tracks 5 and 7, which extend from the logic cell as the bit line BL and the inverted bit line BLB, respectively, and pass through the SRAM cell. Each bit line BL has its corresponding backside bit line B-BL on the back side of the memory array 32, and each inverted bit line BLB has its corresponding backside inverted bit line B-BLB on the back side of the memory array 32. As described above, in this context, if not separately indicated, the bit line BL and the inverted bit line BLB may also be collectively referred to as the front side bit line, and if not separately indicated, the backside bit line B-BL and the backside inverted bit line B-BLB may also be collectively referred to as the backside bit line.

[0076] In layouts 400-1 and 400-2, both the front bit lines (BL, BLB) and the back bit lines (B-BL, B-BLB) extend from column 1 through the SRAM cells in the same row to column N and electrically couple the SRAM cells in the same row to the same bit line control signal. In some embodiments, by making the back bit lines parallel to the corresponding front bit lines, the resistivity along the bit line control signal path is reduced by about 30% to about 50%. Fig.11 In the example, each front side bit line (BL or BLB) has a uniform width W. BL Each backside bit line (B-BL or B-BLB) also has a uniform thickness W B-BL .exist Fig.12 In the example, each front side bit line (BL or BLB) has a uniform width W. BL , and each backside bit line (B-BL or B-BLB) has a non-uniform width, with a major portion having a smaller width W B-BL1 The larger width of the protruding part is W B-BL2 The edge-to-edge spacing S between two adjacent backside bit lines BL ( Fig. 9 S B2 ) can be uniform. Since there are four backside bit lines spaced apart along the Y direction in two adjacent SRAM cells (each with a cell height H), the width of each bit line is W B-BL1 , so the edge-to-edge spacing S BL It can be expressed as S BL =(2×H-4×W B-BL1 ) / 4.

[0077] Reference now Fig.13 , which shows a memory macro 30 ( Figure 2). In layouts 400-1 and 400-2, SRAM cells in different locations of the SRAM array 32 are fed by backside bit lines of the same geometry along with the frontside bit lines. In some applications, the preference for the resistivity of the bitline control signal path may vary depending on whether the SRAM cells are located close to the I / O periphery or at a distance from the I / O periphery. For SRAM cells in columns far from the I / O periphery, the higher resistivity along the bitline control signal path and the corresponding narrower bit lines help achieve reduced parasitic capacitance, thereby achieving faster access times and lower power consumption. In contrast, for SRAM cells in columns close to the I / O periphery, the smaller resistivity along the bitline control signal path and the corresponding wider bit lines help achieve reduced resistance, which helps maintain voltage margin and signal integrity along the bit lines. Alternative layout 400-3 illustrates such an embodiment.

[0078] and Fig.11 and Fig.12 Similar, for simplicity, Fig.13 The front side bit lines (BL, BLB) and back side bit lines (B-BL, B-BLB) in the first two rows (rows 1-2) of the memory array 32 are shown, while many other features are omitted. To better illustrate the embodiment, some vias of the V0 level in the SRAM cell and the back side vias of the BV0 level are shown.

[0079] In the memory array 32, each front side bit line (BL or BLB) and back side bit line (B-BL or B-BLB) is shared by the memory cells in the same row from column 1 to column N. In other words, the N memory cells of the same row are coupled to (or fed by) the same bit line (front side bit line or back side bit line). In some embodiments, N is a power of 2, such as 64, 128, 256, 512, etc. In further embodiments, N is greater than 128 (e.g., N ≥ 256). The present disclosure contemplates that N is any other integer.

[0080] Each front side bit line (BL or BLB) is a line having a uniform width W along the X direction. BL Each backside bit line (B-BL or B-BLB) has a first portion (or segment) coupled to the SRAM cell from column 1 to column Q-1 and a second portion (or segment) coupled to the SRAM cell from column Q to column N. The first portion is a width W along the X axis. B-BL The second part is a straight line along the X direction, but has a first width W. B-BL1 The main part and the second width W B-BL2 Since the first width W B-BL1 Less than uniform width W B-BL, so the second part exhibits a smaller parasitic capacitance. In various cases, the second width W B-BL2 can be equal to, less than, or greater than the uniform width W B-BL . In the illustrated embodiment, the second width W B-BL2 is equal to the uniform width W B-BL .

[0081] The first part of the dorsal bit line (B - BL or B - BLB) feeds the Q - 1 SRAM cells located closer to the I / O region 34, and the second part feeds the N - Q + 1 (defined as P) SRAM cells located at a greater distance from the I / O region 34. In some embodiments, Q = N - 63, meaning the last 64 (P = 64) SRAM cells are fed by the narrower part of the dorsal bit line, while the remaining N - 64 SRAM cells in the same row are fed by the longer part of the dorsal bit line. In some embodiments, Q = N - 31, meaning the last 32 (P = 32) SRAM cells are fed by the narrower part of the dorsal bit line, while the remaining N - 32 SRAM cells in the same row are fed by the wider part of the dorsal bit line. In some embodiments, P is greater than 0 and not greater than 64 (0 < P ≤ 64). This range is not arbitrary or trivial because the last 64 SRAM cells may be most affected by parasitic capacitance. In certain embodiments, P is not less than 32 and not greater than 64 (32 ≤ P ≤ 64). In some embodiments, P can be equal to one - quarter of N (P = N / 4), which means that the last quarter of the SRAM cells at the distal end relative to the I / O perimeter are fed by the narrower part of the dorsal bit line. In some other embodiments, P can be equal to half of N (P = N / 2), which means that the latter half of the SRAM cells at the distal end relative to the I / O perimeter are fed by the narrower part of the dorsal bit line. The transition from the larger width W B-BL to the smaller width W B-BL1 can occur at the cell boundary line between column Q - 1 and column Q. Alternatively, the width transition can be within the cell boundary of the SRAM cell at column Q - 1 or within the cell boundary of the SRAM cell at column Q (as Fig.13 shown).

[0082] Since the metal line width affects the parasitic capacitance, which may impede the circuit speed, the smaller width W B-BL1 reduces the overall parasitic capacitance of the combination of the front - side and dorsal bit lines, thereby improving the circuit speed and reducing the power consumption of the SRAM cells in the last few columns of the memory array 32 without affecting the voltage margin of the remaining SRAM cells along the bit line. At the same time, the larger width W B-BLReduces the resistance of the back-side bit line, thereby reducing the overall resistance of the combination of the front-side and back-side bit lines, which increases the voltage margin along the bit line control signal path and improves signal integrity. Although the larger width W B-BL introduces more parasitic capacitance for the first few columns of the memory array 32, the benefit of a smaller voltage drop across all SRAM cells along the bit line outweighs the slight circuit speed trade-off due to the slightly larger parasitic capacitance.

[0083] As referred to above Fig. 9 described, the bulged portion of the back-side bit line (B-BL or B-BLB) will provide sufficient contact area between the back-side signal line and the back-side via. To facilitate the embodiment as Fig.13 shown, if the second portion of the back-side bit line can have sufficient contact area with the back-side via without the bulged portion, the uneven portion can be omitted. As Fig.14 shown, such an embodiment is shown in layout 400-4. In layout 400-4, the length of the back-side via along the Y direction is substantially similar to the width W1 of the active region, the second portion of the back-side bit line overlaps with the back-side via, and the width along the Y direction is W overlap . If the ratio of the width W overlap to the width W1 is from about 0.3 to about 0.7, it is considered that the second portion of the back-side bit line (B-BL or B-BLB) provides sufficient contact area, and the bulged portion can be optionally omitted. To better align with the back-side via, the edge of the second portion of the back-side bit line (B-BL or B-BLB) can deviate from the edge of the first portion. Fig.14 shows an enlarged area where the transition from the first portion to the second portion occurs. The first distance J1 represents the first distance along the Y direction between the first edge of the first portion and the first edge of the second portion, and the second distance J2 represents the second distance along the Y-axis direction between the second edge of the first portion and the second edge of the second portion. The center line of the second portion also deviates from the center line of the first portion to provide more overlapping area with the back-side via, such that J1 is less than J2 (0 < J1 < J2). As a comparison, in Fig.13 , sufficient overlapping area is provided by the bulged portion, and J2 can take a zero value (J2 = 0), such that the second edges of the first portion and the second portion can be aligned.

[0084] To facilitate the embodiment as Fig.14 shown, since the SRAM cells from column Q to column N are more sensitive to parasitic capacitance but less sensitive to resistance, the second portion of the back-side bit line can be omitted. As Fig.15As shown, such an embodiment is shown in layout 400-5. In layout 400-5, each front side bit line (BL or BLB) is a straight line with a uniform width WBL along the X direction. Each back side bit line (B-BL or B-BLB) has only a first portion (or segment) coupled to the SRAM cell from column 1 to column Q-1, and no second portion (or segment) coupled to the SRAM cell from column Q to column N. The first portion can be a straight line with a uniform width WBL along the X axis. B-BL The straight line (such as Fig.15 ), or may be a first width W along the X direction. B-BL1 The main part and the second width W B-BL2 The protruding part (such as Fig. 9 In other words, the combination of the front bit line and the back bit line feeds the number Q-1 SRAM cells located closer to the I / O area 34, while the front bit line only feeds the number N-Q+1 (P) SRAM cells located farther from the I / O area 34. Fig.15 As shown, the backside bit line (B-BL or B-BLB) can terminate within the cell boundary of the SRAM cell at column Q to ensure good contact with the backside via located at the cell boundary line between column Q-1 and column Q. Without the second portion of the backside bit line (B-BL or B-BLB), the parasitic capacitance of the SRAM cell located far away from the I / O region 34 is smaller, which improves the circuit speed.

[0085] In such Fig.15 In an extended form of the embodiment shown, since the SRAM cells from column Q to column N are more sensitive to parasitic capacitance but less sensitive to resistance, the front bit lines (BL or BLB) of the last few columns of SRAM cells can be omitted. Fig.16 As shown, such an embodiment is shown in layout 400-6. In layout 400-6, each backside bit line (B-BL or B-BLB) may have a uniform width W along the X direction. B-BL The straight line (such as Fig.16 ), it may also be along the X direction but with a first width W B-BL1 The main part and the second width W B-BL2 The straight line of the protruding part (see Fig. 9 ). Each front-side bit line (BL or BLB) has only a first portion (or segment) coupled to the SRAM cell from column 1 to column Q-1, and no second portion (or segment) coupled to the SRAM cell from column Q to column N. The first portion may be a uniform width W along the X direction. BLIn other words, the combination of the front and back bit lines feeds the number Q-1 SRAM cells located closer to the I / O region 34, while the back bit line only feeds the number N-Q+1 (P) SRAM cells located farther from the I / O region 34. Fig.16 As shown, the front side bit line (BL or BLB) can be terminated within the cell boundary of the SRAM cell at column Q to ensure good contact with the front side via located on the cell boundary line between column Q-1 and column Q. Without the second portion of the front side bit line (BL or BLB), the SRAM cell located at the far end of the I / O region 34 has less parasitic capacitance, which improves circuit speed.

[0086] The present disclosure also contemplates other possible combinations of front and back bit lines. For example, the first third of the SRAM cells at the proximal end relative to the I / O perimeter may be fed by a combination of front and back bit lines each having a uniform width, the second third of the SRAM cells in the middle of the memory array may be fed by a combination of back bit lines having a uniform width and back bit lines having a bulge and thus having a reduced width, and the last third of the SRAM cells at the distal end relative to the I / O perimeter may be fed only by the front bit lines.

[0087] The present disclosure also contemplates the addition of Figure 3 The memory array is formed of SRAM cells other than the illustrated single-port (SP) six-transistor (6T) SRAM cell 50. For example, the single-port SRAM cell and / or the multi-port SRAM cell may include various numbers of transistors to meet performance requirements, such as six transistors (6T), seven transistors (7T), eight transistors (8T), ten transistors (10T), or even more. Fig.17 An example circuit schematic of a dual-port SRAM cell 50' including seven transistors (7T) is shown. The dual-port SRAM cell 50' includes a write port 50W and a read port 50R. The write port 50W includes pull-up transistors PU-1, PU-2, pull-down transistors PD-1, PD-2, and pass-gate transistors PG-1, PG-2. In the illustrated embodiment, transistors PU-1 and PU-2 are p-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are n-type transistors.

[0088] The drains of the pull-up transistor PU-1 and the pull-down transistor PD-1 are coupled together, and the drains of the pull-up transistor PU-2 and the pull-down transistor PD-1 are also coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a data latch. The gates of transistors PU-1 and PD-1 are coupled together and coupled to the common drain of transistors PU-2 and PD-2 to form a storage node SN, and the gates of transistors PU-2 and PD-2 are coupled together and coupled to the common drain region of transistors PU-1 and PD-1 to form a complementary storage node SNB. The sources of the pull-up transistors PU-1 and PU-2 are coupled to the power supply voltage VDD, and the source regions of the pull-down transistors PD-1 and PD-2 are coupled to the voltage VSS, which may be an electrical ground in some embodiments.

[0089] The storage node SN of the data latch is coupled to the bit line W_BL of the write port 50W by the pass gate transistor PG-2, and the complementary storage node SNB is coupled to the complementary bit line W_BLB of the write port 50W by the pass gate transistor PG-1. The storage node SN and the complementary storage node SNB are complementary nodes, which are usually at opposite logic levels (logic high or logic low). The gates of the pass gate transistors PG-1 and PG-2 are coupled to the word line W_WL of the write port 50W.

[0090] The read port 50R of the SRAM cell 50' includes a read port pass-gate transistor (R-PG) connected between the bit line R_BL and the storage node SN (or connected to the gates of transistors PU-1 and PD-1). The gate of the read port pass-gate transistor R-PG is coupled to the word line R_WL of the read port 50R. In the illustrated embodiment, the transistor R-PG is a p-type transistor. That is, in the dual-port SRAM cell 50', the pass-gate transistor in the write port is an n-type transistor, and the pass-gate transistor in the read port is a p-type transistor.

[0091] Fig.18 and Fig.19 It shows that Fig.17 The layout 500 of the SRAM cell 50' is shown, wherein Fig.18 The DL level, CO level and V0 level of the layout 500 are shown. Fig.19 Shown are the V0 level and the M0 level of the layout 500. The dual-port SRAM cell 50' includes active regions 502 and 504. The active regions 502 and 504 are both located in Fig.18. The active area 502 is a component of the write port 50W, and the active area 504 has a side portion that is a component of the read port 50R and the rest of the component that is the write port 50W. In other words, the active area 504 is shared by the read port 50R and the write port 50W. In the illustrated embodiment, the active area 504 belongs to the transistors PU-1, PU-2, and R-PG that are PMOS devices. Therefore, the active area 504 is formed above the n-well. At the same time, the active area 502 belongs to the transistors PG-1, PD-1, PD-2, and PG-2 that are NMOS devices. Therefore, the active area 502 is formed on the p-well (or p-type substrate). The active area 502 has a width W1 along the Y direction, and the active area 504 also has a width W2 along the Y direction. In various embodiments, according to design and performance requirements, the width W1 may be less than, equal to, or greater than the width W2. In the illustrated embodiment, the width W1 is equal to the width W2.

[0092] The dual-port SRAM cell 50' also includes gate structures 512, 514, 516, 518, and 520. The gate structures 512-520 all extend longitudinally in the Y direction. The gate structures 512, 514, 516, and 520 are components of the write port 50W. The gate structure 518 is a component of the read port 50R. The gate structures 514, 516 each extend through the two active regions 502, 504. Therefore, the gate structure 514 is shared by the transistors PD-1 and PU-1, and the gate structure 516 is shared by the transistors PD-2 and PU-2.

[0093] The boundary 540 of the dual port SRAM cell 50' is shown using dashed lines. Note that some active regions and gate structures may extend beyond the illustrated boundary 540, as these active regions and gate structures may also form components of other adjacently located SRAM cells. For example, Fig.18 As shown, the gate structure 518 extends beyond the boundary 540. The boundary 540 is longer in the X direction than in the Y direction. In other words, the boundary 540 can be rectangular. The first dimension of the boundary 540 along the X direction is represented as the cell width W, and the second dimension of the boundary 540 along the Y direction is represented as the memory cell height H. In the case where the two-port SRAM cell 50' is repeated in the memory array, the cell width W can be represented and referred to as the memory cell pitch along the X direction in the memory array, and the cell height H can be represented and referred to as the memory cell pitch along the Y direction in the memory array.

[0094] Gate contact 550A electrically connects the gate of read port pass-gate transistor R-PG (formed by gate structure 518) to the read port word line node (R_WL). Gate contact 550C electrically connects the gate of write port pass-gate transistor PG-1 (formed by gate structure 512) to the write port word line node (W_WL). Gate contact 550D electrically connects the gate of write port pass-gate transistor PG-2 (formed by gate structure 520) to the write port word line node (W_WL). Gate contact 550E electrically connects the gate of write port pull-down transistor PD-1 (formed by gate structure 514) and the gate of write port pull-up transistor PU-1 (also formed by gate structure 514) to the storage node (SN). Gate contact 550F electrically connects the gate of write port pull-down transistor PD-2 (formed by gate structure 516) and the gate of write port pull-up transistor PU-2 (also formed by gate structure 516) to the complementary storage node (SNB).

[0095] Source / drain contact 560A and source / drain contact via 570A landed thereon electrically connect the source region of the read port through-gate transistor R-PG to the read port bit line node (R_BL). Source / drain contact 560B is connected to the source / drain region adjacent to the fin cut component and remains electrically floating because there is no corresponding source / drain contact via landed thereon. Source / drain contact 560C and source / drain contact via 570C landed thereon electrically connect the source region of the write port through-gate transistor PG-1 to the write port complementary bit line node (W_BLB). Source / drain contact 560D and source / drain contact via 570D landed thereon electrically connect the source region of the write port through-gate transistor PG-2 to the write port bit line node (W_BL). Source / drain contact 560E and source / drain contact via 570E landed thereon electrically connect the common drain region of write port pass-gate transistor PG-1 and write port pull-down transistor PD-1 together with the drain region of write port pull-up transistor PU-1 to complementary storage node (SNB). Source / drain contact 560F and source / drain contact via 570F landed thereon electrically connect the common drain region of write port pass-gate transistor PG-2 and write port pull-down transistor PD-2 together with the common drain region of write port pull-up transistor PU-2 and read port pass-gate transistor R-PG to storage node (SN). Source / drain contact 560G and source / drain contact via 570G landed thereon electrically connect the common source region of write port pull-down transistor PD-1 and write port pull-down transistor PD-2 to electrical ground node Vss. The source / drain contact 560H and the source / drain contact via 570H landed thereon electrically connect the common source region of the write port pull-up transistor PU-1 and the write port pull-up transistor PU-2 to the power supply voltage node VDD. In the illustrated embodiment, each of the source / drain contacts 560A-560H is elongated and has a longitudinal direction in the Y direction, which is parallel to the extension direction of the gate structure.

[0096] The storage node SN includes a gate contact 550E and a source / drain contact through hole 570F located on two opposite sides of the gate structure 516. As discussed in further detail below, the metal line of the M0 level extends in the X direction to pass through the gate structure 516 and connects the gate contact 550E and the source / drain contact through hole 570F. In other words, the M0 metal line is suspended above the gate structure 516 and provides a cross-coupling function between the gate contact 550E and the source / drain contact through hole 570F. Therefore, in the layout 500, the gate contact 550E and the source / drain contact through hole 570F are positioned flush in the Y direction so that the metal line extending in the X direction can connect the two. Similarly, the complementary storage node (inverted storage node) SNB includes a gate contact 550F and a source / drain contact through hole 570E located on two opposite sides of the gate structure 514. As discussed in further detail below, another metal line at the M0 level extends in the X direction to pass through the gate structure 514 and connect the gate contact 550F and the source / drain contact via 570E. In other words, another M0 metal line is suspended above the gate structure 514 and provides a cross-coupling function between the gate contact 550F and the source / drain contact via 570E. Therefore, in the layout 500, the gate contact 550F and the source / drain contact via 570E are positioned flush in the Y direction so that the metal line extending in the X direction can connect the two.

[0097] Fig.19 The V0 level and the M0 level of the layout 500 of the metal interconnect structure of the dual-port SRAM cell 50' are shown. At the M0 level, the SRAM cell 50' includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 500, the SRAM cell 50' includes six metal tracks arranged in sequence from the first (M0 track 1) to the sixth (M0 track 6) along the Y direction. The center line of the metal track is Fig.19 The dotted line in .

[0098] In layout 500, the first metal track "M0 Track 1" includes a global metal line 680A, which is a VSS line electrically coupled to the source / drain contact via 570G. The VSS line 680A is set on the upper edge of the SRAM cell 50' and can be shared with adjacent SRAM cells. The second metal track "M0 Track 2" includes a local metal line 680B as a pad for the write port word line (W_WL). The local metal line 680B is completely located within the SRAM cell 50' and is electrically connected to the gate contact 550C and the gate contact 550D. The third metal track "M0 Track 3" includes three local metal lines 680C, 680D and 680E. The local metal line 680C provides a landing pad for the write port complementary bit line (W_BLB). The local metal line 680C extends beyond the left edge of the SRAM cell 50' and can be shared with adjacent SRAM cells. Local metal line 680D is completely located within SRAM cell 50', local metal line 680D belongs to storage node (SN), and provides cross coupling between gate contact 550E and source / drain contact via 570F. As described above, local metal line 680D crosses gate structure 516. Local metal line 680E provides a landing pad for write port bit line (W_BL). Local metal line 680E extends beyond the right edge of SRAM cell 50' and can be shared with adjacent SRAM cells. The fourth metal track "M0 Track 4" includes local metal line 680F. Local metal line 680F is completely located within SRAM cell 50', local metal line 680F belongs to complementary storage node (SNB), and provides cross coupling between gate contact 550F and source / drain contact via 570E. As described above, local metal line 680F crosses gate structure 516. The fifth metal track "M0 Track 5" includes a global metal line 680G, which is a read port bit line (R_BL) and is electrically coupled to the source / drain contact via 570A. The sixth metal track "M0 Track 6" includes local metal lines 680H and 680I. The local metal line 680H provides a landing pad for the VDD line electrically coupled to the source / drain contact via 570H. The local metal line 680H is disposed on the lower edge of the SRAM cell 50' and can be shared with adjacent SRAM cells. The local metal line 680I provides a landing pad for the read port word line (R_WL) electrically coupled to the gate contact 550A. The local metal line 680I is disposed on the lower edge of the SRAM cell 50' and can be shared with adjacent SRAM cells.

[0099] The width of the VSS line 680A is represented as Wa, where half of Wa is in one SRAM cell and the other half of Wa is in an adjacent SRAM cell. The width of the landing pad of the VDD line 680H and the width of the landing pad of the read port word line 680I can be substantially the same as the VSS line 680A, where half of Wa is in one SRAM cell and the other half of Wa is in an adjacent SRAM cell. The other M0 metal lines 680B-680G can each have the same width represented as Wb. The spacing between two adjacent M0 metal lines can be uniform and represented as s1. Therefore, the SRAM cell height H is equal to Wa+4xWb+5xS1. Layout 200 (such as that of a single-port SRAM cell 50 having a cell height H corresponding to eleven M0 metal tracks) Fig.11 or Fig.12 Compared with the layout 500 of the dual-port SRAM cell 50', the layout 500 has a memory cell height H corresponding to six metal tracks. Therefore, the dual-port SRAM cell 50' and the logic cell (such as Fig.11 or Fig.12 ) can have the same cell height (H=CH), allowing each dual-port SRAM cell 50' to be directly adjacent to a corresponding logic cell.

[0100] Now refer to Fig. 20 and Fig.21 . Fig. 20 Memory macro 30 ( Figure 2 ), which includes the first two rows (rows 1-2) of the memory array 32 and a portion of the logic cells in the I / O circuit (or I / O region) 34. For clarity, Fig. 20 Simplified to better understand the inventive concepts of the present disclosure. Fig. 20 Some features including well regions, active regions, gate structures, S / D contacts, and vias are omitted. Fig.21 The following diagram shows some embodiments of the present disclosure. Fig. 20 A cross-sectional view of the SRAM array taken along line BB in FIG.

[0101] The memory array 32 ( Figure 2 )'s first two columns and first two rows (i.e., BC 11 , B.C. 12 , B.C. 21 , B.C. 22 ) of the M0 level, but omitted in other columns to better illustrate the embodiment. Each SRAM cell in the array can use Fig.18 and Fig.19Layout 500 of the SRAM cell 50' is shown. As described above, the dual-port SRAM cell 50' and the logic cell can have the same cell height (H=CH). The metal tracks in the SRAM cell are aligned with the alloy tracks in the logic cell, allowing the metal lines in the logic cell to extend into the SRAM cell. Therefore, no edge cells are required between the memory array 32 and the I / O region 34 to provide a metal transition for the metal lines at the M0 level. Take the SRAM cell BC at column 1 as an example. 11 and B.C. 21 For example, M0 track 1 includes a VSS line extending through the first SRAM cell and the first logic cell. M0 track 2 includes a landing pad for W-WL in the first SRAM cell and a metal line as a signal line of the first logic cell. M0 track 3 includes a landing pad for W-BLB in the first logic cell, a local metal line for SN, and a metal line for W-BL, and the metal line as W-BL extends into the first SRAM cell and merges with the landing pad for W-BL. M0 track 4 includes a local metal line for SNB in ​​the first SRAM cell and a metal line as a signal line in the first logic cell. M0 track 5 includes a metal line as R-BL, which extends through the first SRAM cell and the first logic cell. M0 track 6 includes a landing pad for VDD in the logic cell, a landing pad for R-WL, and a metal line for the VDD line. M0 track 7 includes a metal line for R-BL, which extends through the second SRAM cell and the second logic cell. M0 track 8 includes a local metal line for SNB in ​​the second SRAM cell and a metal line for a signal line in the second logic cell. M0 track 9 includes a landing pad for W-BLB in the second logic cell, a local metal line for SN, and a metal line for W-BL, the metal line for W-BL extending into the second SRAM cell and merging with the landing pad for W-BL. M0 track 10 includes a landing pad for W-WL in the second SRAM cell and a metal line for a signal line in the second logic cell. M0 track 11 includes a VSS line extending through the second SRAM cell and the second logic cell.

[0102] The layout 600-1 also includes a backside via at the BV0 level and a backside read port bit line BR-BL at the BM0 level, the backside via being disposed under the source / drain component of the read port pass-gate transistor R-PG and being electrically connected to the source / drain component of the read port pass-gate transistor R-PG, and the backside read port bit line BR-BL being disposed under the backside via and being electrically connected to the backside via. Therefore, the front side read port bit line R-BL and the back side read port bit line BR-BL are electrically coupled to each other through a circuit including the backside via, the source / drain component of the read port pass-gate transistor R-PG, the source / drain contact 560A, and the source / drain contact via 570A. Since the backside read port bit line BR-BL is formed below the SRAM cell, the size of the backside read port bit line BR-BL can be flexibly adjusted to achieve satisfactory performance. That is, the parasitic capacitance and parasitic resistance on the read port bit line can be optimized by adjusting the size (e.g., width) of the backside read port bit line BR-BL. For example, the width W of the backside read end bit line BR-BL can be adjusted B-R-BL To provide satisfactory resistance. Fig. 20 In the embodiment shown, the width W of the backside read port bit line BR-BL is B-R-BL Greater than the thickness Wb (W B-R-BL >Wb). Specifically, the backside read port bit line BR-BL along the Y direction extends from M0 track 2 to M0 track 5, with a width of about 4×Wb+3×S1 (W B-R-BL =4×Wb+3×S1).

[0103] Fig. 22 An alternative layout 600 - 2 is shown in accordance with some embodiments of the present disclosure. Fig. 22 The layout 600-2 represented in is similar to Fig. 20 The wiring 600 - 1 shown in FIG. 6 provides both reduced line width and greater spacing between lines, thereby reducing parasitic capacitance in the backside read port bit lines. Fig. 20 and Fig. 22 One difference between the two is that the backside read port bit lines BR-BL have different shapes. More specifically, compared to the Fig. 20 The backside read port bit lines BR-BL are different. Fig. 22 The backside read port bit lines BR-BL in FIG. 4 have non-uniform widths. Fig. 22 The backside read port bit lines BR-BL in the embodiment each include a plurality of backside read port bit lines BR-BL extending longitudinally along the X direction and having a width W B-R-BL1 The backside read port bit line BR-BL has a width W measured at the protruding portion. B-R-BL2The protrusion provides sufficient contact area between the backside signal line and the backside through hole, allowing the main part of the backside signal line to shrink, thereby increasing the line spacing. In other words, according to design requirements, the protrusion may only partially overlap with the corresponding backside through hole, or it may completely overlap with the corresponding backside through hole. Fig. 22 In the illustrated embodiment shown, the backside read port bit line BR-BL is located at the center of the SRAM cell (the centerline of BR-BL is located at half the cell height H), and the protruding portion overlaps the backside via portion that falls on the backside of the source / drain features of the pass-gate transistor R-PG. In various embodiments. The width W B-R-BL1 The ratio of the width W2 of the active region 504 forming the pass-gate transistor R-PG is about 0.5 to about 2 (0.5 <W B-R-BL1 / W2<2). This range is not arbitrary or trivial. Keeping the ratio within this range can maintain a balance between the active area width for current drive capability in high performance and / or high current transistor designs and the parasitic resistance and capacitance requirements of the backside signal lines.

[0104] Fig.23 An alternative layout 600-3 is shown according to some embodiments of the present disclosure. Fig.23 The layout 600-3 shown is similar to Fig. 20 The wiring 600-1 shown and Fig. 22 Arrangement 600-2 is shown. One difference is that the backside vias are formed under the source / drain features of the write port pass-gate transistors PG-1 and PG-2, and the backside signal lines are dedicated to the backside write port bit lines (BW-BL and BW-BLB) in addition to the backside read port bit line BR-BL. Fig.23 In the illustrated embodiment shown in FIG. 1 , the backside write port bit lines (BW-BL and BW-BLB) have non-uniform widths. The backside write port bit lines (BW-BL and BW-BLB) each include a plurality of backside write port bit lines extending longitudinally in the X direction and having a width W. B-W-BL1 The backside write port bit lines BW-BL and BW-BLB have a width W measured at the protruding portion. B-W-BL2 The protruding portion provides sufficient contact area between the backside signal line and the backside via, allowing the main part of the backside signal line to shrink, thereby increasing the line spacing. In other words, according to design requirements, the protruding portion may only overlap with the corresponding backside via, or may completely overlap with the corresponding backside via. In various embodiments, the width W of the active area 502 of the gate transistors PG-1 and PG-2 is formed B-W-BL1 The ratio of the width W1 is about 0.3 to about 2 (0.3 <W B-W-BL1 / W1<2). This range is not arbitrary or trivial. Keeping the ratio within this range can maintain a balance between the active area width for current drive capability in high performance and / or high current transistor designs and the parasitic resistance and capacitance requirements of the backside signal lines.

[0105] Fig.24 An alternative layout 600-4 is shown according to some embodiments of the present disclosure. Fig.24 The layout 600-4 shown is similar to Fig. 22 The wiring 600-2 shown and Fig.23 One difference is that, in addition to the layout 600-2 in which the backside signal line is dedicated to the backside read port bit line BR-BL or the layout 600-3 in which the backside signal line is dedicated to the backside write port bit lines BW-BL and BW-BLB, the layout 600-4 includes backside signal lines dedicated to the backside read port bit line BR-BL and the backside write port bit lines BW-BL and BW-BLB and the corresponding backside vias. Fig.24 In the illustrated embodiment, each backside signal line may overlap with a corresponding backside via portion to increase the spacing between lines, thereby reducing parasitic capacitance. Fig.24 As shown, the backside write port bit line BW-BL, the backside write port bar bit line BW-BLB, and the backside read port bit line BR-BL may be evenly spaced apart from each other along the Y direction. Fig.24 As shown, the backside read port bit lines BR-BL have a uniform width W B-R-BL1 , there is no protruding portion, the back side write port bit line BW-BL and the back side write port bit line BW-BLB have a width W B-W-BL1 In various embodiments, the width W of the active region 504 on which the pass gate transistor R-PG is formed is B-R-BL1 The ratio of the width W2 is about 0.3 to about 2 (ie, 0.3 < W B-R-BL1 / W2<2), and the width W of the active region 502 on which the pass-gate transistors PG-1 and PG-2 are formed B-W-BL1 The ratio of the width W1 is about 0.3 to about 2 (ie, 0.3 <W B-W-BL1 / W1<2). These ranges are not arbitrary or trivial. Ratios within these ranges maintain a balance between the active area width for current drive capability and the parasitic resistance and capacitance requirements of the backside signal lines in high performance and / or high current transistor designs. In some embodiments, width W1 is equal to width W2.

[0106] In the illustrated exemplary layouts 600-1, 600-2, 600-3, and 600-4, the backside signal lines (e.g., B-R-BL, B-W-BL, and / or B-W-BLB) each couple (or feed) all of the SRAM cells in the same row. The present disclosure also contemplates that the backside signal lines (e.g., B-R-BL, B-W-BL, and / or B-W-BLB) each couple (or feed) a portion, but not all, of the SRAM cells in the same row, similar to the discussion above with reference to layouts 400-5 and 400-6. For example, in the same row, a number Q-1 of SRAM cells proximal to the I / O perimeter may be fed by a combination of frontside bit lines (e.g., R-BL, W-BL, and / or W-BLB) and backside bit lines (such as B-R-BL, B-W-BL, and / or B-W-BLB), while a number N-Q+1 (defined as P) of SRAM cells distal to the I / O perimeter may be fed by the frontside bit lines (such as R-BL, W-BL, and / or W-BLB) without the backside bit lines. In some embodiments, Q = N-31, meaning that the last 32 (P = 32) SRAM cells are fed only by the frontside bit lines, while the remaining N-32 SRAM cells in the same row are fed by a combination of frontside and backside bit lines. In some embodiments, P is greater than 0 and not greater than 64 (0 < P ≤ 64). This range is not arbitrary or trivial because the last 64 SRAM cells may be most affected by parasitic capacitance. In certain embodiments, P is not less than 32 and not greater than 64 (32 ≤ P ≤ 64). In some embodiments, P may be equal to one quarter of N (P = N / 4), meaning that the last quarter of the SRAM cells distal to the I / O perimeter are fed only by the frontside bit lines. In some other embodiments, P may be equal to one half of N (P = N / 2), meaning that the second half of the SRAM cells distal to the I / O perimeter are fed only by the frontside bit lines.

[0107] Various embodiments of the present disclosure illustrate bit line structures that provide a combination of frontside and backside bit lines. In an SRAM array, some exemplary bit lines may have non-uniform widths (e.g., different widths along the bit line). In one embodiment, the SRAM array may have different combinations of frontside and backside bit lines for memory cells at different distances from the I / O perimeter, which improves circuit performance. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0108] In one example aspect, the present disclosure provides a semiconductor device. The semiconductor device includes: a logic cell; a memory array including a plurality of memory cells, wherein the memory cells and the logic cells are arranged in a row, and wherein a first plurality of memory cells are closer to the logic cells than a second plurality of memory cells; a front-side interconnect structure disposed above the memory cells and including a front-side bit line, wherein the front-side bit line is coupled to each memory cell arranged in the row; and a back-side interconnect structure disposed below the memory cells and including a back-side bit line, wherein the back-side bit line is coupled to at least the first plurality of memory cells, and wherein the front-side bit line is coupled to the back-side bit line through a source / drain component of a pass-gate transistor of one of the first plurality of memory cells. In some embodiments, the back-side bit line is not coupled to the second plurality of memory cells. In some embodiments, the number of the second plurality of memory cells is less than the number of the first plurality of memory cells. In some embodiments, the back-side bit line has a first portion coupled to the first plurality of memory cells and a second portion coupled to the second plurality of memory cells, and wherein the first portion of the back-side bit line is wider than the second portion of the back-side bit line. In some embodiments, the number of the second plurality of memory cells is less than the number of the first plurality of memory cells. In some embodiments, the front bit line and the back bit line have different widths. In some embodiments, the front bit line is wider than the back bit line. In some embodiments, the back bit line is wider than the front bit line. In some embodiments, the front bit line has a uniform width and the back bit line has a non-uniform width. In some embodiments, the front bit line completely overlaps the front source / drain contact landing on the source / drain component, and the back bit line partially overlaps the back source / drain contact landing below the source / drain component.

[0109] Another aspect of the present invention provides a semiconductor device. The semiconductor device includes: a memory array including a plurality of memory cells arranged in a row; a front-side interconnect structure disposed above the memory cells and including a front-side bit line, wherein the front-side bit line is coupled to at least some of the memory cells arranged in the row; and a back-side interconnect structure disposed below the memory cells and including a back-side bit line, wherein the back-side bit line is coupled to at least some of the memory cells arranged in the row, wherein in a top view of the semiconductor device, the front-side bit line partially overlaps the back-side bit line, and wherein in a cross-sectional view of the semiconductor device, the front-side bit line and the back-side bit line are both coupled to a source / drain component of a through-gate transistor of one of the memory cells. In some embodiments, in a cross-sectional view of the semiconductor device, the back-side bit line is thicker than the front-side bit line. In some embodiments, in a cross-sectional view of the semiconductor device, the front-side bit line is wider than the back-side bit line. In some embodiments, the back-side bit line is a first back-side bit line, and the back-side interconnect structure includes a second back-side bit line, and in a cross-sectional view of the semiconductor device, the first back-side bit line is wider than the second back-side bit line. In some embodiments, the front side bit line is coupled to each memory cell arranged in a row, and the back side bit line is not coupled to at least one memory cell arranged in a row. In some embodiments, the back side bit line is coupled to each memory cell arranged in a row, and the front side bit line is not coupled to at least one memory cell arranged in a row. In some embodiments, the front side bit line has a uniform width, and the back side bit line has a main portion and a protrusion protruding from the main portion.

[0110] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes: a memory array including memory cells arranged in M ​​rows and N columns, M and N are both integers; a logic area adjacent to the memory array and coupled to the memory cells; and an interconnection structure arranged above the memory array and the logic area, wherein the interconnection structure includes a front signal line suspended directly above a row of the M rows of memory cells and a back signal line arranged directly below a row of the M rows of memory cells, and wherein: the front signal line is coupled to each memory cell of a row of the M rows, the back signal line includes a first segment and a second segment, the first segment is coupled to the memory cells in the first column to the (Q-1)th column of a row of the M rows, the second segment is coupled to the memory cells in the Qth column to the Nth column of a row of the M rows, Q is an integer greater than 1 and less than N, the first column is closer to the logic area than the Nth column, and the first segment has a first width, and the second segment has a second width less than the first width. In some embodiments, N is greater than 128, and N-Q+1 is not greater than 64. In some embodiments, N-Q+1 is one quarter of N.

[0111] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: Logical unit; a memory array comprising a plurality of memory cells, wherein the memory cells and the logic cells are arranged in a row, and wherein a first plurality of memory cells of the plurality of memory cells are closer to the logic cells than a second plurality of memory cells; a front-side interconnect structure disposed above the memory cells and comprising a front-side bit line, wherein the front-side bit line is coupled to each of the memory cells arranged in a row; and a backside interconnect structure disposed below the memory cells and comprising a backside bitline, wherein the backside bitline is coupled to at least the first plurality of memory cells, and wherein the frontside bitline is coupled to the backside bitline through a source / drain feature of a pass-gate transistor of one of the first plurality of memory cells.

2. The semiconductor device according to claim 1, wherein The backside bit line is not coupled to the second plurality of memory cells.

3. The semiconductor device according to claim 1, wherein The front-side bit line and the back-side bit line have different widths.

4. The semiconductor device according to claim 1, wherein: The front side bit line completely overlaps the front side source / drain contact landing on the source / drain feature, and the back side bit line partially overlaps the back side source / drain contact landing under the source / drain feature.

5. A semiconductor device comprising: a memory array comprising a plurality of memory cells arranged in rows; a front-side interconnect structure disposed above the memory cells and comprising front-side bit lines, wherein the front-side bit lines are coupled to at least some of the memory cells arranged in the row; and a backside interconnect structure disposed below the memory cells and comprising backside bit lines, wherein the backside bit lines are coupled to at least some of the memory cells arranged in the row, Wherein, in a top view of the semiconductor device, the front side bit line partially overlaps with the back side bit line, and Wherein, in a cross-sectional view of the semiconductor device, the front-side bit line and the back-side bit line are both coupled to a source / drain component of a pass-gate transistor of one of the memory cells.

6. The semiconductor device according to claim 5, wherein: In a cross-sectional view of the semiconductor device, the backside bit line is thicker than the frontside bit line.

7. The semiconductor device according to claim 5, wherein: The front-side bit line is coupled to each of the memory cells arranged in the row, and the back-side bit line is not coupled to at least one of the memory cells arranged in the row.

8. The semiconductor device according to claim 5, wherein: The backside bit line is coupled to each of the memory cells arranged in the row, and the frontside bit line is not coupled to at least one of the memory cells arranged in the row.

9. The semiconductor device according to claim 5, wherein: The front-side bit line has a uniform width, and the back-side bit line has a main portion and a protrusion protruding from the main portion.

10. A semiconductor device comprising: A memory array comprising memory cells arranged in M ​​rows and N columns, where M and N are both integers; a logic region adjacent to the memory array and coupled to the memory cells; as well as an interconnect structure disposed above the memory array and the logic area, wherein the interconnect structure includes a front side signal line suspended above one of the M rows of memory cells and a back side signal line disposed below the one of the M rows of memory cells, and in: The front side signal line is coupled to each of the memory cells of the row of the M rows, The backside signal line includes a first section and a second section, the first section is coupled to the memory cells in the first column to the (Q-1)th column of the row among the M rows, and the second section is coupled to the memory cells in the Qth column to the Nth column of the row among the M rows, Q is an integer greater than 1 and less than N, The first column is closer to the logic region than the Nth column, and The first section has a first width, and the second section has a second width that is smaller than the first width.

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