Electronic package and substrate structure thereof

Abstract

An electronic packaging piece and a substrate structure thereof are mainly characterized in that an electronic element is arranged on the substrate structure with a circuit layer, an insulating protection layer of the substrate structure is provided with an opening for exposing the circuit layer, and the insulating protection layer is provided with a plurality of extending parts which protrude towards the inside of the opening and are arranged at intervals at the edge of the opening. Therefore, when a space between the electronic component and the substrate structure is filled with a bottom rubber material, the space between the electronic component and the substrate structure can be uniformly filled with the bottom rubber material, so that the bottom rubber material is prevented from generating an air chamber.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, in particular to an electronic packaging component and a substrate structure thereof. Background Art

[0002] With the development of the electronics industry, today's electronic products have tended to be designed to be thin, light, short and with diversified functions. Semiconductor packaging technology has also developed different packaging types. In order to meet the needs of high integration and miniaturization of semiconductor devices, in addition to the traditional wire bonding semiconductor packaging technology, the flip chip method can also be used to increase the wiring density.

[0003] Figure 1 FIG. 1 is a cross-sectional view of a conventional flip-chip semiconductor package 1. Figure 1 As shown, the insulating protection layer 12 of a packaging substrate 10 is formed with a plurality of openings 120 corresponding to the exposed circuit layer 100, so that the semiconductor chip 11 is combined with the circuit layer 100 through the openings 120 through a plurality of solder bumps 13 to electrically connect the circuit layer 100, and then a primer 14 is formed between the semiconductor chip 11 and the packaging substrate 10 to cover the solder bumps 13.

[0004] However, when the base glue 14 flows into the space between the semiconductor chip 11 and the packaging substrate 10, the base glue 14 often cannot fill the tiny gaps between the solder bumps 13, so that air chambers (voids) P are easily generated between the solder bumps 13, resulting in popcorn phenomenon (Popcorn) in the subsequent process, resulting in reduced product yield.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the invention

[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides a substrate structure, including: a substrate body having a circuit layer, which defines at least one crystal placement area; and an insulating protective layer, which is formed on the substrate body and has an opening corresponding to the crystal placement area to expose the circuit layer, wherein the insulating protective layer has a plurality of extension portions protruding toward the opening and spaced apart from each other formed at the edge of the opening.

[0007] The present invention also provides an electronic package, comprising: the aforementioned substrate structure; an electronic component disposed on the die-placement region and electrically connected to the circuit layer; and a base glue material formed between the substrate structure and the electronic component and filling the opening.

[0008] In the aforementioned electronic package and substrate structure thereof, the length of each extension portion is 1200 to 1800 microns, and the distance between each extension portion is 70 to 130 microns. In addition, the circuit layer has a plurality of conductive traces and a plurality of electrical contact pads connected to the conductive traces, so that the plurality of electrical contact pads are exposed to the single opening. For example, the electronic component is combined and electrically connected to the plurality of electrical contact pads through a plurality of conductive bumps.

[0009] In the aforementioned electronic package and substrate structure thereof, a plurality of guide blocks arranged at intervals are formed in the opening to form a plurality of channels. For example, the opening direction of the channels is the same as the mold flow direction of the base glue material.

[0010] In the aforementioned electronic package and substrate structure thereof, the insulating protection layer forms at least one recessed portion at the periphery of the die-placement region. For example, the recessed portion is connected to the opening.

[0011] In the aforementioned electronic package and substrate structure, the electronic element is combined and electrically connected to the circuit layer through a plurality of conductive bumps. For example, the bottom glue material covers the plurality of conductive bumps.

[0012] As can be seen from the above, the electronic package and substrate structure of the present invention are mainly designed by discontinuously extending the insulating protective layer, while limiting its length and spacing distance, so that when the base glue material quickly flows into the opening, the flow efficiency of the packaging colloid of the base glue material can be increased and can be evenly diffused in the space between the electronic component and the substrate structure. At the same time, the guide block can be used to allow the packaging colloid of the base glue material to diffuse by capillary action and flow along the guide block, so as to avoid the formation of air chambers in the base glue material, thereby improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0014] Figure 2A FIG. 4 is a cross-sectional schematic diagram of a first embodiment of an electronic package of the present invention.

[0015] Figure 2B FIG. 1 is a partial top view of a first embodiment of a substrate structure of the present invention.

[0016] Figure 3A FIG. 4 is a cross-sectional schematic diagram of a second embodiment of an electronic package of the present invention.

[0017] Figure 3B FIG. 1 is a partial top view of a second embodiment of a substrate structure of the present invention.

[0018] Description of Reference Numerals

[0019] 1 Semiconductor Package

[0020] 10 Package substrate

[0021] 100,200 Line Layer

[0022] 11. Semiconductor Chip

[0023] 12 Insulation protection layer

[0024] 120 Opening

[0025] 13 Solder Bumps

[0026] 14 Primer

[0027] 2,3 Electronic packaging

[0028] 2a,3a Substrate structure

[0029] 20 substrate body

[0030] 20a First surface

[0031] 20b Second surface

[0032] 200A Conductive Trace

[0033] 200b Electrical contact pad

[0034] 21 Electronic components

[0035] 21a Action surface

[0036] 21b Non-active surface

[0037] 210 Conductive bump

[0038] 22,32 Insulation protection layer

[0039] 220 Opening

[0040] 22a Extension

[0041] 23 Guide block

[0042] 230 channels

[0043] 24 Base material

[0044] 240 Overflow section

[0045] 320 recess

[0046] D Crystal placement area

[0047] F Mold flow direction

[0048] L, L1, L2 Length

[0049] P Air Chamber

[0050] t distance

[0051] S space. DETAILED DESCRIPTION

[0052] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0053] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0054] Figure 2A is a cross-sectional schematic diagram of a first embodiment of an electronic package 2 of the present invention, Figure 2B is a top view of a first embodiment of a substrate structure 2a of the present invention, and Figure 2B The circuit layer 200 is omitted.

[0055] like Figure 2A As shown, an electronic component 21 is combined onto a substrate structure 2a, and then a primer material 24 is formed between the electronic component 21 and the substrate structure 2a, wherein the substrate structure 2a includes a substrate body 20 having a circuit layer 200 and an insulating protection layer 22.

[0056] The substrate body 20 has a first surface 20a and a second surface 20b opposite to each other, and a crystal region D is defined on the first surface 20a. Figure 2B shown.

[0057] In this embodiment, the substrate body 20 is a package substrate having a core layer and a circuit structure, a package substrate having a coreless circuit structure, or other board types.

[0058] Furthermore, the substrate body 20 is formed into a package substrate by a redistribution layer (RDL) manufacturing method, and has an insulating layer and a circuit layer 200 combined with the insulating layer. For example, the circuit layer 200 is made of copper, and the insulating layer is made of a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc.

[0059] In addition, the circuit layer 200 on the first surface 20 a of the substrate body 20 has a plurality of conductive traces 200 a and a plurality of electrical contact pads 200 b connected to the conductive traces 200 a .

[0060] The insulating protection layer 22 is used as a solder mask, such as green paint, and is disposed on the first surface 20 a of the substrate body 20 . An opening 220 is formed corresponding to the crystal region D to expose the plurality of electrical contact pads 200 b .

[0061] In this embodiment, the insulating protection layer 22 is formed with a plurality of extensions 22a protruding toward the opening 220 at the edge of the opening 220, and according to simulation and actual measurement results, the length L of the extension 22a corresponding to the edge of the opening 220 is 1200 to 1800 microns, and the distance t between each of the extensions 22a is 70 to 130 microns (um). It should be understood that in a single substrate body 20, the lengths L1 and L2 of each of the extensions 22a can be the same or different.

[0062] Furthermore, a plurality of island-shaped guide blocks 23 are formed in the opening 220 at intervals to form a plurality of channels 230 in the shape of strips (which may be regular or irregular strips), and the channels 230 are arranged in a staggered manner and interconnected. For example, the material forming the guide blocks 23 is the same as or different from the material of the insulating protective layer 22. It should be understood that the channels may also be arranged side by side without being interconnected.

[0063] The electronic component 21 is an active component, a passive component or a combination thereof, and is disposed on the die-laying region D. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor or an inductor.

[0064] In this embodiment, the electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b relative to each other, and the active surface 21a is flip-chip mounted on the multiple electrical contact pads 200b through multiple conductive bumps 210 such as copper pillars, solder materials, etc. to electrically connect to the circuit layer 200.

[0065] The primer material 24 is formed between the substrate structure 2 a and the electronic component 21 and fills the opening 220 and covers the conductive bumps 210 .

[0066] In this embodiment, the primer material 24 is an insulating material, such as primer, polyimide (PI), dry film, or epoxy encapsulation colloid.

[0067] Furthermore, the outline of the die-placement region D is determined according to the shape of the electronic component 21 , and the area of ​​the die-placement region D is approximately equal to the layout range of the base glue material 24 , so that the area of ​​the die-placement region D is larger than the area of ​​the electronic component 21 .

[0068] In addition, when the process of the base glue material 24 is performed, the single opening 220 of the insulating protective layer 22 makes it possible for the insulating protective layer 22 to block the electrical contact pads 200b (the electrical contact pads 200b may also be blocked by the insulating protective layer 22, which is not shown in the figure), so that the larger particles in the base glue material 24 can easily pass through the space between the electronic component 21 and the substrate structure 2a, and the channel 230 corresponds to the filling direction of the base glue material 24, that is, the mold flow direction F (such as Figure 2B As shown in FIG. 2 , the base glue material 24 flows into the opening 220 according to the mold flow direction F. Therefore, when larger particles in the base glue material 24 touch the guide block 23, they can still bypass the guide block 23 and continue to flow to the other end along the channel 230 to avoid obstruction of the flow of the base glue material 24. At the same time, the guide block 23 can be used to allow the encapsulated colloid of the base glue material 24 to diffuse by capillary action and flow along the guide block 23.

[0069] Therefore, in the electronic package 2 of the present invention, the extension portion 22a of the substrate structure 2a is mainly designed to be discontinuous (discontinuous) and its length and spacing distance are limited. For example, the length L is designed to be 1200 to 1800 microns and the distance t between each extension portion 22a is designed to be 70 to 130 microns. When the base glue material 24 quickly flows into the opening 220, the flow efficiency of the packaging colloid of the base glue material 24 can be increased so that it can be evenly diffused in the space S between the electronic component 21 and the substrate structure 2a. Therefore, compared with the prior art, the base glue material 24 of the electronic package 2 of the present invention can fill the space S between the electronic component 21 and the substrate structure 2a (or the gap between each conductive bump 210) to avoid the formation of a void in the space S between the electronic component 21 and the substrate structure 2a (or between each conductive bump 210).

[0070] Figure 3A is a cross-sectional schematic diagram of a second embodiment of an electronic package 3 of the present invention, Figure 3B is a top view of a second embodiment of a substrate structure 3a of the present invention, and Figure 3B The circuit layer 200 is omitted. The difference between this embodiment and the first embodiment is that the insulating protection layer 32 has a newly added recess 320, and the other structures are substantially the same, so the same parts will not be described again.

[0071] like Figure 3A and Figure 3B As shown, the insulating protection layer 32 forms at least one recess 320 around the periphery of the die-laying region D.

[0072] In this embodiment, the recess 320 is connected to the opening 220. For example, the recess 320 surrounds the die-laying region D to present an annular groove, so that the insulating protection layer 32 forms an inner ring and an outer ring shape. It should be understood that the depth of the recess 320 can be equal to or less than the thickness of the insulating protection layer 32.

[0073] Therefore, the electronic package 3 of the present invention is configured with the recess 320 so that when the flow of the base glue material 24 is too much, the overflow portion 240 of the base glue material 24 can flow from the channel 230 into the recess 320, so that the recess 320 absorbs the overflow portion 240 of the base glue material 24. Therefore, even if the base glue material 24 overflows, the base glue material 24 will not improperly flow to other areas of the insulating protective layer 32 to affect the subsequent semiconductor packaging process, and can even avoid contamination of other areas.

[0074] It should be understood that the shape and position of the recess 320 can be designed according to needs and are not limited to the above.

[0075] The present invention also provides a substrate structure 2 a, 3 a, comprising: a substrate body 20 having a circuit layer 200 and an insulating protection layer 22, 32 formed on the substrate body 20.

[0076] The substrate body 20 is defined with at least one crystal region D.

[0077] The insulating protection layer 22, 32 has an opening 220 exposing the circuit layer 200, wherein the insulating protection layer 22, 32 has a plurality of extension portions 22a protruding toward the opening 220 and spaced apart formed at the edge of the opening 220, wherein the length L thereof is 1200 to 1800 microns, and the distance t between each extension portion 22a is 70 to 130 microns.

[0078] In one embodiment, the circuit layer 200 has a plurality of conductive traces 200 a and a plurality of electrical contact pads 200 b connected to the conductive traces 200 a , such that the plurality of electrical contact pads 200 b are exposed from the single opening 220 .

[0079] In one embodiment, a plurality of guide blocks 23 arranged at intervals are formed in the opening 220 to form a plurality of channels 230 .

[0080] In one embodiment, the insulating protection layer 32 forms at least one recess 320 at the periphery of the die-laying region D. For example, the recess 320 is connected to the opening 220 .

[0081] The present invention further provides an electronic package 2 , 3 , comprising: the substrate structure 2 a , 3 a , at least one electronic component 21 and a primer material 24 .

[0082] The electronic element 21 is disposed on the die-laying region D and is electrically connected to the circuit layer 200 .

[0083] The primer material 24 is formed between the substrate structure 2 a, 3 a and the electronic component 21 and fills the opening 220 .

[0084] In one embodiment, the circuit layer 200 has a plurality of conductive traces 200a and a plurality of electrical contact pads 200b connected to the conductive traces 200a, so that the plurality of electrical contact pads 200b are exposed from the single opening 220. For example, the electronic component 21 is combined and electrically connected to the plurality of electrical contact pads 200b through a plurality of conductive bumps 210.

[0085] In one embodiment, a plurality of guide blocks 23 are formed in the opening 220 and arranged at intervals to form a plurality of channels 230. For example, the opening direction of the channels 230 is the same as the mold flow direction F of the base adhesive material 24.

[0086] In one embodiment, the insulating protection layer 32 forms at least one recess 320 at the periphery of the die-laying region D. For example, the recess 320 is connected to the opening 220 .

[0087] In one embodiment, the electronic component 21 is combined and electrically connected to the circuit layer 200 through a plurality of conductive bumps 210. For example, the primer material 24 covers the plurality of conductive bumps 210.

[0088] In summary, the electronic package and substrate structure of the present invention are mainly designed with an intermittent (discontinuous) extension portion of the insulating protective layer, while limiting its length and spacing distance, so that when the base glue material quickly flows into the opening, the flow efficiency of the packaging colloid of the base glue material can be increased and can be evenly diffused in the space between the electronic component and the substrate structure. At the same time, the guide block can be used to allow the packaging colloid of the base glue material to diffuse by capillary action and flow along the guide block to avoid the base glue material from forming an air chamber, thereby improving the product yield.

[0089] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the inventive concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A substrate structure, comprising: A substrate body having a circuit layer, which defines at least one die-stack region; as well as The insulating protection layer is formed on the substrate body and has an opening corresponding to the crystal area to expose the circuit layer. The insulating protection layer has a plurality of extensions protruding toward the opening and spaced apart at the edge of the opening.

2. The substrate structure according to claim 1, wherein: The length of each of the extension segments is 1200 to 1800 microns, and the distance between each of the extension portions is 70 to 130 microns.

3. The substrate structure according to claim 1, wherein: The circuit layer has a plurality of conductive traces and a plurality of electrical contact pads connected to the conductive traces, so that the plurality of electrical contact pads are exposed from the single opening.

4. The substrate structure according to claim 1, wherein: A plurality of guide blocks arranged at intervals are formed in the opening to form a plurality of channels.

5. The substrate structure according to claim 1, wherein: The insulating protection layer forms at least one concave portion at the periphery of the crystal placement area.

6. The substrate structure according to claim 5, wherein: The recess is communicated with the opening.

7. An electronic package, comprising: The substrate structure according to claim 1; An electronic component is disposed on the die-laying region and electrically connected to the circuit layer; as well as The bottom glue material is formed between the substrate structure and the electronic element and fills the opening.

8. The electronic package of claim 7, wherein: The length of each of the extension segments is 1200 to 1800 microns, and the distance between each of the extension portions is 70 to 130 microns.

9. The electronic package of claim 7, wherein: The circuit layer has a plurality of conductive traces and a plurality of electrical contact pads connected to the conductive traces, so that the plurality of electrical contact pads are exposed from the single opening.

10. The electronic package of claim 9, wherein: The electronic component is combined and electrically connected to the plurality of electrical contact pads through a plurality of conductive bumps.

11. The electronic package of claim 7, wherein: A plurality of guide blocks arranged at intervals are formed in the opening to form a plurality of channels.

12. The electronic package of claim 11, wherein: The opening direction of the channel is the same as the mold flow direction of the base glue material.

13. The electronic package of claim 7, wherein: The insulating protection layer forms at least one concave portion at the periphery of the crystal placement area.

14. The electronic package of claim 13, wherein: The recess is communicated with the opening.

15. The electronic package of claim 7, wherein: The electronic element is combined and electrically connected to the circuit layer through a plurality of conductive bumps.

16. The electronic package of claim 15, wherein: The bottom glue material covers the plurality of conductive bumps.

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