Amplification circuit

Abstract

The amplifier circuit includes a radio frequency input, a radio frequency output, a first amplifier stage circuit, a second amplifier stage circuit, and a variable impedance path. The radio frequency input end is used for receiving a radio frequency signal. The radio frequency output end is used for outputting the amplified radio frequency signal. The first amplifier stage circuit is coupled to the radio frequency input terminal and the radio frequency output terminal. The second amplification stage circuit is coupled to the radio frequency input end and the radio frequency output end. The variable impedance path is coupled to the first amplifier stage circuit and the second amplifier stage circuit. When the second amplification stage circuit is enabled, the variable impedance path has low impedance. When the second amplification stage circuit is disabled, the variable impedance path has a high impedance.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit capable of reducing the voltage difference of transistors in an amplifier stage circuit to improve signal receiving and transmitting performance. Background Art

[0002] As the application of wireless communication increases, radio frequency circuits are also widely used in various electronic devices to send and receive wireless signals. In current radio frequency circuits, when two amplifier stage circuits, such as two-stage low noise amplifiers (LNAs), are used to send, receive and amplify signals, the voltages of the transistors of the two amplifier stages (such as drain-source voltages) may have a voltage difference in the high current mode of the two amplifier stage circuits. For example, this voltage difference may be as high as 50 millivolts. According to actual measurements, since this voltage difference is not easy to reduce, it will cause the operation timing of the two amplifier stage circuits to be different, thereby causing unexpected dynamic error vector magnitude (DEVM) problems, which will reduce the linearity of the circuit and make the performance of signal reception and transmission poor. The art still lacks a suitable solution to deal with this problem. Summary of the invention

[0003] An embodiment may provide an amplifier circuit, including a radio frequency input terminal, a radio frequency output terminal, a first amplifier stage circuit, a second amplifier stage circuit, and a variable impedance path. The radio frequency input terminal may be used to receive a radio frequency signal. The radio frequency output terminal may be used to output the amplified radio frequency signal. The first amplifier stage circuit may include a first terminal, a second terminal, and a third terminal, wherein the first terminal may be coupled to the radio frequency input terminal, and the second terminal may be coupled to the radio frequency output terminal. The second amplifier stage circuit may include a first terminal, a second terminal, a third terminal, and an internal node coupled to the third terminal, wherein the first terminal may be coupled to the radio frequency input terminal, and the second terminal may be coupled to the radio frequency output terminal. The variable impedance path may include a first terminal and a second terminal, wherein the first terminal may be coupled to the third terminal of the first amplifier stage circuit, and the second terminal may be coupled to the third terminal of the second amplifier stage circuit. When the second amplifier stage circuit is enabled, the variable impedance path has a low impedance. When the second amplifier stage circuit is disabled, the variable impedance path has a high impedance, and the internal node is a high impedance node.

[0004] Another embodiment provides an amplifier circuit, including a radio frequency input terminal, a radio frequency output terminal, a first amplifier stage circuit, a second amplifier stage circuit, and a switch. The radio frequency input terminal can be used to receive a radio frequency signal. The radio frequency output terminal can be used to output the amplified radio frequency signal. The first amplifier stage circuit can include a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled in series, a first end of the first transistor is coupled to the radio frequency output terminal, and a control end of the second transistor is coupled to the radio frequency input terminal. The second amplifier stage circuit includes a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are coupled in series, a first end of the third transistor is coupled to the radio frequency output terminal, a control end of the fourth transistor is coupled to the radio frequency input terminal, and the first amplifier stage circuit and the second amplifier stage circuit are coupled in parallel. The switch includes a first end and a second end, the first end can be coupled to a node between the first transistor and the second transistor, and the second end can be coupled to a node between the third transistor and the fourth transistor. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 FIG. 4 is a schematic diagram of an amplifier circuit in an embodiment. Figure 2 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Figure 3 FIG. 5 is a schematic diagram of an amplifier circuit coupled to a load circuit in another embodiment. Figure 4 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Figure 5 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Figure 6 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Figure 7 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Figure 8 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Fig. 9 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Fig.10 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment.

Explanation of symbols

[0005] Each transistor described herein may have a first terminal, a second terminal, and a control terminal. When two transistors are coupled in series, it means that the second terminal of one transistor may be coupled to the first terminal of the other transistor. When two voltages are equal, it means that the difference between the two voltages is less than a predetermined range, for example, the difference between the two voltages is less than 10% of either voltage.

[0006] Figure 1 is a schematic diagram of an amplifier circuit 100 in an embodiment. The amplifier circuit 100 may include an RF input terminal RFIN, an RF output terminal RFOUT, a first amplifier stage circuit 110, a second amplifier stage circuit 120, and a variable impedance path 130. The RF input terminal RFIN may be used to receive an RF signal S1. The RF output terminal RFOUT may be used to output the amplified RF signal S1, that is, the RF signal S2. The RF signal S1 and the RF signal S2 may be alternating current (AC) signals carrying data for wireless communication.

[0007] The first amplifier stage circuit 110 may include a first terminal, a second terminal, and a third terminal, wherein the first terminal may be coupled to the RF input terminal RFIN, and the second terminal may be coupled to the RF output terminal RFOUT.

[0008] The second amplifier stage circuit 120 may include a first terminal, a second terminal, a third terminal and an internal node, wherein the first terminal may be coupled to the RF input terminal RFIN, and the second terminal may be coupled to the RF output terminal RFOUT.

[0009] The variable impedance path 130 may include a first end and a second end, wherein the first end may be coupled to the third end of the first amplifier stage circuit 110, and the second end may be coupled to the third end of the second amplifier stage circuit 120. The internal node (e.g. Figure 1 An internal node NH) of the second amplifier stage circuit 130 may be coupled to the third terminal, and the variable impedance path 130 may be coupled to the internal node.

[0010] When the second amplifier stage circuit 120 is enabled, the variable impedance path 130 may have low impedance and the internal node NH is not a high impedance node. When the second amplifier stage circuit 120 is disabled, the variable impedance path 130 may have high impedance and the internal node NH is a high impedance node. Figure 1 The reference voltage Vr1 in the circuit may be a power supply voltage or a predetermined high reference voltage. In the present embodiment, when the second amplifier stage circuit 120 is disabled, the voltage of the internal node NH is floating, and the variable impedance path 130 has a high impedance, such as a DC high impedance, so the internal node NH will remain a high impedance node. When the second amplifier stage circuit 120 is enabled, the voltage of the internal node NH will change from floating to non-floating, so the internal node NH is not a high impedance node. However, when the second amplifier stage circuit 120 is enabled, the voltage of its internal node NH is mainly determined by the internal circuit architecture or related parameters of the second amplifier stage circuit 120, and may be different from the expected voltage (such as the third terminal voltage inside the first amplifier stage circuit 110), which will make the operation timings of the two amplifier stages different from each other, thereby affecting the dynamic error vector magnitude (DEVM) of the amplifier circuit 100. Therefore, in this embodiment, the variable impedance path 130 can be further made to have a low impedance, so that the voltage of the internal node NH is close to or equal to the voltage of the third terminal of the first amplifier stage circuit 110, so that the operation timings of the two amplifier stages can be close to or equal to each other, thereby reducing the unexpected dynamic error vector amplitude, improving the linearity of the circuit, and improving the efficiency of signal transmission and reception. In addition, since the variable impedance path 130 has a low impedance, such as a DC low impedance, the DC voltage of the internal node NH will be further defined by the third terminal of the first amplifier stage circuit 110 through the variable impedance path 130. In addition, when the first amplifier stage circuit 110 is enabled and the second amplifier stage circuit 120 is disabled, the RF signal S1 is amplified by the first amplifier stage circuit 110 to the RF signal S2, and the amplifier circuit 100 can be in a low current mode. When the first amplifier stage circuit 110 is enabled and the second amplifier stage circuit 120 is enabled, the RF signal S1 is amplified by the first amplifier stage circuit 110 and the second amplifier stage circuit 120 to be amplified into a RF signal S2 , and the amplifier circuit 100 is in a high current mode.

[0011] Figure 2 FIG. 2 is a schematic diagram of an amplifier circuit 200 in an embodiment. Figure 1 , Figure 2 The second amplifier stage circuit 120 may further include a transistor 210. The variable impedance path 130 may further include a transistor 220 coupled to a first terminal, such as a drain, of the transistor 210. The first amplifier stage circuit 110 may further include a transistor 230. The transistor 220 of the variable impedance path 130 may be coupled to a first terminal, such as a drain, of the transistor 230. Figure 2 In the embodiment, when the second amplifier stage circuit 120 is disabled, the transistors 210 and 220 are turned off, and the internal node NH is a high impedance node, and when the second amplifier stage circuit 120 is enabled, the transistors 210 and 220 are turned on, and the internal node NH is not a high impedance node. In the present embodiment, when the second amplifier stage circuit 120 is disabled, the transistors 210 and 220 are turned off, the voltage of the internal node NH is floating, and the variable impedance path 130 has a high impedance, such as a DC high impedance, so the internal node NH will remain a high impedance node. When the second amplifier stage circuit 120 is enabled, the transistors 210 and 220 are turned on, and the voltage of the internal node NH will change from floating to non-floating, so the internal node NH is not a high impedance node; in addition, since the transistor 220 is turned on, the variable impedance path 130 has a low impedance, such as a DC low impedance, so the DC voltage of the internal node NH will be further defined by the first end of the transistor 230 through the variable impedance path 130. In addition, when the first amplifier stage circuit 110 is enabled and the second amplifier stage circuit 120 is disabled, the RF signal S1 is amplified by the first amplifier stage circuit 110 to the RF signal S2, and the amplifier circuit 200 can be in a low current mode. When the first amplifier stage circuit 110 is enabled and the second amplifier stage circuit 120 is enabled, the RF signal S1 is amplified by the first amplifier stage circuit 110 and the second amplifier stage circuit 120 to the RF signal S2, and the amplifier circuit 200 is in a high current mode.

[0012] Figure 3 FIG. 3 is a schematic diagram of another embodiment in which the amplifier circuit 300 is coupled to the load circuit 355. Figure 1 , Figure 3 The second amplifier stage circuit 120 may further include a transistor 210 and a transistor 240, and the transistor 210 and the transistor 240 may be coupled in series. When the transistor 210 and the transistor 240 are turned on, the second amplifier stage circuit 120 is enabled. When the transistor 210 and the transistor 240 are turned off, the second amplifier stage circuit 120 is disabled. For example, the control signal SC1 and the control signal SC4 may be used to turn on and off the transistor 210 and the transistor 240, wherein the control signal SC1 and the control signal SC4 may be direct current (DC) signals, and the control signal SC1 and the control signal SC4 may selectively have the same signal level.

[0013] like Figure 3 As shown, the first amplifier stage circuit 110 may further include a transistor 230 and a transistor 250. The transistor 230 and the transistor 250 may be coupled in series. When the transistor 230 and the transistor 250 are turned on, the first amplifier stage circuit 110 is enabled. When the transistor 230 and the transistor 250 are turned off, the first amplifier stage circuit 110 is disabled. For example, the control signal SC3 and the control signal SC5 may be used to turn on and off the transistor 230 and the transistor 250, wherein the control signal SC3 and the control signal SC5 may be DC signals, and the control signal SC3 and the control signal SC5 may selectively have the same signal level.

[0014] Since the control signals SC1, SC3, SC4 and SC5 can be DC bias signals, and the RF signals S1 and S2 can be AC ​​signals, the control signals SC1, SC3, SC4 and SC5 can be used to control the opening and closing of the transistors 210, 230, 240 and 250, respectively. According to the embodiment, the capacitor C1 and / or the capacitor C2 can be selectively set. The capacitor C1 and the capacitor C2 can block the DC signal, thereby controlling the opening and closing of the transistors, respectively. In the present embodiment, the control end of the transistor 240 or 250 can be coupled to the reference voltage through a capacitor (not shown in the figure) to provide a common AC ground (AC ground) path for the control end of the transistor 240 and the control end of the transistor 250. In another embodiment, the electrical connection between the control end of the transistor 240 and the control end of the transistor 250 can also be disconnected, and the AC ground paths of the control end of the transistor 240 and the control end of the transistor 250 are provided, respectively, so as to omit the configuration of the capacitor C2.

[0015] like Figure 3 As shown, the RF input terminal RFIN can be coupled to the control terminal of the transistor 230 , and the RF input terminal RFIN can be coupled to the control terminal of the transistor 230 .

[0016] The RF output terminal RFOUT may be coupled to the load circuit 355. When the load circuit 355 has a first load, the second amplifier stage circuit 120 may be enabled. When the load circuit 355 has a second load, the second amplifier stage circuit 120 may be disabled. The first load may be different from the second load, for example, the first load may be greater than the second load. In other words, the second amplifier stage circuit 120 may be enabled or disabled corresponding to different loads. Figure 3In the embodiment, the size of transistor 240 may be different from the size of transistor 250 to provide corresponding impedance for different loads. In addition, when the first amplifier stage circuit 110 is enabled and the second amplifier stage circuit 120 is disabled, the RF signal S1 is amplified by the first amplifier stage circuit 110 to the RF signal S2, and the amplifier circuit 300 may be in low current mode. When the first amplifier stage circuit 110 is enabled and the second amplifier stage circuit 120 is enabled, the RF signal S1 is amplified by the first amplifier stage circuit 110 and the second amplifier stage circuit 120 to the RF signal S2, and the amplifier circuit 300 is in high current mode. When the RF output terminal RFOUT is coupled to different loads, it can be switched to low current mode or high current mode to correspond to different loads. For example, when the RF output terminal RFOUT is coupled to the first load, the amplifier circuit 300 can be switched to one of the low current mode or the high current mode; and when the RF output terminal RFOUT is coupled to the second load, the amplifier circuit 300 can be switched to the other of the low current mode or the high current mode.

[0017] like Figure 3 As shown, the variable impedance path 130 may include a transistor 220, and the transistor 220 may include a first end, a second end and a control end, wherein the first end may be coupled to a node N1 between the transistor 230 and the transistor 250, the second end may be coupled to an internal node NH between the transistor 210 and the transistor 240, and the control end may receive a control signal SC2 to turn on or off the transistor 220.

[0018] When the amplifier circuit 300 is in low current mode, the second amplifier stage circuit 120 is disabled and the internal node NH can be a high impedance node. Since the transistors 210, 220 and 230 can be turned off at this time, the voltage of the internal node NH is floating, so the impedance from the internal node NH to the transistors 210, 220 and 230 is high impedance.

[0019] When the amplifier circuit 300 is in high current mode, the second amplifier stage circuit 120 is enabled, and the voltage of the internal node NH changes from floating to non-floating, so the internal node NH is not a high impedance node. However, in the high current mode, the voltage of the internal node NH is mainly determined by the internal circuit structure or related parameters of the second amplifier stage circuit 120, so the voltage of the internal node NH may be different from the expected value. For example, the voltage of the node N1 and the internal node NH may be different because the operating currents flowing through the two amplifier stage circuits are different, the voltage difference between the first end and the second end of the transistors 210 and 230 is different (that is, VDS1≠VDS3), or the voltage difference between the first end and the second end of the transistors 240 and 250 is different. This will make the operation timings of the two amplifier stage circuits different from each other, thereby affecting the dynamic error vector amplitude of the amplifier circuit 300. Therefore, in this embodiment, the transistor 220 can be further turned on to make the variable impedance path 130 have a low impedance, so that the voltage of the node N1 (that is, the voltage of the first end of the transistor 230) is close to or equal to the voltage of the internal node NH (that is, the voltage of the first end of the transistor 210), so that the operation timings of the two amplifier stages can be close to or equal to each other, thereby reducing the unexpected dynamic error vector amplitude, improving the linearity of the circuit, and improving the efficiency of signal transmission and reception. In addition, in the high current mode, the RF signal S1 will not only be amplified by the first amplifier stage circuit 110 and the second amplifier stage circuit 120 respectively, but part of the RF signal amplified by the transistor 230 of the first amplifier stage circuit 110 will also be transmitted to the internal node NH of the second amplifier stage circuit 120 through the variable impedance path 130, and become a part of the RF signal S2, so as to further improve the efficiency of signal transmission and reception.

[0020] When the second amplifier stage circuit 120 is enabled by the control signals SC1 and SC4, the transistor 220 can be turned on by the control signal SC2. When the second amplifier stage circuit 120 is disabled by the control signals SC1 and SC4, the transistor 220 can be turned off by the control signal SC2. Figure 3 As shown, the control terminal of the transistor 220 can receive a control signal SC2 , and the control signal SC2 can be used to control the on and off of the transistor 220 .

[0021] If the transistor is a field effect transistor, the first end, the second end and the control end may be a drain, a source and a gate respectively. If the transistor is a bipolar junction transistor, the first end, the second end and the control end may be a collector, an emitter and a base respectively. Figure 4 FIG. 4 is a schematic diagram of an amplifier circuit 400 in another embodiment. Figure 3 , Figure 4The second amplifier stage circuit 120 may further include a transistor 260. The transistor 260 and the transistor 240 may be coupled in series. The transistor 240 may be coupled between the transistor 210 and the transistor 260. When the second amplifier stage circuit 120 is enabled, the transistor 260 may be turned on. When the second amplifier stage circuit 120 is disabled, the transistor 260 may be turned off. The control end of the transistor 260 may receive a control signal SC6 to control the on and off of the transistor 260. The setting of the control transistor 260 may further ensure the enable / disable state of the second amplifier stage circuit 120. In addition, when the first amplifier stage circuit 110 is enabled by the control signals SC3 and SC5, and the second amplifier stage circuit 120 is disabled by the control signals SC1, SC4, and SC6, the amplifier circuit 400 may be in a low current mode. When the first amplifier stage circuit 110 is enabled by the control signals SC3 and SC5 , and the second amplifier stage circuit 120 is enabled by the control signals SC1 , SC4 , and SC6 , the amplifier circuit 400 is in the high current mode.

[0022] Figure 5 FIG. 5 is a schematic diagram of an amplifier circuit 500 in another embodiment. Figure 3 , Figure 5 The second amplifier stage circuit 120 may further include a transistor 270. The transistor 270 and the transistor 210 may be coupled in series, and the transistor 210 may be coupled between the transistor 240 and the transistor 270. When the second amplifier stage circuit 120 is enabled, the transistor 270 may be turned on. When the second amplifier stage circuit 120 is disabled, the transistor 270 may be turned off. The control end of the transistor 270 may receive a control signal SC7 to control the on and off of the transistor 270. The setting of the control transistor 270 may further ensure the enable / disable state of the second amplifier stage circuit 120. In addition, when the first amplifier stage circuit 110 is enabled by the control signals SC3 and SC5, and the second amplifier stage circuit 120 is disabled by the control signals SC1, SC4, and SC7, the amplifier circuit 500 may be in a low current mode. When the first amplifier stage circuit 110 is enabled by the control signals SC3 and SC5 , and the second amplifier stage circuit 120 is enabled by the control signals SC1 , SC4 , and SC7 , the amplifier circuit 500 is in the high current mode.

[0023] Figure 6 FIG. 6 is a schematic diagram of an amplifier circuit 600 in another embodiment. Figure 3 , Figure 6The second amplifier stage circuit 120 may further include a transistor 260 and a transistor 270. The transistor 260 and the transistor 240 may be coupled in series, the transistor 270 and the transistor 210 may be coupled in series, and the transistor 210 and the transistor 240 may be coupled between the transistor 260 and the transistor 270. When the second amplifier stage circuit 120 is enabled, the transistor 260 and the transistor 270 may be turned on. When the second amplifier stage circuit 120 is disabled, the transistor 260 and the transistor 270 may be turned off. Similar to Figure 4 and Figure 5 , the control signal SC6 can be used to control the on and off of the transistor 260, and the control signal SC7 can be used to control the on and off of the transistor 270. The setting of the control transistors 260 and 270 can further ensure the enable / disable state of the second amplifier stage circuit 120. In addition, when the first amplifier stage circuit 110 is enabled by the control signals SC3 and SC5, and the second amplifier stage circuit 120 is disabled by the control signals SC1, SC4, SC6, and SC7, the amplifier circuit 600 can be in a low current mode. When the first amplifier stage circuit 110 is enabled by the control signals SC3 and SC5, and the second amplifier stage circuit 120 is enabled by the control signals SC1, SC4, SC6, and SC7, the amplifier circuit 600 is in a high current mode. In another embodiment, in order to make the operation timing of the first amplifier stage circuit 110 and the second amplifier stage circuit 120 closer, when the amplifier circuit 600 is in the low current mode, the transistors 230, 250 of the first amplifier stage circuit 110 and the transistors 210, 240 of the second amplifier stage circuit 120 are still controlled by the control signals SC3, SC5, SC1, SC4 to be turned on, but the transistors 260, 270 of the second amplifier stage circuit 120 are controlled by the control signals SC6, SC7 to be turned off, so that the second amplifier stage circuit 120 can still be disabled and the unexpected dynamic error vector amplitude can be further reduced.

[0024] Figure 7 FIG. 7 is a schematic diagram of an amplifier circuit 700 in another embodiment. Figure 6 , Figure 7The amplifier circuit 700 may further include a transistor 280. The first amplifier stage circuit 110 may further include a fourth terminal, such as terminal N14. The second amplifier stage circuit 120 may further include a fourth terminal, such as terminal N24. The transistor 280 may include a first terminal, a second terminal and a control terminal, wherein the first terminal may be coupled to the fourth terminal of the first amplifier stage circuit 110 and the fourth terminal of the second amplifier stage circuit 120, and the second terminal may be used to receive a reference voltage Vr2. The reference voltage Vr2 may be a ground voltage or a predetermined low reference voltage. When the second amplifier stage circuit 120 is enabled, the transistor 280 may be turned on. When the second amplifier stage circuit 120 is disabled, the transistor 280 may be turned off. The control terminal of the transistor 280 may receive a control signal SC8 to control the turning on and off of the transistor 280. Figure 7 As shown, the amplifier circuit 700 can be selectively provided with inductors L11 and L12 for signal tuning and impedance matching. The transistor 280 is connected in parallel with the inductor L12, the first end of the transistor 280 is coupled to the first end of the inductor L12, and the second end of the transistor 280 is coupled to the second end of the inductor L12. For example, when the amplifier circuit 700 is in high current mode and the second amplifier stage circuit 120 is enabled, the transistor 280 is turned on or off. When the amplifier circuit 700 is in low current mode and the second amplifier stage circuit 120 is disabled, the transistor 280 is turned on or off. This will enable the amplifier circuit 700 to have better impedance matching.

[0025] The control signals SC1, SC2, SC3, SC4, SC5, SC7 and SC8 mentioned above may be DC bias signals, so the control signals SC1, SC2, SC3, SC4, SC5, SC7 and SC8 may be used to control the turning on and off of the transistors 210, 220, 230, 240, 250, 260, 270 and 280, respectively. The control signals SC3 and SC5 may selectively have the same signal level; the control signals SC1, SC4, SC6 and SC7 may selectively have the same signal level. In another embodiment, the control signals SC1, SC3, SC4 and SC5 may selectively have the same signal level; the control signals SC6 and SC7 may selectively have the same signal level.

[0026] Figure 8 8 is a schematic diagram of an amplifier circuit 800 in another embodiment. The amplifier circuit 800 may include a radio frequency input terminal RFIN, a radio frequency output terminal RFOUT, a first amplifier stage circuit 81, a second amplifier stage circuit 82, and a switch 83. The radio frequency input terminal RFIN may be used to receive a radio frequency signal S1. The radio frequency output terminal RFOUT may be used to output the amplified radio frequency signal S1, that is, the radio frequency signal S2.

[0027] The first amplifier circuit 81 may include a transistor 810 and a transistor 820, wherein the transistor 810 and the transistor 820 may be coupled in series. A first terminal of the transistor 810 may be coupled to the RF output terminal RFOUT, and a control terminal of the transistor 820 may be coupled to the RF input terminal RFIN.

[0028] The second amplifier stage circuit 82 may include a transistor 830 and a transistor 840, wherein the transistor 830 and the transistor 840 may be coupled in series. The first end of the transistor 830 may be coupled to the RF output terminal RFOUT, the control end of the transistor 840 may be coupled to the RF input terminal RFIN, and the first amplifier stage circuit 81 and the second amplifier stage circuit 82 may be coupled in parallel. That is, the terminal N811 of the first amplifier stage circuit 81 may be coupled to the terminal N821 of the second amplifier stage circuit 82, and the terminal N812 of the first amplifier stage circuit 81 may be coupled to the terminal N822 of the second amplifier stage circuit 82. The switch 83 may include a first end and a second end, wherein the first end may be coupled to a node N813 between the transistor 810 and the transistor 820, and the second end may be coupled to a node N823 between the transistor 830 and the transistor 840. The operating principles and functions of the first amplifier stage circuit 81, the second amplifier stage circuit 82, the switch 83, and the transistors 810, 820, 830, and 840 may refer to Figure 3 The first amplifier stage circuit 110, the second amplifier stage circuit 120, and the transistors 220, 250, 230, 240, and 210 are not described in detail herein.

[0029] Fig. 9 2 is a schematic diagram of an amplifier circuit 900 in another embodiment. The amplifier circuit 900 may be similar to the amplifier circuit 800, but the amplifier circuit 900 may further include a switching circuit 92. The switching circuit 92 may include a transistor 850, wherein the transistor 850 and the second amplifier circuit 82 may be coupled in series.

[0030] like Fig. 9 As shown, the switch 83 may also include a control terminal coupled to the switching circuit 92. When the transistor 850 of the switching circuit 92 is turned on, the switch 83, the transistor 830 and the transistor 840 may be turned on. At this time, the voltages of the node N813 and the node N823 may be equal, so the linearity of the circuit can be improved and the efficiency of signal reception and transmission can be improved. When the second amplifier stage circuit 82 is disabled, the node N823 may be a high impedance node. The operating principles and functions of the first amplifier stage circuit 81, the second amplifier stage circuit 82, the switch 83, the transistors 810, 820, 830, 840, 850 can be referred to Figure 4 The first amplifier stage circuit 110, the second amplifier stage circuit 120, and the transistors 220, 250, 230, 240, 210, and 260 are not described in detail herein.

[0031] Fig.10 FIG. 1 is a schematic diagram of an amplifier circuit 1000 in another embodiment. Compared with the amplifier circuit 900, the switching circuit 92 of the amplifier circuit 1000 may further include a transistor 860. The transistor 860 and the second amplifier circuit 82 may be coupled in series, and the transistor 830 and the transistor 840 may be coupled between the transistor 850 and the transistor 860. Fig. 9 and Fig.10 For example, according to an embodiment, the switching circuit 92 may also include the transistor 860 instead of the transistor 850 . Fig. 9 and Fig.10 When the second amplifier stage circuit 82 is disabled, the switching circuit 92 may be disabled. The operation principles and functions of the first amplifier stage circuit 81, the second amplifier stage circuit 82, the switch 83, and the transistors 810, 820, 830, 840, 850, and 860 may refer to Figure 6 The first amplifier stage circuit 110, the second amplifier stage circuit 120, and the transistors 220, 250, 230, 240, 210, 260, and 270 are not described in detail herein.

[0032] Figure 8 , Fig. 9 and Fig.10 In the embodiment, when transistor 810 and transistor 820 are turned on, and transistor 830 and transistor 840 are turned off, amplifier circuit 800, amplifier circuit 900 and amplifier circuit 1000 can be in low current mode. When transistor 810, transistor 820, transistor 830 and transistor 840 are turned on, amplifier circuit 800, amplifier circuit 900 and amplifier circuit 1000 are in high current mode. When the RF output terminal RFOUT is coupled to different loads, it can be switched to low current mode or high current mode to correspond to different loads. For example, when the RF output terminal RFOUT is coupled to a lower load, it can be switched to low current mode; and when the RF output terminal RFOUT is coupled to a higher load, it can be switched to high current mode. Figures 8 to 10 In the embodiment, the control terminal of each transistor of transistors 810, 820, 830, 840, 850 and 860 can receive a DC bias signal to control the turning on and off of the transistor respectively.

[0033] In summary, by using the amplifier circuits 100, 200, 300, 400, 500, 600, 700, 800, 900 and / or 1000, the voltage difference between the node voltages of the two amplifier stage circuits can be reduced, so that the operation timings of the two amplifier stages can be equal to each other, thereby reducing the impact of unexpected dynamic error vector magnitude (DEVM) and history effect, improving the linearity of the circuit, and effectively improving the performance of signal reception and transmission.

[0034] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the present invention.

Claims

1. An amplifier circuit, characterized in that: include: A radio frequency input terminal, used for receiving a radio frequency signal; A radio frequency output terminal, used to output the amplified radio frequency signal; A first amplifier circuit includes a first terminal coupled to the RF input terminal, a second terminal coupled to the RF output terminal, and a third terminal; a second amplifier circuit, comprising a first terminal coupled to the RF input terminal, a second terminal coupled to the RF output terminal, a third terminal, and an internal node coupled to the third terminal; and a variable impedance path, comprising a first end coupled to the third end of the first amplifier stage circuit, and a second end coupled to the third end of the second amplifier stage circuit; in: When the second amplifier stage circuit is enabled, the variable impedance path has a low impedance; When the second amplifier stage circuit is disabled, the variable impedance path has a high impedance, and the internal node is a high impedance node.

2. The amplifier circuit according to claim 1, characterized in that: in: The second amplifier stage circuit also includes a first transistor; and The variable impedance path also includes a second transistor coupled to a first terminal of the first transistor.

3. The amplifier circuit according to claim 2, characterized in that: in: The first amplifier stage circuit includes a third transistor; and The second transistor of the variable impedance path is coupled to a first terminal of the third transistor.

4. The amplifier circuit according to claim 1, characterized in that: in: The second amplifier stage circuit also includes a first transistor and a fourth transistor; The first transistor and the fourth transistor are coupled in series; When the second amplifier stage circuit is enabled, the first transistor and the fourth transistor are turned on; and When the second amplifier stage circuit is disabled, the first transistor and the fourth transistor are turned off.

5. The amplifier circuit according to claim 4, characterized in that: in: The first amplifier stage circuit also includes a third transistor and a fifth transistor; The third transistor and the fifth transistor are coupled in series; When the first amplifier stage circuit is enabled, the third transistor and the fifth transistor are turned on.

6. The amplifier circuit according to claim 5, characterized in that: The RF input terminal is coupled to a control terminal of the first transistor, and the RF input terminal is coupled to a control terminal of the third transistor.

7. The amplifier circuit according to claim 5, characterized in that: in: When the RF output terminal is coupled to a first load, the second amplifier stage circuit is enabled; When the RF output terminal is coupled to a second load, the second amplifier stage circuit is disabled; and The first load is different from the second load.

8. The amplifier circuit according to claim 5, characterized in that: The size of the fourth transistor is different from the size of the fifth transistor.

9. The amplifier circuit according to claim 5, characterized in that: in: The variable impedance path also includes a second transistor; and The second transistor includes a first terminal coupled to a node between the third transistor and the fifth transistor, and a second terminal coupled to a node between the first transistor and the fourth transistor.

10. The amplifier circuit according to claim 4, characterized in that: in: The variable impedance path also includes a second transistor; When the second amplifier stage circuit is enabled, the second transistor is turned on; and When the second amplifier stage circuit is disabled, the second transistor is turned off.

11. The amplifier circuit according to claim 4, characterized in that: in: The second amplifier stage circuit also includes a sixth transistor; The sixth transistor and the fourth transistor are coupled in series; The fourth transistor is coupled between the first transistor and the sixth transistor; When the second amplifier stage circuit is enabled, the sixth transistor is turned on; and When the second amplifier stage circuit is disabled, the sixth transistor is turned off.

12. The amplifier circuit according to claim 4, characterized in that: in: The second amplifier stage circuit also includes a seventh transistor; The seventh transistor and the first transistor are coupled in series; The first transistor is coupled between the fourth transistor and the seventh transistor; When the second amplifier stage circuit is enabled, the seventh transistor is turned on; and When the second amplifier stage circuit is disabled, the seventh transistor is turned off.

13. The amplifier circuit according to claim 4, characterized in that: in: The second amplifier stage circuit also includes a sixth transistor and a seventh transistor; The sixth transistor and the fourth transistor are coupled in series; The seventh transistor and the first transistor are coupled in series; The first transistor and the fourth transistor are coupled between the sixth transistor and the seventh transistor; When the second amplifier stage circuit is enabled, the sixth transistor and the seventh transistor are turned on; and When the second amplifier stage circuit is disabled, the sixth transistor and the seventh transistor are turned off.

14. The amplifier circuit according to claim 1, characterized in that: Also included is an eighth transistor connected in parallel with an inductor, wherein: The first amplifier stage circuit also includes a fourth terminal; The second amplifier stage circuit also includes a fourth terminal; The eighth transistor includes a first terminal coupled to the fourth terminal of the first amplifier stage circuit and the fourth terminal of the second amplifier stage circuit, and a second terminal for receiving a predetermined voltage; When the second amplifier stage circuit is enabled, the eighth transistor is either turned on or turned off; and When the second amplifier stage circuit is disabled, the eighth transistor is turned on or off.

15. An amplifier circuit, characterized in that: include: A radio frequency input terminal, used for receiving a radio frequency signal; A radio frequency output terminal, used to output the amplified radio frequency signal; A first amplifier circuit comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled in series, a first terminal of the first transistor is coupled to the RF output terminal, and a control terminal of the second transistor is coupled to the RF input terminal; a second amplifier stage circuit, comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are coupled in series, a first terminal of the third transistor is coupled to the RF output terminal, a control terminal of the fourth transistor is coupled to the RF input terminal, and the first amplifier stage circuit and the second amplifier stage circuit are coupled in parallel; and A switch includes a first end coupled to a node between the first transistor and the second transistor, and a second end coupled to a node between the third transistor and the fourth transistor.

16. The amplifier circuit according to claim 15, characterized in that: Also includes: A switching circuit includes a fifth transistor, wherein the fifth transistor and the second amplifier stage circuit are coupled in series.

17. The amplifier circuit according to claim 16, characterized in that: The switch further includes a control terminal coupled to the switching circuit.

18. The amplifier circuit according to claim 17, characterized in that: When the switching circuit is turned on, the switch, the third transistor and the fourth transistor are turned on.

19. The amplifier circuit according to claim 16, characterized in that: The switching circuit further includes a sixth transistor, wherein the sixth transistor and the second amplifier circuit are coupled in series, and the third transistor and the fourth transistor are coupled between the fifth transistor and the sixth transistor.

20. The amplifier circuit according to claim 15, characterized in that: in: When the first transistor and the second transistor are turned on, and the third transistor and the fourth transistor are turned off, the amplifier circuit is in a low current mode; and When the first transistor, the second transistor, the third transistor and the fourth transistor are turned on, the amplifier circuit is in a high current mode.

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