An Error Correction Method and System for FPGA

Abstract

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

Description

Technical Field

[0001] The present invention relates to the technical field of data encoding and decoding, and particularly to an error correction method and system for FPGA. Background Art

[0002] FPGA, namely Field Programmable Gate Array, is a common data processing core in communication systems. FPGA has the reconfigurable characteristic, can adjust and match various communication protocols, and also has high speed, so it is widely used in digital signal transmission. In a typical data transceiver architecture, FPGA docks with a wireless communication module through a high-speed serial interface to complete baseband signal processing, protocol encapsulation and physical layer data transmission. However, during actual operation, the transmission medium usually has non-ideal characteristics. Due to factors such as attenuation caused by the length effect of the transmission cable, impedance mismatch caused by environmental temperature changes, and environmental electromagnetic interference, signal waveform distortion will be caused, resulting in problems such as inter-symbol interference, clock jitter and noise superposition of the signal, and finally generating error codes. To ensure data reliability, traditional solutions adopt a retransmission mechanism and a check and retransmission strategy. For example, let the module send the same data once or multiple times, and the FPGA side can obtain the correct data through multiple receptions. A big problem with this is that the delay for the FPGA to obtain the correct data is large and the real-time performance is poor. Especially in application scenarios with poor channel conditions, the cumulative delay generated by multiple retransmissions will be more obvious.

[0003] Currently, the Chinese invention patent application with the application number CN201110071524.6 discloses an error code testing method based on FPGA. The application includes: performing serial-to-parallel conversion on the received test data to convert it into parallel data; synchronizing the converted parallel data with the symbol data generated locally; comparing the received parallel data with the symbol data generated locally, and statistically calculating the error rate. The error code testing method of this application utilizes the integration and flexibility of FPGA, improves the concept of traditional circuit, instrument and communication protocol design, and can be used as the main control chip of an error code testing instrument in production lines and R & D. However, this application does not consider sufficiently the working conditions with poor channel conditions and lacks the consideration of improving the real-time performance of error correction. Summary of the Invention

[0004] The technical problem solved by the present invention is that the error correction technology of traditional FPGA often needs to retransmit communication data, and in application scenarios with poor channel conditions, it is difficult to balance stability and real-time performance in dealing with error symbols in communication data.

[0005] To solve the above technical problem, the present invention provides the following technical solutions:

[0006] An error correction method for FPGA, including:

[0007] Step S1: Generate Galois field element α^n based on the received symbol vector and the primitive polynomial, and calculate the syndrome polynomial through 8-symbol parallel processing;

[0008] Step S2: Calculate the coefficients of the error-location polynomial based on the syndrome polynomial through the BM iterative algorithm;

[0009] Step S3: Calculate the error location SITE by substituting 10 Galois field elements in parallel based on the error-location polynomial through the Chien search method;

[0010] Step S4: Establish the evaluation polynomial and the error pattern calculation formula, and perform polynomial division in combination with the derivative of the error-location polynomial to obtain the error pattern e;

[0011] Step S5: Perform error code judgment based on the error location SITE and the error pattern e, and correct the error symbols through Galois field exclusive-or operation to obtain the updated symbol vector.

[0012] Preferably, in step S11, define the Galois field GF(2^8) based on the determined primitive polynomial p(x), and denote its primitive element as α;

[0013] Step S12: Obtain the generator polynomial g(x) based on the RS coding theory and the determined primitive polynomial p(x), and solve the roots of the generator polynomial g(x) to obtain the Galois field element α^n;

[0014] where n is the power of the root of the generator polynomial and is also the syndrome index;

[0015] Step S13: Perform pre-calculation based on the Galois field element α^n to obtain the syndrome polynomial weight α^(kn);

[0016] where k is the symbol position index;

[0017] Step S14: Segment the received symbol vector into symbol segments in groups of 8 symbols to obtain a set of symbol segments;

[0018] Perform 8-symbol parallel processing calculations on each group of symbol segments in the set of symbol segments respectively, perform Galois field multiplication and Galois field addition calculations on each group of symbol segments and the corresponding syndrome polynomial weight to obtain partial sum results, perform cumulative summation calculations on the partial sum results corresponding to each group of symbol segments to obtain the coefficients of the syndrome polynomial S, and obtain based on the coefficients of the syndrome polynomial S;

[0019] Its mathematical expression is:

[0020] S = [R(1),..., R(α^n),..., R(a^(2t - 1))];

[0021] p(x) = x^8 + x^4 + x^3 + x^2 + 1;

[0022] ;

[0023] Among them, p(x) represents the expansion of the selected primitive polynomial, g(x) represents the expansion of the generating polynomial, x represents the Galois field formal variable, that is, the power of the primitive element α, S represents the syndrome polynomial, R(α^n) represents the received code element vector corresponding to the syndrome index n, and t represents the maximum number of corrected code elements.

[0024] Preferably, in step S21, an error location polynomial Λ(x) is established, and the mathematical expression of Λ(x) is:

[0025] ;

[0026] Among them, Λ(x) represents the error location polynomial, and t represents the maximum number of corrected code elements;

[0027] In step S22, the error location polynomial Λ(x) is solved by the BM iterative algorithm. Two initial values are assigned to each iteration parameter based on a preset initial value set, and 2t iterative operations are performed on the assigned iteration parameters by the BM iterative algorithm to obtain the error location polynomial coefficients, and the error location polynomial Λ(x) is obtained based on the error location polynomial coefficients;

[0028] Among them, the iteration parameters include the error location polynomial coefficients, the auxiliary polynomial coefficients, the current polynomial degree, the current deviation value, and the previous deviation value, and t represents the maximum number of corrected code elements.

[0029] Preferably, in step S31, the roots of the error location polynomial are calculated in the Galois field GF(2^8) by an improved Chien search method. The processing logic of the improved Chien search method includes:

[0030] Every clock cycle, 10 Galois field elements α^n are simultaneously substituted into the error location polynomial Λ(x), and the error location polynomial value is calculated. If the error location polynomial value is 0, the Galois field element is marked as a candidate root. If the error location polynomial value is a non-zero value, the Galois field element is marked as a screened root;

[0031] The candidate roots are screened at three levels, and the candidate roots are screened by a cascaded 10-to-5 root value selector, a 5-to-3 root value selector, and a 3-to-2 root value selector to obtain the error location roots;

[0032] In step S32, if there are no error location roots, there are no error codes, and the error location SITE is an empty set;

[0033] If there is an error location root, take the reciprocal of the error location root, and obtain the error location SITE based on the reciprocal of the error location root and the Galois field inverse lookup table (LUT).

[0034] Preferably, in step S41, establish an evaluation polynomial, and calculate the error pattern e based on the syndrome polynomial S and the error location polynomial Λ;

[0035] Perform polynomial multiplication on the syndrome polynomial S and the error location polynomial Λ, and perform modulo calculation through x^(2t - 1) to truncate the high-order terms to obtain the evaluation polynomial;

[0036] In step S42, perform derivative calculation on the error location polynomial Λ, and obtain the derivative Λ`(x) of the error location polynomial that only retains the odd-order term coefficients based on the definition of the derivative in the Galois field;

[0037] Establish an error pattern calculation formula, perform polynomial division on the evaluation polynomial and the derivative Λ`(x) of the error location polynomial to obtain the error pattern polynomial e(x), and substitute the error location root into the error pattern polynomial e(x) to calculate the error pattern e corresponding to the error location SITE;

[0038] The mathematical expressions of the error pattern calculation formula and the evaluation polynomial are:

[0039] ;

[0040] e(x)= -(Ω(x) / Λ`(x));

[0041] where, Ω(x) represents the evaluation polynomial, e(x) represents the error pattern polynomial, mod represents the modulo operation, Λ`(x) represents the derivative of the error location polynomial, and x represents the Galois field formal variable.

[0042] Preferably, in step S51, perform error code judgment based on the error location SITE. When the error location SITE is an empty set, the error code judgment result is that there is no error code, and the received symbol vector is output after reaching the preset delay period;

[0043] When the error location SITE is not an empty set, the error code judgment result is that there is an error code. Extract the symbol at the error location SITE from the received symbol vector to obtain the error symbol, perform Galois field addition processing on the error symbol and the corresponding value in the error pattern e to obtain the error correction symbol, replace the error symbol with the corresponding error correction symbol to obtain the updated symbol vector, and output the updated symbol vector after reaching the preset delay period.

[0044] An error correction system for FPGA, comprising: an RS decoding timing adjustment module, an RS decoding syndrome polynomial operation module, an RS decoding iterative operation module, an RS decoding root finding operation module, an RS decoding error pattern operation module, and an RS decoding error correction operation module;

[0045] The RS decoding timing adjustment module is used to unify the timing of the received code elements;

[0046] The RS decoding syndrome polynomial operation module is used to calculate the coefficients of the syndrome polynomial S;

[0047] The RS decoding iterative operation module is used to perform iterative calculation of the BM algorithm to obtain the error location polynomial Λ(x);

[0048] The RS decoding root finding operation module is used to locate the error code element position to obtain the error location SITE;

[0049] The RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error location SITE;

[0050] The RS decoding error correction operation module is used to correct the error code elements in the received code element vector to obtain an updated code element vector.

[0051] Preferably, the RS decoding timing adjustment module is used to unify the timing of the received code elements, perform timing standardization processing on the packet form of the received code elements, eliminate the influence of the dynamic interval between the start symbol, data segment, and end symbol in the packet protocol, and output a received code element sequence with uniform intervals. The packet form is a packet protocol constructed by a packet start, packet data, and packet end, and each packet data consists of 198 code elements;

[0052] The RS decoding syndrome polynomial operation module is used to calculate the coefficients of the syndrome polynomial S, and complete the calculation of the received code element vector at the elements of the Galois field through an 8-code element parallel multiplier array and an exclusive OR accumulation tree to obtain the coefficients of the syndrome polynomial S.

[0053] Preferably, the RS decoding iterative operation module is used to perform iterative calculation of the BM algorithm to obtain the error location polynomial Λ(x), and split the BM algorithm into a non-feedback pipeline through the Galois field multipliers and latch registers in four-level independent iterative units, and update the coefficients of the error location polynomial step by step to obtain the error location polynomial Λ(x);

[0054] The RS decoding root finding operation module is used to locate the error code element position to obtain the error location SITE, implement the Chien search method for parallel substitution processing of 10 Galois field elements through a 10-element parallel test unit, screen the candidate roots through a cascaded 10-to-5 root value selector, 5-to-3 root value selector, and 3-to-2 root value selector to obtain the error location root, and determine the error location SITE based on the error location root.

[0055] Preferably, the RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error position SITE. The polynomial division of the evaluation polynomial and the derivative of the error position polynomial is realized through the polynomial division logic unit, and the error pattern e is calculated based on the error pattern polynomial e(x) and the Galois field inverse element lookup table (LUT).

[0056] The RS decoding error correction operation module is used to correct the error code elements in the received symbol vector to obtain an updated symbol vector. The error code elements are located through the address mapping unit and the error position SITE, and the Galois field exclusive OR calculation is completed through the exclusive OR arithmetic unit array to cover the error code elements to obtain the updated symbol vector.

[0057] The beneficial effects of the present invention: This application innovatively proposes a decoding algorithm, which identifies error code elements through a three-step process of "finding the syndrome polynomial", "finding the error position polynomial", and then "finding the error position". It can correct up to 2 error code elements in every 198 received code elements, and only a small amount of bandwidth is used to transmit supervision code elements to complete error code identification. Without retransmission, the FPGA automatically corrects the received error module data in real time, reducing the delay in obtaining correct data and improving the reliability of the receiving system. The FPGA can correct the received module data in real time, so as to upload and display the correct image data in real time. In some application scenarios with high requirements for image output stability and real-time performance, this application is a technical solution with significantly improved effects, achieving the error code correction performance requirements that are difficult to achieve by current technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a schematic diagram of the basic process of an error code correction method for an FPGA provided by the present invention;

[0059] Figure 2 It is a schematic diagram of the basic framework of an error code correction system for an FPGA provided by the present invention;

[0060] Figure 3 It is a schematic diagram of the structure of the RS decoding syndrome polynomial operation module in an error code correction system for an FPGA provided by the present invention;

[0061] Figure 4 It is a schematic diagram of the structure of the RS decoding iterative operation module in an error code correction system for an FPGA provided by the present invention;

[0062] Figure 5 It is a schematic diagram of the structure of the RS decoding root finding operation module in an error code correction system for an FPGA provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0063] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following provides a detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments.

[0064] Embodiment 1, referring to Figure 1 , which is an embodiment of the present invention, provides an error correction method for FPGA, including:

[0065] Step S1: Generate the Galois field element α^n based on the received symbol vector and the primitive polynomial, and calculate the syndrome polynomial through 8-symbol parallel processing;

[0066] Step S2: Calculate the coefficients of the error location polynomial based on the syndrome polynomial through the BM iterative algorithm;

[0067] Step S3: Calculate the error location SITE by parallel substituting 10 Galois field elements based on the error location polynomial through the Chien search method;

[0068] Step S4: Establish the evaluation polynomial and the error pattern calculation formula, and perform polynomial division in combination with the derivative of the error location polynomial to obtain the error pattern e;

[0069] Step S5: Perform error code judgment based on the error location SITE and the error pattern e, and correct the error symbol through the Galois field exclusive OR operation to obtain the updated symbol vector.

[0070] In this embodiment, in step S11, the Galois field GF(2^8) is defined based on the determined primitive polynomial p(x), and its primitive element is denoted as α;

[0071] Step S12: Obtain the generator polynomial g(x) based on the RS coding theory and the determined primitive polynomial p(x), and solve the roots of the generator polynomial g(x) to obtain the Galois field element α^n;

[0072] Among them, n ∈ {0, 1, 2, 3}, n is the power of the root of the generator polynomial, and at the same time is the syndrome index;

[0073] Step S13: Perform pre-calculation based on the Galois field element α^n to obtain the syndrome polynomial weight α^(kn);

[0074] Among them, k ∈ {0, 1,..., 197}, k is the symbol position index;

[0075] Step S14: Segment the received symbol vector into symbol segment sets in groups of 8 symbols. Among them, the number of symbols in the received symbol vector is 198. When segmenting in groups of 8 symbols, the last group is padded with zeros;

[0076] Perform parallel processing and calculation on each group of symbol segments in the symbol segment set with 8 symbols in parallel, perform Galois field multiplication and Galois field addition calculations on each group of symbol segments and the corresponding adjoint polynomial weights to obtain partial sum results, perform cumulative summation calculations on the partial sum results corresponding to each group of symbol segments to obtain the coefficients of the adjoint polynomial S, and obtain based on the coefficients of the adjoint polynomial S;

[0077] Its mathematical expression is:

[0078] S = [R(1),..., R(α^n),..., R(a^(2t - 1))];

[0079] p(x) = x^8 + x^4 + x^3 + x^2 + 1;

[0080] ;

[0081] Among them, p(x) represents the expansion of the selected primitive polynomial, g(x) represents the expansion of the generating polynomial, x represents the Galois field formal variable, that is, the power of the primitive element α, S represents the adjoint polynomial, R(α^n) represents the received symbol vector corresponding to the adjoint index n, and t represents the maximum number of corrected symbols.

[0082] In this embodiment, in step S21, establish the error location polynomial Λ(x), and the mathematical expression of Λ(x) is:

[0083] ;

[0084] Among them, Λ(x) represents the error location polynomial, and t represents the maximum number of corrected symbols;

[0085] In step S22, solve the error location polynomial Λ(x) through the BM iterative algorithm, assign two initial values to each iterative parameter based on the preset initial value set, perform 2t iterative operations on the assigned iterative parameters through the BM iterative algorithm to obtain the error location polynomial coefficients, and obtain the error location polynomial Λ(x) based on the error location polynomial coefficients;

[0086] Among them, the iterative parameters include the error location polynomial coefficients, the auxiliary polynomial coefficients, the current polynomial degree, the current deviation value, and the previous deviation value, and t represents the maximum number of corrected symbols.

[0087] In this embodiment, in step S31, calculate the roots of the error location polynomial in the Galois field GF(2^8) through the improved Chien search method, and the processing logic of the improved Chien search method includes:

[0088] Simultaneously substitute 10 Galois field elements α^n into the error locator polynomial Λ(x) per clock cycle to calculate the value of the error locator polynomial. If the value of the error locator polynomial is 0, mark the Galois field element as a candidate root; if the value of the error locator polynomial is non-zero, mark the Galois field element as an eliminated root.

[0089] Perform three-level screening on the candidate roots. Screen the candidate roots through a cascaded 10-to-5 root value selector, a 5-to-3 root value selector, and a 3-to-2 root value selector to obtain the error location roots.

[0090] In step S32, if there are no error location roots, there are no error codes, and the error location SITE is an empty set.

[0091] If there are error location roots, take the reciprocal of the error location roots, and based on the reciprocal of the error location roots and the Galois field inverse element lookup table (LUT), obtain the error location SITE.

[0092] In this embodiment, in step S41, establish an evaluation polynomial, and calculate the error pattern e based on the syndrome polynomial S and the error locator polynomial Λ.

[0093] Perform polynomial multiplication on the syndrome polynomial S and the error locator polynomial Λ, and perform modulo calculation through x^(2t - 1) to truncate the high-order terms to obtain the evaluation polynomial.

[0094] In step S42, perform derivative calculation on the error locator polynomial Λ, and based on the definition of the derivative in the Galois field, obtain the derivative Λ`(x) of the error locator polynomial that only retains the odd-order term coefficients.

[0095] Establish an error pattern calculation formula, perform polynomial division on the evaluation polynomial and the derivative Λ`(x) of the error locator polynomial to obtain the error pattern polynomial e(x), and substitute the error location roots into the error pattern polynomial e(x) to calculate the error pattern e corresponding to the error location SITE.

[0096] The mathematical expressions of the error pattern calculation formula and the evaluation polynomial are:

[0097] ;

[0098] e(x)= -(Ω(x) / Λ`(x));

[0099] Where, Ω(x) represents the evaluation polynomial, e(x) represents the error pattern polynomial, mod represents modulo operation, Λ`(x) represents the derivative of the error locator polynomial, and x represents the Galois field formal variable.

[0100] In this embodiment, in step S51, error code judgment is performed based on the error position SITE. When the error position SITE is an empty set, the error code judgment result is that there is no error code, and the received symbol vector is output after reaching the preset delay period.

[0101] When the error position SITE is not an empty set, the error code judgment result is that there is an error code. The symbol at the error position SITE is extracted from the received symbol vector to obtain the error symbol. The error symbol is subjected to Galois field addition processing with the corresponding value in the error pattern e to obtain the error correction symbol. The error symbol is replaced with the corresponding error correction symbol to obtain the updated symbol vector, and the updated symbol vector is output after reaching the preset delay period.

[0102] Embodiment 2, referring to Figures 2 - 5 , is an embodiment of the present invention, which provides an error correction system for an FPGA, including: an RS decoding timing adjustment module, an RS decoding syndrome polynomial operation module, an RS decoding iterative operation module, an RS decoding root finding operation module, an RS decoding error pattern operation module, and an RS decoding error correction operation module;

[0103] The RS decoding timing adjustment module is used to unify the timing of the received symbols.

[0104] The RS decoding syndrome polynomial operation module is used to calculate the coefficients of the syndrome polynomial S.

[0105] The RS decoding iterative operation module is used to perform iterative calculation of the BM algorithm to obtain the error location polynomial Λ(x).

[0106] The RS decoding root finding operation module is used to locate the error symbol position to obtain the error position SITE.

[0107] The RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error position SITE.

[0108] The RS decoding error correction operation module is used to correct the error symbols in the received symbol vector to obtain the updated symbol vector.

[0109] Preferably, the RS decoding timing adjustment module is used to unify the timing of the received symbols, perform timing standardization processing on the packet form of the received symbols, eliminate the influence of the dynamic interval between the start symbol, data segment, and end symbol in the packet protocol, and output a received symbol sequence with uniform intervals. The packet form is a packet protocol constructed by a packet start, packet data, and packet end, and each packet data consists of 198 symbols.

[0110] The RS decoding syndrome polynomial operation module is used to calculate the coefficients of the syndrome polynomial S, and completes the calculation of the received symbol vector at the Galois field elements through an 8-symbol parallel multiplier array and an exclusive-or accumulation tree to obtain the coefficients of the syndrome polynomial S.

[0111] Preferably, the RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error location polynomial Λ(x). The BM algorithm is split into a non-feedback pipeline through the Galois field multiplier and latch register in the four-stage independent iterative unit, and the coefficients of the error location polynomial are updated step by step to obtain the error location polynomial Λ(x).

[0112] The RS decoding root finding operation module is used to implement the positioning of the error symbol position to obtain the error location SITE. The Chien search method for parallel substitution processing of 10 Galois field elements is implemented through a 10-element parallel test unit. The candidate roots are screened through a cascaded 10-to-5 root value selector, 5-to-3 root value selector, and 3-to-2 root value selector to obtain the error location roots, and the error location SITE is determined based on the error location roots.

[0113] Preferably, the RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error location SITE. The polynomial division calculation of the evaluation polynomial and the derivative of the error location polynomial is implemented through a polynomial division logic unit, and the error pattern e is calculated based on the error pattern polynomial e(x) and the Galois field inverse element lookup table (LUT).

[0114] The RS decoding error correction operation module is used to correct the error symbols in the received symbol vector to obtain an updated symbol vector. The error symbols are located through an address mapping unit and the error location SITE, and the Galois field exclusive OR calculation is completed through an exclusive OR operator array to cover the error symbols to obtain the updated symbol vector.

[0115] Among them, Figure 3 shows the parallel structure for finding the syndrome polynomial:

[0116] Refer to Figure 3 , c0~cn7 represent symbols, and r^0~r^n7 represent the coefficients to be multiplied by each symbol. It can be seen that the solution of the syndrome polynomial adopts an 8-symbol parallel structure, that is: every 8 symbols are multiplied by their corresponding coefficients simultaneously, and then added simultaneously (the addition operation in the Galois field is the exclusive OR operation). In this way, the processing results of 8 symbols are obtained at one time. Finally, several processing results of 8 symbols are continuously added to obtain the syndrome polynomial coefficients. The above figure is the coefficient structure for finding one coefficient of the syndrome polynomial. The syndrome polynomial usually has several coefficients, but the implementation structure is the same, and only the symbol corresponding to the multiplication coefficient r needs to be replaced.

[0117] Due to the adoption of an 8-symbol parallel processing structure, if a code length has 255 symbols, only 32 operations are required to process all the symbols. Compared with the usual single-symbol serial processing structure, which requires 255 operations to process all the symbols, the efficiency is increased by nearly 8 times, and the time consumption is reduced by nearly 8 times, achieving algorithm acceleration.

[0118] Among them, Figure 4 shows the design architecture for finding the error location polynomial Λ:

[0119] Refer to Figure 4 , in the structure for solving the error location polynomial, there is no feedback. The output of the current iterative operation serves as the input for the next iterative operation, and the current iterative operation does not require the feedback of the next iterative operation to participate. In this way, a pipeline structure is achieved. A major advantage of this structure is that results can be continuously calculated. Since there is no feedback between each iterative operation, the independence and simultaneity of each iterative operation are guaranteed. Each iterative operation can be carried out simultaneously and without interference. Therefore, the calculation of the error location polynomial can continue, the input is continuously updated, and the results are continuously updated. This structure has stronger real-time performance and a more efficient and rapid processing ability compared to the usual feedback processing structure.

[0120] The fundamental basis for solving the error location polynomial is the BM iterative algorithm. The optimized iterative algorithm is as follows:

[0121] ;

[0122] ;

[0123] During the iterative process of solving the error location polynomial, Lock_1 and Lock_2 are two latches in the RS decoding iterative operation module, used to store the intermediate calculation results generated by the iterative calculation;

[0124] The function of Lock_1 is to latch the operation results d(1) and Λ(1) of d(j)_1 and Λ(j)(x)_1 in the first iterative operation during the second iterative operation, in order to output d(1) and Λ(1) for related operations in the third iterative operation.

[0125] The function of Lock_2 is to latch the operation results d(1), Λ(1), d(2), and Λ(2) of d(j)_1 / 2 and Λ(j)(x)_1 / 2 in the first and second iterative operations during the third iterative operation, in order to output d(1), Λ(1), d(2), and Λ(2) for related operations in the fourth iterative operation.

[0126] For the operations of \(X^{(j - i)}_1\) and \(\Lambda^{(j)}(x)_1\) in the first iteration, only \(S(1)\) is involved. For the operation of \(d^{(j)}_1\), \(\{S(1), S(2)\}\) and \(\Lambda(1)\) are involved.

[0127] For the operations of \(X^{(j - i)}_2\) and \(\Lambda^{(j)}(x)_2\) in the second iteration, \(d(1)\), \(\Lambda(1)\), and \(X(1)\) are all involved. For the operation of \(d^{(j)}_2\), \(\{S(1), S(2), S(3)\}\) and \(\Lambda(2)\) are involved.

[0128] For the operation of \(X^{(j - i)}_3\) in the third iteration, \(d(2)\), \(\Lambda(2)\), and \(X(2)\) are involved, the operation requires \(d(1)\), \(\Lambda(1)\), \(d(2)\), \(\Lambda(2)\), and \(X(2)\). For the operation of \(d^{(j)}_3\), \(\{S(2), S(3), S(4)\}\) and \(\Lambda(3)\) are involved.

[0129] In the fourth iteration, there are no operations for \(X^{(j - i)}\) and \(d^{(j)}\). Only by operating on \(\Lambda^{(j)}(x)\) can the final result of \(\Lambda\) be obtained. For the operation of \(\Lambda^{(j)}(x)_4\), \(d(1)\), \(\Lambda(1)\), \(d(2)\), \(\Lambda(2)\), \(d(3)\), \(\Lambda(3)\), and \(X(3)\) are involved.

[0130] Let \(d(n)\) represent the operation result of \(d^{(j)}_n\), \(\Lambda(n)\) represent the operation result of \(\Lambda^{(j)}(x)_n\), and \(X(n)\) represent the operation result of \(X^{(j - i)}_n\).

[0131] Among them, Figure 5 shows a parallel and pipelined structure for finding the error location:

[0132] Refer to Figure 5 , when finding the error location, a parallel processing method is first adopted, that is, every 10 Galois field values are substituted into \(\Lambda\) for solution. If \(\Lambda = 0\), it means that this Galois field value is a root of \(\Lambda\). The reason for choosing to process 10 Galois field values in parallel instead of 8 is that when finding the syndrome polynomial, every 8 code elements are processed in parallel. The process of finding the error location has a few more steps than finding the syndrome polynomial. To achieve a speed balance between the two, the parallelism of finding the error location needs to be increased a bit more. Therefore, 10 values are chosen for parallel processing; a pipelined structure is also adopted when finding the error location. From Figure 5It can be seen that the solution of each part does not require feedback and is relatively independent. In this case, in a Galois field set, several groups of 10 Galois field values can be continuously and parallelly substituted into Λ to find the roots. Then, the continuously obtained 10 result values are subjected to three-layer screening to continuously narrow down the range where the root values are located. Five result values that may contain root values are selected from the 10 results, then three result values that may contain root values are selected from the five results, and finally two result values that may contain root values are selected from the three results. The 10 result values are continuously generated, and these three-layer screenings are continuously carried out until two root values are found in a Galois field set or the entire Galois field set is searched (in the case where the number of root values is less than 2), and then the search for the error position of the current code length ends. At this time, the error position has been determined.

[0133] The Galois field set GF(2^m) = {0, a^0, a^1, ..., a^(2^m - 2)}. Substitute a^n into Λ. If Λ = 0, it means that a^n is a root of Λ. Therefore, by continuously substituting a^0, a^1, ..., a^(2^m - 2) into Λ, it is possible to determine whether 0, 2^m - 2, 2^m - 3, ..., 1 are error positions, thus verifying whether all positions of a code length are in error.

[0134] The main innovation of the present invention lies in the three major steps from "finding the syndrome polynomial" to "finding the error-location polynomial" and then to "finding the error position". All these three major steps adopt a parallel and pipelined design structure and achieve rate matching among the three, so that not only the operation efficiency and rate of each step are greatly improved, but also each step can work in coordination without being chaotic due to the imbalance of the rates between steps.

[0135] Those skilled in the art should understand that the embodiments of the present invention can provide a method, a system or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Among them, the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM for short), electrically erasable programmable read-only memory (EEPROM for short), erasable programmable read-only memory (EPROM for short), programmable read-only memory (PROM for short), read-only memory (ROM for short), magnetic memory, flash memory, magnetic disk or optical disk. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, and the instruction device implements the process Figure 1 in one process or multiple processes and / or blocks Figure 1 the functions specified in one block or multiple blocks.

[0136] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A method for correcting an error in an FPGA, characterized in that: include: Step S1: Generate a Galois field element α^n based on the received codeword vector and the primitive polynomial, and obtain the adjoint polynomial by parallel processing of 8 codewords; Step S2: Calculate the coefficients of the error position polynomial based on the adjoint polynomial by using the BM iterative algorithm; Step S3: Based on the error location polynomial, the error location SITE is calculated by substituting 10 Galois field elements in parallel through the Qian search method; Step S4: establishing an evaluation polynomial and an error pattern calculation formula, and performing polynomial division calculation based on the derivative of the error position polynomial to obtain the error pattern e; Step S5: error detection is performed based on the error position SITE and the error pattern e, and the error symbol is corrected by Galois field XOR operation to obtain an updated symbol vector; Wherein, step S31, calculates the root of the error position polynomial in the Galois field GF(2^8) by using the improved Qian search method, and the processing logic of the improved Qian search method includes: Substitute 10 Galois field elements α^n into the error position polynomial Λ(x) at the same time in each clock cycle, calculate the error position polynomial value, if the error position polynomial value is 0, mark the Galois field element as a candidate root, if the error position polynomial value is non-zero, mark the Galois field element as a eliminated root; The candidate roots are screened in three levels, and the wrong position roots are obtained by screening the candidate roots through the series connection of 10-choose-5 root value selectors, 5-choose-3 root value selectors and 3-choose-2 root value selectors; Step S32, if there is no error position root, there is no bit error, and the error position SITE is an empty set; If there is an error position root, the reciprocal of the error position root is taken, and the error position SITE is obtained based on the reciprocal of the error position root and the Galois Field inverse element lookup table (LUT); Where x represents a Galois Field formal variable.

2. The method for correcting an error in an FPGA according to claim 1, wherein: Step S11, defining a Galois field GF(2^8) based on the determined primitive polynomial p(x), wherein the primitive element is denoted as α; Step S12, based on the RS coding theory and the determined primitive polynomial p (x) to obtain the generating polynomial g (x), solving the root of the generating polynomial g (x) to obtain the Galois field element α ^ n; Where n is the power of the root of the generator polynomial and is also the syndrome index; Step S13, pre-calculating based on the Galois Field element α^n to obtain the adjoint polynomial weight α^(kn); Wherein, k is the code element position index; Step S14, segmenting the received symbol vector into groups of 8 symbols to obtain a symbol segment set, performing 8-symbol parallel processing calculation on each group of symbol segments in the symbol segment set, performing Galois field multiplication and Galois field addition calculation on each group of symbol segments and the corresponding adjoint polynomial weight to obtain a partial sum result, accumulating and summing the partial sum results corresponding to each group of symbol segments to obtain the coefficient of the adjoint polynomial S, and obtaining based on the coefficient of the adjoint polynomial S; Its mathematical expression is: S=[R(1), ..., R(α^n), ..., R(a^(2t-1))]; p(x)=x^8+x^4+x^3+x^2+1; ; Among them, p(x) represents the expansion of the selected primitive polynomial, g(x) represents the expansion of the generating polynomial, x represents the Galois field form variable, that is, the power of the primitive element α, S represents the adjoint polynomial, R(α^n) represents the received codeword vector corresponding to the adjoint index n, and t represents the maximum number of corrected codewords.

3. The method for correcting an error in an FPGA according to claim 1, wherein: Step S21, establish the error location polynomial Λ(x), the mathematical expression of Λ(x) is: ; Wherein, Λ(x) represents the error position polynomial, and t represents the maximum number of corrected code elements; Step S22, solving the error location polynomial Λ(x) by using the BM iterative algorithm, assigning two initial values ​​to each iteration parameter based on a preset initial value set, performing 2t iteration operations on the assigned iteration parameters based on the BM iterative algorithm to obtain error location polynomial coefficients, and obtaining the error location polynomial Λ(x) based on the error location polynomial coefficients; The iteration parameters include error position polynomial coefficients, auxiliary polynomial coefficients, current polynomial order, current deviation value and last deviation value, and t represents the maximum number of corrected code elements.

4. The method for correcting an error in an FPGA according to claim 1, wherein: Step S41, establishing an evaluation polynomial, and calculating the error pattern e based on the adjoint polynomial S and the error location polynomial Λ; Perform polynomial multiplication on the adjoint polynomial S and the error position polynomial Λ, and truncate the high-order terms by performing modular calculation with x^(2t-1) to obtain the evaluation polynomial; Step S42, performing derivative calculation on the error position polynomial Λ, and obtaining the error position polynomial derivative Λ`(x) retaining only the odd-order coefficients based on the derivative definition in the Galois Field; Establish an error pattern calculation formula, perform polynomial division on the evaluation polynomial and the error position polynomial derivative Λ`(x) to obtain the error pattern polynomial e(x), substitute the error position root into the error pattern polynomial e(x) to calculate the error pattern e corresponding to the error position SITE; The mathematical expressions for the error pattern calculation formula and the evaluation polynomial are: ; e(x) = -(Ω(x) / Λ`(x)); Among them, Ω(x) represents the evaluation polynomial, e(x) represents the error pattern polynomial, mod represents the modular operation, Λ`(x) represents the derivative of the error position polynomial, and x represents the Galois field form variable.

5. The method for correcting an error in an FPGA according to claim 1, wherein: Step S51, performing error judgment based on the error position SITE, when the error position SITE is an empty set, the error judgment result is that there is no error, and the received code element vector is output after reaching a preset delay period; When the error position SITE is not an empty set, the error judgment result is that there is a bit error. The codeword at the error position SITE is extracted from the received codeword vector to obtain the error codeword. The error codeword and the corresponding value in the error pattern e are subjected to Galois field addition processing to obtain the error correction codeword. The error codeword is replaced with the corresponding error correction codeword to obtain an updated codeword vector. After the preset delay period is reached, the updated codeword vector is output.

6. An FPGA error correction system, used to implement the FPGA error correction method according to claim 1, characterized in that: include: RS decoding timing adjustment module, RS decoding adjoint polynomial operation module, RS decoding iteration operation module, RS decoding root calculation module, RS decoding error pattern operation module and RS decoding error correction operation module; The RS decoding timing adjustment module is used to unify the timing of the received code elements; The RS decoding adjoint polynomial operation module is used to realize the coefficient calculation of the adjoint polynomial S; The RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x); The RS decoding root calculation module is used to locate the error symbol position to obtain the error position SITE; The RS decoding error pattern calculation module is used to calculate the error pattern e corresponding to each error position SITE; The RS decoding error correction operation module is used to obtain an updated codeword vector by correcting the error codewords in the received codeword vector.

7. The FPGA error correction system according to claim 6, characterized in that: The RS decoding timing adjustment module is used to unify the timing of the received code elements, perform timing standardization processing on the packet form of the received code elements, eliminate the dynamic interval influence between the start symbol, data segment, and end symbol in the packet protocol, and output a uniformly spaced received code element sequence, wherein the packet form is a packet protocol constructed by packet start, packet data, and packet end, and each packet data consists of 198 code elements; The RS decoding companion polynomial operation module is used to realize the coefficient calculation of the companion polynomial S. The coefficients of the companion polynomial S are obtained by calculating the received codeword vector at the Galois field elements through an 8-codeword parallel multiplier array and an XOR accumulator tree.

8. The FPGA error correction system according to claim 6, characterized in that: The RS decoding iterative operation module is used to implement the iterative calculation of the BM algorithm to obtain the error position polynomial Λ(x). The BM algorithm is split into a non-feedback pipeline through the Galois field multiplier and latch register in the four-stage independent iteration unit, and the coefficients of the error position polynomial are updated stage by stage to obtain the error position polynomial Λ(x). The RS decoding root-finding operation module is used to locate the error codeword position and obtain the error position SITE. The qian search method of parallel substitution of 10 Galois field elements is implemented through a 10-element parallel test unit. The candidate roots are screened through a series of 10-to-5 root value selectors, 5-to-3 root value selectors and 3-to-2 root value selectors to obtain the error position root, and the error position SITE is determined based on the error position root.

9. The FPGA error correction system according to claim 6, characterized in that: The RS decoding error pattern operation module is used to calculate the error pattern e corresponding to each error position SITE, and implements the polynomial division calculation of the evaluation polynomial and the error position polynomial derivative through the polynomial division logic unit, and calculates the error pattern e based on the error pattern polynomial e(x) and the Galois field inverse element lookup table (LUT); The RS decoding error correction operation module is used to correct the error codewords in the received codeword vector to obtain an updated codeword vector, locate the error codeword through the address mapping unit and the error position SITE, and complete the Galois field XOR calculation to cover the error codeword through the XOR operator array to obtain an updated codeword vector.

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