Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of rows of transistors which are distributed in a first direction parallel to a substrate, and each transistor comprises a semiconductor column which extends in a direction perpendicular to the substrate, the semiconductor columns of the transistors in all odd-numbered rows form an array distributed along the first direction and along a second direction parallel to the substrate, and the semiconductor columns of the transistors in all even-numbered rows form an array distributed along the first direction and the second direction. The semiconductor columns of the transistors in the odd-numbered rows and the semiconductor columns of the transistors in the even-numbered rows are staggered in the second direction, and the first direction is perpendicular to the second direction; and a plurality of bit lines extending along the second direction, wherein the transistors in the same column are connected to the same bit line. According to the scheme provided by the embodiment of the invention, by arranging the transistors staggered in the column direction, dislocation etching or dislocation degree reduction during formation of the node contact electrode can be avoided, the process difficulty is reduced, and the yield is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a semiconductor device and a manufacturing method thereof, and an electronic device, which simplifies the process and improves the yield.

[0006] An embodiment of the present application provides a semiconductor device, including:

[0007] A plurality of rows of transistors distributed along a first direction parallel to a substrate, the transistors comprising semiconductor columns extending along a direction perpendicular to the substrate, the semiconductor columns of all odd-numbered rows of transistors forming an array distributed along the first direction and along a second direction parallel to the substrate, the semiconductor columns of all even-numbered rows of transistors forming an array distributed along the first direction and the second direction, and the semiconductor columns of the transistors in the odd-numbered rows are staggered with the semiconductor columns of the transistors in the even-numbered rows in the second direction, and the first direction and the second direction are perpendicular;

[0008] A plurality of bit lines extend along the second direction, and transistors in the same column are connected to the same bit line.

[0009] In some embodiments, every two adjacent columns of transistors share one bit line.

[0010] In some embodiments, each of the bit lines is disposed between semiconductor pillars of two columns of transistors that share the bit line.

[0011] In some embodiments, along the extension direction of the semiconductor column, the side wall of the semiconductor column includes a first region, a channel region, and a second region distributed in sequence, and the first region is arranged on the side of the channel region facing the substrate, and the bit line is connected to the first region of the semiconductor column of two columns of transistors sharing the bit line.

[0012] In some embodiments, in two columns of semiconductor pillars connected to the same bit line, the side wall of the first region of any column of semiconductor pillars facing the other column of semiconductor pillars includes a first sub-region extending in a direction perpendicular to the substrate, and a second sub-region extending from the first sub-region in a direction away from the other column of semiconductor pillars, and a third sub-region extending from the second sub-region in a direction perpendicular to the substrate, the third sub-region being arranged on a side of the first sub-region away from the substrate, the bit line being connected to the second sub-region and an area of ​​the third sub-region adjacent to the second sub-region, and not connected to the first sub-region.

[0013] In some embodiments, the semiconductor device also includes: a plurality of first grooves extending along the second direction, a bit line is arranged in each of the first grooves, two columns of transistors arranged between adjacent first grooves are respectively connected to the bit lines in adjacent first grooves, and the depth of the first groove is less than the height of the semiconductor column, and the side walls of the two columns of semiconductor columns adjacent to the first groove form the bottom wall and side walls of the first groove.

[0014] In some embodiments, a dimension of the bit line along the first direction is smaller than a dimension of the bit line along a direction perpendicular to the substrate.

[0015] In some embodiments, orthographic projections of the channel region and the second region on the substrate fall within orthographic projections of the first region on the substrate.

[0016] In some embodiments, the transistor further includes: a gate electrode surrounding the channel region, wherein the gate electrodes of transistors in the same row are connected to form a word line extending along the first direction.

[0017] In some embodiments, the semiconductor device also includes a plurality of node contact electrodes arranged on the surface of the plurality of semiconductor columns away from the substrate and respectively connected to the plurality of semiconductor columns, and the arrangement of the plurality of node contact electrodes is consistent with the arrangement of the plurality of transistors.

[0018] In some embodiments, the semiconductor device also includes a plurality of capacitors arranged on the side of the plurality of node contact electrodes away from the transistor and corresponding one to the transistor, one of the capacitors being connected to the surface of a node contact electrode away from the transistor, and the arrangement of the plurality of capacitors being consistent with the arrangement of the plurality of transistors.

[0019] The present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0020] Providing a substrate, forming a plurality of first trenches extending along a second direction on the substrate, and forming a bit line extending along the second direction in each of the first trenches;

[0021] A plurality of rows of semiconductor pillars extending in a direction perpendicular to the substrate are formed and distributed along a first direction, and the semiconductor pillars of all odd rows form an array distributed along the first direction and along a second direction, and the semiconductor pillars of all even rows form an array distributed along the first direction and along the second direction, and the semiconductor pillars of odd rows are staggered with the semiconductor pillars of even rows in the second direction; the first trench is arranged between two adjacent columns of semiconductor pillars, and the depth of the first trench is less than the height of the semiconductor pillar.

[0022] In some embodiments, the semiconductor pillar is formed in the following manner: a mask layer including a plurality of first strip-shaped portions extending along a third direction and a plurality of second strip-shaped portions extending along a fourth direction is formed on the substrate, and the substrate covered by the mask layer is etched to form the semiconductor pillar, wherein the third direction intersects with the first direction and the second direction, the fourth direction intersects with the first direction and the second direction, and the third direction intersects with the fourth direction.

[0023] In some embodiments, the method further includes: forming a second trench extending along the first direction between adjacent semiconductor pillars, wherein a bottom wall of the second trench exposes the bit line;

[0024] The semiconductor pillars are exposed in a channel region of the bit line away from the substrate to form a gate electrode surrounding the channel region. The gate electrodes of the semiconductor pillars in the same row are connected to form a word line extending along a first direction.

[0025] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments.

[0026] The embodiment of the present application includes a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of rows of transistors distributed along a first direction parallel to a substrate, the transistors include semiconductor columns extending in a direction perpendicular to the substrate, the semiconductor columns of all odd-numbered rows of transistors form an array distributed in the first direction and in a second direction parallel to the substrate, the semiconductor columns of all even-numbered rows of transistors form an array distributed in the first direction and in the second direction, and the semiconductor columns of the transistors in the odd-numbered rows are staggered with the semiconductor columns of the transistors in the even-numbered rows in the second direction, and the first direction is perpendicular to the second direction; a plurality of bit lines extending in the second direction, and transistors in the same column are connected to the same bit line. The solution provided in this embodiment can avoid dislocation etching when forming node contact electrodes by setting transistors staggered in the column direction, reduce process difficulty, and improve yield. Other features and advantages of the present application will be described in the subsequent description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the description and the drawings.

[0027] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0029] Figure 1A A top view of a semiconductor device is provided for an exemplary embodiment. Figure 1B For along Figure 1A Schematic diagram of the aa' direction; Figure 1C For along Figure 1A Schematic diagram of the bb' direction; Figure 1D For along Figure 1A Schematic diagram of the cc' direction; Figure 1E For along Figure 1A Schematic diagram of the dd' direction;

[0030] Figure 2A A three-dimensional schematic diagram of a semiconductor device provided as an exemplary embodiment;

[0031] Figure 2B A schematic three-dimensional diagram of a semiconductor device provided for another exemplary embodiment;

[0032] Figure 3A A cross-sectional view in the aa' direction after forming a first trench is provided for an exemplary embodiment. Figure 3B This is a cross-sectional view along the bb' direction after the first trench is formed. Figure 3CThis is a cross-sectional view along the cc' direction after forming the first trench. Figure 3D is a cross-sectional view in the dd' direction after forming the first trench;

[0033] Figure 4A A cross-sectional view in the aa' direction after forming a bit line provided by an exemplary embodiment. Figure 4B This is a cross-sectional view in the bb' direction after the bit line is formed. Figure 4C This is a cross-sectional view in the cc' direction after the bit line is formed. Figure 4D It is a cross-sectional view in the dd' direction after the bit line is formed;

[0034] Figure 5A A top view after forming a first sub-pattern is provided for an exemplary embodiment. Figure 5B This is a cross-sectional view in the aa' direction after forming the first sub-pattern. Figure 5C This is a cross-sectional view in the bb' direction after forming the first sub-pattern. Figure 5D This is a cross-sectional view in the cc' direction after forming the first sub-pattern. Figure 5E A cross-sectional view after forming the first sub-pattern dd';

[0035] Fig. 6A A top view after pattern formation is provided for an exemplary embodiment. Figure 6B This is the cross-sectional view in the aa' direction after patterning. Figure 6C This is the cross-sectional view in the bb' direction after patterning. Fig.6D This is the cross-sectional view in the cc' direction after patterning. Fig. 6E It is a cross-sectional view in the dd' direction after pattern formation;

[0036] Fig. 7A A cross-sectional view in the aa' direction after forming a semiconductor column provided by an exemplary embodiment. Figure 7B This is a cross-sectional view in the bb' direction after forming a semiconductor column. Figure 7C This is a cross-sectional view in the cc' direction after forming a semiconductor column. Fig.7D It is a cross-sectional view in the dd' direction after the semiconductor pillar is formed;

[0037] Fig. 8A A cross-sectional view in the aa' direction after forming the third trench provided for an exemplary embodiment. Figure 8B This is a cross-sectional view in the bb' direction after the third trench is formed. Figure 8C This is a cross-sectional view in the cc' direction after forming the third trench. Fig.8D A cross-sectional view in the dd' direction after the third trench is formed;

[0038] Fig.9A A cross-sectional view in the aa' direction after forming the third insulating layer and the fourth insulating layer provided for an exemplary embodiment, Fig. 9B This is a cross-sectional view in the bb' direction after forming the third insulating layer and the fourth insulating layer. Fig. 9CThis is a cross-sectional view in the cc' direction after forming the third insulating layer and the fourth insulating layer. Fig.9D A cross-sectional view in the dd' direction after forming the third insulating layer and the fourth insulating layer;

[0039] Fig. 10A A cross-sectional view in the aa' direction after exposing the second region provided by an exemplary embodiment, Fig. 10B This is a cross-sectional view in the bb' direction after exposing the second region. Fig. 10C This is a cross-sectional view in the cc' direction after exposing the second region. Fig. 10D It is a cross-sectional view along the dd' direction after the second region is exposed;

[0040] Fig.11A A cross-sectional view in the aa' direction after forming a gate insulating layer provided by an exemplary embodiment. Fig. 11B This is a cross-sectional view in the bb' direction after the gate insulating layer is formed. Fig. 11C This is a cross-sectional view in the cc' direction after forming the gate insulating layer. Fig.11D It is a cross-sectional view along the dd' direction after the gate insulating layer is formed;

[0041] Fig. 12A A cross-sectional view in the aa' direction after forming a word line provided by an exemplary embodiment. Fig. 12B This is a cross-sectional view in the bb' direction after the word line is formed. Fig. 12C This is a cross-sectional view in the cc' direction after the word line is formed. Fig.12D It is a cross-sectional view in the dd' direction after the word line is formed;

[0042] Fig.13A A cross-sectional view in the aa' direction after forming the sixth insulating layer provided by an exemplary embodiment. Fig. 13B This is a cross-sectional view along the bb' direction after the sixth insulating layer is formed. Fig. 13C This is a cross-sectional view in the cc' direction after the sixth insulating layer is formed. Fig.13D It is a cross-sectional view along the dd' direction after the sixth insulating layer is formed. DETAILED DESCRIPTION

[0043] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0044] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0045] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0046] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0047] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0048] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0049] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0050] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0051] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0052] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0053] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0054] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0055] In some technical solutions, transistors are implemented using deep buried channels or vertical MOS. From a top view, transistors are mainly arranged in a square stack, and the upper capacitors connected to the transistors are arranged in a hexagonal close stack to improve the utilization of capacitor space. However, this also brings about the problem that the connection between the transistor and the capacitor needs to design a misaligned node contact electrode (NodeContact), which is difficult to process and affects the device yield. In the disclosed embodiment, the transistors are arranged in a hexagonal close stack or a nearly hexagonal close stack, so there is no need to design a misaligned node contact electrode, which reduces the process difficulty and improves the device yield.

[0056] In the present disclosure, the substrate 1 has two main surfaces and side surfaces between the main surfaces, the two main surfaces are respectively an upper surface and a lower surface arranged opposite to each other, the upper surface is the surface on which the transistor is arranged, parallel to the substrate 1 means parallel to the lower surface of the substrate 1, and perpendicular to the substrate 1 means perpendicular to the lower surface of the substrate 1. Before forming the semiconductor pillar 10, the substrate 1 refers to the entire substrate (including the semiconductor region used to manufacture the semiconductor pillar 10), and after forming the semiconductor pillar 10, the substrate 1 refers to the region located below the transistor in the entire substrate.

[0057] Figure 1A A top view of a semiconductor device is provided for an exemplary embodiment. Figure 1B For along Figure 1A Schematic diagram of the aa' direction, Figure 1C For along Figure 1A Schematic diagram of the bb' direction, Figure 1D For along Figure 1A Schematic diagram of the cc' direction, Figure 1E For along Figure 1A Schematic diagram of the dd' direction in FIG. The cc' direction and the dd' direction are parallel to the first direction X, and the aa' direction and the bb' direction are parallel to the second direction Y. Figures 1A to 1E As shown, the present disclosure provides a semiconductor device, including:

[0058] A plurality of rows of transistors are distributed along a first direction X parallel to the substrate 1, wherein the transistors include a semiconductor column 10 extending in a direction perpendicular to the substrate 1, wherein the semiconductor column 10 has a main surface, which is a side surface or a side wall, and also includes an end, which is the top of the semiconductor column 10. The semiconductor column 10 can be formed by epitaxy of the substrate 1 or by etching a groove on the substrate 1, so the other end of the semiconductor column 10 can be connected to the substrate 1 as an integrated structure.

[0059] The semiconductor pillars 10 of all odd-numbered rows of transistors form an array distributed along the first direction X and along a second direction Y parallel to the substrate 1, and the semiconductor pillars 10 of all even-numbered rows of transistors form an array distributed along the first direction X and the second direction Y, and the semiconductor pillars 10 of the transistors in the odd-numbered rows are staggered from the semiconductor pillars 10 of the transistors in the even-numbered rows in the second direction Y, and the first direction X and the second direction Y are perpendicular;

[0060] A plurality of bit lines 30 extending along the second direction Y, transistors in the same column are connected to the same bit line 30; the plurality of bit lines 30 may be distributed at intervals along the first direction X;

[0061] The plurality of word lines 40 extend along the first direction X, and transistors in the same row are connected to the same word line 40 ; the plurality of word lines 40 may be distributed along the second direction Y at intervals.

[0062] In the solution provided in this embodiment, transistors in different rows are staggered in the direction of bit line extension. When connected to capacitors, it is possible to improve capacitor space utilization while eliminating the need to design staggered node contacts or reduce the degree of staggered contact, thereby reducing process difficulty and improving yield.

[0063] In some embodiments, every two adjacent columns of transistors may share one bit line 30. Figure 1A As shown, the adjacent transistors on both sides of the same bit line 30 are connected to the bit line 30. The solution provided by this embodiment can reduce the number of bit lines, and the transistors in adjacent columns share the same bit line, which has a more compact structure and can improve space utilization.

[0064] In some embodiments, each of the bit lines 30 is disposed between semiconductor pillars 10 of two columns of transistors sharing the bit line 30. Compared with the solution in which the bit line 30 is disposed at the bottom of the semiconductor pillar 10, the bit line 30 does not need to cover the area where the two columns of semiconductor pillars 10 are located, the width of the bit line 30 along the first direction X can be reduced, and voids are not easily formed when the bit line 30 is formed.

[0065] In some embodiments, along the extension direction of the semiconductor column 10, the sidewall of the semiconductor column 10 may include a first region 12, a channel region 11, and a second region 13 distributed in sequence, and the first region 12 is arranged on the side of the channel region 11 facing the substrate 1, and the bit line 30 is connected to the first region 12 of the semiconductor column 10 of the two columns of transistors sharing the bit line 30. It can be understood that the sidewalls close to the two ends of the semiconductor column 10 are the first region 12 and the second region 13, and the region between the first region 12 and the second region 13 is the channel region 11, and the channel region 11 can be roughly distinguished from the first region 12 and the second region 13 by the position of the gate electrode, or can be roughly distinguished by the different conductivity of the first region 12 and the second region 13 and the channel region 11.

[0066] In this embodiment, the bit line is arranged on the side wall of the semiconductor column. In one technical solution, isotropic etching is used to form a bit line groove at the bottom of the silicon column, and metal is filled in the groove to form the bit line, but the groove has a large depth-to-width ratio, the process is difficult, and voids may be formed, resulting in high resistance, and it is difficult to form metal silicide for ohmic contact. In the embodiment of the present disclosure, the bit line can be formed on the side wall of the semiconductor column. Compared with the solution in which the bit line is arranged at the bottom of the semiconductor column, the depth-to-width ratio of the bit line groove is reduced, the difficulty of filling the bit line is reduced, and the bit line resistance can be reduced. In addition, it is easier to form metal silicide, realize ohmic contact, and reduce contact resistance.

[0067] In some embodiments, the semiconductor column 10 extending in a direction perpendicular to the substrate 1 may be understood as extending only in a direction perpendicular to the substrate 1 as a whole, and a sidewall of the semiconductor column 10 may have a region extending in a direction parallel to the substrate 1 .

[0068] In some embodiments, the cross-section of the channel region 11 in a direction parallel to the substrate 1 may have substantially the same size and shape at different locations. It can be understood that the channel region 11 of the semiconductor pillar 10 is a continuous and smooth curved surface, and the cross-sections at different locations of the curved surface have similar shapes, but may have different sizes.

[0069] In some embodiments, the size and shape of the cross section of the second region 12 at different positions in the direction parallel to the substrate 1 may be substantially the same. It can be understood that the second region 12 of the semiconductor pillar 10 is a continuous and smooth curved surface, and the cross sections at different positions of the curved surface have similar shapes, but may have different sizes.

[0070] In some embodiments, in two columns of semiconductor pillars 10 connected to the same bit line 30, the sidewall of the first region 12 of any column of semiconductor pillars 10 facing the other column of semiconductor pillars 10 includes a first sub-region 121 extending in a direction perpendicular to the substrate 1, and a second sub-region 122 extending from the first sub-region 121 in a direction away from the other column of semiconductor pillars 10, and a third sub-region 123 extending from the second sub-region 122 in a direction perpendicular to the substrate, wherein the third sub-region 123 is arranged on a side of the first sub-region 121 away from the substrate 1, and the bit line 30 is connected to the second sub-region 122 and the region of the third sub-region 123 adjacent to the second sub-region 122, and is not connected to the first sub-region 121. Figure 1D As shown, the semiconductor pillar 10 forms a platform on the side facing another column of semiconductor pillars 10 (another column of semiconductor pillars 10 sharing the same bit line), and the bit line 30 is arranged on the platform. The bit line 30 does not cover the area of ​​the third sub-region 123 away from the second sub-region 122 to prevent the bit line 30 from being connected to the word line 40.

[0071] In some embodiments, two columns of semiconductor pillars 10 sharing the same bit line 30 are connected to form a pillar extending along the second direction Y between the two columns of semiconductor pillars 10, and the bit line 30 is disposed on the pillar. That is, the aforementioned platforms are connected to each other to form a pillar, and the bit line 30 is disposed on the pillar.

[0072] In some embodiments, the semiconductor device further includes: a plurality of first trenches T1 extending along the second direction Y, each of the first trenches T1 being provided with a bit line 30, two columns of transistors provided between adjacent first trenches T1 being respectively connected to the bit lines 30 in the adjacent first trenches T1, and a depth h1 of the first trenches T1 being less than a height h2 of the semiconductor pillars 10, and side walls of two columns of semiconductor pillars 10 adjacent to the first trenches T1 forming the bottom wall and side walls of the first trenches T1. That is, a first trench T1 is provided between two columns of semiconductor pillars connected to the same bit line 30, a bit line 30 is formed in the first trench T1, and the depth of the first trench T1 is less than the height of the semiconductor pillars 10, so that a large aspect ratio can be avoided and the difficulty of filling the bit line can be reduced.

[0073] In some embodiments, the dimension of the bit line 30 along the first direction X is smaller than the dimension of the bit line 30 along the direction perpendicular to the substrate 1. Compared with the solution of forming the bit line at the bottom of the semiconductor column, which is difficult to fill and has a limited height of the bit line, the solution provided in this embodiment forms the bit line on the side wall of the semiconductor column, which has a low process difficulty. Therefore, the height of the bit line can be increased and the width of the bit line can be reduced, thereby reducing the area occupied by the transistor without increasing the resistance of the bit line.

[0074] In some embodiments, the orthographic projections of the channel region 11 and the second region 13 on the substrate 1 may fall within the orthographic projection of the first region 12 on the substrate 1. That is, the cross-sectional areas of the channel region 11 and the second region 13 of the semiconductor column may be smaller than the cross-sectional area of ​​the first region 11.

[0075] In some embodiments, the transistor may further include: a gate electrode surrounding the channel region 11, wherein the gate electrodes of the transistors in the same row are connected to form a word line 40 extending along the first direction. A gate insulating layer 24 surrounding the channel region 11 is provided between the word line 40 and the channel region 11. The gate insulating layer 24 is located between the word line 40 and the semiconductor column 10 to insulate the word line 40 from the semiconductor column 10.

[0076] In an exemplary embodiment, the semiconductor device may further include an isolation structure filled between the transistors, and the isolation structure may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0077] Figure 2A FIG. 1 is a perspective schematic diagram of a semiconductor device provided by another exemplary embodiment. Figure 2A As shown, the semiconductor device includes multiple rows and columns of transistors, and the arrangement of the transistors refers to the previous embodiment. The transistor includes a semiconductor column 10 extending in a direction perpendicular to the substrate 1. The semiconductor device may also include a plurality of node contact electrodes 50 arranged on the surface of the plurality of semiconductor columns 10 away from the substrate 1 and respectively connected to the plurality of semiconductor columns 10. The arrangement of the plurality of node contact electrodes 50 is consistent with the arrangement of the plurality of transistors. That is, in this embodiment, the node contact electrode 50 does not need to be staggered etched, and can be directly formed on the upper surface of the semiconductor column 10, which reduces the process difficulty. In this embodiment, the morphology of the semiconductor column 10 is different from that of the previous embodiment, which is only for illustration. Please refer to the previous embodiment for the actual structure.

[0078] Figure 2B FIG. 1 is a perspective schematic diagram of a semiconductor device provided by another exemplary embodiment. Figure 2BAs shown, the semiconductor device includes a plurality of storage units, the storage unit includes a transistor and a capacitor 60 arranged on a side of the transistor away from the substrate 1, the transistor and the capacitor 60 are connected through a node contact electrode 50, the arrangement of the transistor refers to the previous embodiment, the capacitor 60 is arranged on a side of the node contact electrode 50 away from the transistor, one of the capacitors 60 is connected to a surface of the node contact electrode 50 away from the transistor, and the arrangement of the plurality of capacitors 60 is consistent with the arrangement of the plurality of transistors. In this embodiment, the arrangement of the transistors can adapt to the arrangement of the capacitors, and under the condition of ensuring the largest possible capacitor area, there is no need to perform dislocation etching or reduce the degree of dislocation, thereby reducing the process difficulty.

[0079] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0080] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0081] 1) forming a first trench T1;

[0082] A substrate 1 is provided, and the substrate 1 is etched to form a plurality of first trenches T1 extending along a second direction Y. Figure 3A , Figure 3B , Figure 3C and Figure 3D As shown, Figure 3A This is a cross-sectional view in the aa' direction after the first trench T1 is formed. Figure 3B This is a cross-sectional view along the bb' direction after the first trench T1 is formed. Figure 3C This is a cross-sectional view in the cc' direction after the first trench T1 is formed. Figure 3DIt is a cross-sectional view in the dd' direction after forming the first trenches T1. The plurality of first trenches T1 are distributed at intervals along the first direction X. Subsequently, a bit line 30 may be formed in the first trenches T1.

[0083] In some embodiments, the substrate 1 can be a semiconductor substrate; for example, it can include at least one elemental semiconductor material (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0084] 2) forming a bit line 30;

[0085] The forming of the bit line 30 may include: depositing a first connection layer film and a first conductive film in the first trench T1 in sequence, etching the first connection layer film and the first conductive film to a preset height, and forming the bit line 30, such as Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown, Figure 4A This is a cross-sectional view in the aa' direction after the bit line 30 is formed. Figure 4B This is a cross-sectional view in the bb' direction after the bit line 30 is formed. Figure 4C This is a cross-sectional view in the cc' direction after the bit line 30 is formed. Figure 4D dd' direction cross-sectional view after forming the bit line 30. The bit line 30 may include an adhesive sublayer 31 formed of a connection layer film and a conductive sublayer 32 formed of a first conductive film.

[0086] In some embodiments, the first connection layer film may be, for example, TiN, etc., which can enhance the adhesion between the bit line 30 and a subsequently formed semiconductor pillar.

[0087] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0088] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0089] Alternatively, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, conductive metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0090] Alternatively, it may be polysilicon, silicon, germanium, silicon germanium, etc. which are conductive after being doped.

[0091] The subsequent second conductive film is similar to the first conductive film and will not be described in detail.

[0092] In some embodiments, a chemical vapor deposition (CVD) or ALD process may be used to deposit the connection layer thin film and the first conductive thin film.

[0093] In some embodiments, metal silicide may be formed by an annealing process to reduce the contact resistance between the bit line 30 and the semiconductor pillar 10 .

[0094] 3) forming a first sub-pattern 41;

[0095] Spin coating a first insulating film on the substrate 1 forming the aforementioned structure to form a first insulating layer 2; the first insulating layer 2 fills the first trench T1 and covers the substrate 1;

[0096] Depositing a first hard mask film to form a first hard mask layer 3, wherein the first hard mask layer 3 covers the first insulating layer 2;

[0097] Deposit a second hard mask film and pattern a first sub-pattern 41, such as Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E As shown, Figure 5A is a top view after the first sub-pattern 41 is formed. Figure 5B This is a cross-sectional view in the aa' direction after the first sub-pattern 41 is formed. Figure 5C The cross-sectional view in the bb' direction after the first sub-pattern 41 is formed, Figure 5D The cc' direction cross-sectional view after forming the first sub-pattern 41, Figure 5E The dd' direction cross-sectional view after forming the first sub-pattern 41. The second hard mask film material is different from the first hard mask film. Figure 5A Only the bit line 30 and the first sub-pattern 41 are shown. Figure 5A As shown, the first sub-pattern 41 includes a plurality of first strip portions extending along a third direction, and the third direction and the second direction Y form an angle greater than 0 and less than 90 degrees.

[0098] In some embodiments, the first insulating film may be a low-k material, such as silicon dioxide (SiO 2 ).

[0099] In some embodiments, the first hard mask film may be, for example, polysilicon (poly), and the second hard mask film may be a low-k material, such as silicon dioxide (SiO 2 ).

[0100] 4) forming a second sub-pattern 42;

[0101] Spin coating a third hard mask film on the substrate 1 having the aforementioned structure, and patterning to form a third hard mask layer 5;

[0102] The second hard mask film is backfilled to form a second sub-pattern 42; the second sub-pattern 42 and the first sub-pattern 41 constitute a pattern 4, such as Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E As shown, Fig. 6A This is a top view after pattern 4 is formed. Figure 6B This is the cross-sectional view in the aa' direction after forming pattern 4. Figure 6C This is a cross-sectional view in the bb' direction after forming pattern 4. Fig.6D This is a cross-sectional view in the cc' direction after pattern 4 is formed. Fig. 6E It is a cross-sectional view in the dd' direction after forming pattern 4. Among them, Fig. 6A Only the bit line 30 , the first sub-pattern 41 , and the second sub-pattern 42 are shown.

[0103] like Fig. 6A As shown, the second sub-pattern 42 includes a plurality of second strip-shaped portions extending along a fourth direction, and the fourth direction forms an angle greater than 0 and less than 90 degrees with the third direction, for example, an angle of 30 to 60 degrees. Subsequently, the substrate 1 covered by the first strip-shaped portion and the second strip-shaped portion is etched to form a plurality of rows of semiconductor columns 10 arranged along the first direction X, and the semiconductor columns 10 in adjacent rows are staggered from each other in the second direction Y. The orthographic projection of the first trench T1 may overlap with the orthographic projection of the intersection of the first strip-shaped portion and the second strip-shaped portion. The first strip-shaped portion and the second strip-shaped portion divide the substrate 1 into a plurality of rhombus-shaped areas, and the same rhombus-shaped area is located on the same side of the first trench T1, that is, the rhombus-shaped area will not be divided into two parts by the first trench T1, and the position of the first trench T1 can refer to the position of the bit line 30, and the rhombus-shaped area will not be divided into two parts by the bit line 30.

[0104] In some embodiments, the third hard mask film may be, for example, a spin-on hard mask (SOH).

[0105] 5) forming a semiconductor column 10;

[0106] Using pattern 4 as a mask, the substrate 1 in the area not covered by pattern 4 is etched to form a plurality of second trenches T2 extending in a direction perpendicular to the substrate 1. The plurality of second trenches T2 divide the substrate 1 into a plurality of semiconductor pillars 10. The plurality of semiconductor pillars 10 are arranged in a hexagonal close-packed arrangement; the shapes of the plurality of second trenches T2 refer to Fig. 6A The shape of the middle pattern 4. The depth of the second trench T2 along the direction perpendicular to the substrate 1 is greater than the depth of the first trench T1 along the direction perpendicular to the substrate 1.

[0107] A second insulating film is deposited or coated, and polished to form a second insulating layer 6, and the second insulating layer 6 fills the second trench T2. Fig. 7A , Figure 7B , Figure 7C and Fig.7D As shown, Fig. 7A This is a cross-sectional view in the aa' direction after the semiconductor column 10 is formed. Figure 7B This is a cross-sectional view along the bb' direction after the semiconductor pillar 10 is formed. Figure 7C This is a cross-sectional view in the cc' direction after the semiconductor column 10 is formed. Fig.7D It is a cross-sectional view taken along the dd′ direction after the semiconductor pillar 10 is formed.

[0108] In some embodiments, the second insulating film may be a low-k material, such as silicon dioxide (SiO 2 ).

[0109] In the solution provided in this embodiment, the second trench T2 is filled with low-k material. Compared with the solution in which the bit line 30 is set at the bottom of the semiconductor column 10, the low-k material is spaced between the bit line 30 and the word line 40, which can reduce the parasitic capacitance between the bit line 30 and the word line 40.

[0110] 6) forming a third trench T3;

[0111] The forming of the third trench T3 may include: forming a plurality of third trenches T3 extending along the first direction X on the substrate 1 forming the aforementioned structure, wherein the plurality of third trenches T3 are spaced apart along the second direction Y, and a row of semiconductor pillars 10 is formed between adjacent third trenches T3, such as Fig. 8A , Figure 8B , Figure 8C and Fig.8D As shown, Fig. 8A This is a cross-sectional view in the aa' direction after the third trench T3 is formed. Figure 8B The cross-sectional view in the bb' direction after the third trench T3 is formed. Figure 8C The cc' direction cross-sectional view after forming the third trench T3, Fig.8DThe dd' direction cross-sectional view after the third trench T3 is formed. The bottom wall of the third trench T3 exposes the bit line 30, that is, when etching the third trench T3, it stops at the upper surface of the bit line 30 (the surface away from the substrate 1). The third trench T3 can isolate different word lines 40 in the same layer. Fig. 8A As shown, it can be seen that there are two third trenches T3 between adjacent semiconductor pillars 10 in the same column, because there is another row of semiconductor pillars 10 between adjacent semiconductor pillars 10 in the same column, and therefore, two third trenches T3 are required for spacing. When forming the third trenches T3, in addition to etching the second insulating layer 6, the semiconductor pillars 10 formed in step 5 are also etched, so that the width of the semiconductor pillars 10 along the second direction Y is reduced.

[0112] In some embodiments, thinning of the semiconductor pillar 10 to the same width may be performed on both sides of the semiconductor pillar 10 along the second direction Y.

[0113] 7) forming a third insulating layer 7 and a fourth insulating layer 8;

[0114] Depositing a third insulating film in the third trench T3 to form a third insulating layer 7, wherein the third insulating layer 7 covers the inner wall (bottom wall and side wall) of the third trench T3;

[0115] A fourth insulating film is deposited in the third trench T3 where the third insulating layer 7 is formed, so as to form a fourth insulating layer 8 filling the third trench T3. Fig.9A , Fig. 9B , Fig. 9C and Fig.9D As shown, Fig.9A This is a cross-sectional view in the aa' direction after the third insulating layer 7 and the fourth insulating layer 8 are formed. Fig. 9B This is a cross-sectional view in the bb' direction after the third insulating layer 7 and the fourth insulating layer 8 are formed. Fig. 9C This is a cross-sectional view in the cc' direction after the third insulating layer 7 and the fourth insulating layer 8 are formed. Fig.9D It is a cross-sectional view along the dd' direction after the third insulating layer 7 and the fourth insulating layer 8 are formed.

[0116] In some embodiments, the third insulating film may be a low-k material, such as silicon dioxide (SiO 2 ).

[0117] In some embodiments, the fourth insulating film can be a material that has an etching selectivity ratio with the third insulating film, such as SiN, etc. When the channel area 11 is subsequently exposed to form the word line 40, the fourth insulating layer 8 located in the third trench T3 will not be etched away, thereby isolating the word lines 40 of different rows.

[0118] 8) exposing the second region 13;

[0119] Etching the second insulating layer 6 and the third insulating layer 7 to expose the second region 13 of the semiconductor pillar 10;

[0120] A fifth insulating film is deposited on the substrate 1 forming the above structure, and the fifth insulating film is etched to form a fifth insulating layer 9. Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D As shown, Fig. 10A This is a cross-sectional view in the aa' direction after the second region 13 is exposed. Fig. 10B This is a cross-sectional view along the bb' direction after the second region 13 is exposed. Fig. 10C This is a cross-sectional view in the cc' direction after exposing the second region 13. Fig. 10D It is a cross-sectional view in the dd' direction after exposing the second region 13. The fifth insulating layer 9 covers the second region 13 of the semiconductor column 10 so as to protect the second region 13, and the fifth insulating layer 9 is provided with a via K1, and the via K1 exposes the surface of the first insulating layer 2 away from the substrate 1 and the surface of the second insulating layer 6 away from 1, so that the first insulating layer 2 and the second insulating layer 6 are subsequently etched through the via K1, thereby exposing the channel region 11 of the semiconductor column 10.

[0121] In some embodiments, the fifth insulating film may be an insulating material having an etching selectivity ratio with the second insulating film, such as SiN, so as to protect the semiconductor 10 in the second region 13 when the sidewalls of the semiconductor column 10 in the channel region 11 are subsequently exposed.

[0122] In some embodiments, the second insulating layer 6 and the third insulating layer 7 may be etched by wet etching.

[0123] 9) forming a gate insulating layer 24;

[0124] Etching the first insulating layer 2 and the second insulating layer 6 through the via hole K1 to expose the channel region 11 of the semiconductor column 10;

[0125] A gate insulating film is deposited to form a gate insulating layer 24; the gate insulating layer 24 surrounds the sidewall of the semiconductor column 10, covers the channel region 11 of the semiconductor column 10, and covers the surface of the semiconductor column 10 away from the substrate 1. Fig.11A , Fig. 11B , Fig. 11C and Fig.11D As shown, Fig.11A This is a cross-sectional view in the aa' direction after the gate insulating layer 24 is formed. Fig. 11B This is a cross-sectional view in the bb' direction after the gate insulating layer 24 is formed. Fig. 11C This is a cross-sectional view in the cc' direction after the gate insulating layer 24 is formed. Fig.11D It is a cross-sectional view taken along the dd' direction after the gate insulating layer 24 is formed.

[0126] In some embodiments, the gate insulating layer 24 may be formed by atomic layer deposition (ALD) and in-situ steam generation (ISSG) methods.

[0127] In some embodiments, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0128] 10) forming a word line 40;

[0129] The second connection layer film and the second conductive film are sequentially deposited, and the second connection layer film and the second conductive film are etched to the bottom of the second region 13 to form a word line 40 extending along the first direction X, that is, the word line 40 only surrounds the channel region 11 of the semiconductor column 10, as shown in FIG. Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D As shown, Fig. 12A This is a cross-sectional view in the aa' direction after the word line 40 is formed. Fig. 12B This is a cross-sectional view in the bb' direction after the word line 40 is formed. Fig. 12C This is a cc' direction cross-sectional view after the word line 40 is formed. Fig.12D dd' direction cross-sectional view after forming word line 40. Word line 40 may include a second adhesive sublayer formed by a second connecting layer film and a second conductive sublayer formed by a second conductive film. A portion of word line 40 may be used as a gate electrode of a transistor, and the gate electrodes of transistors in the same row are connected to form a word line 40.

[0130] In some embodiments, the second connection layer film may be TiN, for example, to enhance adhesion between the word line 40 and the gate insulating layer 24 .

[0131] 11) forming a sixth insulating layer 14;

[0132] A sixth insulating film is deposited on the substrate 1 forming the aforementioned structure to form a sixth insulating layer 14; the sixth insulating layer 14 fills the via hole K1. Fig.13A , Fig. 13B , Fig. 13C and Fig.13DAs shown, Fig.13A This is a cross-sectional view in the aa' direction after the sixth insulating layer 14 is formed. Fig. 13B This is a cross-sectional view along the bb' direction after the sixth insulating layer 14 is formed. Fig. 13C This is a cc' direction cross-sectional view after the sixth insulating layer 14 is formed. Fig.13D It is a cross-sectional view along the dd' direction after the sixth insulating layer 14 is formed.

[0133] In some embodiments, the sixth insulating film may be made of a low-k material, such as SiN.

[0134] The present disclosure also provides an electronic device, including the semiconductor device of the above embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0135] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A plurality of rows of transistors distributed along a first direction parallel to a substrate, the transistors comprising semiconductor columns extending along a direction perpendicular to the substrate, the semiconductor columns of all odd-numbered rows of transistors forming an array distributed along the first direction and along a second direction parallel to the substrate, the semiconductor columns of all even-numbered rows of transistors forming an array distributed along the first direction and the second direction, and the semiconductor columns of the transistors in the odd-numbered rows are staggered with the semiconductor columns of the transistors in the even-numbered rows in the second direction, and the first direction and the second direction are perpendicular; A plurality of bit lines extend along the second direction, and transistors in the same column are connected to the same bit line.

2. The semiconductor device according to claim 1, wherein: Every two adjacent columns of transistors share one bit line.

3. The semiconductor device according to claim 2, characterized in that Each of the bit lines is arranged between semiconductor pillars of two columns of transistors sharing the bit line.

4. The semiconductor device according to claim 2, characterized in that Along the extension direction of the semiconductor column, the side wall of the semiconductor column includes a first region, a channel region and a second region distributed in sequence, and the first region is arranged on the side of the channel region facing the substrate, and the bit line is connected to the first region of the semiconductor columns of two columns of transistors sharing the bit line.

5. The semiconductor device according to claim 4, characterized in that In two columns of semiconductor columns connected to the same bit line, the side wall of the first region of any column of semiconductor columns facing the other column of semiconductor columns includes a first sub-region extending in a direction perpendicular to the substrate, and a second sub-region extending from the first sub-region in a direction away from the other column of semiconductor columns, and a third sub-region extending from the second sub-region in a direction perpendicular to the substrate, the third sub-region is arranged on a side of the first sub-region away from the substrate, the bit line is connected to the second sub-region and an area of ​​the third sub-region adjacent to the second sub-region, and is not connected to the first sub-region.

6. The semiconductor device according to claim 4, characterized in that The semiconductor device also includes: a plurality of first grooves extending along the second direction, a bit line is arranged in each of the first grooves, two columns of transistors arranged between adjacent first grooves are respectively connected to the bit lines in the adjacent first grooves, and the depth of the first grooves is less than the height of the semiconductor column, and the side walls of the two columns of semiconductor columns adjacent to the first grooves form the bottom wall and side walls of the first groove.

7. The semiconductor device according to claim 1, wherein: A dimension of the bit line along the first direction is smaller than a dimension of the bit line along a direction perpendicular to the substrate.

8. The semiconductor device according to claim 4, characterized in that The orthographic projections of the channel region and the second region on the substrate fall within the orthographic projection of the first region on the substrate.

9. The semiconductor device according to claim 4, characterized in that The transistor further includes: a gate electrode surrounding the channel region, wherein the gate electrodes of transistors in the same row are connected to form a word line extending along a first direction.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The semiconductor device further includes a plurality of node contact electrodes disposed on surfaces of the plurality of semiconductor pillars away from the substrate and respectively connected to the plurality of semiconductor pillars, wherein the arrangement of the plurality of node contact electrodes is consistent with the arrangement of the plurality of transistors.

11. The semiconductor device according to claim 10, characterized in that The semiconductor device also includes a plurality of capacitors arranged on a side of the plurality of node contact electrodes away from the transistor and corresponding to the transistors one by one, one of the capacitors being connected to a surface of a node contact electrode away from the transistor, and an arrangement of the plurality of capacitors being consistent with an arrangement of the plurality of transistors.

12. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, forming a plurality of first trenches extending along a second direction on the substrate, and forming a bit line extending along the second direction in each of the first trenches; A plurality of rows of semiconductor pillars extending in a direction perpendicular to the substrate are formed and distributed along a first direction, and the semiconductor pillars of all odd rows form an array distributed along the first direction and along a second direction, and the semiconductor pillars of all even rows form an array distributed along the first direction and along the second direction, and the semiconductor pillars of odd rows are staggered with the semiconductor pillars of even rows in the second direction; the first trench is arranged between two adjacent columns of semiconductor pillars, and the depth of the first trench is less than the height of the semiconductor pillar.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The semiconductor pillar is formed in the following manner: a mask layer including a plurality of first strip-shaped portions extending along a third direction and a plurality of second strip-shaped portions extending along a fourth direction is formed on the substrate, and the substrate covered by the mask layer is etched to form the semiconductor pillar, wherein the third direction intersects with the first direction and the second direction, the fourth direction intersects with the first direction and the second direction, and the third direction intersects with the fourth direction.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The method further includes: forming a second trench extending along the first direction between adjacent semiconductor pillars, wherein a bottom wall of the second trench exposes the bit line; The semiconductor pillars are exposed in a channel region of the bit line away from the substrate to form a gate electrode surrounding the channel region. The gate electrodes of the semiconductor pillars in the same row are connected to form a word line extending along a first direction.

15. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to any one of claims 1 to 11, or a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 12 to 14.

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