Semiconductor device

Abstract

A semiconductor device includes an active pattern, a gate structure extending in a first direction on the active pattern, a bit line electrically connected to the active pattern and extending in a second direction, a gate contact electrically connected to the gate structure, a dummy line between the gate contact and the bit line, and a dummy dielectric layer at least partially surrounded by the dummy line, wherein the dummy line includes a first dummy line portion between the dummy dielectric layer and the bit line, a second dummy line portion spaced apart from the first dummy line portion, and a plurality of connection portions electrically connecting the first dummy line portion and the second dummy line portion to each other, and wherein the dummy dielectric layer is between the first dummy line portion and the second dummy line portion and between the plurality of connection portions.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a dummy line. Background Art

[0002] Semiconductor devices have attracted attention as desirable elements in the electronics industry due to their characteristics such as compactness, versatility, and / or low manufacturing cost. Semiconductor devices may include semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices having both memory elements and logic elements.

[0003] Recently, due to the high speed and low consumption of electronic products, it may be desirable for semiconductor devices embedded in electronic products to have high operating speed and / or lower operating voltage. However, the increase in the integration of semiconductor devices may lead to a decrease in the electrical performance and yield of semiconductor devices. Therefore, many studies have been conducted to improve the electrical performance and yield of semiconductor devices. Summary of the invention

[0004] Some embodiments of the present disclosure provide semiconductor devices with increased reliability and improved electrical performance.

[0005] According to some embodiments of the present disclosure, a semiconductor device may include: an active pattern, a gate structure extending in a first direction on the active pattern, a bit line electrically connected to the active pattern and extending in a second direction intersecting the first direction, a gate contact electrically connected to the gate structure, a dummy line between the gate contact and the bit line, and a dummy dielectric layer at least partially surrounded by the dummy line, wherein the dummy line includes: a first dummy line portion between the dummy dielectric layer and the bit line, a second dummy line portion spaced apart from the first dummy line portion, and a plurality of connection portions electrically connecting the first dummy line portion and the second dummy line portion to each other, and wherein the dummy dielectric layer is between the first dummy line portion and the second dummy line portion and between the plurality of connection portions.

[0006] According to some embodiments of the present disclosure, a semiconductor device may include: a substrate including a cell area, a peripheral area at least partially surrounding the cell area, and a junction area between the cell area and the peripheral area; an active pattern on the substrate; a gate structure on the active pattern; a bit line electrically connected to the active pattern; a dummy line on the junction area; a first external dummy spacer contacting a first outer side wall of the dummy line; a second external dummy spacer contacting a second outer side wall of the dummy line; and an internal dummy spacer contacting an inner side wall of the dummy line, wherein the internal dummy spacer is between the first external dummy spacer and the second external dummy spacer.

[0007] According to some embodiments of the present disclosure, a semiconductor device may include: a substrate, an active pattern on the substrate, a device isolation layer at least partially surrounding the active pattern, a gate structure extending in a first direction on the active pattern, a dielectric pattern and a dummy dielectric pattern on the gate structure, a bit line extending in a second direction on the dielectric pattern (the second direction intersects the first direction), a gate contact electrically connected to the gate structure, a dummy line on the dummy dielectric pattern and between the gate contact and the bit line, a bit line contact electrically connecting the bit line and the active pattern to each other, a node contact electrically connected to the active pattern, a landing pad electrically connected to the node contact, an internal dummy spacer at least partially surrounded by the dummy line, and a dummy dielectric layer at least partially surrounded by the internal dummy spacer, wherein a bottom surface of the internal dummy spacer contacts a top surface of the dummy dielectric pattern, and wherein the dummy dielectric layer extends into the dummy dielectric pattern and contacts the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A simplified plan view showing a semiconductor device according to some embodiments is shown.

[0009] Figure 1B Show Display Figure 1A Magnified view of section E1.

[0010] Figure 1C Shown along Figure 1B A cross-sectional view taken along line AA'.

[0011] Figure 1D Shown along Figure 1B A cross-sectional view taken along line BB'.

[0012] Figure 1E Shown along Figure 1B A cross-sectional view taken along line CC'.

[0013] Figure 1F Shown along Figure 1B A cross-sectional view taken along line D-D'.

[0014] Figure 1G Show Display Figure 1B Magnified view of section E2.

[0015] Figure 2A , 2B , 2C, 2D, 2E, 3A, 3B, 3C, 3D, 4A, 4B, 4C, 5A, 5B and 5C show the manufacturing method according to Figures 1A to 1G FIG. 1 is a diagram of a method for a semiconductor device.

[0016] Figure 6 An enlarged plan view showing a semiconductor device according to some embodiments is shown.

[0017] Figure 7 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0018] Figure 8 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0019] Fig. 9 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0020] Fig.10 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0021] Fig.11 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0022] Fig.12 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0023] Fig.13 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0024] Fig.14 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown.

[0025] Fig.15 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0026] Hereinafter, a semiconductor device and a method of manufacturing the same according to some embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0027] In order to clarify the present disclosure, parts that are not related to the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are shown excessively for better understanding and ease of description.

[0028] It will be understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, it can be directly on the other element, or an intervening element can also exist. On the contrary, when an element is referred to as "directly on" another element, no intervening element exists. In addition, for ease of description, spatial relationship terms such as "under...", "under...", "lower", "above...", "upper", etc. can be used herein to describe the relationship between an element or feature and another element (s) or feature (s) as shown in the figure. It will be understood that spatial relationship terms are intended to also include different orientations of devices in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, the element described as "under" or "under" another element or feature will be oriented to "above" the other element or feature. Thus, the term "under..." can include both upper and lower orientations. The device can be oriented in another way (rotated 90 degrees or in another orientation), and the spatial relationship descriptors used in this article can be interpreted accordingly.

[0029] In addition, unless explicitly described to the contrary, the word "include" and its variants will be understood to mean including the elements described, but not excluding any additional elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A or B or C) using a non-exclusive logical OR, and should not be interpreted as meaning "at least one A, at least one B and at least one C". As used herein, unless the context clearly indicates otherwise, the singular forms of "one", "an" and "the" are intended to also include plural forms. It will be further understood that when used herein, the terms "include", "include", "contain" and / or "contain" indicate the presence of the features, steps, operations, elements and / or parts described, but do not exclude the presence or addition of one or more additional features, steps, operations, elements, parts and / or their groups. The term "and / or" includes any and all combinations of one or more related listed items. The term "connection" can be used herein to refer to physical and / or electrical connections, and can also refer to direct or indirect physical and / or electrical connections. Components or layers described with reference to “overlapping” in a particular direction may be at least partially obscured from each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0030] Figure 1A A simplified plan view showing a semiconductor device according to some embodiments is shown. Figure 1B Show Display Figure 1A Magnified view of section E1. Figure 1C Shown along Figure 1B A cross-sectional view taken along line AA'. Figure 1D Shown along Figure 1BA cross-sectional view taken along line BB'. Figure 1E Shown along Figure 1B A cross-sectional view taken along line CC'. Figure 1F Shown along Figure 1B A cross-sectional view taken along line D-D'. Figure 1G Show Display Figure 1B Magnified view of section E2.

[0031] refer to Figure 1A , 1B , 1C, 1D, 1E and 1F, the semiconductor device may include a substrate 100. The substrate 100 may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP) or gallium arsenide (GaAs). The substrate 100 may have a plate shape extending along a plane extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other.

[0032] The substrate 100 may include a cell region CR, a peripheral region PR at least partially surrounding the cell region CR, and an interface region IN between the cell region CR and the peripheral region PR. When viewed on a plane defined by a first direction D1 and a second direction D2, the cell region CR, the interface region IN, and the peripheral region PR may be distinguished. The peripheral region PR may be provided thereon with a sense amplifier and a sub word line driver overlapping each other in a third direction D3.

[0033] The substrate 100 may be provided with an active pattern AP thereon. The active pattern AP may overlap the cell region CR and the interface region IN in the third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2. The active pattern AP may extend in a direction intersecting the first direction D1 and the second direction D2. The active pattern AP may be included in the substrate 100. The active pattern AP may be defined as referring to an upper portion of the substrate 100 that protrudes or extends in the third direction D3.

[0034] The device isolation layer 20 may be provided to define the active pattern AP. The active pattern AP may be at least partially surrounded by the device isolation layer 20.

[0035] The dielectric structure 10 may be provided in the substrate 100. The dielectric structure 10 may be provided between the interface region IN and the peripheral region PR. In some embodiments, the dielectric structure 10 and the device isolation layer 20 may be connected to have a single integral structure without a boundary therebetween.

[0036] The device isolation layer 20 may include a dielectric material. For example, the device isolation layer 20 may include one or more of an oxide and a nitride. The dielectric structure 10 may include a first dielectric layer 11, a second dielectric layer 12 on the first dielectric layer 11, and a third dielectric layer 13 on the second dielectric layer 12. For example, the first dielectric layer 11 may include an oxide, the second dielectric layer 12 may include a nitride, and the third dielectric layer 13 may include an oxide.

[0037] A gate structure 150 extending in the first direction D1 may be provided. The gate structures 150 may be spaced apart from each other in the second direction D2. The gate structure 150 may overlap the cell region CR and the interface region IN of the substrate 100 in the third direction D3. The gate structure 150 may be provided on the device isolation layer 20, the dielectric structure 10, and the active pattern AP.

[0038] The gate structure 150 may be a buried gate structure buried in the device isolation layer 20, the dielectric structure 10, and the active pattern AP. The gate structure 150 and the active pattern AP may define a cell transistor.

[0039] The gate structure 150 may include a gate dielectric layer 151 on the active pattern AP, a gate electrode GE on the gate dielectric layer 151, and a gate capping layer 154 on the gate electrode GE. The gate electrode GE may include a first gate conductive layer 152 on the gate dielectric layer 151 and a second gate conductive layer 153 on the first gate conductive layer 152.

[0040] The gate dielectric layer 151 and the gate capping layer 154 may include a dielectric material. For example, the gate dielectric layer 151 may include an oxide, and the gate capping layer 154 may include a nitride.

[0041] The first gate conductive layer 152 and the second gate conductive layer 153 may include a conductive material. For example, the first gate conductive layer 152 may include titanium nitride, and the second gate conductive layer 153 may include polysilicon.

[0042] The dielectric pattern 121 and the dummy dielectric pattern 122 may be provided on the gate capping layer 154 of the gate structure 150. The dielectric pattern 121 may overlap the cell region CR in the third direction D3. The dummy dielectric pattern 122 may overlap the interface region IN in the third direction D3. The dielectric pattern 121 and the dummy dielectric pattern 122 may be located at the same horizontal plane. The dielectric pattern 121 and the dummy dielectric pattern 122 may have their top surfaces located at the same horizontal plane. The dielectric pattern 121 and the dummy dielectric pattern 122 may include a dielectric material. In some embodiments, each of the dielectric pattern 121 and the dummy dielectric pattern 122 may include a plurality of dielectric layers.

[0043] A bit line structure 130 extending in the second direction D2 may be provided. The bit line structure 130 may be arranged in the first direction D1. The bit line structure 130 may overlap the cell region CR of the substrate 100 in the third direction D3. The bit line structure 130 may be provided on the dielectric pattern 121 and the active pattern AP. The bit line structure 130 may contact the top surface of the dielectric pattern 121. The bit line structure 130 may be electrically connected to the active pattern AP.

[0044] The bit line structure 130 may include a bit line contact 131, a bit line BL, a first bit line capping layer 136, a second bit line capping layer 171, a third bit line capping layer 183, and a bit line spacer 137. The bit line BL may include a first conductive layer 132, a second conductive layer 133, and a third conductive layer 134. A bottom surface of the bit line BL may contact a top surface of the dielectric pattern 121.

[0045] The bit line contacts 131 of one bit line structure 130 may be arranged in the second direction D2. The first conductive layer 132 of one bit line structure 130 may be arranged in the second direction D2. The bit line contacts 131 and the first conductive layer 132 of one bit line structure 130 may be alternately arranged along the second direction D2. The bit line contacts 131 may be disposed on the active pattern AP. The bit line contacts 131 may electrically connect the active pattern AP and the bit line BL to each other. The bit line contacts 131 may be disposed between the dielectric patterns 121. The bottom surface of the first conductive layer 132 may contact the top surface of the dielectric pattern 121. The bit line contacts 131 and the first conductive layer 132 may include a conductive material. For example, the bit line contacts 131 and the first conductive layer 132 may include polysilicon. In some embodiments, the bit line contacts 131 and the first conductive layer 132 included in one bit line structure 130 may be connected without any boundaries to have a single integral structure.

[0046] A second conductive layer 133 may be provided on the bit line contact 131 and the first conductive layer 132. A third conductive layer 134 may be provided on the second conductive layer 133. A first bit line capping layer 136 may be provided on the third conductive layer 134. A second bit line capping layer 171 may be provided on the first bit line capping layer 136. A third bit line capping layer 183 may be provided on the second bit line capping layer 171.

[0047] The second conductive layer 133 and the third conductive layer 134 may include conductive materials. For example, the second conductive layer 133 may include polysilicon and the third conductive layer 134 may include metal. The first bit line capping layer 136, the second bit line capping layer 171, and the third bit line capping layer 183 may include dielectric materials.

[0048] The number of conductive layers included in one bit line BL may not be limited to the number shown in the drawings. In some embodiments, the number of conductive layers included in one bit line BL may be equal to or less than 2, or may be equal to or greater than 4. In some embodiments, each of the first bit line capping layer 136, the second bit line capping layer 171, and the third bit line capping layer 183 may include a plurality of dielectric layers.

[0049] The bit line spacer 137 may contact sidewalls of the first bit line capping layer 136, the second bit line capping layer 171, and the third bit line capping layer 183, sidewalls of the first conductive layer 132, the second conductive layer 133, and the third conductive layer 134, and sidewalls of the bit line contact 131. The bit line spacer 137 may include a dielectric material. In some embodiments, the bit line spacer 137 may include a plurality of dielectric layers.

[0050] A dummy line structure 140 may be provided. The dummy line structure 140 may overlap the interface region IN of the substrate 100 in the third direction D3. The dummy line structure 140 may be provided on the dummy dielectric pattern 122. The dummy line structure 140 may contact a top surface of the dummy dielectric pattern 122.

[0051] The dummy line structure 140 may include a dummy line DL, a dummy line capping layer 144, a first outer dummy spacer 145, a second outer dummy spacer 147, and an inner dummy spacer 146. The dummy line DL may include a first dummy conductive layer 141, a second dummy conductive layer 142, and a third dummy conductive layer 143. A bottom surface of the dummy line DL may contact a top surface of the dummy dielectric pattern 122.

[0052] A bottom surface of the first dummy conductive layer 141 may contact a top surface of the dummy dielectric pattern 122. The first dummy conductive layer 141 may include the same conductive material as that of the first conductive layer 132. For example, the first dummy conductive layer 141 may include polysilicon.

[0053] A second dummy conductive layer 142 may be provided on the first dummy conductive layer 141. A third dummy conductive layer 143 may be provided on the second dummy conductive layer 142. A dummy line capping layer 144 may be provided on the third dummy conductive layer 143. The second dummy conductive layer 142 may include a conductive material that is the same as that of the second conductive layer 133. For example, the second dummy conductive layer 142 may include polysilicon. The third dummy conductive layer 143 may include a conductive material that is the same as that of the third conductive layer 134. For example, the third dummy conductive layer 143 may include a metal. The dummy line capping layer 144 may include a dielectric material that is the same as that of the first bit line capping layer 136.

[0054] The number of dummy conductive layers included in the dummy line DL may not be limited to the number shown. In some embodiments, the number of dummy conductive layers included in the dummy line DL may be equal to or less than 2, or may be equal to or greater than 4. In some embodiments, the dummy line capping layer 144 may include a plurality of dielectric layers.

[0055] The bit line BL and the dummy line DL may be located at the same horizontal plane. The bottom surface of the bit line BL may be located at the same horizontal plane as the bottom surface of the dummy line DL. The first conductive layer 132 and the first dummy conductive layer 141 may be located at the same horizontal plane. The second conductive layer 133 and the second dummy conductive layer 142 may be located at the same horizontal plane. The third conductive layer 134 and the third dummy conductive layer 143 may be located at the same horizontal plane.

[0056] The first outer dummy spacer 145 may be adjacent to the bit line BL of the bit line structure 130. The first outer dummy spacer 145 may be in contact with first outer sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143. The first outer sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143 may be adjacent to the bit line BL of the bit line structure 130.

[0057] The second outer dummy spacer 147 may be opposite to the first outer dummy spacer 145. The second outer dummy spacer 147 may contact the second outer sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143. The second outer sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143 may be opposite to the first outer sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143.

[0058] The inner dummy spacer 146 may be at least partially surrounded by the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143. The inner dummy spacer 146 may contact the inner sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143. The inner sidewalls of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143 may be disposed between the first outer sidewall and the second outer sidewall of the first dummy conductive layer 141, the second dummy conductive layer 142, and the third dummy conductive layer 143.

[0059] The first outer dummy spacer 145 , the second outer dummy spacer 147 , and the inner dummy spacer 146 may have bottom surfaces thereof contacting a top surface of the dummy dielectric pattern 122 .

[0060] In some embodiments, each of the first outer dummy spacer 145 , the second outer dummy spacer 147 , and the inner dummy spacer 146 may include a plurality of dielectric layers.

[0061] A node contact NC may be provided. The node contact NC may be provided on the active pattern AP. The node contact NC may be electrically connected to the active pattern AP. The node contact NC may be provided between the bit line structures 130 adjacent to each other along the first direction D1, or between the bit line structure 130 and the dummy line structure 140 adjacent to each other along the first direction D1. The node contact NC may include a conductive material. For example, the node contact NC may include polysilicon.

[0062] A landing pad LP may be provided. The landing pad LP may be provided on the node contact NC. The landing pad LP may be electrically connected to the node contact NC. The landing pad LP may include a conductive material. For example, the landing pad LP may include a metal. In some embodiments, a metal silicide layer may be provided between the node contact NC and the landing pad LP. In some embodiments, a barrier layer may be provided between the node contact NC and the landing pad LP.

[0063] A dielectric spacer 240 may be provided. The dielectric spacer 240 may be provided on the gate capping layer 154 of the gate structure 150. The dielectric spacer 240 may contact the gate capping layer 154 of the gate structure 150. The dielectric spacer 240 may be provided between node contacts NC adjacent to each other along the second direction D2. The dielectric spacer 240 may be provided between the bit line structures 130 adjacent to each other along the first direction D1, or between the bit line structure 130 and the dummy line structure 140 adjacent to each other along the first direction D1. The dielectric spacer 240 may be disposed between the dielectric patterns 121 adjacent to each other along the first direction D1, or between the dielectric pattern 121 and the dummy dielectric pattern 122 adjacent to each other along the first direction D1. The dielectric spacer 240 may include a dielectric material. In some embodiments, the dielectric spacer 240 may include a plurality of dielectric layers.

[0064] A dummy dielectric layer 270 may be provided. The dummy dielectric layer 270 may be at least partially surrounded by the dummy line structure 140 and the dummy dielectric pattern 122. The dummy line DL and the dummy line capping layer 144 may at least partially surround the dummy dielectric layer 270 and the inner dummy spacer 146. The dummy dielectric layer 270 may penetrate the dummy line structure 140 and the dummy dielectric pattern 122 or extend into the dummy line structure 140 and the dummy dielectric pattern 122. The dummy dielectric layers 270 may be spaced apart from each other in the second direction D2. The dummy dielectric layers 270 may include the same dielectric material as the dielectric material of the dielectric barrier 240. In some embodiments, the dummy dielectric layer 270 may include a plurality of dielectric layers.

[0065] The dummy dielectric layer 270 may include a dielectric material different from the dielectric materials of the first outer dummy spacer 145, the second outer dummy spacer 147, and the inner dummy spacer 146. The dummy dielectric layer 270 may be provided on the gate capping layer 154 of the gate structure 150. The dummy dielectric layer 270 may contact the gate capping layer 154 of the gate structure 150. The dummy dielectric layer 270 may overlap the plurality of gate structures 150 in the third direction D3.

[0066] The first separation structure 250 may be provided on the dielectric barrier 240 and the dummy dielectric layer 270. The first separation structure 250 may separate the landing pads LP from each other. The first separation structure 250 may at least partially surround the landing pads LP. The first separation structure 250 may include a dielectric material.

[0067] A data storage pattern DSP may be provided. The data storage pattern DSP may be electrically connected to the active pattern AP through a landing pad LP and a node contact NC. In some embodiments, each data storage pattern DSP may be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device including the data storage pattern DSP may be a dynamic random access memory (DRAM). In some embodiments, each data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device including the data storage pattern DSP may be a magnetic random access memory (MRAM). In some embodiments, the data storage pattern DSP may include a phase change material or a variable resistance material. In this case, the semiconductor device including the data storage pattern DSP may be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM). In some embodiments, each data storage pattern DSP may include various materials and / or structures capable of storing data.

[0068] A peripheral gate structure 160 may be provided, which overlaps the peripheral region PR of the substrate 100 in the third direction D3. In some embodiments, the peripheral gate structure 160 may be a gate of a transistor constituting a sub word line driver.

[0069] The peripheral gate structure 160 may include a peripheral dielectric layer 161, a first peripheral conductive layer 162 on the peripheral dielectric layer 161, a second peripheral conductive layer 163 on the first peripheral conductive layer 162, a third peripheral conductive layer 164 on the second peripheral conductive layer 163, a peripheral cover layer 165 on the third peripheral conductive layer 164, and a peripheral spacer 166. The first peripheral conductive layer 162, the second peripheral conductive layer 163, and the third peripheral conductive layer 164 may include a conductive material. For example, the first peripheral conductive layer 162 and the second peripheral conductive layer 163 may include polysilicon, and the third peripheral conductive layer 164 may include a metal. The peripheral dielectric layer 161, the peripheral cover layer 165, and the peripheral spacer 166 may include a dielectric material.

[0070] The pad 170 may be provided on the dummy line structure 140, the gate structure 150, the dielectric structure 10, and the peripheral gate structure 160. The first filling layer 181 may be provided on the pad 170. The first filling layer 181 may be provided between the dummy line structure 140 and the peripheral gate structure 160. The second filling layer 182 may be provided on the pad 170 and the first filling layer 181. The second filling layer 182 may overlap the dummy line structure 140, the first filling layer 181, and the peripheral gate structure 160 in the third direction D3. The pad 170, the first filling layer 181, and the second filling layer 182 may include a dielectric material. In some embodiments, each of the pad 170, the first filling layer 181, and the second filling layer 182 may include a plurality of dielectric layers.

[0071] Conductive structures 191 may be provided on the second filling layer 182. The conductive structures 191 may include a conductive material. At least one of the conductive structures 191 may include a gate contact 192 electrically connected to the gate electrode GE of the gate structure 150. The gate contact 192 may penetrate the gate capping layer 154 of the gate structure 150 or extend into the gate capping layer 154 of the gate structure 150. The dummy line DL of the dummy line structure 140 may be disposed between the gate contact 192 and the bit line BL of the bit line structure 130.

[0072] A second separation structure 260 may be provided. The second separation structure 260 may separate the conductive structures 191 from each other. The second separation structure 260 may include a dielectric material. In some embodiments, the first separation structure 250 and the second separation structure 260 may be connected to have a single integral structure without any boundaries.

[0073] refer to Figure 1G , the dummy line DL may at least partially surround the dummy dielectric layer 270 and the inner dummy spacer 146. The inner dummy spacer 146 may at least partially surround the dummy dielectric layer 270. The dummy line DL may include a first dummy line portion DL1, a second dummy line portion DL2, and a connecting portion DL3. Each of the first dummy line portion DL1, the second dummy line portion DL2, and the connecting portion DL3 may include a portion of the first dummy conductive layer 141, a portion of the second dummy conductive layer 142, and a portion of the third dummy conductive layer 143. For convenience of description, the dummy line DL is shown to be divided into the first dummy line portion DL1, the second dummy line portion DL2, and the connecting portion DL3, but there may be no physical boundary between the first dummy line portion DL1, the second dummy line portion DL2, and the connecting portion DL3.

[0074] A first dummy line portion DL1 may be provided between a dummy dielectric layer 270 and a bit line BL. The first dummy line portion DL1 may be provided between an inner dummy spacer 146 and the bit line BL. The second dummy line portion DL2 may be spaced apart from the first dummy line portion DL1 in the first direction D1. A dummy dielectric layer 270 and an inner dummy spacer 146 may be provided between the first dummy line portion DL1 and the second dummy line portion DL2.

[0075] The connection portion DL3 may connect the first dummy line portion DL1 and the second dummy line portion DL2 to each other. The width of the connection portion DL3 in the first direction D1 may be greater than the sum of the width of the first dummy line portion DL1 in the first direction D1 and the width of the second dummy line portion DL2 in the first direction D1. Two first dummy line portions DL1 and two second dummy line portions DL2 may be connected to one connection portion DL3. The first dummy line portion DL1 and the connection portion DL3 may be alternately arranged along the second direction D2. The second dummy line portion DL2 and the connection portion DL3 may be alternately arranged along the second direction D2. The dummy dielectric layer 270 and the connection portion DL3 may be alternately arranged along the second direction D2. The internal dummy spacer 146 and the connection portion DL3 may be alternately arranged along the second direction D2.

[0076] The first dummy line portion DL1, the dummy dielectric layer 270, the inner dummy spacer 146, and the second dummy line portion DL2 may be provided between two connection portions DL3 adjacent to each other in the second direction D2. The width of the first dummy line portion DL1 in the first direction D1 may be the same as the width of the bit line BL in the first direction D1. The width of the first dummy line portion DL1 in the first direction D1 may be smaller than the width of the second dummy line portion DL2 in the first direction D1.

[0077] Dielectric Barrier (see Figure 1C or Figure 1D The dielectric spacer 240 may be provided between the first dummy line portion DL1 and the bit line BL. The width of the dielectric spacer 240 in the second direction D2 may be smaller than the width of the dummy dielectric layer 270 in the second direction D2.

[0078] The dummy line DL may include a first outer sidewall, a second outer sidewall opposite to the first outer sidewall, and an inner sidewall. The first outer sidewall of the dummy line DL may be adjacent to the bit line BL. The inner sidewall of the dummy line DL may be disposed between the first and second outer sidewalls of the dummy line DL.

[0079] The first outer dummy spacer 145 may be in contact with a first outer sidewall of the dummy line DL. The second outer dummy spacer 147 may be in contact with a second outer sidewall of the dummy line DL. The inner dummy spacer 146 may be in contact with an inner sidewall of the dummy line DL. The first dummy line portion DL1 may be disposed between the first outer dummy spacer 145 and the inner dummy spacer 146. The second dummy line portion DL2 may be disposed between the second outer dummy spacer 147 and the inner dummy spacer 146. The connection portion DL3 may be disposed between the first outer dummy spacer 145 and the second outer dummy spacer 147.

[0080] The first outer sidewall of the dummy line DL may include an outer sidewall DL1_S1 of the first dummy line portion DL1 and a first outer sidewall DL3_S3 of the connection portion DL3. The outer sidewall DL1_S1 of the first dummy line portion DL1 may be coplanar with the first outer sidewall DL3_S3 of the connection portion DL3. The outer sidewall DL1_S1 of the first dummy line portion DL1 and the first outer sidewall DL3_S3 of the connection portion DL3 may be disposed on a straight line extending in the second direction D2.

[0081] The second outer sidewall of the dummy line DL may include an outer sidewall DL2_S2 of the second dummy line portion DL2 and a second outer sidewall DL3_S4 of the connecting portion DL3. The outer sidewall DL2_S2 of the second dummy line portion DL2 may be coplanar with the second outer sidewall DL3_S4 of the connecting portion DL3. The outer sidewall DL2_S2 of the second dummy line portion DL2 and the second outer sidewall DL3_S4 of the connecting portion DL3 may be disposed on a straight line extending along the second direction D2.

[0082] The inner sidewalls of the dummy line DL may include an inner sidewall DL1_S2 of a first dummy line portion DL1, an inner sidewall DL2_S1 of a second dummy line portion DL2, and first and second inner sidewalls DL3_S1 and DL3_S2 of a connection portion DL3. The inner sidewalls DL1_S2 of the first dummy line portion DL1 and DL2_S1 of the second dummy line portion DL2 may be connected to the first and second inner sidewalls DL3_S1 and DL3_S2 of the connection portion DL3. The inner sidewalls DL1_S2 of the first dummy line portion DL1 and DL2_S1 of the second dummy line portion DL2 may be parallel to the second direction D2. The first and second inner sidewalls DL3_S1 and DL3_S2 of the connection portion DL3 may be parallel to the first direction D1. A length of each of the inner sidewalls DL1_S2 and DL2_S1 of the first and second dummy line portions DL1 and DL2 in the second direction D2 may be greater than a length of each of the first and second inner sidewalls DL3_S1 and DL3_S2 of the connection portion DL3 in the first direction D1.

[0083] The internal dummy spacer 146 may include a first portion extending in the first direction D1 and a second portion extending in the second direction D2. The first portion of the internal dummy spacer 146 may contact one of the first inner sidewall DL3_S1 and the second inner sidewall DL3_S2 of the connection portion DL3. The second portion of the internal dummy spacer 146 may contact one of the inner sidewall DL1_S2 of the first dummy line portion DL1 and the inner sidewall DL2_S1 of the second dummy line portion DL2. The first portions of the internal dummy spacers 146 may be spaced apart from each other in the second direction D2. The second portions of the internal dummy spacers 146 may be spaced apart from each other in the first direction D1. The first portion of the internal dummy spacer 146 may be connected to the second portion of the internal dummy spacer 146. The length of the first portion of the internal dummy spacer 146 in the first direction D1 may be less than the length of the second portion of the internal dummy spacer 146 in the second direction D2.

[0084] Since the semiconductor device according to some embodiments includes the dummy dielectric layer 270 and the inner dummy spacer 146 at least partially surrounded by the dummy line DL, uniformity of the cell region CR and electrical performance of the semiconductor device may be improved.

[0085] Figure 2A , 2B , 2C, 2D, 2E, 3A, 3B, 3C, 3D, 4A, 4B, 4C, 5A, 5B, 5C show the manufacturing method according to Figures 1A to 1G FIG. 1 is a diagram of a method for a semiconductor device. Figure 2B Show Display Figure 2A Magnified view of section E3. Figure 3A and Figure 2A Correspondingly, Figure 2C , Figure 3B , Figure 4A and Figure 5A and Figure 1C Correspondingly, Figure 2D , Figure 3C , Figure 4B and Figure 5B and Figure 1D Correspondingly, Figure 2E , Figure 3D , Figure 4C and Figure 5C and Figure 1E Corresponding.

[0086] refer to Figure 2A , 2B , 2C, 2D and 2E, a substrate 100 including a cell region CR, an interface region IN and a peripheral region PR may be provided. A device isolation layer 20 and a dielectric structure 10 may be formed on the substrate 100. An active pattern AP of the substrate 100 may be formed.

[0087] The gate structure 150 may be formed on the active pattern AP, the dielectric structure 10, and the device isolation layer 20. The preliminary dielectric pattern p121 may be formed on the gate structure 150. The preliminary dielectric pattern p121 may include a dielectric material.

[0088] A first preliminary conductive layer p132 may be formed on the preliminary dielectric pattern p121. Figure 1F 131) may be formed to penetrate the first preliminary conductive layer p132 and the preliminary dielectric pattern p121 or extend into the first preliminary conductive layer p132 and the preliminary dielectric pattern p121. The second preliminary conductive layer p133 may be formed on the first preliminary conductive layer p132. The third preliminary conductive layer p134 may be formed on the second preliminary conductive layer p133. The preliminary covering layer p136 may be formed on the third preliminary conductive layer p134. The first preliminary conductive layer p132 and the second preliminary conductive layer p133 may include a conductive material. For example, the first preliminary conductive layer p132 and the second preliminary conductive layer p133 may include polysilicon. The third preliminary conductive layer p134 may include a conductive material. For example, the third preliminary conductive layer p134 may include a metal. The preliminary covering layer p136 may include a dielectric material.

[0089] The second outer dummy spacer 147 may be formed on the sidewalls of the first preliminary conductive layer p132, the second preliminary conductive layer p133, the third preliminary conductive layer p134, and the preliminary cover layer p136. The peripheral gate structure 160 may be formed to overlap the peripheral region PR in the third direction D3. The preliminary pad p170 may be formed on the peripheral gate structure 160, the preliminary cover layer p136, and the second outer dummy spacer 147. The preliminary pad p170 may include a dielectric material. The first filling layer 181 may be formed between the peripheral gate structure 160 and the second outer dummy spacer 147. The preliminary filling layer p182 may be formed on the preliminary pad p170 and the first filling layer 181. The preliminary filling layer p182 may include a dielectric material.

[0090] The first material layer 193 may be formed on the preliminary filling layer p182. The second material layer 194 may be formed on the first material layer 193. The first material layer 193 and the second material layer 194 may include a dielectric material.

[0091] The first mask line ML1, the second mask line ML2, and the third mask line ML3 may be formed on the second material layer 194. The first mask line ML1, the second mask line ML2, and the third mask line ML3 may extend in the second direction D2. The first mask line ML1, the second mask line ML2, and the third mask line ML3 may be arranged to be spaced apart from each other in the first direction D1. The first mask line ML1, the second mask line ML2, and the third mask line ML3 may include a dielectric material. For example, the first mask line ML1, the second mask line ML2, and the third mask line ML3 may include an oxide.

[0092] The mask layer MA may be formed on the second material layer 194. The mask layer MA may include a photoresist material. The mask layer MA may include a first opening OP1, a second opening OP2, and a third opening OP3. The formation of the mask layer MA may include forming a preliminary mask layer on the second material layer 194, and performing a photolithography process to form the first opening OP1, the second opening OP2, and the third opening OP3 on the preliminary mask layer.

[0093] The first opening OP1 may overlap the cell region CR in the third direction D3. The second opening OP2 and the third opening OP3 may overlap the interface region IN in the third direction D3. The second opening OP2 and the third opening OP3 may be connected to the first opening OP1. The second opening OP2 may be connected to one of the first side and the second side of the first opening OP1. The first side and the second side of the first opening OP1 may be spaced apart from each other in the first direction D1. The third opening OP3 may be connected to one of the third side and the fourth side of the first opening OP1. The third side and the fourth side of the first opening OP1 may be spaced apart from each other in the second direction D2.

[0094] The mask layer MA may include a base BA and a protrusion PT. The base BA may overlap the peripheral region PR and the interface region IN in the third direction D3. Figure 2A The base BA may at least partially surround the interface region IN and the cell region CR when viewed in the plan view shown. The protrusion PT may protrude or extend from the base BA toward the cell region CR. The protrusion PT may overlap the interface region IN in the third direction D3.

[0095] The protrusions PT and the second openings OP2 connected to the first side of the first opening OP1 may be alternately arranged along the second direction D2. The protrusions PT and the third openings OP3 connected to the third side of the first opening OP1 may be alternately arranged along the first direction D1.

[0096] The second mask line ML2 may be disposed between the first mask lines ML1. The first mask line ML1 and the second mask line ML2 may be disposed between the third mask line ML3. The first mask line ML1 may be disposed between the second mask line ML2 and the third mask line ML3.

[0097] The second mask line ML2 may be exposed through the first opening OP1 or through the first opening OP1 and the two third openings OP3. The first mask line ML1 may include a first portion exposed by the second opening OP2 and a second portion covered with or overlapped with the protrusion PT. The first portion and the second portion of the first mask line ML1 may be alternately arranged along the second direction D2. The third mask line ML3 may be covered with or overlapped with the base BA of the mask layer MA.

[0098] refer to Figure 3A , 3B , 3C and 3D, an etching process using the mask layer MA and the first mask line ML1, the second mask line ML2 and the third mask line ML3 may be performed. The etching process may remove the mask layer MA, the first mask line ML1, the second mask line ML2, the third mask line ML3, the first material layer 193 and the second material layer 194.

[0099] The etching process may etch the preliminary filling layer p182, the preliminary pad p170, the preliminary cover layer p136, and the first preliminary conductive layer p132, the second preliminary conductive layer p133, and the third preliminary conductive layer p134. The preliminary filling layer p182 may be etched to separate the preliminary filling layer p182 into the second filling layer 182 and the third bit line cover layer 183. The preliminary pad p170 may be etched to separate the preliminary pad p170 into the second bit line cover layer 171 and the pad 170. The preliminary cover layer p136 may be etched to separate the preliminary cover layer p136 into the first bit line cover layer 136 and the dummy line cover layer 144. The third preliminary conductive layer p134 may be etched to separate the third preliminary conductive layer p134 into the third conductive layer 134 and the third dummy conductive layer 143. The second preliminary conductive layer p133 may be etched to separate the second preliminary conductive layer p133 into the second conductive layer 133 and the second dummy conductive layer 142. The first preliminary conductive layer p132 may be etched to separate the first preliminary conductive layer p132 into the first conductive layer 132 and the first dummy conductive layer 141 .

[0100] The second filling layer 182 may include a first filling portion 182a, a second filling portion 182b, and a third filling portion 182c. The third filling portion 182c may connect the first filling portion 182a and the second filling portion 182b to each other. Two first filling portions 182a and two second filling portions 182b may be connected to one third filling portion 182c. The first filling portion 182a and the third filling portion 182c may be alternately arranged along the second direction D2. The second filling portion 182b and the third filling portion 182c may be alternately arranged along the second direction D2.

[0101] The uppermost portion of the first filling portion 182 a may be located at a level lower than levels of the uppermost portion of the second filling portion 182 b and the uppermost portion of the third filling portion 182 c .

[0102] The fourth opening OP4 and the fifth opening OP5 may be defined. The fourth opening OP4 may be defined between the third bit line cover layers 183 adjacent to each other, or between the third bit line cover layers 183 and the second filling layer 182 adjacent to each other. The fifth opening OP5 may be at least partially surrounded by the second filling layer 182. The fifth opening OP5 may be disposed between the first filling portion 182a and the second filling portion 182b. The fifth opening OP5 may be disposed between the third filling portion 182c. The preliminary dielectric pattern p121 may be exposed through the fourth opening OP4 and the fifth opening OP5.

[0103] refer to Figure 4A , 4B 4C, the bit line spacer 137, the first outer dummy spacer 145, and the inner dummy spacer 146 may be formed. The inner dummy spacer 146 may be formed within the fifth opening OP5.

[0104] The preliminary dielectric pattern p121 may be etched to be separated into the dielectric pattern 121 and the dummy dielectric pattern 122 .

[0105] A sacrificial layer 310 may be formed. The sacrificial layer 310 may be formed on the second filling layer 182, the third bit line capping layer 183, the bit line spacer 137, the first outer dummy spacer 145, and the inner dummy spacer 146. The sacrificial layer 310 may fill the fourth opening OP4 and the fifth opening OP5. The sacrificial layer 310 may include, for example, polysilicon.

[0106] refer to Figure 5A , 5B5C, the upper portion of the sacrificial layer 310 may be removed. For example, the upper portion of the sacrificial layer 310 may be removed by a chemical mechanical polishing (CMP) process. The upper portion of the sacrificial layer 310 may be removed to divide the sacrificial layer 310 into a first sacrificial pattern 311 and a second sacrificial pattern 314. The first sacrificial pattern 311 may be disposed in the fourth opening OP4. The first sacrificial pattern 311 may overlap the cell region CR in the third direction D3. The second sacrificial pattern 314 may be disposed in the fifth opening OP5. The second sacrificial pattern 314 may overlap the interface region IN in the third direction D3. The second sacrificial pattern 314 may be at least partially surrounded by the dummy line DL, the dummy line capping layer 144, the internal dummy spacer 146, and the second filling layer 182.

[0107] The second sacrificial pattern 314 may include an upper portion 313 and a lower portion 312. The upper portion 313 of the second sacrificial pattern 314 may be located at a higher level than that of the first sacrificial pattern 311. The uppermost portion of the second sacrificial pattern 314 may be located at a higher level than that of the uppermost portion of the first sacrificial pattern 311.

[0108] refer to Figure 1A , 1B , 1C, 1D, 1E and 1F, the first sacrificial pattern 311 and the second sacrificial pattern 314 may be removed. The dielectric barrier 240, the dummy dielectric layer 270, the first separation structure 250, the node contact NC, the landing pad LP, the data storage pattern DSP, the conductive structure 191 and the second separation structure 260 may be formed.

[0109] In the method of manufacturing a semiconductor device according to some embodiments, the mask layer MA including the second opening OP2 and the third opening OP3 may be used to perform a cell open process to form a fifth opening OP5 overlapping the interface region IN. Since the fifth opening OP5 is additionally formed, in the process of removing the upper portion of the sacrificial layer 310, the influence due to shielding may act relatively more on the second sacrificial pattern 314 and relatively less on the first sacrificial pattern 311. Therefore, since the first sacrificial pattern 311 has a relatively uniform height, the stability of subsequent processes on the cell region CR may be improved and the uniformity of the cell region CR may also be improved.

[0110] Figure 6 An enlarged plan view showing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Figure 6 The semiconductor device can be similar to Figures 1A to 1G semiconductor devices.

[0111] refer to Figure 6The dummy line DLa may include a first dummy line portion DL1a, a second dummy line portion DL2a, and a connection portion DL3a. A distance between the connection portion DL3a and the bit line BL in the first direction D1 may be smaller than a distance between the first dummy line portion DL1a and the bit line BL1 in the first direction D1.

[0112] A distance between the bit line BL and an outer sidewall DL3 a_S of the connection portion DL3 a in the first direction D1 may be smaller than a distance between the bit line BL and an outer sidewall DL1 a_S of the first dummy line portion DL1 a in the first direction D1 .

[0113] The first outer dummy spacer 145a may include a first portion extending in the second direction D2 and a second portion extending in the first direction D1. The first portion of the first outer dummy spacer 145a may contact the outer sidewall DL3a_S of the connection portion DL3a and the outer sidewall DL1a_S of the first dummy line portion DL1a. The second portion of the first outer dummy spacer 145a may be connected to the first portion of the first outer dummy spacer 145a.

[0114] Figure 7 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Figure 7 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0115] refer to Figure 7 The mask layer MAb may include a first opening OP1b overlapping the cell region CR in the third direction D3, a second opening OP2b connected to one of the first and second sides of the first opening OP1b, and a third opening OP3b connected to one of the third and fourth sides of the first opening OP1b.

[0116] The two second openings OP2b may be connected to each of the first side and the second side of the first opening OP1b. The two third openings OP3b may be connected to each of the third side and the fourth side of the first opening OP1b. The first opening OP1b, the second opening OP2b, and the third opening OP3b may have side walls thereof parallel to the first direction D1 or the second direction D2.

[0117] Figure 8 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Figure 8 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0118] refer to Figure 8The mask layer MAc may include a first opening OP1c overlapping the cell region CR in the third direction D3, a second opening OP2c connected to one of the first and second sides of the first opening OP1c, and a third opening OP3c connected to one of the third and fourth sides of the first opening OP1c.

[0119] One second opening OP2c may be connected to each of the first side and the second side of the first opening OP1c. One third opening OP3c may be connected to each of the third side and the fourth side of the first opening OP1c.

[0120] Fig. 9 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig. 9 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0121] refer to Fig. 9 The mask layer MAd may include a first opening OP1d overlapping the cell region CR in the third direction D3, a second opening OP2d connected to one of the first and second sides of the first opening OP1d, and a third opening OP3d connected to one of the third and fourth sides of the first opening OP1d.

[0122] The four second openings OP2d may be connected to each of the first and second sides of the first opening OP1d. The four third openings OP3d may be connected to each of the third and fourth sides of the first opening OP1d.

[0123] The second opening OP2d may have a curved sidewall. The mask layer MAd may have a curved sidewall defining the second opening OP2d. The third opening OP3d may have a curved sidewall. The mask layer MAd may have a curved sidewall defining the third opening OP3d. The second opening OP2d and the third opening OP3d may have arc-shaped sidewalls thereof.

[0124] Fig.10 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig.10 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0125] refer to Fig.10The mask layer MAe may include a first opening OP1e overlapping the cell region CR in the third direction D3, a second opening OP2e connected to one of the first and second sides of the first opening OP1e, and a third opening OP3e connected to one of the third and fourth sides of the first opening OP1e.

[0126] The two second openings OP2e may be connected to each of the first and second sides of the first opening OP1e. The two third openings OP3e may be connected to each of the third and fourth sides of the first opening OP1e.

[0127] The second opening OP2e may have a curved sidewall. The third opening OP3e may have a curved sidewall.

[0128] Fig.11 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig.11 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0129] refer to Fig.11 The mask layer MAf may include a first opening OP1f overlapping the cell region CR in the third direction D3, a second opening OP2f connected to one of the first and second sides of the first opening OP1f, and a third opening OP3f connected to one of the third and fourth sides of the first opening OP1f.

[0130] One second opening OP2f may be connected to each of the first side and the second side of the first opening OP1f. One third opening OP3f may be connected to each of the third side and the fourth side of the first opening OP1f.

[0131] The second opening OP2f may have a curved sidewall. The third opening OP3f may have a curved sidewall.

[0132] Fig.12 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig.12 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0133] refer to Fig.12 , the mask layer MAg may include a first opening OP1g overlapping the cell region CR in the third direction D3 and a second opening OP2g connected to a corner of the first opening OP1g.

[0134] The first opening OP1g may have a side wall parallel to the first direction D1 or the second direction D2. The second opening OP2g may have a side wall parallel to the fourth direction D4 or the fifth direction D5. The fourth direction D4 may intersect with the first direction D1, the second direction D2, and the third direction D3. For example, the fourth direction D4 may be a horizontal direction intersecting with the first direction D1 and the second direction D2 and perpendicular to the third direction D3. The fifth direction D5 may intersect with the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4. For example, the fifth direction D5 may be a horizontal direction intersecting with the first direction D1 and the second direction D2 and orthogonal to the third direction D3 and the fourth direction D4.

[0135] Since the mask layer MAg includes the second openings OP2g connected to the corners of the first openings OP1g, the influence due to shielding may be concentrated on the corner portions, and thus the uniformity in the cell region CR may be improved.

[0136] Fig.13 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig.13 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0137] refer to Fig.13 , the mask layer MAh may include a first opening OP1h overlapping the cell region CR in the third direction D3, and may further include a second opening OP2h and a third opening OP3h connected to corners of the first opening OP1h.

[0138] The first opening OP1h may have sidewalls parallel to the first direction D1 or the second direction D2. The second opening OP2h and the third opening OP3h may have sidewalls thereof parallel to the fourth direction D4 or the fifth direction D5.

[0139] The second openings OP2h and the third openings OP3h adjacent to each other may be spaced apart from each other in the first direction D1 or the second direction D2. The second openings OP2h adjacent to each other may be spaced apart from each other in the fourth direction D4. The third openings OP3h adjacent to each other may be spaced apart from each other in the fifth direction D5.

[0140] The second opening OP2h may have a size (eg, a planar area) smaller than that of the third opening OP3h.

[0141] Fig.14 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig.14 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5CA method for manufacturing a semiconductor device.

[0142] refer to Fig.14 , the mask layer MAi may include a first opening OP1i overlapping the cell region CR in the third direction D3 and a second opening OP2i connected to a corner of the first opening OP1i.

[0143] The first opening OP1i and the second opening OP2i may have sidewalls thereof parallel to the first direction D1 or the second direction D2.

[0144] Fig.15 A plan view showing a method of manufacturing a semiconductor device according to some embodiments is shown. In addition to the following description, according to Fig.15 The method of manufacturing a semiconductor device can be similar to that according to Figures 2A to 5C A method for manufacturing a semiconductor device.

[0145] refer to Fig.15 , the mask layer MAj may include a first opening OP1 j overlapping the cell region CR in the third direction D3 , and may further include a second opening OP2 j and a third opening OP3 j connected to corners of the first opening OP1 j .

[0146] The first opening OP1 j , the second opening OP2 j , and the third opening OP3 j may have sidewalls thereof parallel to the first direction D1 or the second direction D2 .

[0147] The second openings OP2j and the third openings OP3j adjacent to each other may be spaced apart from each other in the first direction D1 or the second direction D2. The second openings OP2j adjacent to each other may be spaced apart from each other in the fourth direction D4. The third openings OP3j adjacent to each other may be spaced apart from each other in the fifth direction D5.

[0148] The second opening OP2 j may have a size (eg, a planar area) smaller than that of the third opening OP3 j.

[0149] In the semiconductor device according to some embodiments of the present disclosure, since the cell opening process is performed by using a mask layer including openings overlapping the interface region, stability of subsequent processes may be improved and reliability and electrical performance of the semiconductor device may also be enhanced.

[0150] Although the present disclosure has been described in conjunction with some embodiments of the present disclosure shown in the accompanying drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the present disclosure. Thus, the embodiments disclosed above should be considered illustrative rather than restrictive. In addition, some embodiments of the present disclosure may be combined with each other.

[0151] This application claims the priority of Korean Patent Application No. 10-2023-0158123 filed on November 15, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Active pattern; a gate structure extending in a first direction on the active pattern; a bit line electrically connected to the active pattern and extending in a second direction intersecting the first direction; a gate contact electrically connected to the gate structure; a dummy line between the gate contact and the bit line; as well as a dummy dielectric layer at least partially surrounded by the dummy line, The virtual line includes: a first dummy line portion between the dummy dielectric layer and the bit line; a second dummy line portion spaced apart from the first dummy line portion; and a plurality of connection portions electrically connecting the first dummy line portion and the second dummy line portion to each other, and The dummy dielectric layer is between the first dummy line portion and the second dummy line portion and between the plurality of connection portions. 2 . The semiconductor device according to claim 1 , further comprising a dielectric spacer between the first dummy line portion and the bit line, wherein a width of the dielectric spacer in the second direction is smaller than a width of the dummy dielectric layer in the second direction.

3. The semiconductor device according to claim 2, wherein: The gate structure includes a gate electrode layer and a gate capping layer on the gate electrode layer, and The dielectric spacer and the dummy dielectric layer contact the gate capping layer.

4. The semiconductor device according to claim 1, wherein: The gate structure includes a plurality of gate structures, and The dummy dielectric layer overlaps the plurality of gate structures in a third direction intersecting the first direction and the second direction. 5 . The semiconductor device of claim 1 , further comprising a dummy line cover layer on the dummy line, wherein the dummy line cover layer at least partially surrounds the dummy dielectric layer. 6 . The semiconductor device according to claim 1 , wherein a width of the first dummy line portion in the first direction is the same as a width of the bit line in the first direction. 7 . The semiconductor device according to claim 1 , wherein a width of the first dummy line portion in the first direction is smaller than a width of the second dummy line portion in the first direction.

8. A semiconductor device comprising: A substrate comprising a cell region, a peripheral region at least partially surrounding the cell region, and a boundary region between the cell region and the peripheral region; an active pattern on the substrate; a gate structure on the active pattern; a bit line electrically connected to the active pattern; a virtual line on the boundary region; a first outer dummy spacer contacting a first outer sidewall of the dummy line; a second outer dummy spacer contacting a second outer sidewall of the dummy line; as well as an inner dummy spacer contacting an inner sidewall of the dummy line, The inner dummy spacer is between the first outer dummy spacer and the second outer dummy spacer.

9. The semiconductor device according to claim 8, wherein the inner dummy spacer comprises: a plurality of first portions extending in a first direction; as well as a plurality of second portions extending in a second direction intersecting the first direction, wherein the plurality of first portions of the inner dummy spacers are spaced apart from each other in the second direction, wherein the plurality of second portions of the inner dummy spacers are spaced apart from each other in the first direction, and wherein one of the plurality of first portions of the inner dummy spacers contacts a corresponding second portion of the second portions of the inner dummy spacers. 10 . The semiconductor device of claim 9 , wherein a length of each of the first portions of the inner dummy spacers in the first direction is smaller than a length of each of the second portions of the inner dummy spacers in the second direction.

11. The semiconductor device according to claim 8, wherein the dummy line comprises: a first dummy line portion and a second dummy line portion spaced apart from each other; as well as a plurality of connection portions electrically connecting the first dummy line portion and the second dummy line portion to each other, wherein the inner sidewall of the dummy line includes the inner sidewall of the first dummy line portion, the inner sidewall of the second dummy line portion and the inner sidewall of the connecting portion, and wherein the inner dummy spacer contacts the inner sidewall of the first dummy line portion, the inner sidewall of the second dummy line portion, and the inner sidewall of the connecting portion.

12. The semiconductor device according to claim 11, wherein: The first dummy line portion is between the first outer dummy spacer and the inner dummy spacer, The second dummy line portion is between the second outer dummy spacer and the inner dummy spacer, and The plurality of connection portions are between the first outer dummy spacer and the second outer dummy spacer.

13. The semiconductor device according to claim 11, wherein: The first dummy line portion and the second dummy line portion are spaced apart from each other in a first direction, and A sum of a width of the first dummy line portion in the first direction and a width of the second dummy line portion in the first direction is smaller than a width of one of the plurality of connection portions in the first direction. 14 . The semiconductor device according to claim 11 , wherein a distance between the first dummy line portion and the bit line is greater than a distance between the plurality of connection portions and the bit line. 15 . The semiconductor device of claim 8 , further comprising a dummy dielectric layer at least partially surrounded by the inner dummy spacer.

16. The semiconductor device according to claim 15, further comprising a dummy dielectric pattern on the gate structure, wherein: A bottom surface of the dummy line contacts a top surface of the dummy dielectric pattern, and The dummy dielectric layer extends into the dummy dielectric pattern and contacts the gate structure. 17 . The semiconductor device of claim 16 , wherein a bottom surface of the first outer dummy spacer, a bottom surface of the second outer dummy spacer, and a bottom surface of the inner dummy spacer contact the top surface of the dummy dielectric pattern.

18. A semiconductor device comprising: substrate; an active pattern on the substrate; a device isolation layer at least partially surrounding the active pattern; a gate structure extending in a first direction on the active pattern; a dielectric pattern and a dummy dielectric pattern on the gate structure; a bit line extending in a second direction on the dielectric pattern, the second direction intersecting the first direction; a gate contact electrically connected to the gate structure; a dummy line on the dummy dielectric pattern and between the gate contact and the bit line; a bit line contact electrically connecting the bit line and the active pattern to each other; a node contact electrically connected to the active pattern; A landing pad electrically connected to the node contact; an inner dummy spacer at least partially surrounded by the dummy line; as well as a dummy dielectric layer at least partially surrounded by the inner dummy spacer, wherein a bottom surface of the inner dummy spacer contacts a top surface of the dummy dielectric pattern, and The dummy dielectric layer extends into the dummy dielectric pattern and contacts the gate structure. 19 . The semiconductor device of claim 18 , wherein the dummy dielectric pattern at least partially surrounds the dummy dielectric layer. 20 . The semiconductor device of claim 18 , further comprising a dummy line covering layer on the dummy line, wherein the dummy line covering layer at least partially surrounds the dummy dielectric layer and the inner dummy spacer.

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