Semiconductor device

Abstract

A semiconductor device may include: a bit line extending in a first direction on a substrate; a first insulating pattern extending in a second direction on the bit line; a channel pattern contacting sidewalls of the first insulating pattern and the bit line, and including an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; and a landing pad electrically connected to the channel pattern. A second portion of the channel pattern between the gate insulating pattern and the bit line may be thicker than a first portion of the channel pattern that may be between the gate insulating pattern and the first insulating pattern. The second direction may intersect the first direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It may be desirable to increase the integration level of semiconductor memory devices to meet consumer demand for superior performance and low prices. In the case of semiconductor memory devices, it may be particularly desirable to increase the integration level because the integration level may be an important factor in determining the price of the product.

[0003] In the case of a two-dimensional semiconductor memory device, the integration level may be mainly determined by the area occupied by the unit memory cell, and therefore may be greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment may be required to form fine patterns, the integration level of two-dimensional semiconductor memory devices is increasing, but may still be limited. Therefore, a semiconductor memory device including a vertical channel transistor has been proposed, in which the channel extends in the vertical direction. Summary of the invention

[0004] The present disclosure relates to a semiconductor device having improved electrical characteristics by reducing contact resistance at an interface between a bit line and a channel pattern.

[0005] According to example embodiments, a semiconductor device may include: a substrate; a bit line extending on the substrate and in a first direction; a first insulating pattern extending on the bit line and in a second direction, the second direction intersecting the first direction; a channel pattern contacting a sidewall of the first insulating pattern and the bit line, the channel pattern including an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; and a landing pad electrically connected to the channel pattern. The channel pattern may include a first portion and a second portion. The first portion of the channel pattern may be between the gate insulating pattern and the first insulating pattern. The second portion of the channel pattern may be between the gate insulating pattern and the bit line. The thickness of the second portion of the channel pattern may be thicker than the thickness of the first portion of the channel pattern.

[0006] According to example embodiments, a semiconductor device may include: a substrate; a bit line extending in a first direction on the substrate; a first insulating pattern extending in a second direction on the bit line, the second direction intersecting the first direction; a channel pattern on an upper surface of the bit line and a sidewall of the first insulating pattern, the channel pattern including an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; and a landing pad electrically connected to the channel pattern. The channel pattern may include a first channel pattern and a second channel pattern. The first channel pattern may be between the bit line and the first insulating pattern, and the second channel pattern may be on an upper surface of the first channel pattern and a sidewall of the first insulating pattern.

[0007] According to example embodiments, a semiconductor device may include: a substrate; a bit line extending in a first direction on the substrate; a first insulating pattern extending in a second direction on the bit line, the second direction intersecting the first direction; a channel pattern on an upper surface of the bit line and a sidewall of the first insulating pattern, the channel pattern including an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; and a landing pad electrically connected to the channel pattern. The channel pattern may include a first channel pattern and a second channel pattern. The first channel pattern may extend from an upper surface of the bit line to a sidewall of the first insulating pattern. The second channel pattern may be between the first channel pattern and the gate insulating pattern.

[0008] According to embodiments, electrical characteristics of a semiconductor device may be improved by reducing contact resistance at an interface between a bit line and a channel pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a layout diagram for describing a semiconductor device according to some embodiments.

[0010] Figure 2A is taken along the lines A-A' and B-B' Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 2B is taken along the lines A-A' and B-B' Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 3 yes Figure 2A and Figure 2B Magnified view of P1 in Figure 2.

[0013] Figure 4 is based on Figure 1The implementation method is along the following Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0014] Figure 5 yes Figure 4 A magnified view of P2 in Figure 2.

[0015] Figures 6 to 23 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0016] Figures 24 to 41 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0017] The present disclosure will be described in detail below with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0018] The drawings and description are illustrative in nature and not restrictive. Throughout the specification, the same reference numerals refer to the same elements.

[0019] For better understanding and ease of description, the sizes and thicknesses of the components in the drawings are arbitrarily illustrated, and the following embodiments are not limited thereto. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for ease of description.

[0020] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, when an element is referred to as being "on" or "above" a reference element, it can be located above or below the reference element, and is not necessarily referred to as being "on" or "above" in a direction opposite to gravity. The concept of elements being "substantially the same" can mean that the elements can be exactly the same, and can also mean that the elements can be determined to be the same taking into account errors or deviations that occur during the process.

[0021] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0022] Furthermore, the phrase "in plane" refers to a view from a position above an object (eg, from the top), and the phrase "in section" refers to a view of a section of an object cut vertically from the side.

[0023] In the following, reference will be made to Figures 1 to 3A semiconductor device according to an embodiment is described as follows.

[0024] Figure 1 is a layout diagram for describing a semiconductor device according to some embodiments. Figure 2A is taken along the lines A-A' and B-B' Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 2B is taken along the lines A-A' and B-B' Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 3 yes Figure 2A and Figure 2B Magnified view of P1 in Figure 2.

[0025] Reference Figures 1 to 3 , the semiconductor device 100 according to the embodiment may include a peripheral circuit structure PS and a cell array structure CS located on the peripheral circuit structure PS.

[0026] The peripheral circuit structure PS may include a substrate 100 and a core and peripheral circuit SA integrated on an upper surface of the substrate 100. The substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but is not limited thereto. For example, the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor on insulator (SOI) substrate. Hereinafter, the substrate 100 will be described as a silicon substrate.

[0027] The core and peripheral circuit SA may include NMOS and PMOS transistors integrated on the substrate 100. The core and peripheral circuit SA may be electrically connected to the bit line BL through a peripheral circuit conductive line and a peripheral circuit contact plug. That is, the sense amplifier may be electrically connected to the bit line BL, and each sense amplifier may amplify and output a difference in voltage levels detected by a pair of bit lines BL.

[0028] The cell array structure CS may include a memory cell including a vertical channel transistor VCT. The vertical channel transistor may refer to a structure in which a channel length extends in a direction perpendicular to an upper surface of the substrate 100.

[0029] In an implementation, the cell array structure CS may include a lower insulating layer 110, a bit line BL, a first insulating pattern 120, a channel pattern CP, word lines WL1 and WL2, a gate insulating pattern Gox, a second insulating pattern 130, a third insulating pattern 140, a landing pad LP, an interlayer insulating layer 150, and a data storage pattern DSP.

[0030] The lower insulating layer 110 may cover the core and peripheral circuit SA, the peripheral circuit wires, and the peripheral circuit contact plugs on the substrate 100. The lower insulating layer 110 may include a plurality of stacked insulating layers. For example, the lower insulating layer 110 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0031] The bit lines BL may be located on the substrate 100. For example, the lower insulating layer 110 may be located on the substrate 100, and the bit lines BL may be located on the lower insulating layer 110. The bit lines BL extend along a first direction (Y direction) and may be arranged to be spaced apart in a second direction (X direction) intersecting the first direction (Y direction). For example, the second direction (X direction) may be perpendicular to the first direction (Y direction). The lower insulating layer 110 may be positioned to fill the space between the bit lines BL. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL may be located at substantially the same level.

[0032] The bit line BL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line BL may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. The bit line BL may include a single layer or multiple layers of the above materials.

[0033] In some embodiments, the bit line BL may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or a combination thereof.

[0034] According to an embodiment, the first insulating pattern 120 may be located on the bit line BL and may extend in the second direction (X direction). The first insulating pattern 120 may be arranged to intersect the bit line BL. The first insulating pattern 120 may be spaced apart along the first direction (Y direction). Since the first insulating pattern 120 is spaced apart along the first direction (Y direction), a channel trench TRC may be formed. Like the first insulating pattern 120, the channel trench TRC extends in the second direction (X direction) and may be arranged to be spaced apart along the first direction (Y direction).

[0035] The first insulating pattern 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low-k material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0036] The low-k material may include, for example, at least one of the following: flowable oxide (FOX), ton-sulphid (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material, or a combination thereof, but is not limited thereto.

[0037] According to an embodiment, the first insulating pattern 120 may be positioned spaced apart from the bit line BL. The first insulating pattern 120 may be spaced apart from the bit line BL by the channel pattern CP.

[0038] According to an embodiment, the channel pattern CP may include a first channel pattern CP1 and a second channel pattern CP2 located on the first channel pattern CP1. The channel pattern CP may be located on the bit line BL. The channel pattern CP may include a first source / drain region and a second source / drain region. For example, a lower portion of the channel pattern CP may be connected to the bit line BL to serve as a first source / drain region, and an upper portion of the channel pattern CP may be connected to a landing pad LP to serve as a second source / drain region. And a portion of the channel pattern CP between the first source / drain region and the second source / drain region may serve as a channel region.

[0039] According to an embodiment, the first channel pattern CP1 may be directly above the bit line BL. The first channel pattern CP1 may be in contact with the bit line BL.

[0040] according to Figure 2A In the embodiment shown, the first channel pattern CP1 may include a portion extending along the first direction (Y direction). The portion of the first channel pattern CP1 extending along the first direction (Y direction) may be spaced apart along the second direction (X direction). The first channel pattern CP1 may include a portion extending along the second direction (X direction) across the bit line BL. The portion of the first channel pattern CP1 extending along the second direction (X direction) may be spaced apart along the first direction (Y direction). The first channel pattern CP1 may have a mesh shape.

[0041] according to Figure 2B In the embodiment shown, the first channel patterns CP1 may extend along the first direction (Y direction). The first channel patterns CP1 may be spaced apart along the second direction (X direction). Each first channel pattern CP1 may have a line shape. That is, Figure 2B In the embodiment shown, different from Figure 2AIn the illustrated embodiment, the first channel pattern CP1 extends only in the Y direction along the bit line BL, but not in the X direction. Figure 2B The embodiment shown in Figure 2A The embodiment shown in FIG. 1 is different only in the shape and structure of the first channel pattern CP1, while other components are the same. Figure 2A The embodiment shown in the figure is described, but the content described below can also be applied to Figure 2B The embodiment shown.

[0042] According to an embodiment, the first channel pattern CP1 may be located between the bit line BL and the first insulating pattern 120. According to an embodiment, the first insulating pattern 120 may be located on the first channel pattern CP1. The first insulating pattern 120 may be located on a portion of the first channel pattern CP1 extending in the second direction (X direction).

[0043] According to an embodiment, the second channel pattern CP2 may be located on the sidewalls of the first insulating pattern 120 and the first channel pattern CP1. The second channel pattern CP2 may be located in the channel groove TRC. The second channel pattern CP2 may cover the bottom surface and sidewalls of the channel groove TRC. The bottom surface of the channel groove TRC may be defined as the upper surface of the first channel pattern CP1. The sidewalls of the channel groove TRC may be defined as the sidewalls of the first insulating pattern 120. The second channel pattern CP2 may cover the upper surface of the first channel pattern CP1 and the sidewalls of the first insulating pattern 120. Therefore, the second channel pattern CP2 may have a "U" shape in a cross section taken along the Y direction and the Z direction.

[0044] According to an embodiment, the second channel pattern CP2 may be positioned close to the sidewall of the first insulating pattern 120. The second channel pattern CP2 may extend along the sidewall of the first insulating pattern 120. The second channel pattern CP2 may contact the sidewall of the first insulating pattern 120. In some embodiments, although not shown, the second channel pattern CP2 may be above the first insulating pattern 120.

[0045] According to an embodiment, the second channel pattern CP2 may have a conformal shape. The second channel pattern CP2 may cover an upper surface of the first channel pattern CP1 and a sidewall of the first insulating pattern 120 with a certain thickness.

[0046] An upper surface of the second channel pattern CP2 adjacent to the sidewall of the first insulation pattern 120 may be located at a lower level than that of the first insulation pattern 120. An upper surface of the second channel pattern CP2 adjacent to the sidewall of the first insulation pattern 120 may contact a landing pad LP, which will be described later.

[0047] The second channel patterns CP2 may be arranged to be spaced apart along the first direction (Y direction) in the channel trench TRC. Second and third insulation patterns 130 and 140 to be described later may be located between the second channel patterns CP2 adjacent in the first direction (Y direction).

[0048] According to an embodiment, the first channel pattern CP1 and the second channel pattern CP2 may include an oxide semiconductor material. The oxide semiconductor material may be a combination of at least two of In, Ga, Zn, Al, Sn, and Hf, but is not limited thereto. The oxide semiconductor material may further include a material such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn added to the above components.

[0049] For example, the first channel pattern CP1 and the second channel pattern CP2 may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), indium gallium oxide (IGO), or a combination thereof. However, not limited thereto, the oxide semiconductor material included in the first channel pattern CP1 and the second channel pattern CP2 may be changed in various ways.

[0050] According to an embodiment, the first channel pattern CP1 and the second channel pattern CP2 may include different oxide semiconductor materials. For example, the second channel pattern CP2 may include IGZO, and the first channel pattern CP1 may not include at least one of indium oxide, zinc oxide, and gallium oxide, or may further include other oxides. Alternatively, the oxide semiconductor material of the first channel pattern CP1 and the oxide semiconductor material of the second channel pattern CP2 may have the same composition but different composition ratios. For example, when the first channel pattern CP1 and the second channel pattern CP2 include IGZO, the composition ratio of indium, gallium, zinc, and oxygen of the first channel pattern CP1 may be different from the composition ratio of indium, gallium, zinc, and oxygen of the second channel pattern CP2.

[0051] According to an embodiment, the first channel pattern CP1 may include an oxide semiconductor material having an indium composition ratio higher than the indium composition ratio of the material of the second channel pattern CP2. As the composition ratio of indium increases, the contact resistance may be improved (reduced). According to an embodiment, the second channel pattern CP2 may include an oxide semiconductor material having a gallium composition ratio higher than the gallium composition ratio of the material of the first channel pattern CP1. The higher the gallium composition ratio, the better the reliability. Here, improving reliability may mean reducing the film quality variation that occurs when the semiconductor device is working.

[0052] According to an embodiment, the first channel pattern CP1 may be formed by patterning an oxide semiconductor material layer deposited by a physical vapor deposition (PVD) process. According to an embodiment, the second channel pattern CP2 may be formed by patterning an oxide semiconductor material layer deposited by an atomic layer deposition (ALD) process.

[0053] In the ALD process, O 3 As a reactant, it is injected together with the precursor. Therefore, when the oxide semiconductor material layer is deposited on the metal layer using the ALD process, metal oxide is generated at the interface between the metal layer and the oxide semiconductor material layer, which may adversely affect the contact characteristics between the metal layer and the oxide semiconductor material layer. For example, the contact resistance between the metal layer and the oxide semiconductor material layer may increase, or the metal layer and the oxide semiconductor material layer may not be properly connected.

[0054] Since the above embodiment uses a PVD process when depositing an oxide semiconductor material layer to form the first channel pattern CP1 on the bit line BL corresponding to the metal layer, the contact characteristics between the bit line BL and the first channel pattern CP1 can be improved by reducing oxidation of the interface between the bit line BL and the first channel pattern CP1.

[0055] Meanwhile, the ALD process has higher step coverage compared to the PVD process, and thus the ALD process may be used to deposit an oxide semiconductor material layer to form the second channel pattern CP2 covering the sidewalls and bottom surfaces of the channel trench TRC.

[0056] According to the above description, the channel pattern CP may cover the sidewalls of the first insulating pattern 120 and the upper surface of the bit line BL. Specifically, the first channel pattern CP1 may cover the top surface of the bit line BL, and the second channel pattern CP2 may cover the sidewalls of the first insulating pattern 120 and the upper surface of the bit line BL located between the first insulating patterns 120 adjacent to each other along the first direction (Y direction).

[0057] Reference Figure 3, the channel pattern CP may include a first portion CP_R1 between the gate insulating pattern Gox and the first insulating pattern 120 and a second portion CP_R2 between the gate insulating pattern Gox and the bit line BL. The first portion CP_R1 may include a portion of the second channel pattern CP2, and the second portion CP_R2 may include a portion of the first channel pattern CP1 and a portion of the second channel pattern CP2. The thickness of the second portion CP_R2 may be thicker than that of the first portion CP_R1.

[0058] The word lines WL1 and WL2 may extend across the bit lines BL in the second direction (X direction) and may be disposed to be spaced apart along the first direction (Y direction). The word lines WL1 and WL2 may be spaced apart from the bit lines BL in the third direction (Z direction).

[0059] A pair of word lines WL1 and WL2 may be located between the second channel pattern CP2 in the channel trench TRC. A pair of word lines WL1 and WL2 may be located between the second channel pattern CP2 covering both sidewalls of the channel trench TRC. Each of the word lines WL1 and WL2 includes one surface and another surface that is an opposite surface to the one surface, and a pair of word lines WL1 and WL2 located in the channel trench TRC may be disposed so that each of their one surfaces faces each other.

[0060] According to an embodiment, the word lines WL1 and WL2 may be spaced apart from the channel pattern CP. The word lines WL1 and WL2 may be spaced apart from the channel pattern CP by a gate insulating pattern Gox, which will be described later.

[0061] The word lines WL1 and WL2 may include upper and lower surfaces facing each other in a third direction (Z direction). The lower surfaces of the word lines WL1 and WL2 may face the bit line BL with the gate insulation pattern Gox and the channel pattern CP interposed therebetween. The upper surfaces of the word lines WL1 and WL2 may face the landing pad LP with the second insulation pattern 130 and the third insulation pattern 140 (to be described later) interposed therebetween.

[0062] The upper surfaces of the word lines WL1 and WL2 are illustrated as being located at a higher level than an upper surface of the second channel pattern CP2 adjacent to the sidewalls of the first insulating pattern 120 , but example embodiments are not limited thereto and the upper surfaces of the word lines WL1 and WL2 may be located at substantially the same level or lower.

[0063] The word lines WL1 and WL2 may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The word lines WL1 and WL2 may be made of, for example, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but are not limited thereto.

[0064] The word lines WL1 and WL2 may include a single layer or multiple layers of the above materials. In some embodiments, the word lines WL1 and WL2 may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or a combination thereof.

[0065] The gate insulating pattern Gox may be located between the channel pattern CP and the word lines WL1 and WL2. The gate insulating pattern Gox may be located on the second channel pattern CP2 in the channel trench TRC. The gate insulating pattern Gox may conformally cover two sidewalls of the second channel pattern CP2 facing each other in the channel trench TRC and an upper surface of the second channel pattern CP2 located between the facing two sidewalls of the second channel pattern CP2.

[0066] The gate insulating pattern Gox covering the sidewall of the second channel pattern CP2 may further extend in the third direction (Z direction). The gate insulating pattern Gox is shown as extending to substantially the same level as the upper surface of the first insulating pattern 120, but is not limited thereto. For example, the top surface of the gate insulating pattern Gox may be located at a level lower than the upper surface of the first insulating pattern 120. The top surface of the gate insulating pattern Gox may be located at a level substantially equal to or higher than the upper surfaces of the word lines WL1 and WL2.

[0067] According to an embodiment, the gate insulating pattern Gox may overlap the first channel pattern CP1 and the second channel pattern CP2 in the third direction (Z direction), and may overlap the second channel pattern CP2 in the first direction (Y direction). A portion of the gate insulating pattern Gox that does not overlap the second channel pattern CP2 may contact a landing pad LP, which will be described later.

[0068] The gate insulating pattern Gox may include one surface in contact with the second channel pattern CP2 and another surface opposite to the one surface. The other surface of the gate insulating pattern Gox may be in contact with the word lines WL1 and WL2 and the second insulating pattern 130, which will be described later. The other surface of the gate insulating pattern Gox may be in contact with the lower surfaces of the word lines WL1 and WL2 and the surface facing the second channel pattern CP2. A portion of the other surface of the gate insulating pattern Gox that is not in contact with the word lines WL1 and WL2 may be in contact with the second insulating pattern 130.

[0069] The gate insulating pattern Gox may include silicon oxide, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. The high dielectric constant material may include metal oxide or metal nitride. The high dielectric constant material may include, for example, HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 However, not limited thereto, the material included in the gate insulating pattern Gox may be changed in various ways.

[0070] The second and third insulating patterns 130 and 140 may be located in the channel trenches TRC. The second and third insulating patterns 130 and 140 may be located on the word lines WL1 and WL2 and the gate insulating pattern Gox.

[0071] The second insulating pattern 130 may contact the word lines WL1 and WL2 and the gate insulating pattern Gox. The second insulating pattern 130 may conformally cover the word lines WL1 and WL2 and the gate insulating pattern Gox. The second insulating pattern 130 may cover the upper surfaces of the word lines WL1 and WL2 located in the channel trench TRC and the sidewalls facing each other. The second insulating pattern 130 may cover the portion of the gate insulating pattern Gox that is not covered by the word lines WL1 and WL2 in the channel trench TRC. The second insulating pattern 130 may cover the upper surface of the gate insulating pattern Gox located between the word lines WL1 and WL2. The second insulating pattern 130 may cover the sidewall of the gate insulating pattern Gox that protrudes more in the third direction (Z direction) than the upper surfaces of the word lines WL1 and WL2.

[0072] The third insulating pattern 140 may be located on the second insulating pattern 130. The third insulating pattern 140 may be spaced apart from the word lines WL1 and WL2 and the gate insulating pattern Gox by the second insulating pattern 130. That is, the second insulating pattern 130 may be located between the word lines WL1 and WL2 and the third insulating pattern 140 and between the gate insulating pattern Gox and the third insulating pattern 140. After forming the second channel pattern CP2, the gate insulating pattern Gox, the word lines WL1 and WL2, and the second insulating pattern 130, the third insulating pattern 140 may fill the remaining channel trench TRC.

[0073] The third insulating pattern 140 may include a vertical portion located between the word lines WL1 and WL2 and a horizontal portion located above the upper surfaces of the word lines WL1 and WL2. Therefore, the third insulating pattern 140 may have a "T" shape in a cross section taken along the Y direction and the Z direction. The vertical portion of the third insulating pattern 140 may extend from the horizontal portion of the third insulating pattern 140 toward the bit line BL in the third direction (Z direction). The vertical portion of the third insulating pattern 140 may be closer to the bit line BL than the horizontal portion of the third insulating pattern 140. In a cross section along the Y direction and the Z direction, the horizontal portion of the third insulating pattern 140 may have a greater width (Y direction width) than the vertical portion of the third insulating pattern 140.

[0074] The second insulating pattern 130 and the third insulating pattern 140 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low-k material having a dielectric constant smaller than silicon oxide, but are not limited thereto. The second insulating pattern 130 and the third insulating pattern 140 may include different materials. For example, the second insulating pattern 130 may include silicon nitride, and the third insulating pattern 140 may include silicon oxide.

[0075] If the second and third insulating patterns 130 and 140 include different materials, they may be sequentially formed, but if the second and third insulating patterns 130 and 140 include the same material, they may be integrally formed.

[0076] The landing pads LP may be arranged to overlap at least a portion of the channel pattern CP in the third direction (Z direction). The landing pads LP may be arranged to be spaced apart from each other in the first direction (Y direction) and the second direction (X direction). The landing pads LP may be arranged in a matrix form, but this is only an example and is not limited thereto. The landing pads LP may be arranged in various shapes, such as a honeycomb shape.

[0077] In addition, the landing pad LP may have a circular, oval, rectangular, square, diamond, or hexagonal shape in a plane, but the plane shape of the landing pad LP is not limited thereto.

[0078] The landing pad LP may be electrically connected to the channel pattern CP. The landing pad LP may contact at least a portion of the channel pattern CP. In some embodiments, the landing pad LP may be located between the first insulating pattern 120 and the gate insulating pattern Gox.

[0079] The landing pad LP may include a first portion LP1 extending in a first direction (Y direction) and a second portion LP2 extending from the first portion LP1 in a third direction (Z direction). The first portion LP1 of the landing pad LP may be located on an upper surface of the gate insulation pattern Gox, an upper surface of the second insulation pattern 130, and an upper surface of the third insulation pattern 140. The lower surface of the first portion LP1 of the landing pad LP is shown to be located at substantially the same level as the upper surfaces of the first insulation pattern 120 and the third insulation pattern 140, but is not limited thereto. For example, the lower surface of the first portion LP1 of the landing pad LP may be located at a lower level than the upper surfaces of the first insulation pattern 120 and the third insulation pattern 140.

[0080] The second portion LP2 of the landing pad LP extends from the first portion LP1 toward the bit line BL in the third direction (Z direction) and may contact the upper surface of the second channel pattern CP2. Therefore, the landing pad LP may be electrically connected to the second channel pattern CP2 and may be electrically connected to the first channel pattern CP1 through the second channel pattern CP2.

[0081] One side of the second portion LP2 of the landing pad LP may be in contact with the first insulating pattern 120, and the other side opposite to the one side of the second portion LP2 of the landing pad LP may be in contact with the gate insulating pattern Gox. The lower surface of the second portion LP2 of the landing pad LP may be located at a level lower than the upper surfaces of the word lines WL1 and WL2, but is not limited thereto. For example, the lower surface of the second portion LP2 of the landing pad LP may be located at a level substantially equal to or higher than the upper surfaces of the word lines WL1 and WL2.

[0082] The landing pad LP may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the landing pad LP may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0083] The interlayer insulating layer 150 may fill the space between the landing pads LP disposed to be spaced apart in the first direction (Y direction) on the first insulating pattern 120 and the third insulating pattern 140. For example, a lower surface of the interlayer insulating layer 150 may be located at substantially the same level as a lower surface of the first portion LP1 of the landing pad LP, but is not limited thereto.

[0084] The data storage patterns DSP may be respectively disposed on the landing pads LP. The data storage patterns DSP may be respectively electrically connected to the channel patterns CP through the landing pads LP. Figure 1 As shown, the data storage patterns DSP may be arranged in a matrix form along a first direction (Y direction) and a second direction (X direction).

[0085] In an embodiment, the data storage pattern DSP may be a capacitor and may include a lower electrode and an upper electrode and a capacitor dielectric layer interposed therebetween. When the data storage pattern DSP is a capacitor, the lower electrode may contact the landing pad LP, and the lower electrode may have various shapes on a plane, such as a circle, an ellipse, a rectangle, a square, a rhombus, and a hexagon.

[0086] In contrast, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the storage element. For example, the data storage pattern DSP may include a phase change material in which a crystal state changes according to an amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0087] The channel pattern CP of the semiconductor device according to the embodiment includes a first channel pattern CP1 formed by patterning an oxide semiconductor material layer deposited on the bit line BL using a PVD process and a second channel pattern CP2 formed by patterning an oxide semiconductor material layer deposited in the channel trench TRC using an ALD process. Therefore, the thickness of the second portion CP_R2 of the channel pattern CP located between the gate insulating pattern Gox and the bit line BL may be thicker than the thickness of the first portion CP_R1 of the channel pattern CP located between the gate insulating pattern Gox and the first insulating pattern 120. In addition, the first channel pattern CP1 may be located between the bit line BL and the first insulating pattern 120. Since the first channel pattern CP1 located directly above the bit line BL is formed using the PVD process, oxidation of the interface between the bit line BL and the first channel pattern CP1 may be reduced, and contact between the bit line BL and the first channel pattern CP may be improved.

[0088] In the following, reference will be made to Figure 1 , Figure 4 and Figure 5Another embodiment of a semiconductor device is described. In the following embodiment, the same components as those in the above-described embodiment will be denoted by the same reference numerals, and redundant description will be omitted or simplified, with the focus on explaining the differences.

[0089] Figure 4 is based on Figure 1 The implementation method is along the following Figure 1 A cross-sectional view taken along lines AA' and BB'. Figure 5 yes Figure 4 A magnified view of P2 in Figure 2.

[0090] Reference Figure 4 and Figure 5 ,and Figure 2A , Figure 2B and Figure 3 Similar to the illustrated embodiment, the first insulating pattern 120 may be located on the bit line BL, and the channel pattern CP may be located on the sidewalls of the first insulating pattern 120 and the bit line BL. Since the first insulating pattern 120 is spaced apart along the first direction (Y direction), the channel trench TRC may be formed.

[0091] However, according to Figure 4 and Figure 5 The embodiment shown, with Figure 2A , Figure 2B and Figure 3 Unlike the illustrated embodiment, the first insulating pattern 120 may be directly located above the bit line BL, and the first channel pattern CP1 may not be located between the bit line BL and the first insulating pattern 120 .

[0092] according to Figure 4 and Figure 5 In the embodiment shown, the bottom surface of the channel trench TRC may be defined as the upper surface of the bit line BL, and the side surface of the channel trench TRC may be defined as the sidewall of the first insulating pattern 120. The channel pattern CP may be located in the channel trench TRC. The channel pattern CP may be located on the upper surface of the bit line BL and the sidewall of the first insulating pattern 120. The channel pattern CP may contact the sidewall of the first insulating pattern 120 and the upper surface of the bit line BL.

[0093] according to Figure 4 and Figure 5 The embodiment shown, with Figure 2A , Figure 2B and Figure 3Unlike the illustrated embodiment, the channel pattern CP may include a first channel pattern CP1 directly above the upper surface of the bit line BL and on the sidewall of the first insulating pattern 120, and a second channel pattern CP2 on the first channel pattern CP1. The first channel pattern CP1 may contact the upper surface of the bit line BL and the sidewall of the first insulating pattern 120. The second channel pattern CP2 may be spaced apart from the upper surface of the bit line BL and the sidewall of the first insulating pattern 120 by the first channel pattern CP1. The first channel pattern CP1 may be located between the bit line BL and the second channel pattern CP2 and between the first insulating pattern 120 and the second channel pattern CP2.

[0094] The first channel pattern CP1 may cover the upper surface of the bit line BL and the sidewall of the first insulating pattern 120. The first channel pattern CP1 may extend from the upper surface of the bit line BL to the sidewall of the first insulating pattern 120. The first channel pattern CP1 may include a horizontal portion extending in a first direction (Y direction) along the bit line BL and a vertical portion extending in a third direction (Z direction) from the horizontal portion along the sidewall of the first insulating pattern 120.

[0095] The second channel pattern CP2 may cover the upper surface of the bit line BL and the sidewall of the first insulating pattern 120 on the first channel pattern CP1. The second channel pattern CP2 may include a horizontal portion extending in a first direction (Y direction) along the bit line BL and a vertical portion extending in a third direction (Z direction) from the horizontal portion along the sidewall of the first insulating pattern 120. The horizontal portion of the second channel pattern CP2 may be located on the horizontal portion of the first channel pattern CP1. The vertical portion of the second channel pattern CP2 may be located on the vertical portion of the first channel pattern CP1.

[0096] As mentioned above Figure 2A , Figure 2B and Figure 3 As described above, the first channel pattern CP1 and the second channel pattern CP2 may include an oxide semiconductor material. The oxide semiconductor material may be a combination of at least two of In, Ga, Zn, Al, Sn, and Hf, but is not limited thereto. The oxide semiconductor material may include a material such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn added to the above components.

[0097] The first channel pattern CP1 and the second channel pattern CP2 may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), indium gallium oxide (IGO), or a combination thereof. However, not limited thereto, the oxide semiconductor material included in the first channel pattern CP1 and the second channel pattern CP2 may be changed in various ways.

[0098] In some embodiments, the first channel pattern CP1 may include an oxide semiconductor material having a higher indium composition ratio than that of the second channel pattern CP2. As the composition ratio of indium increases, contact resistance may be improved (reduced).

[0099] In some embodiments, the second channel pattern CP2 may include an oxide semiconductor material having a higher gallium composition ratio than that of the first channel pattern CP1. The higher the gallium composition ratio, the better the reliability.

[0100] In some embodiments, the first and second channel patterns CP1 and CP2 may include IGZO, but are not limited thereto, and oxide semiconductor materials included in the first and second channel patterns CP1 and CP2 may vary.

[0101] The composition ratio of indium, gallium, zinc, and oxygen of the first channel pattern CP1 may be different from the composition ratio of indium, gallium, zinc, and oxygen of the second channel pattern CP2. In some embodiments, the IGZO of the first channel pattern CP1 may have a higher indium composition ratio than the IGZO of the second channel pattern CP2, and the IGZO of the second channel pattern CP2 may have a higher gallium composition ratio than the IGZO of the first channel pattern CP1.

[0102] As mentioned above Figure 2A , Figure 2B and Figure 3 As described above, the first channel pattern CP1 may be formed by patterning an oxide semiconductor material layer deposited by a physical vapor deposition (PVD) process. The second channel pattern CP2 may be formed by patterning an oxide semiconductor material layer deposited by an atomic layer deposition (ALD) process.

[0103] In the ALD process, due to the 3 When an oxide semiconductor material layer is deposited on the bit line BL including metal using an ALD process, metal oxide may be generated at an interface between the bit line BL and the oxide semiconductor material layer.

[0104] Since O is not injected in the PVD process 3 When the oxide semiconductor material layer is deposited on the bit line BL using the ALD process, less metal oxide may be generated on the interface between the bit line BL and the oxide semiconductor material layer than when deposited using the ALD process.

[0105] In other words, when the oxide semiconductor material layer of the first channel pattern CP1 directly above the bit line BL is deposited using the PVD process, metal oxide generated on the interface of the bit line BL and the first channel pattern CP1 may be reduced and the contact resistance of the bit line BL may be lowered.

[0106] However, in the case of a PVD process, the material to be deposited is evaporated in a vacuum chamber and then the evaporated particles are deposited on the substrate, which can be performed in a high vacuum state without impurities. In this high vacuum state, linearity can be improved, but step coverage may not be very good because deposition does not properly occur on the sidewalls of the pattern with steps. For example, a PVD process may have poor step coverage of the deposited material compared to a CVD process or an ALD process. Therefore, in Figure 4 and Figure 5 In the embodiment shown, Figure 2A , Figure 2B and Figure 3 Unlike the illustrated embodiment, a portion of the first channel pattern CP1 located between the bit line BL and the second channel pattern CP2 may be thicker than a portion of the first channel pattern CP1 located between the first insulating pattern 120 and the second channel pattern CP2 .

[0107] The oxide semiconductor material layer corresponding to the second channel pattern CP2 not contacting the bit line BL may be deposited using an ALD process. Thus, the second channel pattern CP2 may have a conformal shape, and the thickness of a portion of the second channel pattern CP2 extending along the sidewall of the first insulating pattern 120 and the thickness of a portion of the second channel pattern CP2 extending along the bit line BL may be substantially the same.

[0108] according to Figure 4 and Figure 5 In the embodiment shown, the second portion CP_R2 of the channel pattern CP between the gate insulating pattern Gox and the bit line BL may be thicker than the first portion CP_R1 of the channel pattern CP between the gate insulating pattern Gox and the first insulating pattern 120. Figure 2A , Figure 2B and Figure 3In the embodiment shown, the first portion CP_R1 and the second portion CP_R2 may both include a portion of the first channel pattern CP1 and a portion of the second channel pattern CP2. The thickness of the portion of the second channel pattern CP2 located between the gate insulating pattern Gox and the bit line BL may be substantially the same as the thickness of the portion of the second channel pattern CP2 located between the gate insulating pattern Gox and the first insulating pattern 120. The thickness of the portion of the first channel pattern CP1 located between the gate insulating pattern Gox and the bit line BL may be thicker than the thickness of the portion of the first channel pattern CP1 located between the gate insulating pattern Gox and the first insulating pattern 120. Therefore, the thickness of the second portion CP_R2 of the channel pattern CP located between the gate insulating pattern Gox and the bit line BL may be thicker than the thickness of the first portion CP_R1 of the channel pattern CP located between the gate insulating pattern Gox and the first insulating pattern 120.

[0109] like Figure 2A , Figure 2B and Figure 3 As with the illustrated embodiment, the word lines WL1 and WL2 may be located on the channel pattern CP but may be separated from the channel pattern CP by the gate insulating pattern Gox.

[0110] exist Figure 2A , Figure 2B and Figure 3 In the illustrated embodiment, the word lines WL1 and WL2 may overlap the second channel pattern CP2 in the first direction (Y direction) and the third direction (Z direction), and may overlap the first channel pattern CP1 only in the third direction (Z direction). Figure 4 and Figure 5 In the illustrated embodiment, the word lines WL1 and WL2 may overlap the first channel pattern CP1 and the second channel pattern CP2 in the first direction (Y direction) and the third direction (Z direction).

[0111] The gate insulating pattern Gox may be located between the second channel pattern CP2 and the word lines WL1 and WL2. Figure 2A , Figure 2B and Figure 3 In the illustrated embodiment, only the second channel pattern CP2 is located between the gate insulating pattern Gox and the sidewall of the first insulating pattern 120. Figure 4 and Figure 5 The embodiment shown is different from Figure 2A , Figure 2B and Figure 3 In the illustrated embodiment, the first channel pattern CP1 and the second channel pattern CP2 may be located between the gate insulating pattern Gox and the sidewalls of the first insulating pattern 120 .

[0112] exist Figure 4 and Figure 5 , the upper surfaces of the first and second channel patterns CP1 and CP2 are shown to be located at substantially the same level between the gate insulating pattern Gox and the sidewalls of the first insulating pattern 120, but are not limited thereto. For example, the upper surface of the second channel pattern CP2 may be located at a higher level than the upper surface of the first channel pattern CP1.

[0113] Meanwhile, the landing pad LP may be located on the channel pattern CP located between the gate insulating pattern Gox and the sidewall of the first insulating pattern 120. Figure 2A , Figure 2B and Figure 3 As in the illustrated embodiment, the landing pad LP may include a first portion LP1 extending in the first direction (Y direction) and a second portion LP2 extending in the third direction (Z direction) from the first portion LP1 toward the bit line BL.

[0114] according to Figure 4 and Figure 5 The embodiment shown, with Figure 2A , Figure 2B and Figure 3 Unlike the embodiment shown, the landing pad LP may contact the first channel pattern CP1 and the second channel pattern CP2. The second portion LP2 of the landing pad LP may contact the upper surface of the first channel pattern CP1 and the upper surface of the second channel pattern CP2. Therefore, the landing pad LP may be electrically connected to the first channel pattern CP1 and the second channel pattern CP2.

[0115] according to Figure 4 and Figure 5 The channel pattern CP of the semiconductor device of the illustrated embodiment includes a first channel pattern CP1 and a second channel pattern CP2 corresponding to an oxide semiconductor material layer deposited using a PVD process and an oxide semiconductor material layer deposited using an ALD process, respectively, in the channel trench TRC. Therefore, the thickness of the second portion CP_R2 of the channel pattern CP located between the gate insulating pattern Gox and the bit line BL may be thicker than the thickness of the first portion CP_R1 of the channel pattern CP located between the gate insulating pattern Gox and the first insulating pattern 120. Since the first channel pattern CP1 located directly above the bit line BL is formed using the PVD process, oxidation of the interface between the bit line BL and the first channel pattern CP1 may be reduced, and contact between the bit line BL and the first channel pattern CP may be improved.

[0116] In the following, reference will be made to Figures 6 to 23 Description based on Figure 2A and Figure 3 A method for manufacturing a semiconductor device according to an embodiment of the present invention is provided. Figures 6 to 23 For convenience, the Figure 2A and Figure 3 1 and 2. The peripheral circuit structure PS of FIG. 1 is shown, and first, a lower insulating layer 110 formed on the peripheral circuit structure PS is shown.

[0117] Figures 6 to 23 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0118] Reference Figure 6 , the bit line BL may be formed on the lower insulating layer 110 .

[0119] The lower insulating layer 110 may include a plurality of stacked insulating layers. For example, the lower insulating layer 110 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0120] The bit lines BL extend in a first direction (Y direction) and may be arranged to be spaced apart in a second direction (X direction) intersecting the first direction (Y direction). For example, the second direction (X direction) may be perpendicular to the first direction (Y direction). The bit lines BL may be formed by depositing a conductive layer on the lower insulating layer 110 and then patterning the conductive layer.

[0121] Although not shown, the space between the bit lines BL may be filled with an insulating material. The insulating material may include the same insulating material as the lower insulating layer 110, but is not limited thereto. If the insulating material includes the same insulating material as the lower insulating layer 110, the insulating material may be integrated with the lower insulating layer 110. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL may be located at substantially the same level.

[0122] Reference Figure 7 , a first channel pattern material layer CP1_L may be formed on the bit line BL and the lower insulating layer 110. According to an embodiment, the first channel pattern material layer CP1_L may be deposited by a PVD process.

[0123] According to an embodiment, the first channel pattern material layer CP1_L may include an oxide semiconductor material. The oxide semiconductor material may include at least two materials from In, Ga, Zn, Al, Sn, and Hf, and the composition may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, Mn, etc. For example, the oxide semiconductor material may include IGZO. In an embodiment, the first channel pattern material layer CP1_L may include IGZO, but is not limited thereto.

[0124] The first channel pattern material layer CP1_L may include an oxide semiconductor material having better contact properties than an oxide semiconductor material in the second channel pattern material layer CP2_L described below. In some embodiments, the first channel pattern material layer CP1_L may include an oxide semiconductor material having a high indium composition ratio.

[0125] Reference Figure 8 , the first insulating pattern material layer 120_L may be formed on the first channel pattern material layer CP1_L. For example, the first insulating pattern material layer 120_L may be deposited by a chemical vapor deposition or PVD process, but is not limited thereto.

[0126] The first insulating pattern material layer 120_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0127] Reference Fig. 9 , the first insulating pattern 120 may be formed by patterning the first insulating pattern material layer 120_L.

[0128] The first insulating pattern 120 extends in the second direction (X direction) and may define first trenches TRC1 spaced apart from each other in the first direction (Y direction). The first trenches TRC1 may cross the bit lines BL and may expose an upper surface of the first channel pattern material layer CP1_L.

[0129] Reference Fig.10 , the second channel pattern material layer CP2_L may be formed on the upper surface of the first insulating pattern 120 and in the first trench TRC1. According to an embodiment, the second channel pattern material layer CP2_L may be formed by an ALD process. In other words, the second channel pattern material layer CP2_L may be conformally deposited on the upper surface and sidewalls of the first insulating pattern 120 and the upper surface of the first channel pattern material layer CP1_L.

[0130] According to an embodiment, the second channel pattern material layer CP2_L may include an oxide semiconductor material. For example, the second channel pattern material layer CP2_L may include IGZO, but is not limited thereto.

[0131] In some embodiments, the second channel pattern material layer CP2_L may include an oxide semiconductor material different from that of the first channel pattern material layer CP1_L, or may include an oxide semiconductor material having a different composition ratio from that of the first channel pattern material layer CP1_L.

[0132] The second channel pattern material layer CP2_L may include an oxide semiconductor material to improve the reliability of the film. In some embodiments, the second channel pattern material layer CP2 may include an oxide semiconductor material having a high gallium composition ratio. The second channel pattern material layer CP2_L may include an oxide semiconductor material having a gallium composition ratio higher than the gallium composition ratio of the oxide semiconductor material of the first channel pattern material layer CP1_L. The first channel pattern material layer CP1_L may include an oxide semiconductor material having an indium composition ratio higher than the indium composition ratio of the oxide semiconductor material of the second channel pattern material layer CP2_L.

[0133] Reference Fig.11 , the first gate insulating pattern material layer Gox_1 may be formed to conformally cover the second channel pattern material layer CP2_L. For example, the first gate insulating pattern material layer Gox_1 may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0134] The first gate insulating pattern Gox_1 may include silicon oxide, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof The high dielectric constant material may include metal oxide or metal nitride.

[0135] Reference Fig.12 , a spin-on hard mask layer (SOH) may be formed on the first gate insulating pattern material layer Gox_1. The spin-on hard mask layer (SOH) may be formed by a spin coating process. For example, the spin-on hard mask layer (SOH) may include carbon, but is not limited thereto.

[0136] Next, the spin-on hard mask layer (SOH) may be patterned to form a spin-on hard mask pattern, and the spin-on hard mask pattern may be used as an etching mask to etch the first channel pattern material layer CP1_L and the second channel pattern material layer CP2_L.

[0137] Reference Fig.13 , the patterning of the first channel pattern material layer CP1_L can be completed by an etching process to form a first channel pattern CP1, and the second channel pattern material layer CP2_L can be initially patterned to form a preliminary second channel pattern CP2_P. Next, the spin-on hard mask pattern can be removed. For example, the spin-on hard mask pattern can be removed by an ashing or stripping process.

[0138] According to an embodiment, the first channel pattern CP1 may include a portion extending along the first direction (Y direction) on the bit line BL. The portions of the first channel pattern CP1 extending along the first direction (Y direction) may be spaced apart along the second direction (X direction). The first channel pattern CP1 may include a portion extending along the second direction (X direction). The portions of the first channel pattern CP1 extending along the second direction (X direction) may be spaced apart along the first direction (Y direction). That is, the first channel pattern CP1 may have a mesh shape.

[0139] The first insulation pattern 120 may be located on a portion of the first channel pattern CP1 extending in the second direction (X direction).

[0140] The preliminary second channel pattern CP2_P may extend along the first direction (Y direction) on the first channel pattern CP1 and the first insulating pattern 120. The preliminary second channel pattern CP2_P may cover the upper surface of the first channel pattern CP1 and the sidewall and upper surface of the first insulating pattern 120 along the first direction (Y direction). The preliminary second channel pattern CP2_P may be spaced apart along the second direction (X direction).

[0141] In addition, the first gate insulation pattern material layer Gox_1 may be patterned by an etching process to form a preliminary gate insulation pattern Gox_P. The preliminary gate insulation pattern Gox_P may be located on the preliminary second channel pattern CP2_P. The preliminary gate insulation pattern Gox_P may extend along the first direction (Y direction) on the preliminary second channel pattern CP2_P. The preliminary gate insulation pattern Gox_P may be spaced apart along the second direction (X direction).

[0142] Reference Fig.14 , the second gate insulating pattern material layer Gox_2 may be formed to conformally cover the preliminary gate insulating pattern Gox_P. For example, the second gate insulating pattern material layer Gox_2 may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0143] The second gate insulating pattern material layer Gox_2 may include the same material as the first gate insulating pattern material layer Gox_1. Fig.13 The preliminary gate insulation pattern Gox_P is integrated.

[0144] Reference Fig.15 The word line material layer WL_L may be formed to conformally cover the second gate insulation pattern material layer Gox_2. For example, the word line material layer WL_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0145] The word line material layer WL_L may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0146] Reference Fig.16 , an anisotropic etching process may be performed on the word line material layer WL_L to form a pair of word lines WL1 and WL2 spaced apart from each other in the first direction (Y direction) in the first trench TRC1.

[0147] During the anisotropic etching process of the word line material layer WL_L, upper surfaces of the word lines WL1 and WL2 may be lower than upper surfaces of the second channel pattern CP2 and the first insulating pattern 120. In some embodiments, an etching process may be additionally performed to recess upper surfaces of the word lines WL1 and WL2.

[0148] Reference Fig.17 The second insulating pattern material layer 130_L may be formed to conformally cover the second gate insulating pattern material layer Gox_2 and the word lines WL1 and WL2. For example, the second insulating pattern material layer 130_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0149] The second insulating pattern material layer 130_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0150] Reference Fig.18 , a third insulating pattern material layer 140_L may be formed to fill the first trench TRC1 remaining after forming the second insulating pattern material layer 130_L. The third insulating pattern material layer 140_L may cover the upper surface of the first trench TRC1 and the upper surface of the second insulating pattern material layer 130_L. For example, the third insulating pattern material layer 140_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0151] The third insulating pattern material layer 140_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0152] The third insulating pattern material layer 140_L may include a material different from the second insulating pattern material layer 130_L, but is not limited thereto. When the second insulating pattern material layer 130_L and the third insulating pattern material layer 140_L include the same material, they may be integrally formed.

[0153] Reference Fig.19, the second channel pattern CP2, the gate insulating pattern Gox, the second insulating pattern 130, and the third insulating pattern 140 may be formed by a planarization process. By the planarization process, the upper surface of the first insulating pattern 120, the upper surface of the second channel pattern CP2, the upper surface of the gate insulating pattern Gox, the upper surface of the second insulating pattern 130, and the upper surface of the third insulating pattern 140 may be exposed. That is, a portion of the preliminary second channel pattern CP2_P located at a higher level than the upper surface of the first insulating pattern 120, a portion of the second gate insulating pattern material layer Gox_2, a portion of the second insulating pattern material layer 130_L, and a portion of the third insulating pattern material layer 140_L may be removed by the planarization process.

[0154] Reference Fig. 20 , the second trench TRC2 may be formed by an etching process to recess a portion of the second channel pattern CP2.

[0155] Specifically, by etching the second channel pattern CP2 from the upper surface toward the lower surface, a second trench TRC2 extending in a third direction (Z direction) can be formed. For example, a portion of the second channel pattern CP2 can be wet-etched using an etchant that selectively etches the second channel pattern CP2. However, the etching process for recessing the second channel pattern CP2 is not limited thereto and can be changed in various ways.

[0156] Reference Fig.21 The landing pad material layer LP_L may be formed to cover the upper surfaces of the insulating patterns 120, 130, and 140 and the upper surface of the gate insulating pattern Gox and fill the second trench TRC2. The landing pad material layer LP_L fills the second trench TRC2 and may contact the upper surface of the second channel pattern CP2.

[0157] Reference Fig. 22 , after the landing pad material layer LP_L is patterned to form a hole exposing the upper surface of the first insulating pattern 120 and the upper surface of the third insulating pattern 140, the interlayer insulating layer 150 may be embedded in the hole, and then a planarization process may be performed. Thus, the landing pad LP may be formed. However, the order of forming the landing pad LP and the interlayer insulating layer 150 is not limited thereto.

[0158] In some embodiments, after the interlayer insulating layer 150 is formed and patterned on the insulating patterns 120 , 130 , and 140 , the gate insulating pattern Gox, and the second channel pattern CP2 , a landing pad LP penetrating the interlayer insulating layer 150 may be formed.

[0159] Reference Fig.23, the data storage patterns DSP may be formed on the landing pads LP, respectively. In an embodiment, the data storage pattern DSP may be a capacitor including a lower electrode, a capacitor dielectric layer, and an upper electrode. In this case, the lower electrode may contact the landing pad LP.

[0160] In the following, reference will be made to Figures 24 to 41 Description based on Figure 4 and Figure 5 A method for manufacturing a semiconductor device according to an embodiment of the present invention is provided. Figures 24 to 41 For convenience, the Figure 4 and Figure 5 1 and 2. The peripheral circuit structure PS of FIG. 1 is shown, and first, a lower insulating layer 110 formed on the peripheral circuit structure PS is shown.

[0161] Figures 24 to 41 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0162] Reference Fig.24 , the bit line BL may be formed on the lower insulating layer 110 .

[0163] The lower insulating layer 110 may include a plurality of stacked insulating layers. For example, the lower insulating layer 110 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0164] The bit lines BL extend in a first direction (Y direction) and may be arranged to be spaced apart in a second direction (X direction) intersecting the first direction (Y direction). For example, the second direction (X direction) may be perpendicular to the first direction (Y direction). The bit lines BL may be formed by depositing a conductive layer on the lower insulating layer 110 and then patterning the conductive layer.

[0165] Although not shown, the space between the bit lines BL may be filled with an insulating material. The insulating material may include the same insulating material as the lower insulating layer 110, but is not limited thereto. If the insulating material includes the same insulating material as the lower insulating layer 110, the insulating material may be integrated with the lower insulating layer 110. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL may be located at substantially the same level.

[0166] Reference Fig.25 , a first insulating pattern material layer 120_L may be formed on the bit line BL and the lower insulating layer 110. For example, the first insulating pattern material layer 120_L may be deposited by a CVD or PVD process, but is not limited thereto.

[0167] The first insulating pattern material layer 120_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0168] Reference Fig.26 , the first insulating pattern 120_L may be formed by patterning the first insulating pattern material layer 120_L.

[0169] The first insulating pattern 120 extends in the second direction (X direction) and may define first trenches TRC1 spaced apart from each other in the first direction (Y direction). The first trenches TRC1 may cross the bit lines BL, and the first trenches TRC1 may expose upper surfaces of the bit lines BL.

[0170] Reference Fig. 27 , the first channel pattern material layer CP1_L may be formed on the upper surface of the first insulating pattern 120 and in the first trench TRC1. According to an embodiment, the first channel pattern material layer CP1_L may be formed by a PVD process. Therefore, the thickness of the second channel pattern material layer CP2_L deposited on the upper surface of the first insulating pattern 120 and the upper surface of the bit line BL may be thicker than the thickness of the second channel pattern material layer CP2_L deposited on the sidewall of the first insulating pattern 120.

[0171] According to an embodiment, the first channel pattern material layer CP1_L may include an oxide semiconductor material. The oxide semiconductor material may include at least two materials from In, Ga, Zn, Al, Sn, and Hf, and the composition may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, Mn, etc. For example, the oxide semiconductor material may include IGZO. In an embodiment, the first channel pattern material layer CP1_L may include IGZO, but is not limited thereto.

[0172] The first channel pattern material layer CP1_L may include an oxide semiconductor material having better contact properties than an oxide semiconductor material in the second channel pattern material layer CP2_L described below. In some embodiments, the first channel pattern material layer CP1_L may include an oxide semiconductor material having a high indium composition ratio.

[0173] Reference Fig.28, the second channel pattern material layer CP2_L may be formed to conformally cover the first channel pattern material layer CP1_L. According to an embodiment, the second channel pattern material layer CP2_L may be formed by an ALD process. Therefore, the thickness of the second channel pattern material layer CP2_L deposited on the first channel pattern material layer CP1_L deposited on the upper surface of the first insulating pattern 120 and the upper surface of the bit line BL may be substantially the same as the thickness of the second channel pattern material layer CP2_L deposited on the first channel pattern material layer CP1_L deposited on the sidewall of the first insulating pattern 120.

[0174] According to an embodiment, the second channel pattern material layer CP2_L may include an oxide semiconductor material. For example, the second channel pattern material layer CP2_L may include IGZO, but is not limited thereto.

[0175] In some embodiments, the second channel pattern material layer CP2_L may include an oxide semiconductor material different from that of the first channel pattern material layer CP1_L, or an oxide semiconductor material having a composition ratio different from that of the first channel pattern material layer CP1_L.

[0176] The second channel pattern material layer CP2_L may include an oxide semiconductor material to improve the reliability of the film. In some embodiments, the second channel pattern material layer CP2_L may include an oxide semiconductor material having a high gallium composition ratio. The second channel pattern material layer CP2_L may include an oxide semiconductor material having a gallium composition ratio higher than the gallium composition ratio of the oxide semiconductor material of the first channel pattern material layer CP1_L. The first channel pattern material layer CP1_L may include an oxide semiconductor material having an indium composition ratio higher than the indium composition ratio of the oxide semiconductor material of the second channel pattern material layer CP2_L.

[0177] Reference Fig.29 , the first gate insulating pattern material layer Gox_1 may be formed to conformally cover the second channel pattern material layer CP2_L. For example, the first gate insulating pattern material layer Gox_1 may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0178] The first gate insulating pattern material layer Gox_1 may include silicon oxide, silicon oxynitride, a high dielectric constant material having a dielectric constant higher than that of silicon oxide, or a combination thereof The high dielectric constant material may include metal oxide or metal nitride.

[0179] Reference Fig.30, a spin-on hard mask layer (SOH) may be formed on the first gate insulating pattern material layer Gox_1. The spin-on hard mask layer (SOH) may be formed by a spin coating process. For example, the spin-on hard mask layer (SOH) may include carbon, but is not limited thereto.

[0180] Next, the spin-on hard mask layer (SOH) may be patterned to form a spin-on hard mask pattern, and the spin-on hard mask pattern may be used as an etching mask to etch the first channel pattern material layer CP1_L and the second channel pattern material layer CP2_L.

[0181] Reference Fig.31 , the first channel pattern material layer CP1_L may be patterned through an etching process to form a preliminary first channel pattern CP1_P, and the second channel pattern material layer CP2_L may be patterned to form a preliminary second channel pattern CP2_P.

[0182] Next, the spin-on hard mask pattern may be removed. For example, the spin-on hard mask pattern may be removed by an ashing or stripping process.

[0183] The preliminary first channel pattern CP1_P may extend along the first direction (Y direction) on the bit line BL and the first insulating pattern 120. The preliminary first channel pattern CP1_P may cover the upper surface of the bit line BL and the sidewall and upper surface of the first insulating pattern 120 along the first direction (Y direction). The preliminary first channel pattern CP1_P may be spaced apart along the second direction (X direction).

[0184] The preliminary second channel pattern CP2_P may be located on the preliminary first channel pattern CP1_P. The preliminary second channel pattern CP2_P may extend along the first direction (Y direction) on the preliminary first channel pattern CP1_P. The preliminary second channel pattern CP2_P may be spaced apart along the second direction (X direction).

[0185] In addition, the first gate insulation pattern material layer Gox_1 may be patterned by an etching process to form a preliminary gate insulation pattern Gox_P. The preliminary gate insulation pattern Gox_P may be located on the preliminary second channel pattern CP2_P. The preliminary gate insulation pattern Gox_P may extend along the first direction (Y direction) on the preliminary second channel pattern CP2_P. The preliminary gate insulation pattern Gox_P may be spaced apart along the second direction (X direction).

[0186] Reference Fig.32 , the second gate insulating pattern material layer Gox_2 may be formed to conformally cover the preliminary gate insulating pattern Gox_P. For example, the second gate insulating pattern material layer Gox_2 may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0187] The second gate insulating pattern material layer Gox_2 may include the same material as the first gate insulating pattern material layer Gox_1. Fig.31 The preliminary gate insulation pattern Gox_P is integrated.

[0188] Reference Fig.33 The word line material layer WL_L may be formed to conformally cover the second gate insulation pattern material layer Gox_2. For example, the word line material layer WL_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0189] The word line material layer WL_L may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0190] Reference Fig.34 , an anisotropic etching process may be performed on the word line material layer WL_L to form a pair of word lines WL1 and WL2 spaced apart from each other in the first direction (Y direction) in the first trench TRC1.

[0191] During the anisotropic etching process for the word line material layer WL_L, upper surfaces of the word lines WL1 and WL2 may be lower than upper surfaces of the second channel pattern CP2 and the first insulating pattern 120. In some embodiments, an etching process may be additionally performed to recess upper surfaces of the word lines WL1 and WL2.

[0192] Reference Fig.35 The second insulating pattern material layer 130_L may be formed to conformally cover the second gate insulating pattern material layer Gox_2 and the word lines WL1 and WL2. For example, the second insulating pattern material layer 130_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0193] The second insulating pattern material layer 130_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0194] Reference Fig.36 , a third insulating pattern material layer 140_L may be formed to fill the first trench TRC1 remaining after forming the second insulating pattern material layer 130_L. The third insulating pattern material layer 140_L may cover the upper surface of the first trench TRC1 and the upper surface of the second insulating pattern material layer 130_L. For example, the third insulating pattern material layer 140_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0195] The third insulating pattern material layer 140_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material having a lower dielectric constant than silicon oxide, but is not limited thereto.

[0196] The third insulating pattern material layer 140_L may include a material different from that of the second insulating pattern material layer 130_L, but is not limited thereto. When the second insulating pattern material layer 130_L and the third insulating pattern material layer 140_L include the same material, they may be integrally formed.

[0197] Reference Fig.37 , the first channel pattern CP1, the second channel pattern CP2, the gate insulating pattern Gox, the second insulating pattern 130, and the third insulating pattern 140 may be formed by a planarization process. By the planarization process, the upper surface of the first insulating pattern 120, the upper surface of the first channel pattern CP1, the upper surface of the second channel pattern CP2, the upper surface of the gate insulating pattern Gox, the upper surface of the second insulating pattern 130, and the upper surface of the third insulating pattern 140 may be exposed. That is, a portion of the preliminary first channel pattern CP1_P, a portion of the preliminary second channel pattern CP2_P, a portion of the second gate insulating pattern material layer Gox_2, a portion of the second insulating pattern material layer 130_L, and a portion of the third insulating pattern material layer 140_L located at a level higher than the upper surface of the first insulating pattern 120 may be removed by the planarization process.

[0198] Reference Fig.38 , the second trench TRC2 may be formed by an etching process to recess portions of the first channel pattern CP1 and portions of the second channel pattern CP2.

[0199] Specifically, by etching the first channel pattern CP1 and the second channel pattern CP2 from the upper surface toward the lower surface, a second trench TRC2 extending in a third direction (Z direction) can be formed. For example, an etchant that selectively etches the first channel pattern CP1 and the second channel pattern CP2 can be used to wet-etch a portion of the first channel pattern CP1 and a portion of the second channel pattern CP2. However, the etching process for recessing the first channel pattern CP1 and the second channel pattern CP2 is not limited thereto and can be changed in various ways.

[0200] In an embodiment, the upper surface of the first channel pattern CP1 and the upper surface of the second channel pattern CP2 in the second groove TRC2 may be located at substantially the same level, but the present invention is not limited thereto. For example, in the second groove TRC2, the upper surface of the first channel pattern CP1 and the upper surface of the second channel pattern CP2 may be located at different levels.

[0201] Reference Fig.39The landing pad material layer LP_L may be formed to cover the upper surfaces of the insulating patterns 120, 130, and 140 and the upper surface of the gate insulating pattern Gox and fill the second trench TRC2. The landing pad material layer LP_L may fill the second trench TRC2 and may contact the upper surfaces of the first channel pattern CP1 and the second channel pattern CP2.

[0202] Reference Fig.40 , after the landing pad material layer LP_L is patterned to form a hole exposing the upper surfaces of the first insulating pattern 120 and the third insulating pattern 140, the interlayer insulating layer 150 may be embedded in the hole, and then a planarization process may be performed. Thus, the landing pad LP may be formed. However, the order of forming the landing pad LP and the interlayer insulating layer 150 is not limited thereto.

[0203] In some embodiments, after the interlayer insulating layer 150 is formed and patterned on the insulating patterns 120 , 130 , and 140 , the gate insulating pattern Gox, the first channel pattern CP1 , and the second channel pattern CP2 , a landing pad LP penetrating the interlayer insulating layer 150 may be formed.

[0204] Reference Fig.41 , the data storage patterns DSP may be formed on the landing pads LP, respectively. In an embodiment, the data storage pattern DSP may be a capacitor including a lower electrode, a capacitor dielectric layer, and an upper electrode. In this case, the lower electrode may contact the landing pad LP.

[0205] One or more elements disclosed above may include or be implemented in the following: a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0206] Although the embodiments of the present disclosure have been described in detail, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.

[0207] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0159083 filed in the Korean Intellectual Property Office on November 16, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: substrate; a bit line on the substrate and extending in a first direction; a first insulating pattern disposed on the bit line and extending in a second direction, the second direction intersecting the first direction; a channel pattern contacting a sidewall of the first insulating pattern and the bit line, the channel pattern comprising an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; as well as A landing pad is electrically connected to the channel pattern, wherein The channel pattern includes a first portion and a second portion, The first portion of the channel pattern is between the gate insulating pattern and the first insulating pattern, the second portion of the channel pattern is between the gate insulating pattern and the bit line, The second portion of the channel pattern has a thickness thicker than a thickness of the first portion of the channel pattern.

2. The semiconductor device according to claim 1, wherein The channel pattern includes a first channel pattern and a second channel pattern, The first channel pattern is above the bit line, and The second channel pattern is on a sidewall of the first insulating pattern and an upper surface of the first channel pattern.

3. The semiconductor device according to claim 2, wherein The second channel pattern has a conformal shape.

4. The semiconductor device according to claim 2, wherein The first channel pattern is between the bit line and the first insulating pattern, The second channel pattern is along a sidewall of the first insulating pattern.

5. The semiconductor device according to claim 4, wherein The landing pad contacts the second channel pattern.

6. The semiconductor device according to claim 2, wherein The first channel pattern is between the bit line and the second channel pattern and between the first insulating pattern and the second channel pattern, and The second channel pattern is spaced apart from the first insulation pattern.

7. The semiconductor device according to claim 6, wherein A thickness of a portion of the first channel pattern between the bit line and the second channel pattern is thicker than a thickness of a portion of the first channel pattern between the first insulating pattern and the second channel pattern.

8. The semiconductor device according to claim 6, wherein The landing pad contacts the first channel pattern and the second channel pattern.

9. The semiconductor device according to claim 2, wherein The oxide semiconductor material of the channel pattern is in the first channel pattern and the second channel pattern, and An indium composition ratio of the oxide semiconductor material in the first channel pattern is higher than an indium composition ratio of the oxide semiconductor material in the second channel pattern.

10. The semiconductor device according to claim 2, wherein The oxide semiconductor material of the channel pattern is in the first channel pattern and the second channel pattern, A gallium composition ratio of the oxide semiconductor material in the second channel pattern is higher than a gallium composition ratio of the oxide semiconductor material in the first channel pattern.

11. A semiconductor device comprising: substrate; a bit line on the substrate and extending in a first direction; a first insulating pattern disposed on the bit line and extending in a second direction, the second direction intersecting the first direction; a channel pattern on an upper surface of the bit line and a sidewall of the first insulating pattern, the channel pattern comprising an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; and A landing pad is electrically connected to the channel pattern, wherein The channel pattern includes a first channel pattern and a second channel pattern, The first channel pattern is between the bit line and the first insulating pattern, and The second channel pattern is on an upper surface of the first channel pattern and a sidewall of the first insulating pattern.

12. The semiconductor device according to claim 11, wherein The second channel pattern has a conformal shape.

13. The semiconductor device according to claim 11, wherein A first portion of the first channel pattern extends in the first direction along the bit line, and A second portion of the first channel pattern extends in the second direction across the bit line.

14. The semiconductor device according to claim 11, wherein The landing pad contacts the second channel pattern.

15. The semiconductor device according to claim 11, wherein The oxide semiconductor material in the channel pattern is different in the first channel pattern and the second channel pattern.

16. A semiconductor device comprising: substrate; a bit line on the substrate and extending in a first direction; a first insulating pattern disposed on the bit line and extending in a second direction, the second direction intersecting the first direction; a channel pattern on an upper surface of the bit line and a sidewall of the first insulating pattern, the channel pattern comprising an oxide semiconductor material; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern on the word line and the gate insulating pattern; and A landing pad is electrically connected to the channel pattern, wherein The channel pattern includes a first channel pattern and a second channel pattern, The first channel pattern extends from an upper surface of the bit line to a sidewall of the first insulating pattern, and The second channel pattern is between the first channel pattern and the gate insulating pattern.

17. The semiconductor device according to claim 16, wherein A portion of the channel pattern on the upper surface of the bit line is thicker than a portion of the channel pattern on the sidewall of the first insulating pattern.

18. The semiconductor device according to claim 16, wherein The landing pad contacts the first channel pattern and the second channel pattern.

19. The semiconductor device according to claim 16, wherein The oxide semiconductor material includes indium gallium zinc oxide (IGZO), and The oxide semiconductor material of the channel pattern is in the first channel pattern and the second channel pattern, A composition ratio of indium, gallium, zinc, and oxygen in the first channel pattern and a composition ratio of indium, gallium, zinc, and oxygen in the second channel pattern are different from each other.

20. The semiconductor device according to claim 19, wherein The indium composition ratio of the oxide semiconductor material in the first channel pattern is higher than the indium composition ratio of the oxide semiconductor material in the second channel pattern, and A gallium composition ratio of the oxide semiconductor material in the second channel pattern is higher than a gallium composition ratio of the oxide semiconductor material in the first channel pattern.

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