Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a storage region, the storage region comprises a storage unit region and a bit line region which are adjacent, a laminated material layer is formed on the substrate, and the laminated material layer comprises a first gate material layer and a second gate material layer located on the first gate material layer, discrete hard mask layers are formed on the laminated material layer; patterning the laminated material layer along the hard mask layer, reserving the laminated material layer in the storage unit region as a laminated gate structure, taking a first gate material layer in the laminated gate structure as a floating gate structure, and taking a second gate material layer in the laminated gate structure as a control gate structure; removing the hard mask layer; an erase gate structure is formed on the substrate defined by the opposite side walls of the adjacent laminated gate structures in the storage unit area, and the erase gate structure covers the side walls of the laminated gate structures on the two sides; and forming an interlayer dielectric layer covering the tops of the erasing gate structure and the laminated gate structure on the substrate. The yield and reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be divided into three main types: analog circuits, digital circuits, and mixed analog / digital circuits. Among them, memory devices are an important type of digital circuits. In recent years, among memory devices, flash memory has developed particularly rapidly. The main feature of flash memory is that it can retain stored information for a long time without power; it also has the advantages of high integration, fast access speed, easy erasure and rewriting, etc., so it has been widely used in many fields such as microcomputers and automation control.

[0003] Among them, on-chip eFlash (i.e. embedded Flash) is a non-volatile storage module for instructions and data, and is being used more and more widely in the field of low-power embedded chip SoC design. The processor is mainly responsible for tasks such as control, operating system platform and general signal processing, while eFlash is used to store instructions and data. The processor needs to access eFlash to obtain the required instructions and data in order to complete the corresponding task processing operations. Usually, the processor accesses instructions more frequently. Compared with the processor, which can improve performance through instruction-level parallelism, superscalar design and extensive use of registers, the improvement of eFlash performance can only rely on a few methods such as process improvement. Therefore, with the improvement of processor performance, the on-chip instruction fetch speed of eFlash has gradually become a bottleneck of SoC system performance. The speed of eFlash on-chip instruction fetch will directly affect and restrict the overall performance of SoC. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the yield and reliability of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage area, the storage area including an adjacent storage cell area and a bit line area; a stacked gate structure, located on the substrate of the storage cell area, the stacked gate structure including a floating gate structure, and a control gate structure located on the floating gate structure; an erase gate structure, located on the substrate surrounded by opposite side walls of adjacent stacked gate structures in the storage cell area, the erase gate structure covering the side walls of the stacked gate structure on both sides; an interlayer dielectric layer, located on the substrate, the interlayer dielectric layer covering the erase gate structure and the top of the stacked gate structure.

[0006] Optionally, the substrate further includes a logic region; the semiconductor structure further includes: a device gate structure located on the substrate in the logic region; and the interlayer dielectric layer also covers the top of the device gate structure.

[0007] Optionally, the top of the stacked gate structure, the top of the device gate structure and the top of the erase gate structure are flush.

[0008] Optionally, the semiconductor structure also includes: a device gate plug, which passes through the interlayer dielectric layer at the top of the device gate structure and is electrically connected to the device gate structure; a control gate plug, which passes through the interlayer dielectric layer at the top of the control gate structure and is electrically connected to the control gate structure; and a bit line plug, which passes through the interlayer dielectric layer at the top of the substrate of the bit line region and is electrically connected to the substrate of the bit line region.

[0009] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a storage area, the storage area comprising adjacent storage cell areas and a bit line area, a stacked material layer formed on the substrate, the stacked material layer comprising a first gate material layer and a second gate material layer located on the first gate material layer, and a discrete hard mask layer formed on the stacked material layer; patterning the stacked material layer along the hard mask layer, retaining the stacked material layer located in the storage cell area as a stacked gate structure, the first gate material layer in the stacked gate structure as a floating gate structure, and the second gate material layer in the stacked gate structure as a control gate structure; removing the hard mask layer; after removing the hard mask layer, forming an erase gate structure on the substrate surrounded by opposite side walls of adjacent stacked gate structures in the storage cell area, the erase gate structure covering the side walls of the stacked gate structure on both sides; forming an interlayer dielectric layer covering the erase gate structure and the top of the stacked gate structure on the substrate.

[0010] Optionally, the step of removing the hard mask layer includes: forming a blocking layer on the substrate at the side of the stacked gate structure, the blocking layer covering part or all of the sidewalls of the stacked gate structure and exposing the top of the hard mask layer; and removing the hard mask layer using the blocking layer as a mask.

[0011] Optionally, a dry etching process is used to remove the hard mask layer.

[0012] Optionally, in the step of forming a shielding layer on the substrate at the side of the stacked gate structure, the material of the shielding layer includes an organic material.

[0013] Optionally, after removing the hard mask layer, the method further includes: removing the blocking layer.

[0014] Optionally, a wet etching process is used to remove the shielding layer.

[0015] Optionally, the step of patterning the stacked material layer along the hard mask layer includes: patterning the second gate material layer using the hard mask layer as a mask, removing the second gate material layer exposed by the hard mask layer, and retaining the remaining second gate material layer as a control gate structure; forming a side wall covering the control gate structure and the side wall of the hard mask layer; patterning the first gate material layer using the side wall and the hard mask layer as a mask, removing the first gate material layer exposed by the side wall and the hard mask layer, and retaining the remaining first gate material layer as a floating gate structure; in the step of forming a blocking layer on the substrate on the side of the stacked gate structure, the blocking layer at least covers the side wall of the floating gate structure.

[0016] Optionally, after forming a sidewall covering the control gate structure and the sidewall of the hard mask layer, and before patterning the first gate material layer using the sidewall and the hard mask layer as a mask, the method further includes: removing a portion of the thickness of the sidewall on the opposite sidewall of the adjacent stacked gate structure in the storage cell area.

[0017] Optionally, in the step of providing a substrate, the substrate also includes a logic area; after removing the hard mask layer and before forming the interlayer dielectric layer, the formation method also includes: forming a device gate structure on the substrate in the logic area; in the step of forming the interlayer dielectric layer, the interlayer dielectric layer also covers the top of the device gate structure.

[0018] Optionally, the device gate structure and the erase gate structure are formed in the same step.

[0019] Optionally, the steps of forming a device gate structure and an erase gate structure include: forming a third gate material layer covering the substrate and the stacked gate structure; patterning the third gate material layer with the top of the stacked gate structure as the etching stop position to form an erase gate structure located in the storage cell area, on the substrate surrounded by relative side walls of adjacent stacked gate structures, and a device gate structure located in the logic area.

[0020] Optionally, after forming the interlayer dielectric layer, the formation method also includes: forming an interlayer dielectric layer that passes through the top of the control gate and is electrically connected to the control gate structure; forming a device gate plug that passes through the interlayer dielectric layer that passes through the top of the device gate structure and is electrically connected to the device gate structure; forming a bit line plug that passes through the interlayer dielectric layer that passes through the top of the substrate of the bit line area and is electrically connected to the substrate of the bit line area.

[0021] Optionally, the control gate plug and the device gate plug are formed in the same step.

[0022] Optionally, the steps of forming a bit line plug, a control gate plug and a device gate plug include: forming an opening through an interlayer dielectric layer at the top of a substrate in the bit line region, an interlayer dielectric layer at the top of a control gate structure, and an interlayer dielectric layer at the top of a device gate structure; filling the openings to form a bit line plug at the top of the substrate in the bit line region, an erase gate plug at the top of an erase gate, and a device gate plug at the top of the device gate structure.

[0023] Optionally, in the step of providing a substrate, the material of the hard mask layer includes silicon nitride; in the step of forming an interlayer dielectric layer covering the erase gate structure and the top of the stacked gate structure on the substrate, the material of the interlayer dielectric layer includes silicon oxide.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] In the semiconductor structure provided by the embodiment of the present invention, the interlayer dielectric layer covers the top of the erase gate structure and the stacked gate structure; in the embodiment of the present invention, in the process, after the hard mask layer is removed, the erase gate structure is formed, so that the interlayer dielectric layer directly covers the top of the erase gate structure and the stacked gate structure, reducing the height difference between the top of the stacked gate structure and the substrate. In the process of forming the erase gate structure, a fully covered third gate material layer is first formed, and the height difference between the top of the stacked gate structure and the substrate is reduced, so that the height difference between the top of the third gate material layer in the bit line area and the top of the third gate material layer on the stacked gate structure is reduced, and then the third gate material layer of a partial thickness is etched back with the top of the stacked gate structure as the etching stop position, so that the bit line area is formed. The top of the third gate material layer in the line area has good flatness. When the third gate material layer is patterned to form the erase gate structure and the device gate structure, it is beneficial to reduce the probability of regional defects due to large etching height differences (for example, etching residues are present at locations with larger heights, and over-etching damages the substrate at locations with smaller heights), thereby helping to improve the yield and reliability of the semiconductor structure. At the same time, the interlayer dielectric layer directly covers the erase gate structure and the stacked gate structure, so when forming the control gate plug, the step of etching the hard mask layer is omitted, which is beneficial to simplifying the process flow and saving costs. Moreover, the interlayer dielectric layer is usually of low hardness and is easy to etch, thereby making it easy to form a control gate plug on the top of the stacked gate structure, which is beneficial to improving process compatibility.

[0026] In the formation method provided by the embodiment of the present invention, the stacked material layer is patterned along the hard mask layer, the stacked material layer located in the storage area is retained as the stacked gate structure, and the hard mask layer is removed. After the hard mask layer is removed, in the storage cell area, an erase gate structure is formed on a substrate surrounded by opposite side walls of adjacent stacked gate structures, and an interlayer dielectric layer covering the erase gate structure and the top of the stacked gate structure is formed on the substrate; in the embodiment of the present invention, after the hard mask layer is removed, the erase gate structure is formed, and the height difference between the top of the stacked gate structure and the substrate is reduced. In the process of forming the erase gate structure, a fully covering third gate material layer is first formed, and the height difference between the top of the stacked gate structure and the substrate is reduced, so that the height difference between the top of the third gate material layer in the bit line area and the top of the third gate material layer on the stacked gate structure is reduced, and then the stacked gate structure is formed. The top of the structure is the etching stop position, and the third gate material layer of a partial thickness is back-etched, so that the top of the third gate material layer in the bit line area has better flatness. When the third gate material layer is patterned to form the erase gate structure and the device gate structure, it is beneficial to reduce the probability of regional defects due to large etching height differences (for example, etching residues are present at positions with larger heights, and over-etching damages the substrate at positions with smaller heights), thereby helping to improve the yield and reliability of the semiconductor structure. At the same time, the interlayer dielectric layer directly covers the erase gate structure and the stacked gate structure, so when forming the control gate plug, the step of etching the hard mask layer is omitted, which is beneficial to simplifying the process flow and saving costs. Moreover, the interlayer dielectric layer is usually of low hardness and is easy to etch, thereby making it easy to form a control gate plug on the top of the stacked gate structure, which is beneficial to improving process compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0028] Figure 7 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0029] Figures 8 to 18 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0030] At present, it is difficult to improve the product yield of semiconductor structures. Now, the reasons why it is difficult to improve the yield and reliability are analyzed in combination with a method for forming a semiconductor structure.

[0031] Figures 1 to 6 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0032] refer to Figure 1A substrate 10 is provided, including a storage area 10F and a logic area 10L, the storage area 10F includes an adjacent storage cell area 10c and a bit line area 10b, a stacked gate structure is formed on the substrate 10 of the storage cell area 10c, the stacked gate structure includes a floating gate structure 21 and a control gate structure 22 located on the floating gate structure 21, and a hard mask layer 30 is also formed on the stacked gate structure; an erase gate structure 23 is formed on the substrate 10 surrounded by opposite side walls in the adjacent stacked gate structure of the storage cell area 10c, and a device gate structure 24 is formed on the substrate 10 of the logic area 10L.

[0033] Due to the existence of the hard mask layer 30 and its large thickness, the height difference between the top of the stacked gate structure and the substrate 10 is large. In the process of forming the erase gate structure 23, a fully covered gate material layer is first formed. The height difference between the top of the stacked gate structure and the substrate is large, which makes the height difference between the top of the gate material layer in the bit line area 10b and the top of the gate material layer on the stacked gate structure large. Then, the top of the stacked gate structure is used as the etching stop position to back-etch a portion of the gate material layer, so that the top of the gate material layer in the bit line area 10b has poor flatness. When the gate material layer is patterned to form the erase gate structure 23 and the device gate structure 24, regional defects are likely to occur due to the large etching height difference (for example, etching residues are present at the position with a larger height, and the substrate is damaged by over-etching at the position with a smaller height), thereby affecting the yield and reliability of the semiconductor structure.

[0034] refer to Figure 2 , forming a blocking layer 40 covering the stacked gate structure, the erase gate structure 23 , the hard mask layer 30 and the device gate structure 24 , wherein a first opening exposing the top of the hard mask layer 30 is formed in the blocking layer 40 .

[0035] refer to Figure 3 , the hard mask layer 30 is patterned along the first opening to form a second opening exposing the top of the control gate structure 22 .

[0036] refer to Figure 4 , forming an interlayer dielectric layer 50 covering the stacked gate structure, the erase gate structure 23, the hard mask layer 30 and the device gate structure 24 and filling the second opening.

[0037] refer to Figure 5 , patterning the interlayer dielectric layer 50 to form a third opening 51 exposing the top of the control gate structure 22 and the top of the device gate structure 24 .

[0038] refer to Figure 6 , filling the third opening 51 to form a control gate plug located on the top of the control gate structure 22 and a device gate plug located on the top of the device gate structure 24 .

[0039] When forming the control gate plug and the device gate plug, the hard mask layer 30 needs to be etched in advance, which makes the process flow more complicated and difficult to save costs.

[0040] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a storage area, the storage area comprising adjacent storage cell areas and a bit line area, a stacked material layer formed on the substrate, the stacked material layer comprising a first gate material layer and a second gate material layer located on the first gate material layer, and a discrete hard mask layer formed on the stacked material layer; patterning the stacked material layer along the hard mask layer, retaining the stacked material layer located in the storage cell area as a stacked gate structure, the first gate material layer in the stacked gate structure as a floating gate structure, and the second gate material layer in the stacked gate structure as a control gate structure; removing the hard mask layer; after removing the hard mask layer, forming an erase gate structure on the substrate surrounded by opposite side walls of adjacent stacked gate structures in the storage cell area, the erase gate structure covering the side walls of the stacked gate structure on both sides; forming an interlayer dielectric layer covering the erase gate structure and the top of the stacked gate structure on the substrate.

[0041] In the embodiment of the present invention, after the hard mask layer is removed, an erase gate structure is formed, thereby reducing the height difference between the top of the stacked gate structure and the substrate. In the process of forming the erase gate structure, a fully covered third gate material layer is first formed, and the height difference between the top of the stacked gate structure and the substrate is reduced, so that the height difference between the top of the third gate material layer in the bit line area and the top of the third gate material layer on the stacked gate structure is reduced, and then the third gate material layer with a partial thickness is etched back with the top of the stacked gate structure as the etching stop position, so that the top of the third gate material layer in the bit line area has a better flatness, and then the third gate material layer is patterned to form an erase gate structure. When etching the gate structure and the device gate structure, it is beneficial to reduce the probability of regional defects due to large etching height differences (for example, etching residues are present at locations with larger heights, and over-etching damages the substrate at locations with smaller heights), thereby helping to improve the yield and reliability of the semiconductor structure. At the same time, the interlayer dielectric layer directly covers the erase gate structure and the stacked gate structure, and when forming the control gate plug, the step of etching the hard mask layer is omitted, which is beneficial to simplifying the process flow and saving costs. Moreover, the interlayer dielectric layer is usually of low hardness and is easy to etch, thereby making it easy to form a control gate plug on the top of the stacked gate structure, which is beneficial to improving process compatibility.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figure 7 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0044] The semiconductor structure includes: a substrate 100, including a storage area 100F, the storage area 100F includes an adjacent storage cell area 100c and a bit line area 100b; a stacked gate structure 200, located on the substrate 100 in the storage cell area 100c, the stacked gate structure 200 includes a floating gate structure 210, and a control gate structure 220 located on the floating gate structure 210; an erase gate structure 230, located on the substrate 100 surrounded by opposite side walls of adjacent stacked gate structures 200 in the storage cell area 100c, the erase gate structure 230 covers the side walls of the stacked gate structure 200 on both sides; an interlayer dielectric layer 500, located on the substrate 100, the interlayer dielectric layer 500 covers the erase gate structure 230 and the top of the stacked gate structure 200.

[0045] In this embodiment, the semiconductor structure is a Flash memory, specifically, an embedded Flash (eFlash).

[0046] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0047] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0048] The storage area 100F is used to form a memory. Specifically, the storage cell area 100c is used to form a split gate memory structure consisting of a floating gate (Floating Gate) structure 210, a coupling gate (CG) structure 220, and an erase gate (EG) structure 230, and the bit line area 100b is used to form a bit line (BL) in the memory as a drain.

[0049] In this embodiment, the substrate 100 further includes a logic region 100L.

[0050] The logic region 100L is used to form a logic device.

[0051] The stacked gate structure 200 is used to implement signal writing of the memory. Specifically, the floating gate structure 210 is used as a unit structure for storing data in the memory, and the control gate structure 220 is used to electrically connect to the outside to control the longitudinal electric field of the floating gate structure 210 .

[0052] Specifically, in this embodiment, two stacked gate structures 200 are formed in each memory cell region 100 c .

[0053] The erase gate structure 230 is used to implement signal erasure of the memory.

[0054] Specifically, by applying a high voltage to the erase gate structure 230, a potential difference is formed on the first dielectric layer between the erase gate structure 230 and the floating gate structure 210 due to the coupling capacitance, and the electrons in the floating gate structure 210 can be pulled to the erase gate structure 230 through tunneling. As the electrons in the floating gate structure 210 are pulled out, the potential of the floating gate structure 210 increases, and the difference between its potential and the erase gate structure 230 will be reduced, weakening the potential difference between the first dielectric layer, and finally the electrons in the floating gate structure 210 are completely pulled out, realizing the signal erasure of the memory.

[0055] In this embodiment, there are two stacked gate structures 200 in the storage area 100F, and the two adjacent stacked gate structures share the same erase gate structure 230, so that in the storage area 100F, two floating gate structures 210 are used to write signals at the same time, which is beneficial to improving the efficiency of signal writing. The two adjacent stacked gate structures share the same erase gate structure 230, and two floating gate structures 210 are used to erase signals at the same time, which is beneficial to improving the efficiency of signal erasure.

[0056] In this embodiment, the material of the floating gate structure 210 includes polysilicon; the material of the control gate structure 220 includes polysilicon; and the material of the erase gate structure 230 includes polysilicon.

[0057] In this embodiment, a word line (WL) structure is formed on the substrate of the stacked gate structure 200 on the side facing away from the erase gate structure 230 , and the word line structure is used to control channel electrons.

[0058] Specifically, a high voltage is applied to the WL structure and a low voltage is applied to the substrate 100 in the BL region to open the channel. A high voltage is applied to the control gate structure 220 so that there is a strong vertical electric field between the floating gate structure 210 and the control gate structure 220. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a part of the electrons are injected into the floating gate structure 210, thereby realizing electron injection and signal writing.

[0059] The interlayer dielectric layer 500 is used to isolate adjacent devices and is also used to provide a process basis for forming a control gate plug and a device gate plug 520 .

[0060] The material of the interlayer dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0061] In the present embodiment, in the process, after the hard mask layer is removed, the erase gate structure 230 is formed, so that the interlayer dielectric layer 500 directly covers the erase gate structure 230 and the top of the stacked gate structure 200, reducing the height difference between the top of the stacked gate structure 200 and the substrate 100. In the process of forming the erase gate structure 230, a fully covered third gate material layer is first formed, and the height difference between the top of the stacked gate structure 200 and the substrate 100 is reduced, so that the top of the third gate material layer in the bit line region 100b and the third gate on the stacked gate structure 200 are not too close. The height difference at the top of the gate material layer is reduced, and then the third gate material layer of a partial thickness is etched back with the top of the stacked gate structure 200 as the etching stop position, so that the top of the third gate material layer in the bit line area 100b has better flatness. Then, when the third gate material layer is patterned to form the erase gate structure 230 and the device gate structure 240, it is beneficial to reduce the probability of regional defects due to the large etching height difference (for example, etching residues are present at the position with a larger height, and the substrate is damaged by over-etching at the position with a smaller height), thereby helping to improve the yield and reliability of the semiconductor structure.

[0062] In this embodiment, the semiconductor structure further includes: a device gate structure 240 located on the substrate 100 in the logic region 100L; and a source-drain doped layer located in the substrate 100 in the logic region 100L and on both sides of the device gate structure 240 .

[0063] The device gate structure 240 and the source-drain doping layers are used to form a transistor structure.

[0064] The device gate structure 240 is used to control the opening and closing of the channel of the transistor, and the source-drain doped layer is used as the source region or drain region of the transistor. Specifically, the doping type of the source-drain doped layer is the same as the channel conductivity type of the corresponding transistor.

[0065] In this embodiment, the memory and the transistor structure are integrated to obtain a semiconductor structure of an embedded memory.

[0066] In this embodiment, the interlayer dielectric layer 500 also covers the top of the device gate structure 240 .

[0067] The interlayer dielectric layer 500 is also used to provide a process platform for forming a device plug on the top of the device gate structure 240 .

[0068] In this embodiment, the top of the stacked gate structure 200 , the top of the device gate structure 240 , and the top of the erase gate structure 230 are flush with each other.

[0069] In the semiconductor process, after removing the hard mask layer, an erase gate structure 230 and a device gate structure 240 are formed, and the top of the stacked gate structure 200 is used as the etching stop position, so that the top of the device gate structure 240 and the erase gate structure 230 are flush with the top of the stacked gate structure 200.

[0070] In this embodiment, the semiconductor structure further includes a control gate plug 520 , which penetrates the interlayer dielectric layer 500 on the top of the control gate structure 220 and is electrically connected to the control gate structure 220 .

[0071] The control gate plug 520 is used to realize electrical connection between the control gate structure 220 and the outside.

[0072] In this embodiment, the material of the control gate plug 520 is tungsten. In other embodiments, the material of the control gate plug may also be cobalt or ruthenium.

[0073] In this embodiment, when forming the control gate plug 520, the step of etching the hard mask layer is omitted, which is beneficial to simplifying the process flow and saving costs. Moreover, the interlayer dielectric layer 500 is usually of low hardness and easy to etch, so it is easy to form the control gate plug 520 on the top of the stacked gate structure 200, which is beneficial to improving process compatibility.

[0074] In this embodiment, the semiconductor structure further includes: a device gate plug 530 , which penetrates the interlayer dielectric layer 500 on the top of the device gate structure 240 and is electrically connected to the device gate structure 240 .

[0075] The device gate plug 530 is used to realize electrical connection between the device gate structure 240 and the outside.

[0076] In this embodiment, the material of the device gate plug 530 is tungsten. In other embodiments, the material of the device gate plug may also be cobalt or ruthenium.

[0077] In this embodiment, the semiconductor structure further includes: source-drain plugs penetrating the interlayer dielectric layer 500 on the top of the source-drain doped layer and electrically connected to the source-drain doped layer.

[0078] The source-drain plugs are used to realize electrical connection between the source-drain doped layers and the outside.

[0079] In this embodiment, the material of the source-drain plug is tungsten. In other embodiments, the material of the source-drain plug may also be cobalt or ruthenium.

[0080] In this embodiment, the semiconductor structure further includes a bit line plug penetrating through the interlayer dielectric layer 500 on the top of the substrate 100 in the bit line region 100 b and electrically connected to the substrate 100 in the bit line region 100 b .

[0081] The bit line plug is used to realize electrical connection between the bit line region 100 b and the outside.

[0082] In this embodiment, the material of the bit line plug is tungsten. In other embodiments, the material of the bit line plug may also be cobalt or ruthenium.

[0083] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure.

[0084] Figures 8 to 18 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0085] refer to Figure 8 A substrate 100 is provided, including a storage area 100F, the storage area 100F includes adjacent storage cell areas 100c and bit line areas 100b, a stacked material layer is formed on the substrate 100, the stacked material layer includes a first gate material layer 201 and a second gate material layer 202 located on the first gate material layer 201, and a discrete hard mask layer 300 is formed on the stacked material layer.

[0086] In this embodiment, the semiconductor structure is a Flash memory, specifically, an embedded Flash (eFlash).

[0087] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0088] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0089] The storage area 100F is used to form a memory. Specifically, the storage cell area 100c is used to form a split gate memory structure consisting of a floating gate (FloatingGate) structure, a control gate (Coupling Gate, CG) structure, and an erase gate (Erase Gate, EG) structure, and the bit line area 100b is used to form a bit line (Bit Line, BL) in the memory as a drain.

[0090] The first gate material layer 201 is used to form a floating gate structure.

[0091] In this embodiment, the material of the first gate material layer 201 is silicon.

[0092] The second gate material layer 202 is used to form a control gate structure.

[0093] In this embodiment, the material of the second gate material layer 202 is silicon.

[0094] The hard mask layer 300 is used as a mask for subsequent patterning of the first gate material layer 201 and the second gate material layer 202 .

[0095] In this embodiment, the material of the hard mask layer 300 includes silicon nitride.

[0096] Silicon nitride has a relatively high hardness, which is beneficial for achieving a higher pattern transfer accuracy in the subsequent patterning of the first gate material layer 201 and the second gate material layer 202 .

[0097] In this embodiment, in the step of providing the substrate 100 , the substrate 100 further includes a logic region 100L.

[0098] The logic region 100L is used to form a logic device.

[0099] Combined with reference Figures 9 to 11 , the stacked material layer is patterned along the hard mask layer 300, and the stacked material layer located in the memory cell area 100c is retained as the stacked gate structure 200, the first gate material layer 201 in the stacked gate structure 200 is used as the floating gate structure 210, and the second gate material layer 202 in the stacked gate structure 200 is used as the control gate structure 220.

[0100] The stacked gate structure 200 is used to implement signal writing of the memory. Specifically, the floating gate structure 210 is used as a unit structure for storing data in the memory, and the control gate structure 220 is used to electrically connect to the outside to control the longitudinal electric field of the floating gate structure 210 .

[0101] Specifically, in this embodiment, two stacked gate structures 200 are formed in each memory cell region 100 c .

[0102] In this embodiment, the storage cell area 100c has two stacked gate structures 200, and the two adjacent stacked gate structures 200 subsequently share the same erase gate structure, so that in the storage cell area 100c, two floating gate structures 210 are used simultaneously to write signals, which is beneficial to improving the efficiency of signal writing. The two adjacent stacked gate structures 200 share the same erase gate structure, and two floating gate structures 210 are used simultaneously to erase signals, which is beneficial to improving the efficiency of signal erasure.

[0103] In this embodiment, the material of the floating gate structure 210 includes polysilicon; the material of the control gate structure 220 includes polysilicon.

[0104] Specifically, refer to Fig. 9 The step of patterning the stacked material layer along the hard mask layer 300 includes: patterning the second gate material layer 202 using the hard mask layer 300 as a mask, removing the second gate material layer 202 exposed by the hard mask layer 300, and retaining the remaining second gate material layer 202 as the control gate structure 220.

[0105] First, the second gate material layer 202 is patterned using the hard mask layer 300 as a mask to form a control gate structure 220. After the sidewalls are subsequently formed, the floating gate structure 210 is patterned again so that the floating gate structure 210 can form a tip protruding from the sidewall of the control gate structure 220. Accordingly, the erase gate structure formed subsequently can wrap around the tip of the control gate structure 220, so that the electrons in the floating gate structure 210 can be pulled to the erase gate structure through the tip by tunneling.

[0106] In this embodiment, in the step of patterning the second gate material layer 202 using the hard mask layer 300 as a mask, a partial thickness of the first gate material layer 201 is also patterned, so that a stepped floating gate structure 210 is subsequently formed, which makes it easy for the erase gate structure formed subsequently to wrap the tip of the control gate structure 220.

[0107] refer to Fig.10 , forming a spacer 400 covering the sidewalls of the control gate structure 220 and the hard mask layer 300 .

[0108] The spacer 400 is used together with the hard mask layer 300 as a mask for subsequent patterning of the remaining second gate material layer 202 .

[0109] In this embodiment, the spacer 400 is an Oxide-Nitride-Oxide (ONO) structure of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0110] Continue to refer Fig.10 After forming the sidewall 400 covering the sidewalls of the control gate structure 220 and the hard mask layer 300, before subsequently patterning the first gate material layer 201 using the sidewall 400 and the hard mask layer 300 together as a mask, it also includes: removing a portion of the thickness of the sidewall 400 on the opposite sidewall of the adjacent stacked gate structure 200 in the storage cell area 100c.

[0111] Subsequently, in the memory cell area 100c, an erase gate structure is formed on the substrate 100 surrounded by opposite side walls of adjacent stacked gate structures 200. Therefore, a portion of the thickness of the sidewalls 400 on the opposite side walls of adjacent stacked gate structures 200 in the memory cell area 100c is removed, so that the tips of the floating gate structures 210 in adjacent stacked gate structures 200 in the memory cell area 100c are opposite to each other, so that subsequently, in the memory cell area 100c, an erase gate structure is formed on the substrate 100 surrounded by opposite side walls of adjacent stacked gate structures 200 to cover the tips of the two floating gate structures 210 of the stacked gate structures 200 in the memory cell area 100c.

[0112] Specifically, in the present embodiment, in the step of removing a portion of the thickness of the sidewall spacer 400 on the opposite sidewalls of adjacent stacked gate structures 200 in the memory cell region 100c, the outermost silicon oxide layer of the sidewall spacer 400 on the opposite sidewalls of adjacent stacked gate structures 200 in the memory cell region 100c is removed.

[0113] refer to Fig.11 The first gate material layer 201 is patterned using the spacer 400 and the hard mask layer 300 as a mask, the first gate material layer 201 exposed by the spacer 400 and the hard mask layer 300 is removed, and the remaining first gate material layer 201 is retained as a floating gate structure 210.

[0114] Specifically, the first gate material layer 201 is patterned with the spacer 400 and the hard mask layer 300 as masks, and the remaining first gate material layer 201 exposed by the spacer 400 and the hard mask layer 300 is removed to form a stepped floating gate structure 210 .

[0115] Combined with reference Fig.12 and Fig.13 , and remove the hard mask layer 300 .

[0116] The hard mask layer 300 is removed to reduce the height difference between the top of the stacked gate structure 200 and the substrate 100 when an erase gate structure is subsequently formed.

[0117] In this embodiment, after the hard mask layer 300 is removed, an erase gate structure is formed, thereby reducing the height difference between the top of the stacked gate structure 200 and the substrate 100. In the subsequent process of forming the erase gate structure, a fully covered third gate material layer is first formed, and the height difference between the top of the stacked gate structure 200 and the substrate 100 is reduced, so that the height difference between the top of the third gate material layer in the bit line area 100b and the top of the third gate material layer on the stacked gate structure 200 is reduced. Then, the third gate material layer is partially etched back with the top of the stacked gate structure 200 as the etching stop position, so that the top of the third gate material layer in the bit line area 100b has better flatness. When the third gate material layer is patterned to form the erase gate structure and the device gate structure, it is beneficial to reduce the probability of regional defects (for example, etching residues are present at the position with a larger height, and the substrate is damaged by over-etching at the position with a smaller height) due to the large etching height difference, thereby facilitating improving the yield and reliability of the semiconductor structure.

[0118] It should be noted that in other embodiments, in the step of removing the hard mask layer, a portion of the hard mask layer may be removed, and the remaining thickness of the hard mask layer may be retained for subsequent protection of the top of the stacked gate structure.

[0119] In this embodiment, a dry etching process is used to remove the hard mask layer 300 .

[0120] The dry etching process has a high etching directionality, which is beneficial to reducing the damage to the stacked gate structure 200 when removing the hard mask layer 300 .

[0121] refer to Fig.12 The step of removing the hard mask layer 300 includes: forming a blocking layer 600 on the substrate 100 at the side of the stacked gate structure 200, wherein the blocking layer 600 covers part or all of the sidewalls of the stacked gate structure 200 and exposes the top of the hard mask layer 300.

[0122] The blocking layer 600 is used as a mask for removing the hard mask layer 300 . The blocking layer 600 covers part or all of the sidewalls of the stacked gate structure 200 and exposes the top of the hard mask layer 300 , preparing for removing the hard mask layer 300 and protecting the sidewalls of the stacked gate structure 200 .

[0123] In this embodiment, in the step of forming the shielding layer 600 on the substrate 100 at the side of the stacked gate structure 200 , the material of the shielding layer 600 includes an organic material.

[0124] The shielding layer 600 needs to be removed later, and the organic material is easy to remove, which is beneficial to the subsequent removal of the shielding layer 600.

[0125] As an example, the material of the shielding layer 600 includes a bottom anti-reflective coating (BARC) material.

[0126] In this embodiment, in the step of forming the shielding layer 600 on the substrate 100 at the side of the stacked gate structure 200 , the shielding layer 600 at least covers the sidewalls of the floating gate structure 210 .

[0127] In this embodiment, the sidewall 400 covers the sidewall of the control gate structure 220, which can protect the sidewall of the control gate structure 220 and expose the remaining sidewall of the floating gate structure 210. Therefore, the blocking layer 600 at least covers the sidewall of the floating gate structure 210 to protect the sidewall of the floating gate structure 210 when the hard mask layer 300 is removed.

[0128] refer to Fig.13 , using the blocking layer 600 as a mask, the hard mask layer 300 is removed.

[0129] refer to Fig.14 After removing the hard mask layer 300 , the method further includes: removing the blocking layer 600 .

[0130] The shielding layer 600 is removed to prepare for the subsequent formation of an erase gate structure.

[0131] In this embodiment, a wet etching process is used to remove the shielding layer 600 .

[0132] The wet etching process can easily remove the shielding layer 600 completely and can achieve a larger etching selectivity ratio, thereby reducing damage to other film layers when removing the shielding layer 600.

[0133] refer to Fig.15 After removing the hard mask layer 300 , in the memory cell region 100 c , an erase gate structure 230 is formed on the substrate 100 surrounded by opposite side walls of adjacent stacked gate structures 200 , and the erase gate structure 230 covers the side walls of the stacked gate structures 200 on both sides.

[0134] The erase gate structure 230 is used to implement signal erasure of the memory.

[0135] Specifically, by applying a high voltage to the erase gate structure 230, a potential difference is formed on the first dielectric layer between the erase gate structure 230 and the floating gate structure 210 due to the coupling capacitance, and the electrons in the floating gate structure 210 can be pulled to the erase gate structure 230 through tunneling. As the electrons in the floating gate structure 210 are pulled out, the potential of the floating gate structure 210 increases, and the difference between its potential and the erase gate structure 230 will be reduced, weakening the potential difference between the first dielectric layer, and finally the electrons in the floating gate structure 210 are completely pulled out, realizing the signal erasure of the memory.

[0136] In this embodiment, a word line (WL) structure is formed on the substrate of the stacked gate structure 200 on the side facing away from the erase gate structure 230 , and the word line structure is used to control channel electrons.

[0137] Specifically, a high voltage is applied to the WL structure and a low voltage is applied to the BL region to open the channel. A high voltage is applied to the control gate structure 220 so that there is a strong vertical electric field between the floating gate structure 210 and the control gate structure 220. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a part of the electrons are injected into the floating gate structure 210, thereby realizing electron injection and signal writing.

[0138] In this embodiment, the material of the erase gate structure 230 includes polysilicon.

[0139] In this embodiment, after removing the hard mask layer 300 and before subsequently forming the interlayer dielectric layer, the formation method further includes: forming a device gate structure 240 on the substrate 100 in the logic area 100L, and a source-drain doping layer in the substrate 100 located on both sides of the device gate structure 240 .

[0140] The device gate structure 240 and the source-drain doping layers are used to form a transistor structure.

[0141] The device gate structure 240 is used to control the opening and closing of the channel of the transistor, and the source-drain doped layer is used as the source region or drain region of the transistor. Specifically, the doping type of the source-drain doped layer is the same as the channel conductivity type of the corresponding transistor.

[0142] In this embodiment, the memory and the transistor structure are integrated to obtain a semiconductor structure of an embedded memory.

[0143] In this embodiment, the device gate structure 240 and the erase gate structure 230 are formed in the same step.

[0144] Forming the device gate structure 240 and the erase gate structure 230 in the same step is beneficial to improving process efficiency, simplifying the process flow, and reducing process costs.

[0145] In this embodiment, the steps of forming the device gate structure 240 and the erase gate structure 230 include: forming a third gate material layer covering the substrate 100 and the stacked gate structure 200; patterning the third gate material layer with the top of the stacked gate structure 200 as the etching stop position to form an erase gate structure 230 located in the storage cell area on the substrate 100 surrounded by relative side walls of adjacent stacked gate structures 200, and a device gate structure 240 located in the logic area 100L.

[0146] Accordingly, in this embodiment, the top of the stacked gate structure 200 , the top of the erase gate structure 230 , and the top of the device gate structure 240 are flush.

[0147] Specifically, in this embodiment, the step of patterning the third gate material layer with the top of the stacked gate structure 200 as the etching stop position includes: back-etching the third gate material layer of the storage area 100F with the top of the stacked gate structure 200 as the etching stop position; back-etching the third gate material layer of the logic area 100L; after back-etching, patterning the third gate material layer of the storage area 100F and the logic area 100L to form an erase gate structure 230 and a device gate structure 240.

[0148] refer to Fig.16 , an interlayer dielectric layer 500 is formed on the substrate 100 to cover the erase gate structure 230 and the top of the stacked gate structure 200 .

[0149] The interlayer dielectric layer 500 is used to isolate adjacent devices and also to provide a process basis for the subsequent formation of control gate plugs, device gate plugs, and source and drain plugs.

[0150] The material of the interlayer dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0151] As an example, in this embodiment, the material of the interlayer dielectric layer 500 is silicon oxide, and the hardness of silicon oxide is relatively low.

[0152] Combined with reference Fig.17 and Fig.18After forming the interlayer dielectric layer 500, the forming method further includes: forming the interlayer dielectric layer 500 penetrating the control gate top 230 and the control gate plug 520 electrically connected to the control gate structure 230; forming the interlayer dielectric layer 500 penetrating the top of the device gate structure 240 and the device gate plug 530 electrically connected to the device gate structure 240; forming the interlayer dielectric layer 500 penetrating the top of the substrate 100 of the bit line region 100b and the bit line plug electrically connected to the substrate 100 of the bit line region 100b.

[0153] In this embodiment, when forming the control gate plug 520, the step of etching the hard mask layer is omitted, which is beneficial to simplifying the process flow and saving costs. Moreover, the interlayer dielectric layer 500 is usually of low hardness and easy to etch, so it is easy to form the control gate plug 520 on the top of the stacked gate structure 200, which is beneficial to improving process compatibility.

[0154] The control gate plug 520 is used to realize electrical connection between the control gate structure 220 and the outside.

[0155] In this embodiment, the material of the control gate plug 520 is tungsten. In other embodiments, the material of the control gate plug may also be cobalt or ruthenium.

[0156] The device gate plug 530 is used to realize electrical connection between the device gate structure 240 and the outside.

[0157] In this embodiment, the material of the device gate plug 530 is tungsten. In other embodiments, the material of the device gate plug may also be cobalt or ruthenium.

[0158] The bit line plug is used to realize electrical connection between the bit line region 100 b and the outside.

[0159] In this embodiment, the material of the bit line plug is tungsten. In other embodiments, the material of the bit line plug may also be cobalt or ruthenium.

[0160] In this embodiment, the device gate plug 530 and the control gate plug 520 are formed in the same step.

[0161] Forming the device gate plug 530 and the control gate plug 520 in the same step is beneficial to improving process efficiency, saving process time, and simplifying the process flow.

[0162] Specifically, refer to Fig.17 The steps of forming the bit line plug, the device gate plug 530 and the control gate plug 520 include: forming an opening 510 of the interlayer dielectric layer 500 on the top of the substrate 100 that passes through the bit line region 100b, the interlayer dielectric layer 500 on the top of the control gate structure 220, and the interlayer dielectric layer 500 on the top of the device gate structure 240.

[0163] The opening 510 is used to provide a space for forming a bit line plug, a device gate plug 530 and a control gate plug 520 .

[0164] In this embodiment, the opening 510 also penetrates the interlayer dielectric layer 500 on the top of the source-drain doped layer.

[0165] In this embodiment, the opening 510 is formed in the same step.

[0166] refer to Fig.18 , filling the opening 510 to form a bit line plug located at the top of the substrate 100 in the bit line region 100 b , a control gate plug 520 located at the top of the control gate 220 , and a device gate plug 530 located at the top of the device gate structure 240 .

[0167] In this embodiment, the opening 510 is filled in the same step.

[0168] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a storage area, wherein the storage area comprises adjacent storage cell areas and bit line areas; A stacked gate structure, located on the substrate of the memory cell region, the stacked gate structure comprising a floating gate structure and a control gate structure located on the floating gate structure; An erase gate structure, located on a substrate surrounded by opposite side walls of adjacent stacked gate structures in the memory cell region, the erase gate structure covering the side walls of the stacked gate structures on both sides; An interlayer dielectric layer is located on the substrate, and covers the top of the erase gate structure and the stacked gate structure.

2. The semiconductor structure according to claim 1, wherein: The substrate also includes a logic region; The semiconductor structure further comprises: a device gate structure, located on the substrate of the logic region; The interlayer dielectric layer also covers the top of the device gate structure.

3. The semiconductor structure according to claim 2, wherein: The top of the stacked gate structure, the top of the device gate structure and the top of the erase gate structure are flush.

4. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: a device gate plug, which penetrates the interlayer dielectric layer on the top of the device gate structure and is electrically connected to the device gate structure; A control gate plug, penetrating the interlayer dielectric layer on the top of the control gate structure and electrically connected to the control gate structure; The bit line plug penetrates the interlayer dielectric layer on the top of the substrate in the bit line area and is electrically connected to the substrate in the bit line area.

5. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a storage area, the storage area including adjacent storage cell areas and bit line areas, a stacked material layer formed on the substrate, the stacked material layer including a first gate material layer and a second gate material layer located on the first gate material layer, and a separate hard mask layer formed on the stacked material layer; Patterning the stacked material layer along the hard mask layer, retaining the stacked material layer located in the memory cell area as a stacked gate structure, the first gate material layer in the stacked gate structure as a floating gate structure, and the second gate material layer in the stacked gate structure as a control gate structure; removing the hard mask layer; After removing the hard mask layer, an erase gate structure is formed on a substrate surrounded by opposite side walls of adjacent stacked gate structures in the storage cell area, and the erase gate structure covers the side walls of the stacked gate structure on both sides; an interlayer dielectric layer covering the erase gate structure and the top of the stacked gate structure is formed on the substrate.

6. The method for forming a semiconductor structure according to claim 5, wherein: The step of removing the hard mask layer comprises: forming a blocking layer on the substrate at the side of the stacked gate structure, wherein the blocking layer covers part or all of the sidewalls of the stacked gate structure and exposes the top of the hard mask layer; The hard mask layer is removed using the blocking layer as a mask.

7. The method for forming a semiconductor structure according to claim 6, wherein: The hard mask layer is removed by a dry etching process.

8. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming a shielding layer on the substrate at the side of the stacked gate structure, the material of the shielding layer includes an organic material.

9. The method for forming a semiconductor structure according to claim 6, wherein: After removing the hard mask layer, the method further includes: removing the blocking layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The shielding layer is removed by a wet etching process.

11. The method for forming a semiconductor structure according to claim 5, wherein: The step of patterning the stacked material layer along the hard mask layer includes: patterning the second gate material layer using the hard mask layer as a mask, removing the second gate material layer exposed by the hard mask layer, and retaining the remaining second gate material layer as the control gate structure; forming a sidewall covering the control gate structure and the sidewall of the hard mask layer; Patterning the first gate material layer using the sidewall and the hard mask layer as a mask, removing the first gate material layer exposed by the sidewall and the hard mask layer, and retaining the remaining first gate material layer as the floating gate structure; In the step of forming a shielding layer on the substrate at the side of the stacked gate structure, the shielding layer at least covers the side wall of the floating gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the sidewalls covering the control gate structure and the sidewalls of the hard mask layer, and before patterning the first gate material layer using the sidewalls and the hard mask layer as masks, the method further includes: removing a portion of the thickness of the sidewalls on the opposite sidewalls of the adjacent stacked gate structure in the storage cell area.

13. The method for forming a semiconductor structure according to claim 5, wherein: In the step of providing the substrate, the substrate further includes a logic area; After removing the hard mask layer and before forming the interlayer dielectric layer, the forming method further comprises: forming a device gate structure on the substrate of the logic region; In the step of forming the interlayer dielectric layer, the interlayer dielectric layer also covers the top of the device gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The device gate structure and the erase gate structure are formed in the same step.

15. The method for forming a semiconductor structure according to claim 14, wherein: The steps of forming the device gate structure and the erase gate structure include: forming a third gate material layer covering the substrate and the stacked gate structure; The third gate material layer is patterned with the top of the stacked gate structure as the etching stop position to form an erase gate structure located in the storage cell area on a substrate surrounded by opposite side walls of adjacent stacked gate structures, and a device gate structure located in the logic area.

16. The method for forming a semiconductor structure according to claim 13, wherein: After forming the interlayer dielectric layer, the forming method further comprises: forming a control gate plug penetrating the interlayer dielectric layer on the top of the control gate and electrically connected to the control gate structure; forming a device gate plug penetrating through the interlayer dielectric layer on the top of the device gate structure and electrically connected to the device gate structure; A bit line plug is formed which penetrates the interlayer dielectric layer on the top of the substrate in the bit line region and is electrically connected to the substrate in the bit line region.

17. The method for forming a semiconductor structure according to claim 16, wherein: The control gate plug and the device gate plug are formed in the same step.

18. The method for forming a semiconductor structure according to claim 17, wherein: The steps of forming the bit line plug, the control gate plug and the device gate plug include: forming an opening of the interlayer dielectric layer on the top of the substrate of the bit line region, the interlayer dielectric layer on the top of the control gate structure, and the interlayer dielectric layer on the top of the device gate structure; The opening is filled to form a bit line plug located on the top of the substrate in the bit line region, a control gate plug located on the top of the control gate, and a device gate plug located on the top of the device gate structure.

19. The method for forming a semiconductor structure according to claim 5, wherein: In the step of providing the substrate, the material of the hard mask layer includes silicon nitride; In the step of forming an interlayer dielectric layer on the substrate to cover the erase gate structure and the stacked gate structure, the material of the interlayer dielectric layer includes silicon oxide.

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