High electron mobility transistor and preparation method thereof

Abstract

The invention provides a high electron mobility transistor and a preparation method thereof. The transistor comprises a substrate. And the heterojunction structure layer is arranged on one side of the substrate. And the functional layer is arranged on one side, far away from the substrate, of the heterojunction structure layer. And the source electrode is arranged on the first side of the functional layer, and at least part of the source electrode is embedded into the heterojunction structure layer. The drain electrode is arranged on the second side of the functional layer, at least part of the drain electrode is embedded into the heterojunction structure layer, and the first side and the second side are opposite sides. And the grid is arranged on one side, far away from the substrate, of the functional layer. Wherein the heterojunction structure layer comprises a channel layer, the channel layer is used for providing a transmission channel for two-dimensional electron gas, the functional layer comprises a doping layer, and the doping layer is used for providing free electrons for the channel layer. According to the transistor disclosed by the invention, the doping layer capable of providing free electrons is arranged, so that the two-dimensional electron gas density at the interface of the channel layer can be increased, the carrier mobility of the channel is not influenced, and a high-frequency and high-power GaN-based HEMT device can be further obtained.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor transistors, and in particular to a high electron mobility transistor and a method for preparing the same. Background Art

[0002] As a third-generation semiconductor, GaN-based materials have attracted widespread attention due to their adjustable wide bandgap, high breakdown electric field, and high saturation velocity. High Electron Mobility Transistor (HEMT) made from GaN-based materials has excellent high-frequency and high-power characteristics and is the core device of millimeter-wave amplifiers.

[0003] However, the traditionally designed GaN-based HEMT has difficulty in achieving a balance between carrier density and carrier mobility, making it difficult for the device to simultaneously possess high frequency and high power characteristics. Summary of the invention

[0004] In view of the above problems, embodiments of the present disclosure provide a high electron mobility transistor and a method for manufacturing the same.

[0005] One aspect of the present disclosure provides a high electron mobility transistor, comprising: a substrate. A heterojunction structure layer, arranged on one side of the substrate. A functional layer, arranged on a side of the heterojunction structure layer away from the substrate. A source electrode, arranged on a first side of the functional layer, and at least partially embedded in the heterojunction structure layer. A drain electrode, arranged on a second side of the functional layer, and at least partially embedded in the heterojunction structure layer, the first side and the second side being opposite sides. A gate electrode, arranged on a side of the functional layer away from the substrate. The heterojunction structure layer includes a channel layer, the channel layer is used to provide a transmission channel for a two-dimensional electron gas, and the functional layer includes a doping layer, the doping layer is used to provide free electrons to the channel layer.

[0006] According to an embodiment of the present disclosure, the functional layer further includes: a cap layer, which is disposed on a side of the doping layer away from the substrate, and the cap layer is used to protect the doping layer and provide a passivation effect.

[0007] According to an embodiment of the present disclosure, the functional layer further includes: at least one of a first buffer layer and an isolation layer, wherein the first buffer layer is disposed between the heterojunction structure layer and the doping layer, and the isolation layer is disposed between the doping layer and the cap layer.

[0008] According to an embodiment of the present disclosure, the material of the doping layer is a GaN-based material doped with Si or Ge, and the doping concentration is 1×10 12 cm -2 ~1×10 21 cm -2 . The thickness of the doping layer is less than or equal to 10 nm.

[0009] According to an embodiment of the present disclosure, the gate electrode is partially embedded in or penetrates the functional layer.

[0010] According to an embodiment of the present disclosure, at least one of the first buffer layer and the isolation layer has a thickness of 0 nm to 100 nm, and the cap layer has a thickness of 0 nm to 50 nm.

[0011] According to an embodiment of the present disclosure, the heterojunction structure layer further includes: at least one of an insertion layer and a barrier layer arranged in sequence. The channel layer is in contact with the surfaces of the opposite sides of the source and the drain, respectively, and the insertion layer is located between the channel layer and the barrier layer. The insertion layer is used to reduce interlayer stress and electron scattering, and the barrier layer is used to provide a polarization effect to form a two-dimensional electron gas at the interface of the channel layer away from the substrate.

[0012] According to an embodiment of the present disclosure, at least one of the source and the drain comprises: a material layer, which is arranged on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer. A first metal layer, which is arranged on a side of the material layer away from the substrate. The material layer is an n-type doped gallium nitride-based material. Or a second metal layer, which is arranged on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer.

[0013] According to an embodiment of the present disclosure, the high electron mobility transistor further includes: a second buffer layer, which is disposed between the substrate and the heterojunction structure layer, and the thickness of the second buffer layer is 0 nm to 500 μm.

[0014] Another aspect of the present disclosure provides a method for preparing a high electron mobility transistor, comprising: depositing a heterojunction structure layer and a functional layer in sequence on one side of a substrate, the heterojunction structure layer comprising a channel layer, the channel layer being used to provide a transmission channel for a two-dimensional electron gas, and the functional layer comprising a doping layer, the doping layer being used to provide free electrons to the channel layer. Etching the functional layer and the heterojunction structure layer to obtain two grooves that do not penetrate the heterojunction structure layer, the two grooves being located on opposite sides of the functional layer. Depositing a source electrode and a drain electrode in the two grooves respectively. And depositing a gate electrode on the side of the functional layer away from the substrate to obtain a high electron mobility transistor.

[0015] The present disclosure arranges a doping layer having the function of providing free electrons above the heterojunction structure layer in a non-polarized manner, thereby increasing the two-dimensional electron gas density at the interface of the channel layer without affecting the channel carrier mobility, thereby reducing the material square resistance of the GaN-based HEMT channel, and thus obtaining a high-frequency and high-power GaN-based HEMT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 Schematically shows a cross-sectional structure diagram of a high electron mobility transistor according to an embodiment of the present disclosure;

[0018] Figure 2 Schematically shows a cross-sectional structure diagram of a high electron mobility transistor according to another embodiment of the present disclosure;

[0019] Figure 3 The flowchart of the method for preparing a high electron mobility transistor according to an embodiment of the present disclosure is schematically shown.

[0020] [Description of Reference Numerals]

[0021] 1-substrate; 2-heterojunction structure layer; 3-functional layer; 31-doping layer; 32-cap layer; 33-first buffer layer; 34-isolation layer; 4-source; 5-drain; 6-gate; 7-second buffer layer. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0023] It should be noted that in the drawings or descriptions, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form a new solution without conflict. In addition, each claim can be used as an embodiment alone or the technical features in each claim can be combined as a new embodiment. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are in a form known to a person of ordinary skill in the art. In addition, although demonstrations of parameters containing specific values ​​may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0024] Unless there are technical obstacles or contradictions, the above-mentioned various embodiments of the present disclosure can be freely combined to form additional embodiments, and these additional embodiments are all within the protection scope of the present disclosure.

[0025] Although the present disclosure is described in conjunction with the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to exemplify the preferred embodiments of the present disclosure and should not be construed as limiting the present disclosure. The dimensional ratios in the accompanying drawings are merely illustrative and should not be construed as limiting the present disclosure.

[0026] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

[0027] Figure 1 The cross-sectional structure of a high electron mobility transistor according to an embodiment of the present disclosure is schematically shown.

[0028] According to the embodiments of the present disclosure, Figure 1 As shown, the present disclosure provides a high electron mobility transistor, comprising: a substrate 1. A heterojunction structure layer 2, arranged on one side of the substrate 1. A functional layer 3, arranged on a side of the heterojunction structure layer 2 away from the substrate 1. A source electrode 4, arranged on a first side of the functional layer 3, and at least partially embedded in the heterojunction structure layer 2. A drain electrode 5, arranged on a second side of the functional layer 3, and at least partially embedded in the heterojunction structure layer 2, the first side and the second side being opposite sides. A gate electrode 6, arranged on a side of the functional layer 3 away from the substrate 1. The heterojunction structure layer 2 includes a channel layer, the channel layer is used to provide a transmission channel for the two-dimensional electron gas, and the functional layer 3 includes a doping layer 31, the doping layer 31 is used to provide free electrons to the channel layer.

[0029] In some embodiments, the substrate is made of high-quality semiconductor materials, such as silicon (Si), sapphire (Al2O3), gallium nitride (GaN) or silicon carbide (SiC). Based on the substrate, the growth of other layers can be better controlled, defects and impurities can be reduced, and the quality can be improved. At the same time, the stress distribution of other layers can be optimized, stress concentration can be reduced, and the stability and reliability of the device can be improved.

[0030] For example, a heterojunction structure layer can be grown directly on a substrate and is composed of two or more semiconductor materials with different energy band structures, such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN). Among them, the AlGaN layer forms a heterojunction interface with the GaN layer due to its wider bandgap and higher conduction band bottom energy. Due to the band bending effect, a two-dimensional electron gas (2DEG) channel will spontaneously form at this interface.

[0031] For another example, the material type of the channel layer includes but is not limited to GaN, AlGaN or InGaN, and the thickness is 0 nm to 100 μm.

[0032] The heterojunction structure layer can provide an effective electron transmission channel. In a gallium nitride-based high electron mobility transistor with a functional layer, electrons are mainly transmitted in the channel layer. By optimizing the material and energy level structure of the channel layer, the electron transport behavior can be controlled to achieve efficient electron injection and collection.

[0033] The functional layer is located on the heterojunction structure layer and is mainly composed of one or more layers of semiconductor materials with a specific doping concentration. Among them, it includes a doped layer, which is introduced by ion implantation or epitaxial growth technology. Its main component is the same as or compatible with the material in the heterojunction structure layer, but after n-type heavy doping treatment, it can provide abundant free electrons. These free electrons can cross the heterojunction interface under the action of the electric field and enter the 2DEG channel in the channel layer, thereby increasing the carrier density. At the same time, since the doped layer contains free electrons, it can also shield the surface charge, reduce the electric field strength of the barrier layer, and suppress the current collapse phenomenon of the device.

[0034] The source and drain are located on the first side and the second side (opposite sides) of the functional layer, respectively, and are symmetrical about the gate. They are at least partially embedded in the heterojunction structure layer to ensure good electrical contact and current injection / extraction efficiency. The source and drain materials can be, for example, metals or alloys with low resistivity, such as titanium (Ti) / aluminum (Al) / nickel (Ni) / gold (Au) multilayer structures.

[0035] The gate is set on the side of the functional layer away from the substrate, and can be isolated from the 2DEG channel below by a thin insulating medium (such as silicon nitride Si3N4 or silicon dioxide SiO2). The gate material is also made of low-resistivity metal or alloy, and its shape and size design must meet the effective control of the channel current. The gate bias can adjust the electron concentration in the 2DEG channel, thereby controlling the on and off state of the transistor.

[0036] For example, the gate is a strip structure, and the cross-section includes but is not limited to T-shaped, square and other polygonal shapes, and the material type includes but is not limited to alloys such as Ni / Au, Pt / Au, Mo / Au, Ni / Al / Ti / Au, etc. The gate and the top structure of the heterojunction structure layer form a Schottky barrier, which can control the injection and transmission behavior of electrons. By adjusting the height and width of the barrier, the switching characteristics of the transistor can be effectively controlled.

[0037] In the heterojunction structure layer, especially the channel layer formed at the AlGaN / GaN interface, it is the main transmission channel for the two-dimensional electron gas. These two-dimensional electron gases have extremely high electron mobility and concentration, which is the key to achieving the high-frequency and high-power characteristics of HEMT.

[0038] In order to further optimize device performance, the growth process of the heterojunction structure layer and the functional layer requires strict control of material quality, doping concentration and interface flatness.

[0039] The metallization process of the source, drain and gate must ensure good ohmic contact and Schottky contact characteristics. The thickness and quality of the gate insulating dielectric have an important influence on key parameters such as the threshold voltage, transconductance and leakage current of the device. By precisely controlling the doping concentration and depth of the doping layer, the relationship between carrier density and mobility can be further balanced to achieve more efficient current transmission.

[0040] This embodiment effectively improves the density of two-dimensional electron gas carriers at the interface of the channel layer by setting a doping layer with the function of providing free electrons above the heterojunction structure layer, while maintaining the high mobility of the channel carriers. The material square resistance of the GaN-based HEMT (high electron mobility transistor) channel is reduced, thereby making it possible to realize high-frequency and high-power GaN-based HEMT devices, which has broad application prospects in microwave, millimeter wave communications, radar, power electronics and other fields.

[0041] According to the embodiments of the present disclosure, Figure 1 As shown, the functional layer 3 further includes: a cap layer 32, which is arranged on a side of the doping layer 31 away from the substrate 1, and the cap layer 32 is used to protect the doping layer 31 and provide a passivation effect.

[0042] In some embodiments, the structures of the substrate, the heterojunction structure layer, the channel layer, the source electrode, the drain electrode and the gate electrode are the same as those in the above embodiments and are not described in detail.

[0043] While maintaining the doping layer, this embodiment adds a cap layer on the side of the doping layer away from the substrate.

[0044] The main function of the cap layer is to protect the other parts of the functional layer below and the barrier layer from the external environment (such as moisture, pollutants, etc.), while providing passivation to reduce the impact of surface states on the transport of two-dimensional electron gas, thereby reducing current collapse, and further reducing the DC-RF dispersion of the GaN-based high electron mobility transistor during operation, thereby improving the stability and reliability of the device.

[0045] The cap layer material can be a semiconductor material or insulating material that is compatible with the heterojunction structure layer, such as silicon nitride (Si3N4), aluminum oxide (Al2O3) or aluminum nitride (AlN). Its thickness needs to be thin enough to maintain good electrical properties and thick enough to provide adequate protection.

[0046] For example, the thickness of the cap layer is 0 nm to 50 nm.

[0047] This embodiment enhances the design of the functional layer by adding a cap layer, which not only provides effective protection for the doped layer, but also reduces the interface state density, thereby improving the stability and reliability of the device.

[0048] According to the embodiments of the present disclosure, Figure 1As shown, the functional layer 3 further includes: at least one of a first buffer layer 33 and an isolation layer 34. The first buffer layer 33 is disposed between the heterojunction structure layer 2 and the doping layer 31, and the isolation layer 34 is disposed between the doping layer 31 and the cap layer 32.

[0049] In some embodiments, a first buffer layer is added between the heterojunction structure layer and the doping layer, and an isolation layer is added between the doping layer and the cap layer.

[0050] The first buffer layer is arranged between the heterojunction structure layer and the doping layer. Its main function is to relieve the lattice mismatch and stress at the heterojunction interface and reduce the dislocation density, thereby improving the performance and reliability of the device. The first buffer layer material is usually a semiconductor material compatible with the heterojunction structure layer, and its thickness and doping concentration need to be carefully designed to achieve the best lattice matching and stress relief effect.

[0051] The isolation layer is set between the doped layer and the cap layer. Its main function is to isolate the electrical interference between the doped layer and the cap layer, prevent the cap layer material from having adverse effects on the doped layer, and provide additional passivation to further reduce the interface state density. The thickness of the isolation layer needs to be thin enough to maintain good electrical properties, and thick enough to provide effective isolation.

[0052] For example, the first buffer layer and the isolation layer are undoped gallium nitride-based materials, the thickness of the first buffer layer is 0 nm to 100 nm, and the thickness of the isolation layer is 0 nm to 100 nm.

[0053] This embodiment provides a more detailed enhancement design for the functional layer by adding a first buffer layer and an isolation layer. The first buffer layer effectively alleviates the lattice mismatch and stress at the heterojunction interface, improving the performance and reliability of the device; the isolation layer isolates the electrical interference between the doped layer and the cap layer, further reducing the interface state density.

[0054] According to an embodiment of the present disclosure, the material of the doping layer is a GaN-based material doped with Si or Ge, and the doping concentration is 1×10 12 cm -2 ~1×10 21 cm -2 . The thickness of the doping layer is less than or equal to 10 nm.

[0055] In some embodiments, the material of the doping layer is, for example, a GaN-based material doped with Si or Ge. Si and Ge, as n-type dopants, can effectively provide free electrons in the GaN-based material and increase the carrier density of the two-dimensional electron gas (2DEG) at the interface of the channel layer. The doping concentration is controlled at 1×10 12 cm -2 ~1×10 21 cm -2The concentration range is selected to balance the relationship between carrier density and mobility to achieve optimal device performance. At the same time, the thickness of the doping layer can be controlled to be less than or equal to 10nm, such as 5nm, 1nm and atomic level to ensure good electrical performance and process feasibility.

[0056] This embodiment realizes effective regulation of the two-dimensional electron gas carrier density at the channel layer interface by selecting Si or Ge-doped GaN-based materials and controlling the doping concentration and thickness.

[0057] According to an embodiment of the present disclosure, the gate 6 is partially embedded in or penetrates the functional layer 3 .

[0058] In some embodiments, for example, the metallization portion of the gate is embedded into the functional layer through specific process steps (such as photolithography, etching, etc.), but does not completely penetrate the functional layer to reach the underlying heterojunction structure layer. This design allows the gate electric field to more effectively modulate the two-dimensional electron gas (2DEG) in the channel layer, thereby providing more precise current control capabilities.

[0059] For example, the gate is designed to completely penetrate the functional layer and contact the heterojunction structure layer. This design further enhances the gate's ability to control the channel current, but also requires more sophisticated process control to avoid damage to the channel layer.

[0060] It is understandable that no matter whether the gate is partially embedded or penetrates the functional layer, a thin insulating medium (such as silicon nitride, silicon dioxide, etc.) is required to isolate it from the 2DEG channel below. The thickness, quality and uniformity of this insulating medium have an important impact on the performance of the device.

[0061] This embodiment describes the structure of the gate, and realizes a special structure in which the gate is partially embedded in or penetrates the functional layer. This design not only enhances the gate's ability to control the channel current, but also provides a more sophisticated current modulation characteristic for the HEMT device.

[0062] According to an embodiment of the present disclosure, at least one of the first buffer layer 33 and the isolation layer 34 has a thickness of 0 nm to 100 nm, and the cap layer 32 has a thickness of 0 nm to 50 nm.

[0063] In some embodiments, when the first buffer layer is present, its thickness is controlled to be in the range of 0 nm to 100 nm. This thickness is selected to alleviate the lattice mismatch and stress at the heterojunction interface while maintaining good electrical properties. In practical applications, the thickness of the first buffer layer may need to be fine-tuned according to specific material properties, equipment conditions, and performance requirements.

[0064] When the isolation layer is present, its thickness is also controlled to be in the range of 0 nm to 100 nm. The selection of this thickness is intended to isolate the electrical interference between the doped layer and the cap layer, while providing additional passivation.

[0065] It should be noted that if the isolation layer is too thick, it may increase the series resistance of the device and reduce its performance; if it is too thin, it may not provide effective isolation. Therefore, in practical applications, the thickness of the isolation layer needs to be reasonably designed.

[0066] The thickness of the cap layer is controlled in the range of 0nm to 50nm. This thickness is chosen to provide sufficient protection while maintaining good electrical properties.

[0067] To ensure good contact and interface quality between the layers, specific process steps (such as cleaning, passivation, etc.) may be required to reduce interface state density and contamination.

[0068] This embodiment achieves further improvement in the performance of the HEMT device by precisely controlling the thickness of the relevant layers.

[0069] According to the embodiments of the present disclosure, Figure 1 As shown, the heterojunction structure layer 2 further includes: at least one of an insertion layer and a barrier layer which are sequentially arranged. The channel layer is in contact with the surfaces of the opposite sides of the source 4 and the drain 5, respectively, and the insertion layer is located between the channel layer and the barrier layer. The insertion layer is used to reduce interlayer stress and electron scattering, and the barrier layer is used to provide a polarization effect to form a two-dimensional electron gas at the interface of the channel layer away from the substrate 1.

[0070] In some embodiments, the channel layer is, for example, located on the substrate and made of a semiconductor material having a different energy band structure from the substrate material to form a two-dimensional electron gas (2DEG) channel. The channel layer is in contact with the opposite sides of the source and drain, respectively, to allow current to flow between the source and drain.

[0071] The insertion layer is located between the channel layer and the barrier layer and is made of semiconductor materials with specific energy band structures and lattice constants. The insertion layer can improve the interface quality between the channel layer and the barrier layer, reduce the interface state density, and reduce the impact of interface scattering on electron transmission, thereby improving the performance and stability of the transistor.

[0072] For example, the material type of the insertion layer includes but is not limited to AlN, SiN or InN, and the thickness is 0 nm to 50 nm.

[0073] The barrier layer is located on the insertion layer (if an insertion layer exists), or directly on the channel layer (if no insertion layer exists). The barrier layer is made of a semiconductor material with a high energy band gap to provide piezoelectric polarization and spontaneous polarization effects. This polarization effect forms one or more two-dimensional electron gas channels at the interface of the channel layer away from the substrate. This layer of two-dimensional electron gas is very thin, with almost no thickness, but has a high surface density and mobility. At the same time, the insertion layer also provides a part of the polarization effect, which can reduce interlayer stress and electron scattering and improve mobility.

[0074] For example, the material type of the barrier layer includes but is not limited to AlN, InAlN, AlGaN or InGaN, and the thickness is 0nm~50nm. The barrier layer plays a role in modulating the electric field in the heterojunction structure layer. By adjusting the thickness of the barrier layer, the electric field distribution can be changed, further affecting the transmission behavior of electrons.

[0075] It can be understood that the channel layer, the insertion layer and the barrier layer are all in contact with the surface opposite to the source and the drain.

[0076] This embodiment reduces the stress and electron scattering between the channel layer and the barrier layer by introducing an insertion layer, thereby improving the mobility of 2DEG. At the same time, the barrier layer provides a polarization effect, forming a high-quality 2DEG channel.

[0077] According to the embodiments of the present disclosure, Figure 1 As shown, at least one of the source 4 and the drain 5 includes: a material layer 41, which is arranged on a side of the heterojunction structure layer 2 away from the substrate 1 and at least partially embedded in the heterojunction structure layer 2. A first metal layer 42, which is arranged on a side of the material layer 41 away from the substrate 1. The material layer 41 is an n-type doped gallium nitride-based material. Or a second metal layer, which is arranged on a side of the heterojunction structure layer 2 away from the substrate 1 and at least partially embedded in the heterojunction structure layer 2.

[0078] In some embodiments, the structures of the source and the drain are described. The source and the drain, for example, both include a material layer and a metal layer.

[0079] The material layer is arranged on a side of the heterojunction structure layer away from the substrate, and is at least partially embedded in the heterojunction structure layer. The material layer is made of n-type doped gallium nitride-based material, which has excellent conductivity and good compatibility with the heterojunction structure layer. The embedded design of the material layer helps to enhance the electrical contact between the source and drain and the heterojunction structure layer, and reduce the contact resistance.

[0080] For example, the material layer is a regrown high-concentration n-type doped gallium nitride-based material, the material type includes but is not limited to GaN, AlGaN, InGaN, the thickness is, for example, 0nm~100μm, and the n-type doping concentration is 1e 15 cm-3 ~1e 20 cm -3 The selection of this concentration range provides greater flexibility for the material layer, and the appropriate concentration can be selected according to actual needs to optimize the specific or main performance of the device.

[0081] At the same time, when the thickness of the material layer is less than the depth of the epitaxial groove (i.e., the embedded functional layer and the heterojunction structure layer), poor contact may occur between the metal and the material layer in the vertical direction, or between the material layer and the two-dimensional electron gas in the horizontal direction. Therefore, the thickness of the material layer is greater than or equal to the depth of the epitaxial groove.

[0082] The first metal layer is disposed on a side of the material layer away from the substrate, and is used to provide a connection with an external circuit. The first metal layer may be made of a metal material with high conductivity and good stability. An ohmic contact may be formed between the first metal layer and the material layer to ensure that current flows smoothly between the source and the drain.

[0083] As another option, the source and drain can also be directly formed by the second metal layer, which is arranged on the side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer. A good ohmic contact needs to be formed between the second metal layer and the heterojunction structure layer.

[0084] For example, the material types of the first metal layer and the second metal layer include but are not limited to alloys such as Ti / Au, Al / Au, Ti / Al / Ti / Au, and Ti / Al / Ni / Au.

[0085] The first metal layer or the second metal layer, as the main current output and collection electrode of the transistor, can realize efficient and stable current transmission, and export electrons from the inside of the transistor and transport them to the external circuit. At the same time, the first metal layer or the second metal layer, as the connection point between the transistor and the external circuit, can realize the effective integration of the transistor and the external circuit.

[0086] In this embodiment, by introducing an n-type doped gallium nitride-based material layer as a part of the source and drain, and at least partially embedding it in the heterojunction structure layer, the electrical contact between the source and drain and the heterojunction structure layer is enhanced, and the contact resistance is reduced. At the same time, the provision of the first metal layer or the second metal layer provides a stable connection with an external circuit.

[0087] Figure 2 The cross-sectional structure of a high electron mobility transistor according to another embodiment of the present disclosure is schematically shown.

[0088] According to the embodiments of the present disclosure, Figure 2 As shown, the high electron mobility transistor further includes: a second buffer layer 7 disposed between the substrate 1 and the heterojunction structure layer 2, and the thickness of the second buffer layer 7 is 0 nm to 500 μm.

[0089] In some embodiments, a second buffer layer is added between the substrate and the heterojunction structure layer.

[0090] The second buffer layer may be made of a semiconductor material that is compatible with the substrate and the heterojunction structure layer, such as GaN, AlN, SiC, etc.

[0091] The thickness of the second buffer layer is, for example, between 0 nm and 500 μm, such as 100 μm. The thickness design within this range is intended to optimize lattice matching, reduce stress accumulation, and improve the electrical performance of the device.

[0092] When the thickness is 0 nm, it indicates that the substrate is in direct contact with the heterojunction structure layer, which generally requires excellent lattice matching between the substrate and the heterojunction structure layer.

[0093] When the thickness is between a few nanometers and tens of nanometers, the second buffer layer mainly plays the role of lattice transition and stress relief.

[0094] When the thickness reaches tens of microns or even close to 500 μm, the second buffer layer not only has the functions of lattice transition and stress relief, but may also have a positive impact on the heat dissipation performance of the device.

[0095] For example, a nucleation layer may be added between the substrate and the second buffer layer. The main function of the nucleation layer is to control the nucleation process of material growth and promote more uniform, orderly and consistent growth of the material on the substrate.

[0096] In this embodiment, by selecting a buffer layer with a suitable energy level, the energy level matching between the heterojunction structure layer and the substrate can be adjusted, thereby optimizing the electron transport characteristics of the transistor. At the same time, by selecting an appropriate buffer layer material and thickness, the carrier concentration of the heterojunction can be adjusted, further optimizing the conductive characteristics of the transistor.

[0097] Figure 3 The flowchart of the method for preparing a high electron mobility transistor according to an embodiment of the present disclosure is schematically shown.

[0098] Another aspect of the present disclosure provides a method for preparing a high electron mobility transistor, such as Figure 3 As shown, for example, it includes: operations S310~S340.

[0099] In operation S310, a heterojunction structure layer 2 and a functional layer 3 are sequentially deposited on one side of a substrate 1, wherein the heterojunction structure layer 2 includes a channel layer for providing a transmission channel for a two-dimensional electron gas, and the functional layer 3 includes a doping layer 31 for providing free electrons to the channel layer.

[0100] For example, semiconductor materials such as high-resistance silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or sapphire (Al2O3) are used as substrates. Chemical solutions are used to clean the substrate surface to remove contaminants and ensure the uniformity and adhesion of subsequent deposited layers.

[0101] For example, a heterojunction structure layer and a functional layer may be sequentially deposited on one side of the substrate using techniques such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD), atomic layer deposition, etc.

[0102] The heterojunction structure layer includes a channel layer, and the channel layer material, such as GaN, is used to provide a transmission channel for the two-dimensional electron gas (2DEG). The thickness and doping concentration of the channel layer need to be precisely controlled to optimize the concentration and mobility of 2DEG.

[0103] The functional layer includes a doping layer. The doping layer material can be n-type doped GaN or AlGaN, and doping elements such as silicon (Si) or germanium (Ge) are used to provide free electrons to the channel layer. The thickness and doping concentration of the doping layer need to be precisely adjusted according to the device performance requirements.

[0104] In operation S320 , the functional layer 3 and the heterojunction structure layer 2 are etched to obtain two grooves that do not penetrate the heterojunction structure layer, and the two grooves are located at opposite sides of the functional layer 3 .

[0105] The functional layer and the heterojunction structure layer are patterned using photolithography and etching techniques to obtain two grooves that do not penetrate the heterojunction structure layer. The depth of the grooves ranges from 0 to 100 μm, for example. At the same time, all other areas outside the device area are etched as a whole to reduce the height by about 50 nm, thereby preventing the device from leaking electricity to the surrounding area.

[0106] The two grooves are, for example, located at opposite sides of the functional layer for subsequent deposition of the source and drain electrodes. The depth of the grooves needs to be precisely controlled to ensure that the source and drain electrodes form good ohmic contacts with the channel layer.

[0107] In operation S330 , a source electrode 4 and a drain electrode 5 are respectively deposited in the two grooves.

[0108] Source and drain materials are deposited in the two grooves respectively.

[0109] The source and drain materials may be metals or alloys, such as a titanium / aluminum / nickel / gold (Ti / Al / Ni / Au) multilayer structure, to provide good electrical contact and current transmission performance.

[0110] After deposition, an annealing process is performed to enhance the ohmic contact between the source and drain electrodes and the channel layer.

[0111] In operation S340 , a gate 6 is deposited on a side of the functional layer 3 away from the substrate 1 to obtain a high electron mobility transistor.

[0112] A gate material is deposited on the side of the functional layer facing away from the substrate.

[0113] The gate material can be a metal or a metal nitride, such as nickel / gold (Ni / Au) or titanium nitride (TiN), which is used to control the 2DEG concentration in the channel.

[0114] A layer of insulating medium, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), is deposited between the gate and the functional layer to isolate the gate from the channel layer and prevent the gate from leaking current.

[0115] Example 1

[0116] For example, the size of the substrate is 2 inches and the material is sapphire.

[0117] The material of the second buffer layer is Fe-doped high-resistance GaN, and the thickness is 200 nm.

[0118] The heterojunction structure layer includes a channel layer, an insertion layer and a barrier layer. The channel layer is made of GaN with a thickness of 2 μm. The insertion layer is made of AlN with a thickness of 1 nm. The barrier layer is made of In 0.17 AlN, thickness is 7nm.

[0119] The first buffer layer is made of unintentionally doped GaN with a thickness of 9nm. The delta-doping planar doping layer (i.e. the above-mentioned doping layer) has a thickness of 0.5nm and is made of Si-doped GaN with a doping concentration of 5E 12 cm -2 The thickness of the isolation layer is 7nm and the material is unintentionally doped GaN. The thickness of the cap layer is 1nm and the material is SiN.

[0120] The heterostructure layer is etched by ICP method to form epitaxial grooves in the source / drain region with a depth of 70nm.

[0121] A metal layer of a gate is deposited on the heterojunction structure layer. The material is Ni / Au with a thickness of 80nm / 120nm.

[0122] After cleaning the surface of the epitaxial groove, a material layer is selectively grown in the epitaxial groove along the epitaxial growth direction as the source and drain region of the GaN-based HEMT device with an ohmic contact interface passivation layer, with a thickness of 90nm and a doping concentration of 3e 19 cm -3 .

[0123] A metal layer of source and drain is deposited on the material layer. The material is Ti / Au with a thickness of 70nm / 130nm.

[0124] Necessary cleaning, drying and packaging processes can be performed later to ensure the stability and reliability of the device. The device performance can also be tested, including key parameters such as current-voltage (IV) characteristics, transconductance (gm) and cutoff frequency (ft), to verify whether the device performance meets the design requirements.

[0125] This embodiment successfully fabricated a high electron mobility transistor with excellent electrical performance by precisely controlling the material, thickness and doping concentration of each layer and optimizing the photolithography and etching processes. This method is applicable to microwave, millimeter wave communications, radar, power electronics and other fields, and has broad application prospects.

[0126] Any details not included in the method example section are similar to those in the product example section. Please refer to the product example section and will not be repeated here.

[0127] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The attached method claims present the elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.

[0128] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. In addition, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships.

[0129] In the above detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are clearly stated in each claim. On the contrary, as reflected in the attached claims, the disclosure is in a state of having less than all the features of the disclosed individual embodiments. Therefore, the attached claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the disclosure.

[0130] In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", as explained in terms of "including," used as a transitional word in the claims. Any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0131] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A high electron mobility transistor, characterized in that: include: substrate; A heterojunction structure layer is disposed on one side of the substrate; A functional layer is disposed on a side of the heterojunction structure layer away from the substrate; A source electrode, disposed on the first side of the functional layer and at least partially embedded in the heterojunction structure layer; a drain electrode, disposed on a second side of the functional layer and at least partially embedded in the heterojunction structure layer, wherein the first side and the second side are opposite sides; A gate is arranged on a side of the functional layer away from the substrate; The heterojunction structure layer includes a channel layer, and the channel layer is used to provide a transmission channel for the two-dimensional electron gas. The functional layer includes a doping layer, and the doping layer is used to provide free electrons to the channel layer.

2. The high electron mobility transistor according to claim 1, characterized in that: The functional layer also includes: The cap layer is arranged on a side of the doped layer away from the substrate, and the cap layer is used to protect the doped layer and provide a passivation effect.

3. The high electron mobility transistor according to claim 2, characterized in that: The functional layer also includes: at least one of a first buffer layer and an isolation layer; Wherein, the first buffer layer is arranged between the heterojunction structure layer and the doping layer, and the isolation layer is arranged between the doping layer and the cap layer.

4. The high electron mobility transistor according to claim 1, characterized in that: The material of the doping layer is Si or Ge doped GaN-based material, and the doping concentration is 1×10 12 cm -2 ~1×10 21 cm -2 ; The thickness of the doping layer is less than or equal to 10 nm.

5. The high electron mobility transistor according to claim 1, characterized in that: The gate electrode is partially embedded in or penetrates the functional layer.

6. The high electron mobility transistor according to claim 3, characterized in that: At least one of the first buffer layer and the isolation layer has a thickness of 0 nm to 100 nm, and the cap layer has a thickness of 0 nm to 50 nm.

7. The high electron mobility transistor according to claim 1, characterized in that: The heterojunction structure layer further includes: at least one of an insertion layer and a barrier layer disposed in sequence; The channel layer is in contact with the surfaces on opposite sides of the source and the drain respectively, the insertion layer is located between the channel layer and the barrier layer, the insertion layer is used to reduce interlayer stress and electron scattering, and the barrier layer is used to provide a polarization effect to form the two-dimensional electron gas at the interface of the channel layer away from the substrate.

8. The high electron mobility transistor according to claim 1, characterized in that: At least one of the source and the drain comprises: A material layer, disposed on a side of the heterojunction structure layer away from the substrate and at least partially embedded in the heterojunction structure layer; A first metal layer is disposed on a side of the material layer away from the substrate; Wherein, the material layer is an n-type doped gallium nitride-based material; or The second metal layer is arranged on a side of the heterojunction structure layer away from the substrate and is at least partially embedded in the heterojunction structure layer.

9. The high electron mobility transistor according to claim 1, characterized in that: Also includes: The second buffer layer is arranged between the substrate and the heterojunction structure layer, and the thickness of the second buffer layer is 0 nm to 500 μm.

10. A method for preparing a high electron mobility transistor, characterized in that: include: Depositing a heterojunction structure layer and a functional layer in sequence on one side of the substrate, wherein the heterojunction structure layer includes a channel layer, the channel layer is used to provide a transmission channel for the two-dimensional electron gas, and the functional layer includes a doping layer, the doping layer is used to provide free electrons to the channel layer; Etching the functional layer and the heterojunction structure layer to obtain two grooves that do not penetrate the heterojunction structure layer, and the two grooves are respectively located at opposite sides of the functional layer; Depositing a source electrode and a drain electrode in the two grooves respectively; as well as A gate is deposited on a side of the functional layer away from the substrate to obtain the high electron mobility transistor.

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