Multi-junction hafnium oxide-based ferroelectric transistor and three-dimensional integrated preparation method
By adopting a multi-junction hafnium oxide-based ferroelectric transistor structure in the third generation semiconductor channel device, and using magnetron sputtering to stack layered vertical channels, four pairs of PN junctions are formed, the problem of sharp increase in electron mobility after heat treatment is solved, and a higher switching ratio and response rate is achieved, reducing power consumption.
Patent Information
- Application Number
- CN202510191375.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-05-16
AI Technical Summary
The electron mobility of the third-generation semiconductor channel devices has increased sharply after heat treatment, making it difficult for the device to control the disconnection of the channel, resulting in the problem of small switches and poor gate control capabilities.
Using a multi-junction hafnium oxide-based ferroelectric transistor structure, the P-type and N-type semiconductor channel materials are stacked by magnetron sputtering to form layered vertical channels in the order of N/P/N/P/N stacking to form four pairs of PN junctions to improve the switching ratio and response rate.
The switching ratio is improved, and the storage data error phenomenon caused by large junction current under high integration is reduced, power consumption is reduced, and the response rate is improved to meet the development needs of advanced microelectronic devices.
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Figure CN120018555A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of microelectronic devices, and in particular to a multi-junction hafnium oxide-based ferroelectric transistor and a three-dimensional integrated preparation method. Background Art
[0002] Since hafnium oxide was experimentally found to have ferroelectricity in 2011, hafnium oxide-based ferroelectric thin films have developed rapidly, with a remanent polarization of more than 20μC / cm at a thickness of less than 10nm. 2 , and at the same time, there have been great improvements in fatigue performance, retention performance, etc.
[0003] Ferroelectric transistor (FeFET) is one of the application directions of ferroelectric thin film. Its structure is similar to that of field effect transistor (MOSFET). The main difference is that the gate oxide layer in MOSFET is replaced by a ferroelectric layer. The bistable characteristics of the ferroelectric layer are used to make the transistor transfer characteristic curve drift, so as to be used as a storage device. Since the currently commonly used flash memory cells are similar to FeFETs in storage process and are both non-volatile storage, FeFETs that can read and write at high speed have the potential to replace flash memory.
[0004] Currently, the main channel material of FeFET is doped silicon oxide. Due to the poor interface between silicon oxide and the ferroelectric film, it will seriously affect the performance of the ferroelectric layer. Therefore, new channel materials, such as third-generation semiconductor materials, such as gallium nitride, silicon carbide, zinc oxide and other materials have become candidate materials to replace silicon oxide.
[0005] Currently, the main problem with the third-generation semiconductor channel devices is the process problem of the thin film. The performance of the third-generation semiconductor thin film before and after heat treatment is very different. After heat treatment, the electron mobility increases sharply, which makes it difficult to control the disconnection of the channel in the device after heat treatment, resulting in the problem of relatively small switches and poor gate control capabilities. If the film is not heat treated, the mobility is low and a larger size is required, which is not conducive to three-dimensional integration. Summary of the invention
[0006] In view of this, the embodiments of the present invention provide a multi-junction hafnium oxide-based ferroelectric transistor and a three-dimensional integrated preparation method, which improves the response rate and reduces power consumption, and is expected to meet the development needs of advanced microelectronic devices.
[0007] To achieve the above object, the technical solution of the present invention is achieved as follows:
[0008] In the first aspect, an embodiment of the present invention provides a multi-junction hafnium oxide-based ferroelectric transistor, comprising: a silicon substrate, a silicon oxide isolation layer and at least one transistor unit from bottom to top, wherein the transistor unit comprises a gate perpendicular to the silicon substrate, a ferroelectric layer perpendicular to the silicon substrate, a drain, a stacked channel and a source distributed in sequence in the vertical direction, wherein the stacked channel stacks P-type and N-type semiconductor channel materials to form a layered vertical channel in an N / P / N / P / N stacking order, wherein the drain, the stacked channel and the source are perpendicular to the ferroelectric layer, and the oxide isolation layer is deposited between each device.
[0009] Preferably, the semiconductor channel material comprises a ZnO-based semiconductor material, such as one or more of IZO, IGZO, and AZO.
[0010] Preferably, the material of the hafnium oxide ferroelectric layer comprises hafnium oxide or doped hafnium oxide, and the doped hafnium oxide is doped with one or more of zirconium, aluminum, gallium, lanthanum and yttrium.
[0011] In a second aspect, an embodiment of the present invention provides a three-dimensional integrated preparation method for a multi-junction hafnium oxide-based ferroelectric transistor, the method comprising:
[0012] Step 1: Using silicon as a substrate to obtain a silicon substrate;
[0013] Step 2: depositing an oxide layer on the surface of the silicon substrate by magnetron sputtering deposition;
[0014] Step 3: depositing a metal layer source on the substrate by magnetron sputtering;
[0015] Step 4: alternately depositing n-type semiconductor layers and p-type semiconductor layers on the substrate by magnetron sputtering deposition to form a layered vertical channel in a stacking order of N / P / N / P / N;
[0016] Step 5: depositing a metal layer drain on the substrate by magnetron sputtering;
[0017] Step 6: The above structure is subjected to multiple photolithography patterning and etching to present a stepped exposure, including three steps of source-semiconductor layer / gate-oxide layer, and this is repeated as a basic unit;
[0018] Step 7: Photolithography and etching are performed on the other side of the step to form a through hole, and the ferroelectric layer and the gate are deposited in sequence;
[0019] Step 8: Filling the steps with oxide;
[0020] Step 9: Perform annealing using a rapid thermal annealing process.
[0021] Preferably, the annealing temperature is 300-600°C.
[0022] Preferably, an oxide layer, a metal layer, a semiconductor layer and a metal layer are sequentially deposited on the substrate.
[0023] Preferably, the metal layer includes a gate, a source, and a drain, and the metal layer material includes one or more of titanium nitride, molybdenum titanium, tungsten, platinum, and gold.
[0024] The embodiment of the present invention provides a multi-junction hafnium oxide-based ferroelectric transistor and a three-dimensional integrated preparation method, comprising: a silicon substrate, a silicon oxide isolation layer and at least one transistor unit from bottom to top, wherein the transistor unit comprises a gate perpendicular to the silicon substrate, a ferroelectric layer perpendicular to the silicon substrate, a drain, a stacked channel and a source distributed in sequence in the vertical direction, wherein the stacked channel stacks P-type and N-type semiconductor channel materials to form a layered vertical channel in the N / P / N / P / N stacking order, wherein the drain, the stacked channel and the source are perpendicular to the ferroelectric layer, and the oxide isolation layer is deposited between the devices; thus, the P-type and N-type semiconductor channel materials are stacked in the vertical direction by magnetron sputtering to form a layered vertical channel in the N / P / N / P / N stacking order, and the layered stacked channel forms four pairs of PN junctions. When the transistor is turned on, the two layers of P-type semiconductor are inverted to N-type, making the channel conductive in the vertical direction. When the transistor is turned off, four pairs of PN junctions hinder the flow of current between the source and the drain. Compared with common transistors, multiple PN junctions ensure that the source-drain current remains small enough in the off state and is not affected in the on state, thereby improving the switching ratio and reducing the storage data errors caused by the large off-state current under high integration. At the same time, multiple P regions reduce the subthreshold swing of the transistor, improve the response rate, and reduce power consumption, which is expected to meet the development needs of advanced microelectronic devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of the structure of a multi-junction hafnium oxide-based ferroelectric transistor provided in one embodiment of the present invention;
[0026] Wherein, electrode parts: 111: transistor gate, 112: transistor source, 113: transistor drain;
[0027] Semiconductor layer part: 121: P-type semiconductor, 122: N-type semiconductor;
[0028] Oxide layer part: 131: silicon oxide isolation layer, 132: ferroelectric layer;
[0029] Substrate part: 141: silicon substrate. DETAILED DESCRIPTION
[0030] In order to better illustrate the present embodiment, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances. The technical solution of the present invention is further described below in conjunction with the drawings and embodiments.
[0031] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0033] See also Figure 1 An embodiment of the present invention provides a multi-junction hafnium oxide-based ferroelectric transistor, comprising: a silicon substrate, a silicon oxide isolation layer and at least one transistor unit from bottom to top, wherein the transistor unit comprises a gate electrode vertical to the silicon substrate, a ferroelectric layer vertical to the silicon substrate, a drain electrode, a stacked channel and a source electrode vertically distributed in sequence, wherein the stacked channel stacks P-type and N-type semiconductor channel materials to form a layered vertical channel in a stacking order of N / P / N / P / N, wherein the drain electrode, the stacked channel and the source electrode are perpendicular to the ferroelectric layer, and the oxide isolation layer is deposited between each device.
[0034] Here, the integrated structure is formed by stacking and integrating multiple transistor units on the left side of the legend. The leftmost electrode of the small unit is the gate, and the structure on the right side of the gate is the ferroelectric layer. On the right side of the ferroelectric layer is a layered stacked channel and a source and drain in contact with the channel. The current flows in the vertical direction and is only turned on when a positive voltage is applied to the gate, causing the P-type semiconductor to be inverted. All small units are integrated in the vertical direction and share a gate. Silicon oxide is used to isolate each small unit. All small units are etched to lead contact electrodes from the source and drain electrode layer to form a 3D NAND structure similar to flash memory. Unlike the flash memory structure, the channel of this structure is a horizontal layered stack instead of a vertical stack. Accordingly, the original horizontally stacked gate is changed to a vertical stack to adapt to the change.
[0035] In this way, P-type and N-type semiconductor channel materials are stacked vertically by magnetron sputtering to form a layered vertical channel in the order of N / P / N / P / N, and the layered stacked channel forms four pairs of PN junctions. When the transistor is turned on, the two layers of P-type semiconductor are inverted to N-type, making the channel conductive in the vertical direction. When the transistor is turned off, the four pairs of PN junctions hinder the flow of current between the source and the drain. Compared with common transistors, multiple PN junctions ensure that the source and drain currents remain small enough in the off state and are not affected in the on state, which improves the switching ratio and reduces the storage data errors caused by the large off-state current under high integration. At the same time, multiple P regions reduce the subthreshold swing of the transistor, improve the response rate, and reduce power consumption, which is expected to meet the development needs of advanced microelectronic devices.
[0036] In one embodiment, the semiconductor channel material includes a ZnO-based semiconductor material, such as one or more of IZO, IGZO, and AZO.
[0037] In one embodiment, the material of the hafnium oxide ferroelectric layer includes hafnium oxide or doped hafnium oxide, and the doped hafnium oxide is doped with one or more of zirconium, aluminum, gallium, lanthanum and yttrium.
[0038] An embodiment of the present invention provides a three-dimensional integrated preparation method for a multi-junction hafnium oxide-based ferroelectric transistor, the method comprising:
[0039] Step 1: Using silicon as a substrate to obtain a silicon substrate;
[0040] Step 2: depositing an oxide layer on the surface of the silicon substrate by magnetron sputtering deposition;
[0041] Step 3: depositing a metal layer source on the substrate by magnetron sputtering;
[0042] Step 4: alternately depositing n-type semiconductor layers and p-type semiconductor layers on the substrate by magnetron sputtering deposition to form a layered vertical channel in a stacking order of N / P / N / P / N;
[0043] Step 5: depositing a metal layer drain on the substrate by magnetron sputtering;
[0044] Step 6: The above structure is subjected to multiple photolithography patterning and etching to present a stepped exposure, including three steps of source-semiconductor layer / gate-oxide layer, and this is repeated as a basic unit;
[0045] Step 7: Photolithography and etching are performed on the other side of the step to form a through hole, and the ferroelectric layer and the gate are deposited in sequence;
[0046] Step 8: Filling the steps with oxide;
[0047] Step 9: Perform annealing using a rapid thermal annealing process.
[0048] Here, an oxide layer, a metal layer, a semiconductor layer, and a metal layer are sequentially deposited on a silicon substrate, and this sequence is repeated.
[0049] Here, the film is subjected to multiple photolithography patterning and etching to expose the film in a step-shaped manner, that is, three steps of lower metal layer-semiconductor layer / upper metal layer-oxide layer, and this is repeated as a basic unit.
[0050] Here, photolithography and etching are performed on the other side of the step to form a through hole (retaining the bottom oxide layer), and the ferroelectric layer and the electrode are deposited in sequence.
[0051] Here, the steps are filled with a low dielectric oxide, and again vias are etched to the metal layer, a metal ingot is deposited to make contact, and annealing is performed to crystallize the ferroelectric layer.
[0052] In one embodiment, the annealing temperature is 300-600°C.
[0053] In one embodiment, an oxide layer, a metal layer, a semiconductor layer, and a metal layer are sequentially deposited on the substrate.
[0054] In one embodiment, the metal layer includes a gate, a source, and a drain, and the metal layer material includes one or more of titanium nitride, molybdenum titanium, tungsten, platinum, and gold.
[0055] Example 1
[0056] 1. In this embodiment, silicon (Si) is used as a substrate.
[0057] 2. Depositing an oxide layer on the surface of the substrate by magnetron sputtering deposition (PVD),
[0058] In this embodiment, the oxide is 50nm silicon oxide.
[0059] 3. Depositing a metal layer on the substrate using PVD,
[0060] In this embodiment, the metal layer is 20 nm titanium nitride.
[0061] 4. Using PVD to alternately deposit n-type semiconductor layers and p-type semiconductor layers on the substrate to form a 5-layer stacking structure of n / p / n / p / n,
[0062] In this embodiment, the n-type and p-type semiconductor layers are aluminum-doped zinc oxide (Al:ZnO) and copper-doped zinc oxide (Cu:ZnO), respectively, and the thickness of each single layer is 5 micrometers, and the total thickness is 25 micrometers.
[0063] 5. Depositing a metal layer on the substrate using PVD,
[0064] In this embodiment, the metal layer is 20 nm titanium nitride.
[0065] 6. Repeat steps 2-5 to form several repeated stacking 1 structures.
[0066] 7. Use photolithography for patterning and form steps through etching to expose all metal layers.
[0067] 8. Use photolithography for patterning, and form a through hole on the other side of the step by etching, retaining the bottom oxide layer.
[0068] 9. Depositing a ferroelectric layer at the through hole by atomic layer deposition (ALD),
[0069] In this embodiment, the ferroelectric layer is 14nm zirconium-doped hafnium oxide (Zr:HfO 2 ).
[0070] 10. Depositing a metal layer at the through hole using PVD,
[0071] In this embodiment, the metal layer is 20 nm titanium nitride.
[0072] 11. Depositing an oxide layer on the surface of the substrate by PVD,
[0073] In this embodiment, the oxide layer is silicon oxide.
[0074] 12. Use photolithography for patterning and etch through holes to connect the steps.
[0075] 13. Use PVD to fill the through hole with metal layer.
[0076] In this embodiment, the metal layer is titanium nitride.
[0077] 14. Use rapid thermal annealing process (RTP) to perform annealing at 450 degrees Celsius.
[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement and improvement made within the spirit and scope of the present invention are included in the protection scope of the present invention.
Claims
1. A multi-junction hafnium oxide-based ferroelectric transistor, characterized in that: include: A silicon substrate, a silicon oxide isolation layer and at least one transistor unit from bottom to top, wherein the transistor unit includes a gate electrode vertical to the silicon substrate, a ferroelectric layer vertical to the silicon substrate, a drain electrode, a stacked channel and a source electrode vertically distributed in sequence, wherein the stacked channel stacks P-type and N-type semiconductor channel materials to form a layered vertical channel in the stacking order of N / P / N / P / N, wherein the drain electrode, the stacked channel and the source electrode are perpendicular to the ferroelectric layer, and the oxide isolation layer is deposited between each device.
2. The multi-junction hafnium oxide-based ferroelectric transistor according to claim 1, characterized in that: The semiconductor channel material includes a ZnO-based semiconductor material, such as one or more of IZO, IGZO, and AZO.
3. The multi-junction hafnium oxide-based ferroelectric transistor according to claim 1, characterized in that: The material of the hafnium oxide ferroelectric layer includes hafnium oxide or doped hafnium oxide, and the doped hafnium oxide is doped with one or more of zirconium, aluminum, gallium, lanthanum and yttrium.
4. A three-dimensional integrated preparation method for a multi-junction hafnium oxide-based ferroelectric transistor, characterized in that: The method comprises: Step 1: Using silicon as a substrate to obtain a silicon substrate; Step 2: depositing an oxide layer on the surface of the silicon substrate by magnetron sputtering deposition; Step 3: depositing a metal layer source on the substrate by magnetron sputtering; Step 4: alternately depositing n-type semiconductor layers and p-type semiconductor layers on the substrate by magnetron sputtering deposition to form a layered vertical channel in a stacking order of N / P / N / P / N; Step 5: depositing a metal layer drain on the substrate by magnetron sputtering; Step 6: The above structure is subjected to multiple photolithography patterning and etching to present a stepped exposure, including three steps of source-semiconductor layer / gate-oxide layer, and this is repeated as a basic unit; Step 7: Photolithography and etching are performed on the other side of the step to form a through hole, and the ferroelectric layer and the gate are deposited in sequence; Step 8: Filling the steps with oxide; Step 9: Perform annealing using a rapid thermal annealing process.
5. The three-dimensional integrated preparation method of multi-junction hafnium oxide-based ferroelectric transistor according to claim 4, characterized in that: The annealing temperature is 300-600°C.
6. The three-dimensional integrated preparation method of multi-junction hafnium oxide-based ferroelectric transistor according to claim 4, characterized in that: An oxide layer, a metal layer, a semiconductor layer and a metal layer are sequentially deposited on the substrate.
7. The three-dimensional integrated preparation method of multi-junction hafnium oxide-based ferroelectric transistor according to claim 4, characterized in that: The metal layer includes a gate, a source, and a drain, and the metal layer material includes one or more of titanium nitride, molybdenum titanium, tungsten, platinum, and gold.