Si 1-x Ge x / Si heterojunction stacked gate oxide layer stepped channel dual gate tunnel field effect transistor

Abstract

The present application relates to Si 1‑x Ge x / Si heterojunction gate oxide layer ladder channel double gate tunnel field effect transistor; the purpose is to further improve the on-state current and on-off current ratio of double gate TFET (DGTFET) and reduce the subthreshold swing on the basis of relieving the bipolar effect problem of double gate TFET (DGTFET); it comprises a drain region, a channel region and a source region, the channel region is a ladder structure, the thin end of the channel region is connected with the source region, and the thick end of the channel region is connected with the drain region; both sides of the channel region are provided with ladder structure low-k gate oxide layers matched with the shape of the channel region, the step surface of the low-k gate oxide layer is located on the left side of the step surface of the channel region, and the thickness of the thin end of the low-k gate oxide layer is smaller than the thickness of the thick end of the low-k gate oxide layer; both sides of the thin end of the low-k gate oxide layer are provided with high-k gate oxide layers with the same length; the low-k gate oxide layer is prepared by using low-k dielectric material, and the high-k gate oxide layer is prepared by using high-k dielectric material; the source region is prepared by using Si 1‑x Ge x , the channel region and the drain region are prepared by using silicon.

Description

Technical Field

[0001] This invention relates to a dual-gate tunneling field-effect transistor, specifically to Si. 1-x Ge x / Si heterojunction stacked gate oxide stepped trench dual-gate tunnel field-effect transistor. Background Technology

[0002] In recent decades, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) has continued to shrink with Moore's Law, but their total power consumption and off-state leakage current have inevitably increased. At the same time, due to the carrier transport mechanism of MOSFETs, their subthreshold swing (SS) is limited to above 60mV / dec. Obviously, these defects make MOSFETs no longer suitable for the future demand for ultra-low power integrated circuits.

[0003] In 1934, Zener first proposed the concept that particles could overcome the energy barrier of classical constraints through tunneling. Based on this concept, the tunneling field-effect transistor (TFET) broke the subthreshold swing limitation of MOSFETs with its inter-band tunneling conduction mechanism, greatly reducing the power consumption of the device.

[0004] However, TFETs have the disadvantage of low on-state current, which is generally two to three orders of magnitude lower than that of MOSFETs. This is the biggest problem with TFETs at present.

[0005] like Figure 1 The diagram shows a schematic of a silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET), including a drain region 03, a channel region 02, and a source region 01 arranged from right to left. A low-k gate oxide layer 04 is disposed at both the top and bottom ends of the channel region 02. As can be seen from the figure, the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) is a dual-gate TFET (DGTFET) structure. Its dual-gate structure exhibits twice the gate control capability of the channel region, improving the on-state current of the device. However, due to its left-right symmetrical structure, the DGTFET exhibits severe bipolar behavior. In practical applications, this bipolar effect will lead to a decrease in circuit performance. Summary of the Invention

[0006] The purpose of this invention is to further improve the on-state current and switching current ratio of a dual-gate TFET (DGTFET), and reduce the subthreshold swing, while mitigating the bipolar effect problem of the DGTFET, thereby providing a Si 1-x Ge x / Si heterojunction stacked gate oxide stepped trench dual-gate tunnel field-effect transistor.

[0007] The technical solution adopted in this invention is:

[0008] A Si 1-x Ge x The Si heterojunction stacked gate oxide stepped-channel dual-gate tunnel field-effect transistor includes a drain region, a channel region, and a source region arranged sequentially from right to left. Its special feature is that:

[0009] The channel region has a stepped structure, with the thin end of the channel region connected to the source region and both having the same thickness, and the thick end of the channel region connected to the drain region and both having the same thickness.

[0010] Both the upper and lower sides of the channel region are provided with a stepped low-k gate oxide layer that matches the shape of the channel region. The stepped surface of the low-k gate oxide layer is located to the left of the stepped surface of the channel region. The length of the low-k gate oxide layer is equal to the length of the channel region. The thickness of the thin end of the low-k gate oxide layer is less than the thickness of the thick end of the low-k gate oxide layer. Both the upper and lower sides of the thin end of the low-k gate oxide layer are provided with a high-k gate oxide layer of equal length.

[0011] The low-k gate oxide layer is fabricated using a low-k dielectric material, and the high-k gate oxide layer is fabricated using a high-k dielectric material; the source region is made of Si. 1-x Ge x The channel region and drain region are prepared using silicon, where x represents the germanium content in SiGe, and 0 < x < 1.

[0012] Definition: Let A be the thickness of the high-k gate oxide layer, B be the thickness of the thin end of the low-k gate oxide layer, C be the thickness of the thick end of the low-k gate oxide layer, D be the thickness of the thin end of the channel region, E be the thickness of the thick end of the channel region, and L be the distance between the step surface of the low-k gate oxide layer and the step surface of the channel region. Then A, B, C, D, E, and L satisfy the following formulas: 2A + 2B + D ≤ 2C + E; and A + B ≥ C; L = C.

[0013] Furthermore, the high-k dielectric material is HfO2 or Al2O3;

[0014] The low-k dielectric material is SiO2.

[0015] Furthermore, the thickness of the thick end of the low-k gate oxide layer is twice the thickness of the thin end of the low-k gate oxide layer; and the distance between the step surface of the low-k gate oxide layer and the step surface of the channel region is equal to the thickness of the thick end of the low-k gate oxide layer.

[0016] Furthermore, the thickness of the thick end of the low-k gate oxide layer is 2 nm, and the thickness of the thin end of the low-k gate oxide layer is 1 nm; the thickness of the high-k gate oxide layer is 1 nm.

[0017] Furthermore, the length of the thin end of the channel region is the same as the length of the thick end of the channel region.

[0018] Furthermore, the source region is P-type and the drain region is N-type; or the source region is N-type and the drain region is P-type; the doping type of the channel region is the same as that of the source region; wherein, the N-type doping element is arsenic or phosphorus, and the P-type doping element is boron.

[0019] Furthermore, the doping concentration of the drain region is 1×10⁻⁶. 17 ~1×10 18 cm -3 ;

[0020] The doping concentration of the source region is 1×10⁻⁶. 19 ~1×10 20 cm -3 ;

[0021] The doping concentration in the channel region is 1×10⁻⁶. 15 ~1×10 16 cm -3 .

[0022] Furthermore, the length of the drain region is 10-20 nm, the length of the source region is 10-20 nm, and the length of the channel region is greater than or equal to 50 nm.

[0023] Furthermore, the thickness of the thin end of the channel region is 5-10 nm, and the thickness of the thick end of the channel region is 20-30 nm.

[0024] Furthermore, the work function of the gate metal is set to 3.9–4.3 eV.

[0025] The beneficial effects of this invention are:

[0026] 1. In this invention, an asymmetric channel thickness structure is formed by setting the channel region as a stepped structure and setting the low-k gate oxide layer around the channel region as a stepped structure that matches the shape of the channel region.

[0027] A stacked gate oxide structure is formed by setting a high-k gate oxide layer on the thin peripheral side of the low-k gate oxide layer;

[0028] By using Si in the source region 1-x Ge x The channel and drain regions are made of silicon to form Si between the source and channel regions. 1-x Ge x / Si tunneling heterojunction;

[0029] Through the aforementioned asymmetric channel thickness structure, gate oxide layer structure, and Si 1-x Ge xThe multidimensional combination of / Si tunneling heterojunction alleviates the problem that the bipolar effect of dual-gate TFET (DGTFET) can lead to a decrease in circuit performance, and further improves the on-state current and switching current ratio of dual-gate TFET (DGTFET), as well as reducing the subthreshold swing.

[0030] The tunneling field-effect transistor of this invention reduces bipolar current and subthreshold swing while maintaining high on-state current, high switching current ratio and low subthreshold swing.

[0031] 2. In this invention, the asymmetric channel thickness structure can effectively alleviate the bipolar effect of dual-gate TFET (DGTFET) by introducing asymmetry.

[0032] 3. In this invention, the stacked gate oxide structure places a high dielectric constant material on a low dielectric constant material, which can reduce interface defects and lattice mismatch between the high dielectric constant material and the semiconductor material, while also enabling the high dielectric constant material to enhance the carrier band tunneling rate from the source region to the channel region.

[0033] 4. In this invention, the Si used 1-x Ge x The / Si tunneling heterojunction reduces the bandgap of the source region material, greatly improving the carrier band tunneling efficiency from the source region to the channel region.

[0034] 5. In this invention, through asymmetric channel thickness structure, stacked gate oxide layer structure, and Si... 1-x Ge x The multi-dimensional combination of / Si tunneling heterojunction utilizes the excellent gate control capability of dual-gate tunneling field-effect transistors to optimize the overall structure of TFET devices, thereby improving device performance and avoiding the shortcomings of traditional TFETs such as low on-state current and significant bipolar behavior, enabling TFETs to meet the requirements of ultra-low power integrated circuits.

[0035] 6. This invention can be used in the fabrication of semiconductor devices in the field of high-performance, low-power integrated circuits. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a current-technical dual-gate tunneling field-effect transistor (Si-DGTFET);

[0037] Figure 1 Explanation of reference numerals in the attached diagram:

[0038] 01. Source region; 02. Channel region; 03. Drain region; 04. Low-k gate oxide layer;

[0039] Figure 2 This invention is Si 1-x Ge xA schematic diagram of a Si heterojunction stacked gate oxide stepped channel dual-gate tunnel field-effect transistor embodiment;

[0040] Figure 3 This is a comparison chart of the transfer characteristic curves of the embodiments of the present invention and the prior art in the range of -1V to 1V gate voltage;

[0041] Figure 4 This is a comparison diagram of the energy band structure of the embodiment of the present invention and the prior art under the on-state condition, along the channel region 1 nm below the gate oxide layer;

[0042] Figure 5 This is a comparison diagram of the energy band structure of the embodiment of the present invention and the prior art under off-state conditions, along the channel region 1 nm below the gate oxide layer;

[0043] Figure 6 This is a comparison diagram of the energy band structure of the channel region 1 nm below the gate oxide layer under bipolar conditions between the embodiments of the present invention and the prior art.

[0044] Figure 7 This is a comparison diagram of the electric field of the embodiment of the present invention and the prior art under the on-state condition, along the channel region 1 nm below the gate oxide layer.

[0045] Figure 2 Explanation of reference numerals in the attached diagram:

[0046] 1. Source region; 2. Channel region; 3. Drain region; 4. Low-k gate oxide layer; 5. High-k gate oxide layer. Detailed Implementation

[0047] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0048] The left and right in the text are... Figure 1 or Figure 2 Described from the perspective of [the author / organization].

[0049] This invention proposes a Si based on stepped channels 1-x Ge x / Si heterojunction stacked gate oxide double-gate tunnel field-effect transistor, such as Figure 2 As shown, it includes source region 1, channel region 2, drain region 3, low-k gate oxide layer 4, and high-k gate oxide layer 5;

[0050] The channel region 2 has a stepped structure, with a thin end on the left and a thick end on the right. The lengths of the thick and thin ends in the left and right directions are equal. The thin end is connected to the source region 1, and the thick end is connected to the drain region 3.

[0051] Both the upper and lower sides of the channel region 2 are provided with low-k gate oxide layers 4 in a stepped shape that are adapted to the shape of the channel region 2. The left end (i.e., the thin end) of the low-k gate oxide layer 4 is connected to the left end of the channel region 2, and the right end (i.e., the thick end) of the low-k gate oxide layer 4 is connected to the right end of the channel region 2. The thickness of the thick end of the low-k gate oxide layer 4 is twice the thickness of the thin end of the low-k gate oxide layer 4. The stepped surface of the low-k gate oxide layer 4 is located to the left of the stepped surface of the channel region 2. The distance between the stepped surface of the low-k gate oxide layer 4 and the stepped surface of the channel region 2 is the same as the thickness of the thick end of the low-k gate oxide layer 4. The low-k gate oxide layer 4 connects the left and right sides of the channel region 2.

[0052] High-k gate oxide layers 5 are provided at both the top and bottom ends of the thin end of the low-k gate oxide layer 4, and the two ends of the high-k gate oxide layer 5 are respectively connected to the two ends of the thin end of the low-k gate oxide layer 4.

[0053] The high-k gate oxide layer 5 uses materials with a dielectric constant higher than SiO2, such as HfO2 and Al2O3; the low-k gate oxide layer 4 uses SiO2 with a relatively low dielectric constant.

[0054] Si based on stepped channels 1-x Ge x The entire / Si heterojunction stacked gate oxide double-gate tunnel field-effect transistor is symmetrical about the left and right directions as the axis of symmetry.

[0055] Source region 1 uses Si 1-x Ge x The material used is silicon, while channel region 2 and drain region 3 still use silicon to form Si between source region 1 and channel region 2. 1-x Ge x / Si tunneling heterojunction.

[0056] Source region 1 and drain region 3 are doped with opposite types of impurities, i.e., source region 1 is P-type and drain region 3 is N-type; or source region 1 is N-type and drain region 3 is P-type. Channel region 2 is doped with the same type of impurities as source region 1, i.e., channel region 2 and source region 1 are both P-type or N-type. The N-type dopant is arsenic or phosphorus, and the P-type dopant is boron. That is, for N-type Si... 1-x Ge x / Si heterojunction stacked gate oxide stepped-channel dual-gate tunnel field-effect transistor, source region 1 is P-type doped with a doping concentration of 1×10 19 ~1×10 20 cm -3 Drain region 3 is N-type doped with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 Channel region 2 is P-type doped with a doping concentration of 1×10⁻⁶. 15 ~1×10 16 cm -3For P-type Si 1-x Ge x / Si heterojunction stacked gate oxide stepped-channel dual-gate tunnel field-effect transistor, source region 1 is N-type doped with a doping concentration of 1×10 19 ~1×10 20 cm -3 Drain region 3 is P-type doped with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 Channel region 2 is N-type doped with a doping concentration of 1×10⁻⁶. 15 ~1×10 16 cm -3 .

[0057] The length of drain region 3 is 10-20 nm, the length of source region 1 is 10-20 nm, the length of channel region 2 is 50 nm, the thickness of the thin end of channel region 2 is 5-10 nm, and the thickness of the thick end of channel region 2 is 20-30 nm.

[0058] The basic structure of the device in this invention is a silicon-based stepped-channel dual-gate tunnel field-effect transistor (TFET). An asymmetric source-drain structure is constructed to reduce the bipolar current of a conventional silicon-based TFET. This invention utilizes a heterojunction and stacked gate oxide structure to achieve high on-state current while reducing the bipolar current of the conventional silicon-based TFET, and further reduces the subthreshold swing (SS). Source region 1 uses Si... 1-x Ge x The heterojunction formed by the material and the Si material in the channel region 2 can further shorten the effective tunneling length at the tunnel junction, increase the tunneling probability from the source region 1 to the channel region 2, and improve the on-state current of the device. In addition, the gate oxide layer near the source region 1 is a high-k gate dielectric (HfO2 or Al2O3) stacked on a low-k gate dielectric (SiO2) to improve the gate's control over the channel region 2, increase the tunneling probability at the tunnel junction, and reduce the subthreshold swing (SS). At the same time, the structure of the stacked gate oxide layer can also effectively alleviate problems such as interface defects and lattice mismatch between the high-k dielectric and the semiconductor material.

[0059] This invention effectively avoids the shortcomings of traditional silicon-based TFETs, such as low on-state current, high bipolar current, and large subthreshold swing. It has good bipolar performance, high on-state current, and low off-state leakage current, and reduces them by about 77% compared to traditional silicon-based TFETs.

[0060] In this invention, a specific embodiment is given as follows:

[0061] The doping concentration of P-type source region 1 is 1×10⁻⁶. 20 cm -3 It has a length of 10 nm and a thickness of 5 nm, and uses Si with x = 0.9.0.1 Ge 0.9 Materials; the doping concentration of N-type drain region 3 is 1×10⁻⁶. 17 cm -3 The drain region 3 has a length of 10 nm and a thickness of 20 nm, and is made of silicon (Si); the doping concentration of the P-type channel region 2 is 1 × 10⁻⁶. 15 cm -3 The length is 50nm, the thickness at the thin end is 5nm, the thickness at the thick end is 20nm, the thickness at the thick end of the low-k gate oxide layer 4 is 2nm, the N-type dopant is arsenic (As), the P-type dopant is boron (B), the thickness at the thin end of the low-k gate oxide layer 4 is 1nm, the thickness at the high-k gate oxide layer 5 is 1nm, the material is high-k dielectric material HfO2, and the gate work function is set to 4.3eV.

[0062] like Figure 1 The diagram shown is a schematic of a silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET), including: source region 01, channel region 02, drain region 03, and low-k gate oxide layer 04. Source region 01 and channel region 02 are P-type boron doped with doping concentrations of 1×10⁻⁶. 20 cm -3 and 1×10 15 cm -3 Drain region 03 is doped with N-type arsenic at a concentration of 1×10⁻⁶. 20 cm -3 The source region 01, channel region 02 and drain region 03 are all made of silicon with a thickness of 20nm. The lengths of the source region 01, channel region 02 and drain region 03 are 10nm, 50nm and 10nm respectively. The low-k gate oxide layer 04 at the top and bottom ends of the channel region 2 is made of SiO2 with a thickness of 2nm. The gate work function is set to 4.3eV.

[0063] like Figure 3 The figure shows a comparison of the transfer characteristic curves of the embodiment of the present invention and the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) in the gate voltage range of -1V to 1V. As can be seen from the figure, compared with the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET), the transistor using the structure of the present invention has a higher on-state current and a lower off-state current. At the same time, the bipolar effect is effectively suppressed. In addition, the SS of the transistor in the present invention is significantly better than that of the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET).

[0064] like Figure 4 The figure shows a comparison of the energy bands of the embodiment of the present invention and the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) under the on-state condition, along the channel region 2 1 nm below the gate oxide layer. It can be seen from the figure that, due to the Si of the present invention... 1- x Gex With its Si heterojunction structure, the transistor of this invention has the smallest effective tunneling distance. Therefore, compared with the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET), the transistor of this invention has a significantly improved electron band tunneling rate in the on-state, effectively increasing the on-state current of the device.

[0065] like Figure 5 The figure shows a comparison of the energy bands of the embodiment of the present invention and the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) under the off-state condition, along the channel region 2 1 nm below the gate oxide layer. As can be seen from the figure, under the off-state condition, since the top of the valence band and the bottom of the conduction band are not aligned at the tunnel junction of the source region 1 and the channel region 2, the effect of tunneling on the current can be ignored. However, compared with the transistor of the present invention, the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) has a lower potential barrier between the channel region 2 and the drain region 3, making it easier for electrons to transport to the drain. Therefore, the transistor in the present invention has a lower off-state current.

[0066] like Figure 6 The figure shows a comparison of the energy band structure of the embodiment of the present invention and the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) under bipolar conditions, along the channel region 2 1 nm below the gate oxide layer. It can be seen from the figure that under bipolar conditions, band-to-band tunneling of electrons occurs at the tunnel junction between channel region 2 and drain region 3. Compared to the transistor in the present invention, the effective tunneling distance at the tunnel junction between channel region 2 and drain region 3 of the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) is shorter. Therefore, compared to the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET), the transistor in the present invention has a lower electron band-to-band tunneling rate in bipolar conditions, effectively mitigating the bipolar effect of the device.

[0067] like Figure 7 The figure shows a comparison of the electric field of the embodiment of the present invention and the silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) under the on-state condition, along the channel region 2 1 nm below the gate oxide layer. As can be seen from the figure, due to the stacked gate oxide layer structure in the present invention, the electric field of the embodiment of the present invention can reach up to 5 MV / cm in the on-state, which greatly improves the electron band tunneling rate and further enhances the on-state current.

[0068] Furthermore, this invention uses N-type Si 1-x Ge x Taking the Si heterojunction stacked gate oxide stepped channel dual-gate tunnel field-effect transistor (HJSGO-SC-DGTFET) as an example, when the embodiment of the present invention is in the on-state (Vd = 1V, Vg = 1V), the on-state current of the N-type HJSGO-SC-DGTFET is close to 10. -4The current per A / μm is approximately five orders of magnitude larger than that of a conventional silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) under the same operating conditions (Vd = 1V, Vg = 1V). When the embodiment of this invention is in the bipolar state (Vd = 1V, Vg = -1V), the bipolar current is also approximately three orders of magnitude lower than that of a conventional silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET) under the same operating conditions (Vd = 1V, Vg = -1V). Furthermore, when the embodiment of this invention is in the off state (Vd = 1V, Vg = 0V), the off-state current is only 10... -18 A / μm. Furthermore, the device's minimum SS is only 12.3mV / dec, approximately 77% lower than that of a traditional TFET. These electrical characteristics ensure the device possesses excellent operating performance, meeting the requirements of next-generation devices.

[0069] This invention, through research on the structural optimization and performance prediction of tunneling field-effect transistors, finds the optimal solution that helps to improve the shortcomings such as small on-state current and significant bipolar effect.

Claims

1. A Si 1-x Ge x A Si heterojunction stepped-channel dual-gate tunnel field-effect transistor, comprising a drain region (3), a channel region (2), and a source region (1) arranged sequentially from right to left, characterized in that: The channel region (2) has a stepped structure. The thin end of the channel region (2) is connected to the source region (1) and the two have the same thickness. The thick end of the channel region (2) is connected to the drain region (3) and the two have the same thickness. Both sides of the channel region (2) are provided with a stepped low-k gate oxide layer (4) that matches the shape of the channel region (2). The step surface of the low-k gate oxide layer (4) is located on the left side of the step surface of the channel region (2). The length of the low-k gate oxide layer (4) is equal to the length of the channel region (2). The thickness of the thin end of the low-k gate oxide layer (4) is less than the thickness of the thick end of the low-k gate oxide layer (4). Both sides of the thin end of the low-k gate oxide layer (4) are provided with a high-k gate oxide layer (5) of equal length. The low-k gate oxide layer (4) is fabricated using a low-k dielectric material, and the high-k gate oxide layer (5) is fabricated using a high-k dielectric material; the source region (1) is made of Si. 1-x Ge x The channel region (2) and drain region (3) are prepared using silicon, where x represents the germanium content in SiGe, 0 <x<1; Definition: The thickness of the high-k gate oxide layer (5) is A, the thickness of the thin end of the low-k gate oxide layer (4) is B, the thickness of the thick end of the low-k gate oxide layer (4) is C, the thickness of the thin end of the channel region (2) is D, the thickness of the thick end of the channel region (2) is E, and the distance between the step surface of the low-k gate oxide layer (4) and the step surface of the channel region (2) is L. Then A, B, C, D, E, and L satisfy the following formulas: 2A+2B+D≤2C+E; and A+B≥C; L=C.

2. The Si according to claim 1 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The high-k dielectric material is HfO2 or Al2O3; The low-k dielectric material is SiO2.

3. The Si according to claim 2 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The thickness of the thick end of the low-k gate oxide layer (4) is twice the thickness of the thin end of the low-k gate oxide layer (4); and the distance between the step surface of the low-k gate oxide layer (4) and the step surface of the channel region (2) is equal to the thickness of the thick end of the low-k gate oxide layer (4).

4. The Si according to claim 3 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The thickness of the thick end of the low-k gate oxide layer (4) is 2 nm, and the thickness of the thin end of the low-k gate oxide layer (4) is 1 nm; the thickness of the high-k gate oxide layer (5) is 1 nm.

5. The Si according to claim 4 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The length of the thin end of the channel region (2) is the same as the length of the thick end of the channel region (2).

6. The Si according to any one of claims 1-5 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The source region (1) is P-type and the drain region (3) is N-type; or the source region (1) is N-type and the drain region (3) is P-type; the doping type of the channel region (2) is the same as that of the source region (1); wherein, the N-type doping element is arsenic or phosphorus, and the P-type doping element is boron.

7. The Si according to claim 6 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The doping concentration of the drain region (3) is 1×10⁻⁶. 17 ~1×10 18 cm -3 ; The doping concentration of the source region (1) is 1×10 19 ~1×10 20 cm -3 ; The doping concentration of the channel region (2) is 1×10 15 ~1×10 16 cm -3 .

8. The Si according to claim 7 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The length of the drain region (3) is 10-20 nm, the length of the source region (1) is 10-20 nm, and the length of the channel region (2) is greater than or equal to 50 nm.

9. The Si according to claim 8 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The thickness of the thin end of the channel region (2) is 5-10 nm, and the thickness of the thick end of the channel region (2) is 20-30 nm.

10. The Si according to claim 9 1-x Ge x The / Si heterojunction stacked gate oxide stepped trench dual-gate field-effect transistor is characterized by: The work function of the gate metal is set to 3.9–4.3 eV.

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