Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises M routing groups, wherein at least one routing group in the M routing groups comprises a grid line and a first routing line which extend along the first direction; the first wires and the grid lines are electrically connected at at least one end part position; the N second wires extend along the second direction and are arranged along the first direction; wherein the nth second wire is electrically connected with the first wire in the nth wire group at the intersection position, n is smaller than or equal to N, n is smaller than or equal to M, and M, N and n are positive integers; the first gate driving circuit is located in the binding opposite side area; and one end of the second wire is electrically connected with the first gate driving circuit so as to provide a signal of the first gate driving circuit to the gate line.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Active-matrix organic light emitting diode (AMOLED) displays have the advantages of active light emission without backlight, high contrast, and flexibility, and are very likely to become the next generation display technology. Gate Driver On Array (GOA) technology is a technology that integrates the gate drive circuit of a display device on an array substrate. The use of GOA technology can reduce the use of ICs, thereby reducing the production cost and power consumption of the product, and the use of GOA technology can also achieve a narrow frame of the display device. Summary of the invention

[0003] The present invention provides a display substrate and a display device. The display substrate comprises a display area, a binding area located on one side of the display area, and a binding opposite side area located on the other side of the display area and opposite to the binding area; wherein the display substrate comprises:

[0004] substrate;

[0005] M routing groups, the M routing groups extending along a first direction and arranged along a second direction, at least one routing group among the M routing groups comprising: a gate line extending along the first direction and a first routing line; the first routing line and the gate line are electrically connected at at least one end position;

[0006] N second routing lines, the N second routing lines extending along the second direction and arranged along the first direction; wherein the nth second routing line is electrically connected to the first routing line in the nth routing line group at a crossing position, n≤N, n≤M, and M, N, and n are positive integers;

[0007] The first gate driving circuit is located in the binding opposite side area; one end of the second wiring is electrically connected to the first gate driving circuit to provide the signal of the first gate driving circuit to the gate line.

[0008] In a possible implementation manner, the first routing line includes: a first routing line main portion extending along the first direction, and a first convex portion connected to the first routing line main portion; a width of the first convex portion perpendicular to the first direction is greater than a width of the first routing line main portion perpendicular to the first direction;

[0009] The second routing line includes: a second routing line main portion extending along the second direction, and a second convex portion connected to the second routing line main portion; a width of the second convex portion perpendicular to the second direction is greater than a width of the second routing line main portion perpendicular to the second direction;

[0010] The orthographic projection of the second convex portion on the substrate overlaps with the orthographic projection of the first convex portion on the substrate, and a hole is punched at the overlapping position to electrically connect the two.

[0011] In a possible implementation manner, the first wiring and the gate line are electrically connected at two end positions in the extension direction.

[0012] In a possible implementation manner, the first routing line further includes: a third protrusion connected to the end of the first routing line main portion; a width of the third protrusion in a direction perpendicular to the first direction is greater than a width of the first routing line main portion in a direction perpendicular to the first direction;

[0013] The gate line comprises: a gate line main portion extending along the first direction, and a gate line convex portion connected to an end of the gate line main portion; a width of the gate line convex portion perpendicular to the first direction is greater than a width of the gate line main portion perpendicular to the first direction;

[0014] The orthographic projection of the third convex portion on the substrate overlaps with the orthographic projection of the gate line convex portion on the substrate, and the gate line convex portion and the gate line convex portion are connected by punching holes at the overlapping positions.

[0015] In a possible implementation manner, the third convex portion includes: a first sub-convex portion and a second sub-convex portion arranged and connected along the second direction;

[0016] The first sub-protrusion is connected to the first wiring main part; the orthographic projection of the second sub-protrusion on the substrate covers the orthographic projection of the gate line protrusion on the substrate.

[0017] In a possible implementation, the display substrate further includes: a plurality of data lines extending along the second direction and arranged along the first direction;

[0018] The second wiring and the data line are formed on the same layer and made of the same material.

[0019] In a possible implementation manner, the data line is located on a side of the gate line away from the substrate; and the first routing line is located on a side of the data line away from the gate line.

[0020] In a possible implementation, the first gate driving circuit includes: a plurality of M gate driving units sequentially arranged and cascaded along the first direction;

[0021] One end of the nth second wiring is electrically connected to the nth gate driving unit to provide the signal of the nth gate driving unit to the gate line in the nth wiring group.

[0022] In a possible implementation, the first gate driving circuit includes: a first sub-gate driving circuit, and a second sub-gate driving circuit located on a side of the first sub-gate driving circuit away from the display area; the first sub-gate driving circuit and the second sub-gate driving circuit extend along the first direction and are arranged along the second direction;

[0023] The first sub-gate driving circuit includes: a plurality of M first sub-gate driving units arranged in sequence along the first direction and cascaded in sequence from the first end to the second end; the second sub-gate driving circuit includes: a plurality of M second sub-gate driving units arranged in sequence along the first direction and cascaded in sequence from the second end to the first end.

[0024] In a possible implementation, the display substrate further includes: P third routing lines, the P third routing lines extending along the second direction and arranged along the first direction; wherein the nth third routing line is electrically connected to the first routing line in the M-(n-1)th routing group at an intersection position, n≤P, and P is a positive integer.

[0025] In a possible implementation manner, one end of the nth second routing line is electrically connected to the nth first sub-gate driving unit from the first end to the second end, so as to provide a signal of the nth first sub-gate driving unit to the gate line in the nth routing line group;

[0026] One end of the nth third routing line is electrically connected to the M-(n-1)th second sub-gate driving unit from the first end to the second end, so as to provide a signal of the M-(n-1)th second sub-gate driving unit from the first end to the second end to the gate line in the M-(n-1)th routing group.

[0027] In a possible implementation manner, the third routing line and the second routing line are made of the same layer and the same material.

[0028] In a possible implementation manner, the display substrate further comprises a first side region connecting one end of the binding region and one end of the binding opposite side region, and a second side region connecting the other end of the binding region and the other end of the binding opposite side region;

[0029] The display substrate further includes: a plurality of first signal lines; the first signal lines extend from one end of the binding area, through the first side area, the binding opposite side area, and the second side area to the other end of the binding area.

[0030] In a possible implementation manner, the first signal line includes: a trigger signal line, and / or a first clock signal line, and / or a second clock signal line.

[0031] The embodiment of the present disclosure further provides a display device, which includes the display substrate provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 One of the schematic diagrams of a display substrate provided by an embodiment of the present invention;

[0033] Figure 2A Can be Figure 1 An enlarged schematic diagram of a sub-pixel in FIG.

[0034] Figure 2B Can be Figure 2A The schematic diagram only includes the first routing line G1 and the second routing line G2;

[0035] Figure 3A Can be Figure 1 An enlarged schematic diagram of the end of a middle pixel row;

[0036] Figure 3B Can be Figure 3A A schematic diagram of the dashed line position and only including the first routing line G1 and the gate line G0;

[0037] Figure 3C Can be Figure 3A The schematic diagram only includes the first routing line G1;

[0038] Figure 4 A second schematic diagram of a display substrate provided by an embodiment of the present invention;

[0039] Figure 5 A third schematic diagram of a display substrate provided by an embodiment of the present invention;

[0040] Figure 6 The fourth schematic diagram of the display substrate provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0044] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0045] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0046] As AMOLED products mature, the market demand for extremely narrow borders is getting stronger. Therefore, it is becoming more and more important to achieve narrow border design without affecting the image quality (partial single-side drive). The challenges of narrow borders are mainly in the left and right borders and the bottom border, and the top border is often designed to be larger simply because it needs to maintain a similar size to the left and right bottom borders. In fact, the top border does not need such a large space. One of the main factors limiting the left and right borders is the GOA circuit. Because of the demand for display quality, all GOAs are generally required to be driven on both sides, and in order to optimize the display, more GOA signals are often introduced, for example, 5 groups of GOA are required. Therefore, the space of the upper border can be used to place GOA to reduce the left and right borders.

[0047] In the related art, when part of the GOA is set on the upper frame of the display substrate, the position of the brightest (or darkest) sub-pixel of the GOA signal in each row of pixels will be different. For example, in the first pixel row, the brightest sub-pixel is the first column sub-pixel, while in the second pixel row, the brightest sub-pixel may be the second or fourth column sub-pixel. The mura of the entire display panel has no regularity, and grayscale compensation (Demura) is more difficult to perform.

[0048] See also Figure 1 As shown, an embodiment of the present invention provides a display substrate, comprising a display area AA, a binding area BB1 located at one side of the display area AA, a binding opposite side area BB2 located at the other side of the display area A and opposite to the binding area BB1, a first side area BB3 connecting one end of the binding area BB1 and one end of the binding opposite side area BB2, and a second side area BB4 connecting the other end of the binding area BB1 and the other end of the binding opposite side area BB2; wherein the display substrate comprises:

[0049] substrate;

[0050] M routing groups G, the M routing groups G extend along the first direction X and are arranged along the second direction Y, at least one routing group G of the M routing groups G comprises: a gate line G0 extending along the first direction X and a first routing line G1; the first routing line G1 and the gate line G0 are electrically connected at at least one end position (such as Figure 1 The location indicated by the large black dot in the middle);

[0051] N second routing wires G2, the N second routing wires G2 extend along the second direction Y and are arranged along the first direction X; wherein the nth second routing wire G2 is electrically connected to the first routing wire G1 in the nth routing wire group G at the intersection position (such as Figure 1 The positions indicated by the small black dots), n≤N, n≤M, and M, N, and n are positive integers; for example, combined with Figure 1 As shown, the direction from the first side area BB3 to the second side area BB4 (that is, Figure 1The second second routing line G2 on the left-to-right direction in the figure is connected to the direction from the binding opposite side area BB2 to the binding area BB1 (i.e. Figure 1 The first wiring G1 in the second gate line group G2 on the upper and lower sides of the grid is electrically connected at the intersection; M and N may be equal, or may be unequal;

[0052] The first gate driving circuit GOA is located in the bonding opposite side area BB2; one end of the second wiring G2 is electrically connected to the first gate driving circuit GOA to provide a signal of the first gate driving circuit GOA to the gate line G0.

[0053] In the disclosed embodiment, the display substrate includes: a first gate drive circuit GOA located in the binding opposite side area BB2, which can narrow the width of the left and right frames of the display substrate to achieve a narrow frame of the display panel; and the display substrate also includes: a second routing line G2 connected to the first gate drive circuit GOA and extending along the second direction Y, a first routing line G1 connected to the second routing line G2 and extending along the first direction X, and the first routing line G1 is electrically connected to the gate line G0 at the end position, so that the signal output by the first gate drive circuit GOA can be transmitted to the end portion of the gate line G0 through the second routing line G2 and the first routing line G1. The gate line G0 is placed at a position where the signal is transmitted from the end position of the gate line G0 to the inside of the display area, so that the strongest driving point to the weakest driving point in each row of pixels are all from the end to the middle of the display area AA, that is, the brightest sub-pixel to the darkest sub-pixel in each row of pixels are all from the end to the middle of the display area AA, which is convenient for subsequent grayscale compensation and realizes uniform display of the display panel. It improves the problem in the related art that when the gate driving circuit is set on the upper frame of the display substrate, the position of the GOA signal in the brightest (or darkest) sub-pixel in each row of pixels is different, resulting in no regularity in the mura of the entire display panel and difficulty in grayscale compensation (Demura).

[0054] In the disclosed embodiment, each second routing wire G2 may extend from the binding opposite side area BB2 to the binding area BB1, and the extension length of each second routing wire G2 may be equal, so as to simplify the manufacturing process; the second routing wire G2 may cross with multiple first routing wires G1, but only when it is necessary to transmit the signal of the first gate driving circuit to the gate line G0 corresponding to the row of pixels, the first routing wire G1 located in the same routing group G as the gate line G0 will be electrically connected, that is, multiple first routing wires G1 are connected to each second routing wire G2 one by one.

[0055] In one possible embodiment, the number of gate lines of the display substrate may be consistent with the number of gate lines G0 in the routing group G, that is, a first routing line G1 may be correspondingly arranged at each gate line position in the display substrate, and a second routing line G2 may be correspondingly arranged, that is, all gate drive circuits of the display substrate may be arranged in the binding opposite side area BB2, and the scanning signal of each gate line is provided by the first gate drive circuit GOA located in the binding opposite side area BB2; in another possible embodiment, the number of gate lines of the display substrate may also be greater than the number of gate lines G0 in the routing group G, that is, the first routing line G1 may be correspondingly arranged at only the positions of some of the gate lines in the display substrate, and the second routing line G2 may be correspondingly arranged, that is, the display substrate may also have other gate drive circuits located in the first side area BB1 and / or the second side area BB2, and the remaining gate lines for which the first routing line G1 is not arranged may be directly provided with scanning signals by other gate drive circuits located in the first side area BB1 and / or the second side area BB2.

[0056] It should be noted that, in the embodiment of the present disclosure, the gate line G0 extends along the first direction X, and the gate line G0 may extend along the first direction X as a whole, but may be bent at a local position; similarly, the first wiring G1 extends along the first direction X, and the first wiring G1 may extend along the first direction X as a whole, but may be bent at a local position; similarly, the second wiring G2 extends along the second direction Y, and the second wiring G2 may extend along the second direction Y as a whole, but may be bent at a local position.

[0057] In one possible implementation, see Figure 2A and Figure 2B As shown, Figure 2A Can be Figure 1 A magnified schematic diagram of a sub-pixel in the figure. Figure 2B Can be Figure 2A The schematic diagram only includes the first routing line G1 and the second routing line G2, and the first routing line G1 includes: a first routing line main part G11 extending along the first direction X, and a first convex part G12 (which can be used as a lap pad) connected to the first routing line main part G11; a width b1 of the first convex part G12 perpendicular to the first direction X is greater than a width b2 of the first routing line main part G11 perpendicular to the first direction X;

[0058] The second routing line G2 includes: a second routing line main portion G21 extending along the second direction Y, and a second convex portion G22 (which can be used as a bonding pad) connected to the second routing line main portion G21; a width b3 of the second convex portion G22 perpendicular to the second direction Y is greater than a width b4 of the second routing line main portion G21 perpendicular to the second direction Y;

[0059] The orthographic projection of the second convex portion G22 on the substrate overlaps with the orthographic projection of the first convex portion G12 on the substrate, and a hole is punched at the overlapping position to electrically connect. Figure 2B As shown, the second protrusion G22 is electrically connected to the first protrusion G12 at the overlapping position through the first via K1.

[0060] In the disclosed embodiment, the first routing line G1 is also provided with a wider first protrusion G12, and the second routing line G2 is also provided with a wider second protrusion G22. Thus, when the electrical connection is made through punching, a better contact and conduction effect can be achieved, thereby avoiding the problem of the second routing line G2 and the first routing line G1 being too thin at the intersection, resulting in failure of conduction or poor conduction effect.

[0061] In one possible implementation, see Figure 2A and Figure 2B As shown, the size of the second convex portion G22 may be greater than the size of the first convex portion G12, that is, the orthographic projection of the second convex portion G22 on the substrate may cover and overlap the orthographic projection of the first convex portion G12 on the substrate.

[0062] In one possible embodiment, the second protrusion G22 and the first protrusion G12 may be provided only at the position where the second wiring G2 is connected to the first wiring G1; in another possible embodiment, the second protrusion G22 and the first protrusion G12 may be provided at the position where the second wiring G2 intersects the first wiring G1.

[0063] In one possible implementation, see Figure 1 As shown in FIG. 1 , the first wiring G1 and the gate line G0 are electrically connected at both end positions in the extension direction. Figure 1 As shown, the first wiring G1 and the gate line G0 are electrically connected at both left and right ends. In this way, the strongest point to the weakest point of the driving force in each row of pixels can be both at the left and right edges → the middle of the display area AA.

[0064] In a possible implementation, the first routing line G1 and the gate line G0 may also be electrically connected at one of the end positions in the extension direction, for example, they may be electrically connected only at a position close to the first side area BB3, for example, they may also be electrically connected only at a position close to the second side area BB4.

[0065] In one possible implementation, see Figure 3A , Figure 3B , Figure 3C As shown, Figure 3A Can be Figure 1 A magnified schematic diagram of the end of a pixel row in the middle. Figure 3B Can be Figure 3A The schematic diagram only includes the first routing line G1 and the gate line G0, Figure 3C Can be Figure 3A The schematic diagram only includes the first routing line G1, and the first routing line G1 also includes: a third convex portion G13 connected to the end of the first routing line main portion G11; a width b5 of the third convex portion G13 perpendicular to the first direction X is greater than a width b2 of the first routing line main portion G11 perpendicular to the first direction X;

[0066] The gate line G0 includes: a gate line main portion G01 extending along the first direction X, and a gate line convex portion G02 connected to the end of the gate line main portion G01; a width b6 of the gate line convex portion G02 perpendicular to the first direction X is greater than a width b7 of the gate line main portion G01 perpendicular to the first direction X;

[0067] The orthographic projection of the third convex portion G13 on the substrate overlaps with the orthographic projection of the gate line convex portion G02 on the substrate, and the two are connected by drilling holes at the overlapping positions.

[0068] In the disclosed embodiment, the first routing line G1 is further provided with a wider third protrusion G13 at the end position, and the gate line G0 is further provided with a gate protrusion G02 at the end position. In this way, when the electrical connection is made through punching, a better contact and conduction effect can be achieved, thereby avoiding the problem of failure to conduct or poor conduction effect due to the gate line G0 and the first routing line G1 being thin at the intersection.

[0069] In one possible implementation, see Figure 3C As shown, the third protrusion G13 includes: a first sub-protrusion G131 and a second sub-protrusion G132 arranged and connected along the second direction Y; the first sub-protrusion G131 is connected to the first wiring main part G11; the orthographic projection of the second sub-protrusion G132 on the substrate covers the orthographic projection of the gate line protrusion G02 on the substrate.

[0070] In one possible implementation, see Figure 2A As shown, the display substrate further includes: a plurality of data lines D extending along the second direction Y and arranged along the first direction X; and a second routing line G2 and the data line D are made of the same layer and the same material. In the disclosed embodiment, the second routing line G2 and the data line D are made of the same layer and the same material, and the second routing line G2 can be formed at the same time as the data line D is formed, thereby simplifying the manufacturing process of the display panel and reducing the cost.

[0071] In another possible implementation manner, the second wiring G2 and the data line D may also be in a different layer.

[0072] In a possible implementation, the data line D is located on the side of the gate line G0 away from the substrate; the first wiring G1 is located on the side of the data line D away from the gate line G0. Specifically, the display substrate may include: a first source-drain layer (SD1 layer), and a second source-drain layer (SD2 layer) located on the side of the first source-drain layer away from the substrate; the first source-drain layer may include a data line and a second wiring G2; the first wiring G1 may be located on the second source-drain layer. In this way, when the second source-drain layer is formed, the first wiring G1 may be formed to simplify the manufacturing process of the display panel and reduce costs.

[0073] In a possible implementation manner, the display substrate may further include a plurality of pixel circuits. Figure 2A As shown, the pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T7, and an eighth transistor T8; the connection relationship between the transistors may be the same as the connection method of a pixel circuit conventionally including eight transistors in a display substrate.

[0074] In one possible implementation, see Figure 1 As shown, the first gate driving circuit GOA includes: a plurality of M gate driving units arranged in sequence and cascaded along a first direction X (such as Figure 1 One end of the nth second wiring G2 is electrically connected to the nth gate driving unit to provide the signal of the nth gate driving unit to the gate line G0 in the nth wiring group G. For example, in combination with Figure 1 As shown, the direction from the first side area BB3 to the second side area BB4 (that is, Figure 1 The second second routing line G2 on the left-to-right direction in the figure and the second second routing line G3 on the left-to-right direction in the figure and the second second routing line G2 ... Figure 1 The second gate driving unit (from left to right in the figure) is electrically connected to provide the signal of the second gate driving unit (GO2) to the gate line G0 in the second wiring group G.

[0075] In one possible implementation, see Figure 4 As shown, the first gate driving circuit GOA includes: a first sub-gate driving circuit GO11, and a second sub-gate driving circuit GO12 located on a side of the first sub-gate driving circuit GO11 away from the display area AA; the first sub-gate driving circuit GO11 and the second sub-gate driving circuit GO11 extend along the first direction X and are arranged along the second direction Y;

[0076] The first sub-gate driving circuit GO11 includes: a plurality of M first sub-gate driving units (such as Figure 1GO1, GO2 . . . GOM shown in FIG); the second sub-gate driving circuit GO12 includes: a plurality of M second sub-gate driving units (such as GO1, GO2 . . . GOM) arranged in sequence along the first direction X and cascaded in sequence from the second end H2 to the first end H1 Figure 1 GOM, GOM-1, ... GO1) shown in FIG.

[0077] In the disclosed embodiment, the first gate drive circuit GOA includes: a first sub-gate drive circuit GO11, and a second sub-gate drive circuit GO12, which can enhance the driving force of GOA on the display substrate. Two rows of GOA units are designed in the binding opposite side area BB2 (i.e., the upper frame), one row of GOA units are arranged from left to right, and the other row of GOA units are arranged from right to left. Then, each row of pixels in the AA area will have two GOA output signals through the second routing line G2, and then connected to the first routing line G1, and finally connected to the gate line G0 of this row on the left and right sides of each row of pixels. With this design, the driving force of GOA on the display substrate is twice that of the conventional design.

[0078] In one possible implementation, see Figure 4 As shown, the display substrate further includes: P third wirings G3, the P third wirings G3 extend along the second direction Y and are arranged along the first direction X; wherein the nth third wiring G3 is electrically connected to the first wiring G1 in the M-(n-1)th wiring group G at the intersection position, n≤P, and P is a positive integer. For example, in combination Figure 4 As shown, the direction from the first side area BB3 to the second side area BB4 (that is, Figure 4 The second third routing line G3 on the left-to-right direction in FIG. 1 and the direction from the binding opposite side area BB2 to the binding area BB1 (i.e., Figure 4 The first wiring G1 in the M-(2-1)th gate line group G2 in the top-to-bottom direction (in the middle) is electrically connected at the crossing position.

[0079] In one possible implementation, see Figure 4 As shown, one end of the nth second wiring G2 is electrically connected to the nth first sub-gate driving unit from the first end H1 to the second end H2, so as to provide the signal of the nth first sub-gate driving unit to the gate line G0 in the nth wiring group; for example, in combination with Figure 4 As shown, the direction from the first side area BB3 to the second side area BB4 (that is, Figure 4 The second second trace G2 in the direction from left to right in the figure and the second second trace G2 in the direction from the first end H1 to the second end H2 (i.e. Figure 1The second first sub-gate driving unit (GO2 in the first sub-gate driving circuit GO11) is electrically connected to provide a signal of the second first sub-gate driving unit (GO2 in the first sub-gate driving circuit GO11) to the gate line G0 in the second wiring group G;

[0080] One end of the nth third routing wire G3 is electrically connected to the M-(n-1)th second sub-gate driving unit from the first end H1 to the second end H2, so as to provide the signal of the M-(n-1)th second sub-gate driving unit from the first end H1 to the second end H2 to the gate wire G0 in the M-(n-1)th routing wire group. Figure 4 As shown, the direction from the first side area BB3 to the second side area BB4 (that is, Figure 4 The second third trace G3 on the left-to-right direction in FIG. 1 and the second third trace G3 on the left-to-right direction in FIG. 1 and the second third trace G3 on the right-to-left ... Figure 4 The M-(2-1)th second sub-gate driving unit (GOM-1 in the second sub-gate driving circuit GO12) is electrically connected to provide the signal of the M-(2-1)th second sub-gate driving unit (GOM-1 in the second sub-gate driving circuit GO12) to the gate line G0 in the M-(2-1)th routing group G.

[0081] In a possible implementation, the third routing line G3 and the second routing line G2 are in the same layer and material. In the disclosed embodiment, the third routing line G3 and the second routing line G2 are in the same layer and material, and the second routing line G2 and the data line D are in the same layer and material. The second routing line G2 and the third routing line G3 can be formed at the same time as the data line D is formed, thereby simplifying the manufacturing process of the display panel and reducing costs.

[0082] In one possible implementation, see Figure 1 or Figure 4 As shown, the display substrate further includes: a plurality of first signal lines; the first signal lines extend from one end of the binding area BB1 to the other end of the binding area BB1 through the first side area BB3, the binding opposite side area BB2, and the second side area BB4.

[0083] In one possible implementation, see Figure 1 or Figure 4 As shown, the first signal line includes: a trigger signal line gstv, and / or a first clock signal line ck, and / or a second clock signal line cb.

[0084] In one possible implementation, see Figure 1 or Figure 4 As shown, the trigger signal line gstv can be connected to the first-stage gate driving unit (such as Figure 1 GO1 in, or, as Figure 4 GO1 in the first sub-gate drive circuit GO11, or, as Figure 4 GO1) in the second sub-gate driving circuit GO12 is electrically connected.

[0085] In one possible implementation, see Figure 1 or Figure 4 As shown, the first clock signal line ck and the second clock signal line cb can be alternately connected to the level gate driving unit in the first gate driving circuit GOA, for example, in combination with Figure 1 As shown, the first clock signal line ck can be connected to the first-level gate driving unit (GO1), the third-level gate driving unit (GO2), the fifth-level gate driving unit (GO5)... in the first gate driving circuit GOA, and the second clock signal line cb can be connected to the second-level gate driving unit (GO2), the fourth-level gate driving unit (GO4), the sixth-level gate driving unit (GO6)... in the first gate driving circuit GOA.

[0086] In one possible implementation, see Figure 5 or Figure 6 As shown, the display substrate may not be provided with the first wiring G1, and the second wiring G2 is directly connected to the gate G0. In this way, the signal in the first gate driving circuit GOA provided in the binding opposite side area BB2 can be transmitted to the gate line G0, and the narrow frame of the display panel can also be achieved.

[0087] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which includes a display substrate as provided in the embodiment of the present disclosure. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0088] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display substrate, comprising a display area, a binding area located on one side of the display area, and a binding opposite side area located on the other side of the display area and opposite to the binding area; wherein: The display substrate comprises: substrate; M routing groups, the M routing groups extending along a first direction and arranged along a second direction, at least one routing group among the M routing groups comprising: a gate line extending along the first direction and a first routing line; the first routing line and the gate line are electrically connected at at least one end position; N second routing lines, the N second routing lines extending along the second direction and arranged along the first direction; wherein the nth second routing line is electrically connected to the first routing line in the nth routing line group at a crossing position, n≤N, n≤M, and M, N, and n are positive integers; The first gate driving circuit is located in the binding opposite side area; one end of the second wiring is electrically connected to the first gate driving circuit to provide the signal of the first gate driving circuit to the gate line.

2. The display substrate according to claim 1, wherein: The first routing line includes: a first routing line main portion extending along the first direction, and a first convex portion connected to the first routing line main portion; a width of the first convex portion perpendicular to the first direction is greater than a width of the first routing line main portion perpendicular to the first direction; The second routing line includes: a second routing line main portion extending along the second direction, and a second convex portion connected to the second routing line main portion; a width of the second convex portion perpendicular to the second direction is greater than a width of the second routing line main portion perpendicular to the second direction; The orthographic projection of the second convex portion on the substrate overlaps with the orthographic projection of the first convex portion on the substrate, and a hole is punched at the overlapping position to electrically connect the two.

3. The display substrate according to claim 2, wherein: The first routing line and the gate line are electrically connected at two end positions in the extension direction.

4. The display substrate according to claim 3, wherein: The first routing line further includes: a third protrusion connected to the end of the main portion of the first routing line; the width of the third protrusion in a direction perpendicular to the first direction is greater than the width of the main portion of the first routing line in a direction perpendicular to the first direction; The gate line comprises: a gate line main portion extending along the first direction, and a gate line convex portion connected to an end of the gate line main portion; a width of the gate line convex portion perpendicular to the first direction is greater than a width of the gate line main portion perpendicular to the first direction; The orthographic projection of the third convex portion on the substrate overlaps with the orthographic projection of the gate line convex portion on the substrate, and the gate line convex portion and the gate line convex portion are connected by punching holes at the overlapping positions.

5. The display substrate according to claim 4, wherein: The third convex portion includes: a first sub-convex portion and a second sub-convex portion arranged and connected along the second direction; The first sub-protrusion is connected to the first wiring main part; the orthographic projection of the second sub-protrusion on the substrate covers the orthographic projection of the gate line protrusion on the substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: The display substrate further includes: a plurality of data lines extending along the second direction and arranged along the first direction; The second wiring and the data line are formed on the same layer and made of the same material.

7. The display substrate according to claim 6, wherein: The data line is located at a side of the gate line away from the substrate; and the first wiring is located at a side of the data line away from the gate line.

8. The display substrate according to any one of claims 1 to 7, wherein: The first gate driving circuit comprises: a plurality of M gate driving units sequentially arranged and cascaded along the first direction; One end of the nth second wiring is electrically connected to the nth gate driving unit to provide the signal of the nth gate driving unit to the gate line in the nth wiring group.

9. The display substrate according to any one of claims 1 to 8, wherein: The first gate driving circuit includes: a first sub-gate driving circuit, and a second sub-gate driving circuit located on a side of the first sub-gate driving circuit away from the display area; the first sub-gate driving circuit and the second sub-gate driving circuit extend along the first direction and are arranged along the second direction; The first sub-gate driving circuit includes: a plurality of M first sub-gate driving units arranged in sequence along the first direction and cascaded in sequence from the first end to the second end; the second sub-gate driving circuit includes: a plurality of M second sub-gate driving units arranged in sequence along the first direction and cascaded in sequence from the second end to the first end.

10. The display substrate according to claim 9, wherein: The display substrate also includes: P third routing lines, the P third routing lines extending along the second direction and arranged along the first direction; wherein the nth third routing line is electrically connected to the first routing line in the M-(n-1)th routing line group at a crossing position, n≤P, and P is a positive integer.

11. The display substrate according to claim 10, wherein: One end of the nth second routing line is electrically connected to the nth first sub-gate driving unit from the first end to the second end, so as to provide a signal of the nth first sub-gate driving unit to the gate line in the nth routing line group; One end of the nth third routing line is electrically connected to the M-(n-1)th second sub-gate driving unit from the first end to the second end, so as to provide a signal of the M-(n-1)th second sub-gate driving unit from the first end to the second end to the gate line in the M-(n-1)th routing group.

12. The display substrate according to any one of claims 10 or 11, wherein: The third routing line is formed on the same layer and made of the same material as the second routing line.

13. The display substrate according to any one of claims 1 to 12, wherein: The display substrate further comprises a first side region connecting one end of the binding region and one end of the binding opposite side region, and a second side region connecting the other end of the binding region and the other end of the binding opposite side region; The display substrate further includes: a plurality of first signal lines; the first signal lines extend from one end of the binding area, through the first side area, the binding opposite side area, and the second side area to the other end of the binding area.

14. The display substrate according to claim 13, wherein: The first signal line includes: a trigger signal line, and / or a first clock signal line, and / or a second clock signal line.

15. A display device, wherein: Comprising the display substrate as described in any one of claims 1-14.

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