Display device

Abstract

The invention relates to a display device. The display device includes a substrate, a driving transistor, an insulating layer, a light emitting element, and an insulating pattern. The driving transistors are disposed in the pixel region on the substrate and each include a first electrode and a second electrode. An insulating layer is disposed over the driving transistor to cover the first and second electrodes of the driving transistor, and has contact holes overlapping the first electrodes of the driving transistor, respectively. The light emitting element is disposed on the insulating layer and includes pixel electrodes overlapping the first electrodes of the driving transistors, respectively. Further, an insulating pattern is disposed in at least one of the contact holes to prevent the corresponding pixel region from emitting light.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0157652 filed in the Korean Intellectual Property Office on November 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device and a method of manufacturing a display device. Background Art

[0004] A variety of display devices have been developed. Examples include organic light emitting displays (OLEDs) and liquid crystal displays (LCDs). These display devices may include a display panel having a plurality of light emitting elements, such as light emitting diodes (LEDs). Examples of LEDs include organic LEDs using organic materials, such as fluorescent materials, and inorganic LEDs using inorganic materials, such as fluorescent materials.

[0005] However, in the process of manufacturing the lines and switches of the display device and the driving thin film transistor, a lighting defect may occur in the light emitting element due to the degradation of the characteristics of the driving thin film transistor or the occurrence of an internal short circuit. Therefore, the pixel area where the lighting defect occurs should be repaired. Summary of the invention

[0006] Embodiments provide a display device and a method of manufacturing the display device, which may have improved efficiency by repairing illumination defects of pixels.

[0007] According to aspects of the present disclosure, a display device having a pixel area is provided, the display device including: a substrate; a driving transistor, which is arranged in the pixel area on the substrate, and each of the driving transistors includes a first electrode and a second electrode; an insulating layer, which is arranged above the driving transistor to cover the first electrode and the second electrode of the driving transistor, and the insulating layer has contact holes that overlap with the first electrode of the driving transistor, respectively; a light-emitting element, which is arranged on the insulating layer, and the light-emitting element includes a pixel electrode that overlaps with the first electrode of the driving transistor, respectively; and an insulating pattern, which is arranged in at least one of the contact holes to prevent the corresponding pixel area in the pixel area from emitting light.

[0008] The pixel electrode may include a first pixel electrode and a second pixel electrode. The first pixel electrode may overlap the insulating pattern. The first pixel electrode may be electrically separated from a first electrode overlapping the first pixel electrode among the first electrodes of the driving transistor by the insulating pattern.

[0009] The second pixel electrode may be electrically connected to a first electrode of the first electrodes of the driving transistor overlapping the second pixel electrode through another contact hole of the contact holes.

[0010] The insulating pattern may include an inorganic material or an organic material.

[0011] The pixel circuits may be respectively arranged in the pixel regions on the substrate. The pixel circuits may include a driving transistor. The pixel circuits of the pixel regions overlapped with the insulating pattern in the pixel regions may correspond to defective pixel circuits.

[0012] The display device may further include a repair line extending from a first pixel electrode among the pixel electrodes overlapping the insulation pattern to overlap the common voltage line.

[0013] The common voltage line may be disposed on a bottom of the insulating layer. The repair line may be electrically connected to the common voltage line through another contact hole formed in the insulating layer.

[0014] The repair line may be formed in the same layer as the first pixel electrode.

[0015] The repair line may include a conductive material.

[0016] The first pixel electrode may be electrically connected to the common voltage line through the repair line.

[0017] The pixel area may extend in the first direction. The common voltage line may extend in the first direction to overlap the pixel area.

[0018] According to another aspect of the present disclosure, a method for manufacturing a display device is provided, the method comprising: forming driving transistors each including a first electrode and a second electrode in a pixel region on a substrate; forming an insulating layer covering the first electrode and the second electrode of the driving transistor, the insulating layer having contact holes respectively overlapping with the first electrode of the driving transistor; and forming a light-emitting element on the insulating layer, the light-emitting element including pixel electrodes respectively overlapping with the first electrode of the driving transistor, wherein forming the insulating layer further comprises forming an insulating pattern in at least one of the contact holes to prevent a corresponding pixel region in the pixel region from emitting light.

[0019] The pixel electrode may include a first pixel electrode and a second pixel electrode. The first pixel electrode may overlap the insulating pattern. The first pixel electrode may be electrically separated from a first electrode overlapping the first pixel electrode among the first electrodes of the driving transistor by the insulating pattern.

[0020] The second pixel electrode may be electrically connected to a first electrode of the first electrodes of the driving transistor overlapping the second pixel electrode through another contact hole of the contact holes.

[0021] The insulating pattern may include an inorganic material or an organic material.

[0022] The method may further include forming a repair line extending from a first pixel electrode among the pixel electrodes overlapping the insulation pattern to overlap the common voltage line.

[0023] The first pixel electrode may be electrically connected to the common voltage line through a repair line. The repair line may include a conductive material.

[0024] According to one embodiment, a pixel includes: a light emitting element; a pixel circuit configured to drive the light emitting element; and an insulating pattern that electrically disconnects the pixel circuit from the light emitting element when the pixel is defective. The pixel may also include a planarized insulating layer between a driving transistor of the pixel circuit and the light emitting element, wherein the planarized insulating layer includes a contact hole in which the insulating pattern is disposed. The pixel may also include a repair line that electrically connects an electrode of the light emitting element to a power supply voltage line, the power supply voltage line being configured to stabilize the electrode of the light emitting element when the pixel is defective. The insulating pattern may include insulating ink. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0026] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown that the Figure 1 A block diagram of an implementation of a pixel area in a unit pixel shown in FIG.

[0029] Figure 3 It is shown Figure 2 A circuit diagram of an embodiment of any one of the pixel circuits shown in .

[0030] Figure 4 It is shown that the Figure 2 0 is a plan view of an embodiment of the first conductive layer in the first pixel to the third pixel shown in .

[0031] Figure 5 It shows that the setting Figure 4 A plan view of an embodiment of an active layer on a first conductive layer is shown in FIG.

[0032] Figure 6 It shows that the setting Figure 5 A plan view of an embodiment of a second conductive layer on an active layer is shown in FIG.

[0033] Figure 7 It shows that the setting Figure 6 A plan view of an embodiment of a third conductive layer on a second conductive layer shown in FIG.

[0034] Figure 8 It shows that the setting Figure 7 A plan view of an embodiment of a pixel electrode layer on a third conductive layer shown in FIG.

[0035] Fig. 9 It shows that the setting Figure 8 A plan view of an insulating pattern in a unit pixel shown in FIG.

[0036] Fig.10 It shows that the setting Fig. 9 A plan view of the repair line in the unit pixel shown in FIG.

[0037] Fig.11 It is shown along Fig. 9 0 is a cross-sectional view of a portion of a pixel circuit and a light emitting element taken along a cross-sectional line II′ shown in FIG. 1 , which includes an insulating pattern in a contact hole of a defective pixel.

[0038] Fig.12 is a flow chart illustrating an embodiment of a method of manufacturing a display device. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the necessary parts for understanding the operation according to the present disclosure are described, and the description of other parts is omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the exemplary embodiments described herein, but can be implemented in various different forms. On the contrary, the exemplary embodiments described herein are provided to thoroughly and completely describe the disclosed content and fully convey the ideas of the present disclosure to those of ordinary skill in the art.

[0040] Throughout the specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or indirectly connected or coupled to the other element with one or more intervening elements interposed therebetween.

[0041] Figure 1 is a block diagram showing a display device DD according to an embodiment of the present disclosure.

[0042] refer to Figure 1 , the display device DD may include a display panel DP, a controller 110 , a data driver 120 , and a scan driver 130 .

[0043] The display panel DP may further include a plurality of unit pixels PX. The plurality of unit pixels PX may be arranged in the first direction DR1 and the second direction DR2. In addition, the display panel DP may be connected to a plurality of scan lines SCL1 to SCLm and a plurality of data lines DL1 to DLn. The plurality of scan lines SCL1 to SCLm and the plurality of data lines DL1 to DLn may be provided on the display panel DP and intersect each other at corresponding unit pixels PX in the unit pixels PX. The plurality of unit pixels PX in the display panel DP may be electrically connected to the scan lines SCL1 to SCLm and the data lines DL1 to DLn.

[0044] In addition, the plurality of unit pixels PX may be electrically connected to the sensing lines SL1 to SLn and the sensing control lines SSL1 to SSLm. The sensing control lines SSL1 to SSLm and the sensing lines SL1 to SLn may be arranged on the display panel DP while intersecting each other. As described in more detail below, the sensing lines SL1 to SLn may be configured to provide an initialization voltage Vint (see Figure 3 ) is applied to the corresponding unit pixel PX.

[0045] The display panel DP may be a panel of various types. A non-limiting example is an organic light emitting diode (OLED) panel. The type and number of lines provided in the display panel DP may vary according to the structure of the unit pixel PX, the type of display panel DP implemented, and / or various other features of the display panel DP.

[0046] The controller 110 may control the operation of the data driver 120 and the scan driver 130. In operation, the controller 110 may receive an image signal RGB and a control signal CTRL. The controller 110 may provide a first control signal SCS to the scan driver 130 to control the scan driver 130 to apply a scan signal to the scan lines SCL1 to SCLm at a timing implemented in each of a plurality of frames. In addition, the controller 110 may be configured to generate an image data signal DATA, which may be obtained by converting a data format of the image signal RGB into a form suitable for an interface specification of the data driver 120. The controller 110 may output a second control signal DCS to the data driver 120 to control the data driver 120 to apply a data voltage to the data lines DL1 to DLn when the scan signal is provided to the scan lines SCL1 to SCLm.

[0047] The controller 110 may be a timing controller or a control device including a timing controller capable of performing another control function. The controller 110 may be implemented as a separate component from the data driver 120 or implemented as an integrated circuit together with the data driver 120.

[0048] The data driver 120 may output data signals to a plurality of data lines DL1 to DLn. For example, the data driver 120 may receive a second control signal DCS and an image data signal DATA from the controller 110. The data driver 120 may convert the image data signal DATA into a data signal and output the data signal to a corresponding data line among the data lines DL1 to DLn. The data signal may be an analog voltage corresponding to a grayscale value of the image data signal DATA. For example, when a specific scan line is selected by the scan driver 130, the data driver 120 may provide a data voltage in an analog form to the plurality of data lines DL1 to DLn.

[0049] The data driver 120 may provide an initialization voltage Vint to the sensing lines SL1 to SLn during a display period. Thereafter, according to an embodiment, when a sensing control signal is provided to any one of the sensing control lines SSL1 to SSLm through the scan driver 130, the data driver 120 may sense emission characteristics of the corresponding unit pixels PX through the sensing lines SL1 to SLn.

[0050] In an embodiment, it is shown that the sensing lines SL1 to SLn are connected to the data driver 120. However, in some embodiments, a sensing driver separate from the data driver 120 may be provided in the display device DD, eg, the data driver 120 and the sensing driver may be implemented as components separate from each other.

[0051] The scan driver 130 may operate in response to a first control signal SCS from the controller 110. The scan driver 130 may output scan signals to a plurality of scan lines SCL1 to SCLm. In an embodiment, the scan driver 130 may include a gate driver. The scan driver 130 may sequentially provide scan signals to the scan lines SCL1 to SCLm according to the first control signal SCS from the controller 110.

[0052] The unit pixel PX receiving the scan signal may receive an analog voltage corresponding to the grayscale value of the image data signal DATA. Therefore, the unit pixel PX may output light having a brightness corresponding to the analog voltage. Therefore, an image may be displayed on the display panel DP.

[0053] At least one of the controller 110, the data driver 120, and the scan driver 130 may be mounted on the display panel DP in the form of an integrated circuit chip. Others of the controller 110, the data driver 120, and the scan driver 130 may be attached to the display panel DP in the form of a tape carrier package (TCP), for example, or mounted on a separate printed circuit board.

[0054] Figure 2 It is shown that the Figure 1 0 is a block diagram of an embodiment of a pixel area in a unit pixel PX shown in FIG.

[0055] refer to Figure 2 , each of the unit pixels PX may include a plurality of pixels (or sub-pixels), for example, each unit pixel PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. These pixels may emit light of a predetermined color. For example, the first pixel PX1 may emit red light, the second pixel PX2 may emit green light, and the third pixel PX3 may emit blue light. Alternatively, each of the unit pixels PX may emit color light of different combinations, and / or may further include a fourth pixel that emits white light.

[0056] exist Figure 2 In the embodiment, for the convenience of description, the first pixel PX1 to the third pixel PX3 are shown as being arranged in sequence. However, the embodiment is not limited thereto. For example, the present disclosure may be applied to a different number (eg, two) of pixels arranged in sequence.

[0057] Each of the pixels PX1 to PX3 may include a pixel circuit and at least one light emitting element. For example, the first pixel PX1 may include a first pixel circuit PC1 and a first light emitting element 410 controlled by the first pixel circuit PC1 to emit light. The second pixel PX2 may include a second pixel circuit PC2 and a second light emitting element 420 controlled by the second pixel circuit PC2 to emit light. The third pixel PX3 may include a third pixel circuit PC3 and a third light emitting element 430 controlled by the third pixel circuit PC3 to emit light. Each of the light emitting elements 410 to 430 may be, for example, an organic light emitting diode.

[0058] The first pixel area PXA1 to the third pixel area PXA3 may be arranged in a predetermined pattern, for example, may be sequentially arranged in the first direction DR1 on the substrate. The first pixel circuit PC1 of the first pixel PX1 may be disposed in the first pixel area PXA1 among the first pixel area PXA1 to the third pixel area PXA3 arranged in the first direction DR1. The second pixel circuit PC2 of the second pixel PX2 may be disposed in the second pixel area PXA2 among the first pixel area PXA1 to the third pixel area PXA3 arranged in the first direction DR1. The third pixel circuit PC3 of the third pixel PX3 may be disposed in the third pixel area PXA3 among the first pixel area PXA1 to the third pixel area PXA3 arranged in the first direction DR1. However, Figure 2 The arrangement of the pixel areas PXA1, PXA2, and PXA3 shown in FIG. 1 is merely illustrative, and embodiments are not limited thereto. In other embodiments, the pixel areas PXA1, PXA2, and PXA3 may be disposed in a different arrangement or pattern.

[0059] Figure 3 is shown as Figure 2 A circuit diagram of an embodiment of a pixel circuit is a representative example of any one of the pixel circuits shown in FIG. A first pixel PX1 is provided as a representative example. In the following, reference will be made to Figure 3 To describe Figure 2 The first pixel PX1 shown in FIG. Figure 2 The second pixel PX2 and the third pixel PX3 shown in FIG. 4 may be configured similarly to the first pixel PX1 .

[0060] refer to Figure 3 , the first pixel PX1 may include a first pixel circuit PC1 and a first light emitting element 410 connected to the first pixel circuit PC1. The first pixel circuit PC1 may include a plurality of transistors and at least one capacitor. For example, the first pixel circuit PC1 may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first transistor T1 may be a driving transistor, the second transistor T2 may be a switching transistor, and the third transistor T3 may be a sensing transistor. Figure 3 Each of the first transistor T1, the second transistor T2, and the third transistor T3 shown in FIG. 1 is shown as an N-type transistor, for example, a thin film transistor, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 may be a P-type transistor.

[0061] The first electrode of the first transistor T1 may be connected (or coupled) to a driving voltage line PL to which a driving voltage ELVDD is applied, and the second electrode of the first transistor T1 may be connected to a first pixel electrode (or anode electrode) of the first light emitting element 410. The gate electrode of the first transistor T1 may be connected to a first node N1. For example, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The first transistor T1 may control the amount of driving current provided to the first light emitting element 410 in correspondence with a voltage of the first node N1 (which corresponds to received data, for example, corresponding to an image data signal DATA).

[0062] The first electrode of the second transistor T2 may be connected to the jth data line DLj, and the second electrode of the second transistor T2 may be connected to the first node N1. In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line SCLi. When a signal having a turn-on voltage (e.g., a voltage having a high level) is provided from the i-th scan line SCLi, the second transistor T2 may be turned on. When the second transistor T2 is turned on, the second transistor T2 may electrically connect the j-th data line DLj and the first node N1 to each other. The image data signal DATA of the corresponding frame may be provided to the j-th data line DLj. The data signal may be transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged (or stored) in the storage capacitor Cst.

[0063] A first electrode of the storage capacitor Cst may be connected to the first node N1, and a second electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst may charge (or store) a voltage corresponding to a data signal supplied to the first node N1, and may maintain the charged voltage for a predetermined time, for example, until a data signal of a next frame is supplied.

[0064] A first electrode of the third transistor T3 may be connected to the jth sensing line SLj, and a second electrode of the third transistor T3 may be connected to the second node N2. The second node N2 may be connected to the first light emitting element 410. A gate electrode of the third transistor T3 may be connected to the i-th sensing control line SSLi. When a signal having a turn-on voltage (e.g., a voltage having a high level) is provided to the i-th sensing control line SSLi during a sensing period, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the third transistor T3 may electrically connect the j-th sensing line SLj and the second node N2 to each other. An initialization voltage Vint may be provided to the second node N2 through the third transistor T3.

[0065] In some embodiments, the sensing period may be a period for extracting characteristic information (e.g., a threshold voltage of the first transistor T1, etc.) of the unit pixel PX (or the corresponding first to third pixels PX1 to PX3). During the sensing period, the first transistor T1 may be turned on. The first transistor T1 may be connected to the j-th sensing line SLj through the third transistor T3. The characteristic information of the first pixel PX1 (e.g., including the threshold voltage of the first transistor T1, etc.) may be extracted through the j-th sensing line SLj.

[0066] The first light emitting element 410 may include a first pixel electrode (or anode electrode) and a second pixel electrode (or cathode electrode). A common voltage ELVSS may be applied to the second pixel electrode of the first light emitting element 410. The common voltage ELVSS may be a ground voltage or a predetermined reference voltage, which is a voltage higher or lower than the ground voltage. The common voltage ELVSS may vary according to a driving state such as image driving or sensing driving.

[0067] The first pixel circuit PC1 may be a pixel circuit of a first pixel PX1 arranged on an i-th row and a j-th column (i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n). In addition, the first pixel circuit PC1 may be connected to a j-th sensing line SLj and an i-th sensing control line SSLi. The first pixel circuit PC1 may control the first light emitting element 410 to emit light in response to a signal received through an i-th scan line SCLi and a j-th data line DLj.

[0068] Figure 4 It is shown that the Figure 2 1 is a plan view of an embodiment of the first conductive layer 10 in the first to third pixels PX1 to PX3 shown in FIG. The plan view may be an overlay view as a representative of the first conductive layer 10 of the first to third pixels PX1 to PX3.

[0069] The display panel DP may include a first conductive layer 10, an active layer 20 (see Figure 5 ), the second conductive layer 30 (see Figure 6 ), the third conductive layer 40 (see Figure 7 ) and the pixel electrode layer 50 (see Figure 8 ).

[0070] refer to Figure 4 , the first to third pixel regions PXA1 to PXA3 may be sequentially arranged in the first direction DR1. In addition, Figure 2The first pixel circuit PC1 to the third pixel circuit PC3 and the first light emitting element 410 to the third light emitting element 430 shown in the figure can be arranged in the first pixel area PXA1 to the third pixel area PXA3. The pixel circuits can be configured substantially similarly to each other in the corresponding pixel areas. Hereinafter, the technical scope of the present disclosure will be described based on the first pixel area PXA1. Each of the second pixel area PXA2 and the third pixel area PXA3 can be configured in a manner similar to the first pixel area PXA1.

[0071] The first conductive layer 10 may be formed on the substrate. The first conductive layer 10 may be a light blocking layer that blocks light introduced through the lower surface of the substrate. For example, the first conductive layer 10 may block light introduced into the first transistor T1 (see Figure 3 ), thereby preventing malfunction of the first transistor T1. For example, at least a portion of the first conductive layer 10 may be disposed on the substrate to overlap with the gate electrode of the first transistor T1.

[0072] The first conductive layer 10 may be electrically connected to the transistor. The first conductive layer 10 may include an auxiliary initialization voltage line 133, an auxiliary driving voltage line 134, an auxiliary common voltage line 135, a first auxiliary lower electrode 131, and a data line 150. The auxiliary initialization voltage line 133, the auxiliary driving voltage line 134, the auxiliary common voltage line 135, the first auxiliary lower electrode 131, and the data line 150 may be formed, for example, by the same process or different processes.

[0073] The auxiliary initialization voltage line 133, the auxiliary driving voltage line 134, the auxiliary common voltage line 135, and the data line 150 may extend substantially along the first direction DR1. The auxiliary initialization voltage line 133, the auxiliary driving voltage line 134, the auxiliary common voltage line 135, and the data line 150 may be disposed to be spaced apart from each other in the second direction DR2 (and thus may not be electrically connected to each other).

[0074] The data lines 150 may include a first data line 151, a second data line 152, and a third data line 153. The first data line 151, the second data line 152, and the third data line 153 may be disposed to be spaced apart from each other by a predetermined distance (and thus not electrically connected to each other). Any one of the data lines 150 may be used as included in Figure 3 The j-th data line DLj in the first pixel circuit PC1 shown in FIG.

[0075] In addition, the first auxiliary lower electrodes 131 may be individually formed for each pixel region. The first auxiliary lower electrodes 131 of the first to third pixel regions PXA1 to PXA3 may be disposed to be spaced apart from each other in the first direction DR1.

[0076] Figure 5 It shows that the setting Figure 4 0 is a plan view of an embodiment of an active layer 20 on a first conductive layer 10 shown in FIG. The active layer 20 may include an active (channel) region of a transistor used in a pixel circuit, which will be described in more detail below.

[0077] refer to Figure 5 , the first pixel circuit PC1 of the first pixel PX1 disposed in the first pixel area PXA1 may include a first driving transistor T11, a first switching transistor T12, and a first sensing transistor T13. The first driving transistor T11, the first switching transistor T12, and the first sensing transistor T13 may correspond to the first pixel circuit PC1 included in the first pixel area PXA1. Figure 3 The transistors T1 to T3 in the first pixel circuit PC1 shown in FIG.

[0078] The active layer 20 may be provided at Figure 4 The active layer 20 may include active regions of the first driving transistor T11, the first switching transistor T12, and the first sensing transistor T13, and the active regions may all be arranged in the same layer. The active layer 20 may form channels of the above-mentioned transistors T11 to T13. The active layer 20 may include a silicon semiconductor material or an oxide semiconductor material. For example, the active layer 20 may include amorphous silicon, polycrystalline silicon, etc.

[0079] The active layer 20 may include a channel region, a source region, and a drain region for each of the transistors T11 to T13. For example, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region may be electrically connected to the third conductive layer 40 (see FIG. 4 ) of each of the transistors T11 to T13, respectively. Figure 7 ) includes a first electrode (e.g., a source electrode) and a second electrode (e.g., a drain electrode).

[0080] refer to Figure 5 , the first driving active layer ACT11 may include a first driving channel region CA11 and a first driving source region and a first driving drain region disposed at respective sides of the first driving channel region CA11. These regions correspond to the first driving transistor T11. The first switching active layer ACT12 may include a first switching channel region CA12 and a first switching source region and a first switching drain region disposed at respective sides of the first switching channel region CA12. These regions correspond to the first switching transistor T12. In addition, the first sensing active layer ACT13 may include a first sensing channel region CA13 and a first sensing source region and a first sensing drain region disposed at respective sides of the first sensing channel region CA13. These regions correspond to the first sensing transistor T13.

[0081] Figure 6 It shows that the setting Figure 5 1 is a plan view of an embodiment of a second conductive layer 30 on the active layer 20 shown in FIG. The second conductive layer 30 provides lines for the unit pixels PX.

[0082] refer to Figure 6 , the second conductive layer 30 may include a scan line pattern 121, a sensing control line pattern 123, a first lower electrode 141, a driving voltage line pattern 124, and a common voltage line pattern 125. The scan line pattern 121, the sensing control line pattern 123, the first lower electrode 141, the driving voltage line pattern 124, and the common voltage line pattern 125 may include the same material or different materials. For example, the scan line pattern 121, the sensing control line pattern 123, the first lower electrode 141, the driving voltage line pattern 124, and the common voltage line pattern 125 may include metal, alloy, conductive metal oxide, transparent conductive material, etc., and are formed as a single layer or multiple layers.

[0083] A portion or a protruding portion of each of the scan line pattern 121, the sensing control line pattern 123, and the first lower electrode 141 may correspond to a portion of the scanning line pattern 121, the sensing control line pattern 123, and the first lower electrode 141. Figure 3 The gate electrode of each of the transistors T1 to T3 in the first pixel circuit PC1 shown in FIG.

[0084] refer to Figure 5 and Figure 6 , the scan line pattern 121 may extend substantially in the first direction DR1 according to a predetermined pattern (e.g., a zigzag pattern). In addition, the scan line pattern 121 may overlap the first switch active layer ACT12 of the first switch transistor T12. The region where the scan line pattern 121 and the first switch channel region CA12 overlap each other may correspond to the gate electrode G12 of the first switch transistor T12.

[0085] The sensing control line pattern 123 may also extend substantially in the first direction DR1 in a zigzag pattern, unlike the pattern of the scan line pattern 121. In addition, the sensing control line pattern 123 may overlap the first sensing active layer ACT13 of the first sensing transistor T13. The region where the sensing control line pattern 123 and the first sensing channel region CA13 overlap each other may correspond to the gate electrode G13 of the first sensing transistor T13.

[0086] The first lower electrode 141 may be disposed between the scan line pattern 121 and the sensing control line pattern 123 along the second direction DR2. The first lower electrode 141 may overlap the first driving active layer ACT11 of the first driving transistor T11. A region where the first lower electrode 141 and the first driving channel region CA11 overlap each other may correspond to the gate electrode G11 of the first driving transistor T11. The first lower electrode 141 may also serve as a lower storage plate of the storage capacitor Cst.

[0087] The driving voltage line pattern 124 may be separately formed for each pixel region, and may extend between the scan line pattern 121 and the sensing control line pattern 123. The driving voltage line patterns 124 of the first to third pixel regions PXA1 to PXA3 may be disposed to be spaced apart from each other in the first direction DR1 (and thus electrically disconnected). On the other hand, the common voltage line pattern 125 may extend in the first direction DR1, and may be shared by (or overlapped with) the first to third pixel regions PXA1 to PXA3 or a greater number of pixel regions arranged in the first direction DR1.

[0088] Figure 7 It shows that the setting Figure 6 1 is a plan view of an embodiment of a third conductive layer 40 on the second conductive layer 30 shown in FIG. The third conductive layer 40 provides an additional line for the unit pixel PX.

[0089] refer to Figure 7 , the third conductive layer 40 may include a scan line 171, a sensing control line 173, a first upper electrode 161, a driving voltage line 234, and a common voltage line 235. The scan line 171, the sensing control line 173, the first upper electrode 161, the driving voltage line 234, and the common voltage line 235 may include the same or different materials. For example, the scan line 171, the sensing control line 173, the first upper electrode 161, the driving voltage line 234, and the common voltage line 235 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc., and are formed as a single layer or multiple layers. The third conductive layer 40 may also include an initialization voltage line 233.

[0090] refer to Figure 6 and Figure 7 The scan line 171 may be disposed at an upper side of the first upper electrode 161 in the first direction DR1 and extend in the second direction DR2. The scan line 171 may be connected to the scan line pattern 121 of the second conductive layer 30 through the contact hole 121a. The scan line 171 may be used as a Figure 3 The i-th scan line SCLi in the first pixel circuit PC1 shown in FIG.

[0091] The sensing control line 173 may be disposed at a lower side of the first upper electrode 161 in the first direction DR1 and may extend in the second direction DR2. The sensing control line 173 may be connected to the sensing control line pattern 123 of the second conductive layer 30 through the contact hole 123a. The sensing control line 173 may be used as a Figure 3 The i-th sensing control line SSLi in the first pixel circuit PC1 shown in FIG.

[0092] The initialization voltage line 233 may be arranged to be aligned with the sensing control line pattern 123 ( Figure 6 ) are adjacent to each other and extend in the first direction DR1. The initialization voltage line 233 may be connected to the first sensing active layer ACT13 through the contact hole 133a (see Figure 5 ) of the first sensing source region or the first sensing drain region. The initialization voltage line 233 can be used to provide Figure 3 The j-th sensing line SLj of the initialization voltage Vint shown in FIG.

[0093] The driving voltage line 234 may be arranged to be aligned with the driving voltage line pattern 124 ( Figure 6 ) overlap. Therefore, the driving voltage line 234 can be separately formed for each pixel region. In addition, the driving voltage line 234 can be connected to the first driving transistor T11 through the contact hole 135a (see Figure 5 ) of the first driving source region or the first driving drain region of the first driving active layer ACT11. In addition, the driving voltage line 234 may be connected to the driving voltage line pattern 124 of the second conductive layer 30 through another contact hole 135b.

[0094] The common voltage line 235 may be disposed to overlap the common voltage line pattern 125. The common voltage line 235 may be shared by a plurality of pixel regions PXA1, PXA2, and PXA3. The common voltage line 235 may be connected to the second conductive layer 30 ( Figure 6 ) of the common voltage line pattern 125. In this way, the driving voltage line 234 and the common voltage line 235 can be formed into a double-layer structure. In addition, the driving voltage line 234 and the common voltage line 235 can be used to provide, for example, Figure 3 1 and 2. The power lines of the driving voltage ELVDD and the common voltage ELVSS are shown in FIG.

[0095] The first upper electrode 161 may be disposed in each pixel region, respectively. The first upper electrodes 161 of the first to third pixel regions PXA1 to PXA3 may be disposed to be spaced apart from each other in the first direction DR1 . In addition, the first upper electrode 161 may be disposed to overlap the first lower electrode 141 .

[0096] The first upper electrode 161 may be connected to the first driving transistor T11 (see FIG. Figure 5 ) of the first driving source region or the first driving drain region of the first driving active layer ACT11. In addition, the first upper electrode 161 may be connected to the first sensing transistor T13 (see Figure 5 )'s first sensing source region or the first sensing drain region of the first sensing active layer ACT13.

[0097] The first upper electrode 161 may be a first electrode (eg, source electrode) or a second electrode (eg, drain electrode) of the first driving transistor T11, and may also function as an upper storage plate of the storage capacitor Cst. The first upper electrode 161 and the first lower electrode 141 may form Figure 3 The storage capacitor Cst shown in FIG.

[0098] The second data line 152 of the data lines 150 may be connected to the first switch transistor T12 through the contact hole 150a (see Figure 5 )'s first switch source region or first switch drain region of the first switch active layer ACT12.

[0099] Figure 8 It shows that the setting Figure 7 2 is a plan view of an embodiment of a pixel electrode layer 50 on a third conductive layer 40 shown in FIG.

[0100] refer to Figure 8 The pixel electrode layer 50 may include a first pixel electrode 320R, a second pixel electrode 320G, and a third pixel electrode 320B. In addition, the pixel electrode layer 50 may further include an auxiliary electrode 340 .

[0101] The first pixel electrode 320R, the second pixel electrode 320G and the third pixel electrode 320B are adjacent to each other and are arranged in a predetermined pattern, but can be arranged not to overlap each other. The first pixel electrode 320R can overlap with the first contact hole CNTH1. As described in more detail below, when the corresponding pixel in the pixel is found to be defective, the first contact hole CNTH1 can be filled with an insulating pattern. Therefore, the insulating pattern can repair the defective pixel by preventing the pixel from emitting light. The second pixel electrode 320G can overlap with the second contact hole CNTH2. In addition, the third pixel electrode 320B can overlap with the third contact hole CNTH3. In the case where these pixels are found to be defective, these additional holes may also include insulating patterns.

[0102] refer to Figure 7 and Figure 8, when the pixel is not defective, the first pixel electrode 320R can be connected to the first upper electrode 161 through the first contact hole CNTH1. The first pixel electrode 320R can be connected to the first upper electrode 161 to connect to the first electrode (e.g., source electrode) or the second electrode (e.g., drain electrode) of the first driving transistor T11. When the pixel is defective, the insulating pattern prevents the electrical connection between the first pixel electrode 320R and the first electrode or the second electrode of the first driving transistor T11. In addition, the first pixel electrode 320R can be connected to the first lower electrode 141 of the second conductive layer 30 through the first upper electrode 161.

[0103] The first pixel electrode 320R may be disposed to overlap with the driving voltage line 234. In addition, the first pixel electrode 320R may be disposed not to overlap with the sensing control line 173 (eg, see Figure 7 )overlapping.

[0104] Similarly, the second pixel electrode 320G may be connected to the first upper electrode 161 of the second pixel region PXA2 through the second contact hole CNTH2 , and the third pixel electrode 320B may be connected to the first upper electrode 161 of the third pixel region PXA3 through the third contact hole CNTH3 .

[0105] The auxiliary electrode 340 may be disposed at one side of the first pixel electrode 320R in the second direction DR2. The auxiliary electrode 340 may be connected to the common voltage line 235 (eg, see FIG. 2 ) through the fourth contact hole CNTH4. Figure 7 ).

[0106] Fig. 9 It shows that the setting Figure 8 2 is a plan view of an example of an insulating pattern IP in a unit pixel PX shown in FIG.

[0107] refer to Fig. 9 and Fig.11 , when a defect occurs in the pixel circuit according to the electrical inspection result, the insulating pattern IP may be disposed in at least one of the first to third contact holes CNTH1 to CNTH3 .

[0108] According to an embodiment, when a defect occurs in the first pixel circuit PC1 of the first pixel PX1, the first contact hole CNTH1 may be filled with the insulating pattern IP before the first pixel electrode 320R. Therefore, the first pixel circuit PC1 and the first pixel electrode 320R are electrically disconnected from each other by the insulating pattern IP, so that the degradation of the electrical characteristics according to the lighting defect of the first pixel PX1 can be prevented or at least reduced. For example, the leakage current in the first pixel circuit PC1 and / or the first pixel electrode 320R can be prevented or at least reduced. Therefore, when the first pixel PX1 is defective, the electrical characteristics of the first pixel PX1 can be repaired in this way. The first contact hole CNTH1 may be a contact hole overlapping with the first pixel electrode 320R of the first pixel PX1 in which the defect occurs. The first contact hole CNTH1 may be a contact hole connected to the first upper electrode 161.

[0109] The insulating pattern IP may include an inorganic material or an organic material. For example, the inorganic material may include silicon oxide, silicon nitride, silicon oxynitride, etc., and may be used alone or in combination. In addition, the organic material may include a carbon component and include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0110] The insulating pattern IP may be formed in the first contact hole CNTH1 using, for example, an inkjet method. For example, when a defect occurs in the first pixel circuit PC1 of the first pixel PX1, insulating ink may be applied through a corresponding inkjet nozzle to fill in the first contact hole CNTH1. The filling process may fill the first contact hole CNTH1 completely or partially. In an embodiment where insulating ink is applied, the insulating pattern IP may be formed at the bottom surface and the side surface of the first contact hole CNTH1. In an embodiment, the insulating ink may be a solution including the same material as the insulating pattern IP.

[0111] In this way, the first pixel circuit PC1 corresponding to the defective pixel circuit can be separated from the first pixel electrode 320R by the insulating pattern IP provided in the first contact hole CNTH1. For example, the first electrode (e.g., source electrode) or the second electrode (e.g., drain electrode) of the first driving transistor T11 included in the first pixel circuit PC1 can be electrically separated (or disconnected) from the first pixel electrode 320R by the insulating pattern IP provided in the first contact hole CNTH1. Therefore, the first pixel PX1 can be blackened, for example, not emitting light.

[0112] On the other hand, the second pixel PX2 and the third pixel PX3 other than the first pixel PX1 may emit light normally.

[0113] In this way, the defective pixel of the display device DD can be blackened, for example, not emitting light. The pixel electrode of the defective pixel can remain in the emission area of ​​the display device DD, and maintain visibility similar to that of the peripheral normal pixel due to external light reflection. Therefore, the quality degradation of the display device DD can be suppressed or prevented.

[0114] In addition, since the insulating pattern IP is disposed in the first contact hole CNTH1, any separate space margin for a process for electrically separating the first pixel electrode 320R from the first pixel circuit PC1 may not be required. In addition, a repair process performed by laser cutting using a mask pattern may be omitted. Therefore, manufacturing costs may be reduced.

[0115] Fig.10 It shows that the setting Fig. 9 . A plan view of a repair line in a unit pixel PX shown in FIG. When the result of the electrical inspection indicates that the corresponding pixel is defective, a repair line may be formed. As will be described in more detail below, the repair line may stabilize the voltage of the pixel electrode of the defective pixel, which may otherwise be in a floating or other unstable state.

[0116] refer to Fig.10 The pixel electrode overlapped with the insulating pattern IP can be electrically connected to the common voltage line 235 through the repair line (see Figure 7 ).

[0117] According to an embodiment, when a defect occurs in the first pixel circuit PC1 of the first pixel PX1, a first repair line RL1 may be formed between the first pixel electrode 320R and the auxiliary electrode 340 overlapping the insulating pattern IP. The auxiliary electrode 340 may be connected to the first pixel circuit PC1 through the fourth contact hole CNTH4 (see FIG. Figure 8 ) is connected to the common voltage line 235.

[0118] The first repair line RL1 may be formed between the first pixel electrode 320R and the auxiliary electrode 340 using, for example, an inkjet method. For example, when the insulating pattern IP is formed in the first contact hole CNTH1, a conductive ink may be sprayed through an inkjet nozzle. The conductive ink may be sprayed onto the same layer as the first pixel electrode 320R. The conductive ink may be a conductive material including nanoparticles of a predetermined material, such as silver Ag.

[0119] For example, the first repair line RL1 may be formed by printing a conductive material in the same layer as the first pixel electrode 320R. Therefore, any additional process such as a deposition process and a patterning process for forming the first repair line RL1 is not required. Therefore, the manufacturing process may be simplified and the manufacturing cost may be reduced.

[0120] In addition, the first pixel electrode 320R may be connected to the auxiliary electrode 340 through the first repair line RL1. When the first pixel electrode 320R is separated from the first pixel circuit PC1 through the insulating pattern IP, the voltage of the first pixel electrode 320R may become unstable. The first pixel electrode 320R and the common voltage line 235 are connected to each other through the first repair line RL1, so that the voltage of the first pixel electrode 320R can be stabilized. For example, the voltage of the common voltage line 235 may be equal to the voltage applied to the light emitting elements 410 to 430 (see Figure 2 ). The first pixel region PXA1 may be more stably blackened, for example, more stably in a state where no light emission occurs.

[0121] On the other hand, the second pixel circuit PC2 and the third pixel circuit PC3 included in the second pixel PX2 and the third pixel PX3 (except the first pixel PX1) may be normal pixel circuits. Therefore, the repair line may not be formed in the second pixel circuit PC2 and the third pixel circuit PC3.

[0122] Fig.11 It is shown along Fig. 9 A cross-sectional view of a portion of a pixel circuit and a light-emitting element taken along line II' shown in FIG. Fig.11 In the embodiment, the pixel circuit is defective and thus includes the insulating pattern IP as explained previously.

[0123] refer to Fig.11 , a plurality of insulating layers may be disposed on the substrate SUB. A plurality of insulating layers may be disposed between the first conductive layer 10, the active layer 20, the second conductive layer 30, the third conductive layer 40 and the pixel electrode layer 50 as described above.

[0124] The buffer layer BUF may be disposed on the first conductive layer 10 (see Figure 4 ). The buffer layer BUF may include an inorganic insulating material covering the first conductive layer 10. For example, the buffer layer BUF may include a silicon oxide (SiO x ) or an oxide layer such as silicon nitride (SiN x The buffer layer BUF can prevent metal atoms or impurities from diffusing from the first conductive layer 10 into the active layer 20.

[0125] The gate insulating layer GI may be disposed on the active layer 20 (see Figure 5 ) and a second conductive layer 30 (see Figure 6 ). In addition, an interlayer insulating layer ILD may be disposed between the second conductive layer 30 and the third conductive layer 40 (see Figure 7 )between.

[0126] The planarization insulating layer PVX may be disposed on the third conductive layer 40. The planarization insulating layer PVX may be interposed between the pixel circuit and the light emitting element. The planarization insulating layer PVX may prevent damage to the pixel circuit or extraction of metal in subsequent processes. In addition, the planarization insulating layer PVX may stably support the light emitting element.

[0127] refer to Fig. 9 and Fig.11 As a result of the repair process, the first pixel PX1 may include an insulating pattern IP in a first contact hole CNTH1 formed in the planarization insulating layer PVX, for example, by the inkjet process discussed previously. The first pixel circuit PC1 included in the first pixel PX1 may correspond to a defective pixel circuit. Fig.11 As shown in FIG. 1 , the insulating pattern IP at least partially fills the first contact hole CNTH1 to electrically disconnect the first pixel circuit PC1 (eg, the drain region or the source region of the first driving transistor T11 ) from the light emitting element.

[0128] According to an embodiment, the first contact hole CNTH1 may expose the first electrode (eg, source electrode) A11 or the second electrode (eg, drain electrode) A12 of the first driving transistor T11 while passing through the planarization insulating layer PVX. Fig.11 , it is exemplarily shown that the first contact hole CNTH1 overlaps the first electrode A11 of the first driving transistor T11. The first contact hole CNTH1 may be disposed between the first pixel electrode 320R and the first electrode A11 of the first driving transistor T11.

[0129] When the first pixel circuit PC1 included in the first pixel area PXA1 is a defective pixel circuit, the insulating pattern IP may be disposed in the first contact hole CNTH1. The insulating pattern IP disposed in the first contact hole CNTH1 may electrically separate (or disconnect) the first electrode A11 of the first driving transistor T11 from the first pixel electrode 320R. Therefore, the first pixel PX1 may be blackened, for example, not emit light.

[0130] The first pixel electrode 320R may be disposed on the planarization insulating layer PVX. The pixel defining layer PDL may be disposed on the planarization insulating layer PVX. The pixel defining layer PDL may define an emission region. The pixel defining layer PDL may expose an upper surface of the first pixel electrode 320R. The intermediate layer 310 may be disposed on the first pixel electrode 320R exposed by the pixel defining layer PDL. The intermediate layer 310 may include a light emitting layer 312. In addition, the light emitting layer 312 may include an organic material including a fluorescent material or a phosphorescent material that emits light of a predetermined color (e.g., red, green, blue, or white). Functional layers 311 and 313 such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be further selectively disposed on the top / bottom of the light emitting layer 312. The common electrode 330 may be disposed on the light emitting layer 312. The first pixel electrode 320R, the light emitting layer 312, and a portion of the common electrode 330 may be used as a first light emitting element 410 (see Figure 3 ).

[0131] In an implementation, the first pixel electrode 320R may be a reflective electrode, and the common electrode 330 may be a transmissive electrode.

[0132] In the following, the manufacturing reference Figures 1 to 11 A method of displaying a device DD is described.

[0133] Fig.12 is a flow chart illustrating an embodiment of a method of manufacturing a display device DD.

[0134] refer to Fig.11 and Fig.12 In S1010 , a driving transistor may be formed in a corresponding pixel region (or pixel circuit) of a pixel on a substrate SUB.

[0135] In S1020, a planarization insulating layer PVX covering the first electrode and the second electrode of the driving transistor may be formed. The planarization insulating layer PVX may be considered to be included in the pixel circuit, or may be considered to be a layer between the pixel circuit and the light emitting element.

[0136] In S1030, a contact hole overlapping the first electrode of the driving transistor may be formed in the planarization insulating layer PVX. The contact hole may expose the first electrode of the driving transistor while passing through the planarization insulating layer PVX.

[0137] In S1040, at least one of the contact holes CNTH1 (eg, see Fig.11 ) to form an insulating pattern IP. Figure 2When a defect occurs in the first pixel circuit PC1 shown in , an insulating pattern IP may be formed in the first contact hole CNTH1 formed in the first pixel circuit PC1. The insulating pattern IP may be formed in the first contact hole CNTH1 using, for example, the inkjet method explained above. Therefore, when a defect occurs in the first pixel circuit PC1, insulating ink may be partially or completely filled in the first contact hole CNTH1 through an inkjet nozzle. For example, when forming the filled insulating ink, the insulating pattern IP may be formed at the bottom surface and the side surface of the first contact hole CNTH1. The insulating ink may be a solvent including the same material as the insulating pattern IP.

[0138] In this way, the insulating pattern IP disposed in the first contact hole CNTH1 may electrically separate (or disconnect) the first electrode A11 of the first driving transistor T11 from the first pixel electrode 320R formed subsequently, thereby preventing the light emitting element from emitting light.

[0139] In S1050, a light emitting element may be formed in the pixel region on the planarization insulating layer PVX. For example, a pixel electrode may be formed on the planarization insulating layer PVX, a light emitting layer may be formed on the pixel electrode, and a common electrode may be formed on the light emitting layer.

[0140] The first pixel circuit PC1 corresponding to the defective pixel circuit may be separated (electrically disconnected) from the first pixel electrode 320R by the insulating pattern IP provided in the first contact hole CNTH1. For example, the first electrode A11 of the first driving transistor T11 included in the first pixel circuit PC1 may be electrically separated from the first pixel electrode 320R by the insulating pattern IP provided in the first contact hole CNTH1. Therefore, the first pixel PX1 may be blackened, for example, may not emit light.

[0141] On the other hand, except for the first pixel PX1, the insulating pattern may not be formed in the contact holes of the other second pixels PX2 and the third pixels PX3. Therefore, the other second pixels PX2 and the third pixels PX3 may emit light normally.

[0142] Therefore, the defective pixel of the display device DD can be effectively blackened, for example, so that it does not work or is placed in a state where it does not emit light. The pixel electrode of the defective pixel can be retained in the emission area of ​​the display device DD, and maintains visibility similar to that of the peripheral normal pixel due to external light reflection. Therefore, the quality degradation of the display device DD can be suppressed or prevented.

[0143] In addition, since the insulating pattern IP is disposed in the contact hole, any separate space margin for a process for electrically separating the first pixel electrode 320R from the first pixel circuit PC1 may not be required. In addition, a repair laser cutting process using a mask pattern may be omitted. Therefore, manufacturing costs may be reduced.

[0144] According to the present disclosure, a display device and a method for manufacturing the same can be provided, which can have improved efficiency by repairing illumination defects of pixels. In an embodiment, the repair process can be understood as making the defective pixels non-functional, for example, placing the defective pixels in a non-luminous state.

[0145] Exemplary embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted only in a general and descriptive sense, and not for limiting purposes. In some cases, as will be apparent to one of ordinary skill in the art, at the time of filing this application, unless otherwise specifically stated, the features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the appended claims. The embodiments may be combined to form additional embodiments.

Claims

1. A display device having a pixel area, the display device comprising: substrate; a driving transistor disposed in the pixel region on the substrate, each of the driving transistors comprising a first electrode and a second electrode; an insulating layer, disposed on the driving transistor to cover the first electrode and the second electrode of the driving transistor, the insulating layer having contact holes respectively overlapping with the first electrode of the driving transistor; a light emitting element disposed on the insulating layer, the light emitting element comprising pixel electrodes respectively overlapping the first electrodes of the driving transistor; as well as An insulating pattern is disposed in at least one of the contact holes to prevent a corresponding pixel area among the pixel areas from emitting light.

2. The display device according to claim 1, wherein: The pixel electrode includes a first pixel electrode and a second pixel electrode. The first pixel electrode overlaps the insulating pattern, and The first pixel electrode is electrically separated from a first electrode of the first electrodes of the driving transistor that overlaps the first pixel electrode by the insulating pattern.

3. The display device according to claim 2, wherein: The second pixel electrode is electrically connected to a first electrode of the first electrodes of the driving transistor that overlaps with the second pixel electrode through another contact hole of the contact holes.

4. The display device according to claim 1, wherein: The insulating pattern includes an inorganic material or an organic material.

5. The display device according to claim 1, wherein: The pixel circuits are respectively arranged in the pixel areas on the substrate, The pixel circuit includes the driving transistor, and A pixel circuit of a pixel region among the pixel regions that overlaps the insulating pattern corresponds to a defective pixel circuit.

6. The display device according to claim 1, further comprising: A repair line extends from a first pixel electrode among the pixel electrodes overlapping the insulating pattern to overlap the common voltage line.

7. The display device according to claim 6, wherein: The common voltage line is disposed on the bottom of the insulating layer, and The repair line is electrically connected to the common voltage line through another contact hole formed in the insulating layer.

8. The display device according to claim 6, wherein: The repair line is formed in the same layer as the first pixel electrode.

9. The display device according to claim 6, wherein: The repair line includes a conductive material.

10. The display device according to claim 6, wherein: The first pixel electrode is electrically connected to the common voltage line through the repair line.

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