Display device

Abstract

A display device comprises a substrate, a circuit layer and an element layer. The substrate includes a display area and a non-display area disposed around the display area. The circuit layer includes: a first power line and a second power line disposed in the non-display area; light emitting pixel drivers arranged to be parallel to each other in the first direction and the second direction; a first power line extending in a first direction and electrically connected between the first power line and the light emitting pixel driver; a second power line extending in the first direction and transmitting third power; and grid auxiliary lines extending in the second direction. The grid auxiliary line includes: a first grid auxiliary line electrically connected to the first power line; and a second grid auxiliary line electrically connected to the second power line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0157155, filed on November 14, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device. Background Art

[0004] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0005] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light-emitting display device. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, a micron light-emitting display device including a micron light-emitting element, or a nano light-emitting display device including a nano light-emitting element.

[0006] Organic light-emitting display devices use light-emitting elements to display images, and each light-emitting element includes a light-emitting layer made of an organic light-emitting material. Since organic light-emitting display devices use self-luminous elements to realize image display, they can have relatively superior performance in terms of power consumption, response speed, emission efficiency, brightness, and wide viewing angle compared to other display devices.

[0007] The surface of the display device may be a display surface including a display area displaying an image and a non-display area surrounding the display area. A light emitting area emitting light having corresponding brightness and color may be arranged in the display area. Summary of the invention

[0008] The display device may include a light emitting element disposed in a light emitting region and a light emitting pixel driver electrically connected to the light emitting element.

[0009] Each of the light emitting pixel drivers may include a first transistor generating a driving current for the light emitting element.

[0010] For example, in order to make the first transistor of the light emitting pixel driver generate the driving current under the same condition even during high-speed driving, each of the light emitting pixel drivers may further include a circuit that compensates for the potential of the gate electrode of the first transistor.

[0011] However, for the uniformity of the first transistor, since the power for compensating the potential of the gate electrode of the first transistor needs to be uniformly supplied throughout the display area, the power for compensating the potential of the gate electrode of the first transistor needs to be transmitted through a grid-shaped line. Therefore, in the case where a separate power for compensating the potential of the gate electrode of the first transistor is transmitted to the light-emitting pixel driver, this may not be conducive to improving the resolution of the display device.

[0012] Aspects of the present disclosure provide a display device which is relatively advantageous in improving resolution while transmitting separate power for compensating for a potential of a gate electrode of a first transistor to a light emitting pixel driver through a mesh-shaped wire.

[0013] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0014] According to one aspect of the present disclosure, a display device is provided, which may include: a substrate; a circuit layer, which is arranged on the substrate; and an element layer, which is arranged on the circuit layer. The substrate may include a display area in which a light-emitting area is arranged and a non-display area arranged around the display area. The element layer may include a light-emitting element arranged in the light-emitting area. The circuit layer may include: a first power line and a second power line, which are arranged in the non-display area and transmit a first power and a second power for driving the light-emitting element, respectively; a light-emitting pixel driver, which is electrically connected to the light-emitting element and is arranged to be parallel to each other in a first direction and a second direction; a first power line, which extends in a first direction and is electrically connected between the first power line and the light-emitting pixel driver; a second power line, which extends in the first direction and transmits a third power different from the first power and the second power to the light-emitting pixel driver; and a grid auxiliary line, which extends in a second direction. The grid auxiliary line may include: a first grid auxiliary line, which is electrically connected to the first power line; and a second grid auxiliary line, which is electrically connected to the second power line.

[0015] The circuit layer may further include a data line extending in the second direction and transmitting the data signal to the light-emitting pixel driver. The data line may be adjacent to the grid auxiliary line. Each of the light-emitting elements may be electrically connected between each of the light-emitting pixel drivers and the line transmitting the second power. Each of the light-emitting pixel drivers may include: a first transistor electrically connected between a first node and a second node; a first pixel capacitor electrically connected between a third node and a fourth node; a second transistor electrically connected between a corresponding data line in the data line and a fourth node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a first initialization voltage line transmitting a first initialization voltage and a third node; a fifth transistor electrically connected between a corresponding second power line in the second power line and a fourth node; and a second pixel capacitor electrically connected between a corresponding first power line in the first power line and a fourth node. The first node may be electrically connected to a first electrode of the first transistor. The second node may be electrically connected to a second electrode of the first transistor. The third node may be electrically connected to a gate electrode of the first transistor.

[0016] Each of the light-emitting pixel drivers may further include: a sixth transistor electrically connected between the corresponding first power line and the first node; a seventh transistor electrically connected between the second node and the fifth node; an eighth transistor electrically connected between a bias voltage line transmitting a bias voltage and the first node; and a ninth transistor electrically connected between a second initialization voltage line transmitting a second initialization voltage and the fifth node. The fifth node may be electrically connected to each of the light-emitting elements.

[0017] The second transistor can be turned on by a scan write signal of a scan write line. The third transistor and the fifth transistor can be turned on by a gate control signal of a gate control line. The fourth transistor can be turned on by a scan initialization signal of a scan initialization line. The sixth transistor can be turned on by a first emission control signal of a first emission control line. The seventh transistor can be turned on by a second emission control signal of a second emission control line. The eighth transistor and the ninth transistor can be turned on by a bias control signal of a bias control line.

[0018] The first power lines and the second power lines may be arranged to alternate with each other in the second direction. Each of the light emitting pixel drivers may overlap with a corresponding first power line and a corresponding second power line.

[0019] The grid auxiliary lines may be disposed on one or more insulating layers covering the first power lines and one or more insulating layers covering the second power lines.

[0020] The circuit layer may further include a third power line disposed in the non-display area and transmitting a third power. Each of the second power line and the second grid auxiliary line may extend into the non-display area and may be electrically connected to the third power line.

[0021] The luminous pixel driver may include a first luminous pixel driver, a second luminous pixel driver, a third luminous pixel driver, and a fourth luminous pixel driver adjacent to each other in a first direction. The first grid auxiliary line may be arranged adjacent to a boundary between the first luminous pixel driver and the second luminous pixel driver. The second grid auxiliary line may be arranged adjacent to a boundary between the third luminous pixel driver and the fourth luminous pixel driver. The corresponding first power line and the corresponding second power line overlap with the first luminous pixel driver, the second luminous pixel driver, the third luminous pixel driver, and the fourth luminous pixel driver. The corresponding first power line may be electrically connected to the first grid auxiliary line through a first grid connection hole. The corresponding second power line may be electrically connected to the second grid auxiliary line through a second grid connection hole. The first grid connection hole may overlap with the first luminous pixel driver or the second luminous pixel driver. The second grid connection hole may overlap with the third luminous pixel driver or the fourth luminous pixel driver.

[0022] The luminous pixel driver may include a first luminous pixel driver and a second luminous pixel driver adjacent to each other in a first direction. The first grid auxiliary line may be adjacent to a boundary between the first luminous pixel driver and the second luminous pixel driver, and may overlap with the first luminous pixel driver. The second grid auxiliary line may be adjacent to a boundary between the first luminous pixel driver and the second luminous pixel driver, and may overlap with the second luminous pixel driver. The corresponding first power line and the corresponding second power line overlap with the first luminous pixel driver and the second luminous pixel driver. The corresponding first power line may be electrically connected to the first grid auxiliary line through a first grid connection hole. The corresponding second power line may be electrically connected to the second grid auxiliary line through a second grid connection hole. The first grid connection hole may overlap with the first luminous pixel driver. The second grid connection hole may overlap with the second luminous pixel driver.

[0023] The light-emitting area may include: a first light-emitting area emitting light of a first color; a second light-emitting area emitting light of a second color in a wavelength band lower than the wavelength band of the first color; and a third light-emitting area emitting light of a third color in a wavelength band lower than the wavelength band of the second color. The first light-emitting area and the third light-emitting area may be arranged to alternate with each other in a first direction. The second light-emitting area may be arranged to be parallel to each other in the first direction. The first light-emitting pixel driver may be electrically connected to a light-emitting element of one of the first light-emitting area and the third light-emitting area, and the second light-emitting pixel driver may be electrically connected to a light-emitting element of the second light-emitting area.

[0024] The circuit layer may include: a semiconductor layer, arranged on a substrate; a first gate insulating layer, covering the semiconductor layer; a first gate conductive layer, arranged on the first gate insulating layer; a second gate insulating layer, covering the first gate conductive layer; a second gate conductive layer, arranged on the second gate insulating layer; a third gate insulating layer, covering the second gate conductive layer; a third gate conductive layer, arranged on the third gate insulating layer; an interlayer insulating layer, covering the third gate conductive layer; a first source-drain conductive layer, arranged on the interlayer insulating layer; a first planarizing layer, covering the first source-drain conductive layer; a second source-drain conductive layer, arranged on the first planarizing layer; and a second planarizing layer, covering the second source-drain conductive layer. The first power line may be formed as the third gate conductive layer. The second power line may be formed as the first source-drain conductive layer. The grid auxiliary line may be formed as the second source-drain conductive layer.

[0025] The circuit layer may further include a capacitor electrode formed as a second gate conductive layer and electrically connected to the fourth node. The gate electrode of the first transistor may be formed as the first gate conductive layer. The first pixel capacitor may be formed between the capacitor electrode and the gate electrode of the first transistor. The second pixel capacitor may be formed between the capacitor electrode and the first power line.

[0026] Each of the first grid auxiliary line and the second grid auxiliary line may include a main line portion extending in the second direction and a secondary protrusion portion protruding from the main line portion. The circuit layer may further include a power connection electrode overlapping the secondary protrusion portion of the first grid auxiliary line and the first grid connection hole. The power connection electrode may be electrically connected to the first grid auxiliary line through the first grid auxiliary connection hole, and may be electrically connected to the corresponding first power line through the second grid auxiliary connection hole. The first grid connection hole may include a first grid auxiliary connection hole and a second grid auxiliary connection hole. The secondary protrusion portion of the second grid auxiliary line may overlap a portion of the corresponding second power line and the second grid connection hole.

[0027] The main line portion of the first grid auxiliary line and the main line portion of the second grid auxiliary line may be symmetrical to each other based on a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

[0028] According to one aspect of the present disclosure, a display device is provided, which may include: a substrate; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer. The substrate may include a display area in which a light-emitting area is arranged and a non-display area disposed around the display area. The element layer may include a light-emitting element disposed in the light-emitting area. The circuit layer may include: a first power line and a second power line, which are disposed in the non-display area and transmit a first power and a second power for driving the light-emitting element, respectively; a third power line, which is disposed in the non-display area and transmits a third power different from the first power and the second power; a light-emitting pixel driver, which is electrically connected to the light-emitting element and is arranged to be parallel to each other in a first direction and a second direction; a first power line, which extends in a first direction and is electrically connected between the first power line and the light-emitting pixel driver; a second power line, which extends in the first direction and transmits the third power to the light-emitting pixel driver; and a grid auxiliary line, which extends in a second direction. The grid auxiliary line may include: a first grid auxiliary line, which is electrically connected to the first power line; and a second grid auxiliary line, which is electrically connected to the second power line. The first grid auxiliary line and the second grid auxiliary line may be arranged to alternate with each other in the first direction. The first power line and the second power line may be arranged to alternate with each other in the second direction. Each of the light-emitting pixel drivers may overlap with a corresponding first power line and a corresponding second power line. Each of the second power line and the second grid auxiliary line may extend into the non-display area and may be electrically connected to the third power line.

[0029] The circuit layer may further include a data line extending in the second direction and transmitting the data signal to the light-emitting pixel driver. The data line may be adjacent to the grid auxiliary line. Each of the light-emitting elements may be electrically connected between each of the light-emitting pixel drivers and the line transmitting the second power. Each of the light-emitting pixel drivers may include: a first transistor electrically connected between a first node and a second node; a first pixel capacitor electrically connected between a third node and a fourth node; a second transistor electrically connected between a corresponding data line in the data line and a fourth node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a first initialization voltage line transmitting a first initialization voltage and a third node; a fifth transistor electrically connected between a corresponding second power line in the second power line and a fourth node; and a second pixel capacitor electrically connected between a corresponding first power line in the first power line and a fourth node. The first node may be electrically connected to a first electrode of the first transistor. The second node may be electrically connected to a second electrode of the first transistor. The third node may be electrically connected to a gate electrode of the first transistor.

[0030] The light-emitting pixel driver may include a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver adjacent to each other in a first direction. Each of the first grid auxiliary lines may be disposed adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. Each of the second grid auxiliary lines may be disposed adjacent to a boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver. The corresponding first power line and the corresponding second power line may overlap with the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver.

[0031] The luminous pixel driver may include a first luminous pixel driver and a second luminous pixel driver adjacent to each other in a first direction. Each of the first grid auxiliary lines may be adjacent to a boundary between the first luminous pixel driver and the second luminous pixel driver, and may overlap with the first luminous pixel driver. Each of the second grid auxiliary lines may be adjacent to a boundary between the first luminous pixel driver and the second luminous pixel driver, and may overlap with the second luminous pixel driver. The corresponding first power line and the corresponding second power line overlap with the first luminous pixel driver and the second luminous pixel driver.

[0032] The light-emitting area may include: a first light-emitting area emitting light of a first color; a second light-emitting area emitting light of a second color in a wavelength band lower than the wavelength band of the first color; and a third light-emitting area emitting light of a third color in a wavelength band lower than the wavelength band of the second color. The first light-emitting area and the third light-emitting area may be arranged to alternate with each other in a first direction. The second light-emitting area may be arranged to be parallel to each other in the first direction. The first light-emitting pixel driver may be electrically connected to a light-emitting element of one of the first light-emitting area and the third light-emitting area, and the second light-emitting pixel driver may be electrically connected to a light-emitting element of the second light-emitting area.

[0033] Each of the first grid auxiliary line and the second grid auxiliary line may include a main line portion extending in the second direction and a secondary protrusion portion protruding from the main line portion. The circuit layer may further include a power connection electrode overlapping the secondary protrusion portion of the corresponding first grid auxiliary line and the first grid connection hole. The power connection electrode may be electrically connected to the corresponding first grid auxiliary line through the first grid auxiliary connection hole, and may be electrically connected to the corresponding first power line through the second grid auxiliary connection hole. The first grid connection hole may include a first grid auxiliary connection hole and a second grid auxiliary connection hole. The secondary protrusion portion of the corresponding second grid auxiliary line may overlap with a portion of the corresponding second power line and the second grid connection hole. The main line portion of the corresponding first grid auxiliary line and the main line portion of the corresponding second grid auxiliary line may be symmetrical to each other based on the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

[0034] The display device according to the embodiment may include a substrate, a circuit layer, and an element layer.

[0035] The element layer may include light emitting elements respectively provided in light emitting regions arranged in the display region of the substrate.

[0036] The circuit layer may include: a first power line and a second power line, which are arranged in a non-display area of ​​the substrate and respectively transmit a first power and a second power for driving a light-emitting element; light-emitting pixel drivers, each electrically connected to the light-emitting element and arranged in a first direction and a second direction; a first power line, extending in a first direction and electrically connected between the first power line and the light-emitting pixel driver; a second power line, extending in the first direction and transmitting a third power different from the first power and the second power to the light-emitting pixel driver; and a grid auxiliary line, extending in a second direction.

[0037] The grid auxiliary line may include a first grid auxiliary line electrically connected to the first power line and a second grid auxiliary line electrically connected to the second power line.

[0038] According to an embodiment, each of the light-emitting pixel drivers may include: a first transistor between a first node and a second node; a first pixel capacitor between a third node and a fourth node; a second transistor between a data line and a fourth node; a third transistor between the second node and the third node; a fourth transistor between a first initialization voltage line and a third node; a fifth transistor between a second power line and a fourth node; and a second pixel capacitor between the first power line and the fourth node. The first node may correspond to a first electrode of the first transistor, the second node may correspond to a second electrode of the first transistor, and the third node may correspond to a gate electrode of the first transistor.

[0039] Therefore, according to an embodiment, when the fifth transistor is turned on, the potential of the third node (e.g., the gate electrode of the first transistor) can be compensated by the third power. For example, each light-emitting pixel driver may include a fifth transistor as a circuit for compensating the potential of the gate electrode of the first transistor.

[0040] Here, since the compensation of the potential of the gate electrode of the first transistor can be performed based on the third power instead of the first power, the first power can be used only to generate a drive current for the light-emitting element. Therefore, unlike the first power used to generate the drive current, since the third power is not used to generate the current, the compensation of the potential of the gate electrode of the first transistor can be performed more stably. As a result, high-speed driving of the display device can become more advantageous, and the image quality of the display device can be improved.

[0041] For example, according to an embodiment, first grid auxiliary lines that are some of the grid auxiliary lines adjacent to the data line may transmit first power, and second grid auxiliary lines that are the remaining ones of the grid auxiliary lines may transmit separate third power different from the first and second powers.

[0042] Since the first power lines in the first direction are electrically connected to the first grid auxiliary lines in the second direction, the first power may be applied to the light-emitting pixel driver through the grid-shaped lines.

[0043] In addition, since the second power lines in the first direction are electrically connected to the second grid auxiliary lines in the second direction, the third power may also be applied to the light-emitting pixel driver through the grid-shaped lines.

[0044] Therefore, since a separate third power for compensating for the potential of the gate electrode of the first transistor can be applied to the light emitting pixel driver through the mesh-shaped wires without adding a separate wire, it may be advantageous in improving resolution.

[0045] However, the effects according to the embodiment are not limited to those examples above, and various other effects are also incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0047] Figure 1 is a schematic perspective view illustrating a display device according to an embodiment;

[0048] Figure 2 It is a graphic Figure 1 A schematic plan view of a display device;

[0049] Figure 3 is along Figure 2 A schematic cross-sectional view taken along line AA';

[0050] Figure 4 It is a graphic Figure 2 a layout diagram of part B;

[0051] Figure 5 According to the embodiment Figure 4 A schematic diagram of an equivalent circuit of a light-emitting pixel driver;

[0052] Figure 6 It is a graphic Figure 2 A schematic plan view of a substrate and a circuit layer;

[0053] Figure 7 is a diagram illustrating a method according to an embodiment Figure 6a layout diagram of part C;

[0054] Figure 8 It is a graphic Figure 7 A schematic plan view of a portion D of FIG.

[0055] Fig. 9 is a diagram illustrating a method according to another embodiment Figure 6 a layout diagram of part C;

[0056] Fig.10 It is a graphic Fig. 9 A schematic plan view of a portion D of FIG.

[0057] Fig.11 It is a graphic Fig.10 A schematic plan view of a portion F of FIG.

[0058] Fig.12 It is a graphic Fig.11 A schematic plan view of a semiconductor layer, a first gate conductive layer, and a second gate conductive layer in a schematic plan view of ;

[0059] Fig.13 It is a graphic Fig.11 A schematic plan view of a semiconductor layer, a first gate conductive layer, a second gate conductive layer and a third gate conductive layer in a schematic plan view of ;

[0060] Fig.14 It is a graphic Fig.11 A schematic plan view of a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a third gate conductive layer and a first source-drain conductive layer in a schematic plan view of ;

[0061] Fig.15 is along Fig.11 A schematic cross-sectional view taken along line G-G'; and

[0062] Fig.16 is along Fig.11 Schematic cross-sectional view taken along line H-H'. DETAILED DESCRIPTION

[0063] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words of non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not necessarily have to be exclusive or limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment may be used or implemented in another embodiment.

[0064] Unless otherwise specified, the illustrated embodiments should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0065] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. Further, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiment can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals refer to the same elements.

[0066] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. In addition, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as, the X axis, the Y axis and the Z axis), and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be understood as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0067] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0068] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein, and thereby describe the relationship of one element relative to another (other) element as illustrated in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the term "below" can cover both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or oriented in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0069] The terms used herein are used to describe the purpose of specific embodiments, and are not intended to limit. As used herein, the singular forms "one" and "the (described)" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate the existence of stated features, integral bodies, steps, operations, elements, parts and / or its groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or its groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and are therefore utilized to consider the inherent deviations of the values ​​recognized by those of ordinary skill in the art, calculated and / or provided.

[0070] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes as a result of, for example, manufacturing techniques and / or tolerances, may be expected. Therefore, the embodiments disclosed herein need not be construed as limited to the specific illustrated shapes of the regions, but rather should include deviations in shape resulting from, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore are not necessarily intended to be limiting.

[0071] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control blocks, units and / or modules to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In addition, each block, unit and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0072] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0073] Figure 1 is a schematic perspective view illustrating a display device according to an embodiment. Figure 2 It is a graphic Figure 1 A schematic plan view of a display device. Figure 3 is along Figure 2 Schematic cross-sectional view taken along line AA'.

[0074] refer to Figure 1 and Figure 2 The display device 100 may be a device that displays moving images or still images, and may be used as a display screen for each of a variety of products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile personal computers (UMPCs).

[0075] The display device 100 may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device including a micro light-emitting diode or a nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device 100 will be mainly described based on the fact that it is an organic light-emitting display device. However, the embodiment is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light-emitting material, or a metal material.

[0076] The display device 100 may be formed to be flat, but the embodiment is not limited thereto. For example, the display device 100 may include a curved surface portion formed at the left and right distal ends thereof and having a constant curvature or a variable curvature. For example, the display device 100 may be flexibly formed to be bent, folded, or curled.

[0077] like Figure 1 , Figure 2 and Figure 3 As illustrated in FIG. 1 , the display device 100 may include a substrate 110 .

[0078] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub area SBA protruding from one side of the main area MA.

[0079] like Figure 2 As illustrated in FIG. 1 , the main area MA may include a display area DA disposed at most of a central portion and a non-display area NDA disposed around the display area DA.

[0080] The display area DA may be formed in a quadrilateral plane having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 crossing the first direction DR1. Corner portions where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a selected curvature or may be formed at a right angle. The plane shape of the display area DA is not limited to a quadrilateral shape, and the display area DA may be formed in other polygonal shapes, a circular shape, or an elliptical shape different from the quadrilateral shape.

[0081] The non-display area NDA may be disposed at an edge portion of the main area MA to surround the display area DA.

[0082] The sub area SBA may be an area protruding to one side from the non-display area NDA of the main area MA in the second direction DR2.

[0083] When a portion of the sub area SBA is deformed into a curved shape, the other portion of the sub area SBA may be disposed on the rear surface of the display device 100 .

[0084] Figure 2 and Figure 3 The display device 100 is illustrated in which a portion of the sub-area SBA is bent.

[0085] refer to Figure 3 , the display device 100 according to the embodiment may include a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0086] The display device 100 according to the embodiment may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140 .

[0087] For example, the display device 100 according to the embodiment may further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce or minimize reflection of external light.

[0088] The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that is bendable, foldable, or rollable.

[0089] In another example, the substrate 110 may be made of an insulating material such as glass.

[0090] The substrate 110 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0091] refer to Figure 3 The circuit board 300 may be connected (eg, electrically connected) to the circuit layer 120 and the display driving circuit 200 disposed on the substrate 110. The power supply unit 400 may be mounted on the circuit board 300. The power supply unit 400 may supply a power supply voltage to the circuit layer 120 through the circuit board 300.

[0092] Figure 4 It is a graphic Figure 2 Layout diagram of part B.

[0093] refer to Figure 4 , the display area DA of the display device 100 according to the embodiment may include the emission area EA. For example, the display area DA may further include a non-emission area disposed in a spacing area between the emission areas EA.

[0094] The light-emitting pixel drivers EPDs, each corresponding to the light-emitting area EA, may be arranged in parallel with each other in the first direction DR1 and the second direction DR2 in the display area DA. The light-emitting pixel drivers EPDs may be connected (e.g., electrically connected) to the light-emitting elements (e.g., Figure 5 LE in ).

[0095] The light emitting area EA may have a rhombus planar shape or a rectangular planar shape (eg, a square planar shape). However, this is an example, and the planar shape of the light emitting area EA according to the embodiment is not limited to Figure 4 For example, the light emitting area EA may have other polygonal plan shapes such as a pentagon or a hexagon, or a circular plan shape or an elliptical plan shape including a curved edge portion.

[0096] The light emitting area EA may include a first light emitting area EA1 emitting light of a first color in a selected wavelength band, a second light emitting area EA2 emitting light of a second color in a wavelength band lower than the wavelength band of the first color, and a third light emitting area EA3 emitting light of a third color in a wavelength band lower than the wavelength band of the second color.

[0097] As an example, the first color may be red in a wavelength band of about 600 nm to about 750 nm. The second color may be green in a wavelength band of about 480 nm to about 560 nm. The third color may be blue in a wavelength band of about 370 nm to about 460 nm.

[0098] The first and third light emitting regions EA1 and EA3 may be arranged to alternate with each other in at least one of the first and second directions DR1 and DR2.

[0099] As an example, in the second direction DR2, the first light emitting areas EA1 may be arranged parallel to each other, and the third light emitting areas EA3 may be arranged parallel to each other. For example, in the first direction DR1, the first light emitting areas EA1 and the third light emitting areas EA3 may be arranged alternately with each other.

[0100] The second light emitting areas EA2 may be arranged to be parallel to each other in at least one direction of the first direction DR1 and the second direction DR2.

[0101] For example, the second light emitting region EA2 may be adjacent to the first and third light emitting regions EA1 and EA3 in diagonal directions DR4 and DR5 crossing the first and second directions DR1 and DR2.

[0102] As an example, the second light emitting regions EA2 may be arranged parallel to each other in each of the first direction DR1 and the second direction DR2 , but may not be parallel to the first and third light emitting regions EA1 and EA3 .

[0103] According to an embodiment, the light-emitting pixel driver EPD may include a first light-emitting pixel driver EPD1 and a second light-emitting pixel driver EPD2 arranged in parallel with each other in the first direction DR1. For example, the light-emitting pixel driver EPD may further include a third light-emitting pixel driver EPD3 and a fourth light-emitting pixel driver EPD4 arranged in parallel with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 in the first direction DR1.

[0104] Since the light emitting area EA includes the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, each of the first light emitting pixel driver EPD1 and the third light emitting pixel driver EPD3 can be connected (e.g., electrically connected) to one of the light emitting elements of the first light emitting area EA1 and the third light emitting area EA3. For example, each of the second light emitting pixel driver EPD2 and the fourth light emitting pixel driver EPD4 can be connected (e.g., electrically connected) to the light emitting element in the second light emitting area EA2.

[0105] In addition, since the light-emitting area EA includes a first light-emitting area EA1, a second light-emitting area EA2, and a third light-emitting area EA3, the pixel PX displaying each brightness and color can be provided by one or more first light-emitting areas EA, one or more second light-emitting areas EA2, and one or more third light-emitting areas EA3 that are adjacent to each other in the light-emitting area EA.

[0106] For example, the pixel PX may be a basic unit for displaying various colors including white at a selected brightness.

[0107] Each of the pixels PX may include one or more first light emitting regions EA1, one or more second light emitting regions EA2, and one or more third light emitting regions EA3 adjacent to each other. As an example, each of the pixels PX may include a single first light emitting region EA1 and a single third light emitting region EA3 adjacent to each other in the first direction DR1, and two second light emitting regions EA2 adjacent to the single first light emitting region EA1 and the single third light emitting region EA3 in the fourth direction DR4. Accordingly, each of the pixels PX may display various colors by mixing light emitted from the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 adjacent to each other.

[0108] Figure 5 According to the embodiment Figure 4Schematic diagram of the equivalent circuit of the light-emitting pixel driver.

[0109] refer to Figure 5 , one of the light emitting elements LE of the element layer 130 may be connected (eg, electrically connected) between one of the light emitting pixel drivers EPD of the circuit layer 120 and a line transmitting the second power ELVSS.

[0110] For example, the first power ELVDD may be applied to the light emitting pixel driver EPD, the anode electrode of the light emitting element LE may be connected (e.g., electrically connected) to the light emitting pixel driver EPD, and the second power ELVSS having a voltage level lower than that of the first power ELVDD may be applied to the cathode electrode of the light emitting element LE. Accordingly, a driving current between the first power ELVDD and the second power ELVSS may be supplied to the light emitting element LE through the light emitting pixel driver EPD.

[0111] The circuit layer 120 may further include a data line DL transmitting a data signal Vdata, a first power line VDL transmitting a first power ELVDD, a first initialization voltage line VIL transmitting a first initialization voltage VINT, a second initialization voltage line VAIL transmitting a second initialization voltage VAINT, a second power line VRFL transmitting a third power VREF different from the first power ELVDD and the second power ELVSS, and a bias voltage line VBL transmitting a bias voltage VBS.

[0112] The circuit layer 120 may further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, a gate control line GCL for transmitting a gate control signal GC, a first emission control line ECL1 for transmitting a first emission control signal EC1, a second emission control line ECL2 for transmitting a second emission control signal EC2, and a bias control line BCL for transmitting a bias control signal BC.

[0113] One of the light emitting pixel drivers EPD of the circuit layer 120 may include a first transistor T1 generating a driving current for driving the light emitting element LE, two or more transistors T2 to T9 connected (eg, electrically connected) to the first transistor T1, and one or more pixel capacitors PC1 and PC2.

[0114] For example, according to an embodiment, the light-emitting pixel driver EPD may include a first transistor T1 connected (e.g., electrically connected) between a first node N1 and a second node N2, a first pixel capacitor PC1 connected (e.g., electrically connected) between a third node N3 and a fourth node N4, a second transistor T2 connected (e.g., electrically connected) between a data line DL and a fourth node N4, a third transistor T3 connected (e.g., electrically connected) between the second node N2 and the third node N3, a fourth transistor T4 connected (e.g., electrically connected) between a first initialization voltage line VIL and the third node N3, and a fifth transistor T5 connected (e.g., electrically connected) between a second power line VRFL and the fourth node N4.

[0115] The first node N1 may be connected (e.g., electrically connected) to a first electrode (e.g., a source electrode) of the first transistor T1. The second node N2 may be connected (e.g., electrically connected) to a second electrode (e.g., a drain electrode) of the first transistor T1. The third node N3 may be connected (e.g., electrically connected) to a gate electrode of the first transistor T1.

[0116] According to an embodiment, the light-emitting pixel driver EPD may further include a sixth transistor T6 connected (e.g., electrically connected) between the first power line VDL and the first node N1, a seventh transistor T7 connected (e.g., electrically connected) between the second node N2 and the fifth node N5, an eighth transistor T8 connected (e.g., electrically connected) between the bias voltage line VBL and the first node N1, and a ninth transistor T9 connected (e.g., electrically connected) between the second initialization voltage line VAIL and the fifth node N5.

[0117] The fifth node N5 may be connected (eg, electrically connected) to the light emitting element LE.

[0118] The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0119] Accordingly, the potential of the third node N3 may be initialized to the first initialization voltage VINT through the turned-on fourth transistor T4.

[0120] The third transistor T3 and the fifth transistor T5 may be turned on by a gate control signal GC of a gate control line GCL.

[0121] Accordingly, the voltage difference between the second node N2 and the third node N3 may be reset by the turned-on third transistor T3. For example, the voltage difference between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1 may be reset (or initialized).

[0122] For example, the third power VREF may be applied to the fourth node N4 through the turned-on fifth transistor T5. Accordingly, since the charged voltage of the first pixel capacitor PC1 connected to the fourth node N4 varies based on the third power VREF, the potential of the gate electrode of the first transistor T1 connected to the first pixel capacitor PC1 may also be compensated based on the third power VREF.

[0123] The second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL.

[0124] Accordingly, the data signal Vdata of the data line DL may be transmitted to the first pixel capacitor PC1 connected to the fourth node N4 through the turned-on second transistor T2.

[0125] For example, the first pixel capacitor PC1 between the third node N3 and the fourth node N4 may be charged to a voltage level corresponding to a differential voltage (VREF-Vdata) between the third power VREF and the data signal Vdata.

[0126] When the voltage difference (e.g., gate-source voltage difference) between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 becomes a threshold voltage or more due to the voltage charged in the first pixel capacitor PC1, the first transistor T1 may be turned on. When the first transistor T1 is turned on, a drain-source current may be generated between the first electrode of the first transistor T1 and the second electrode of the first transistor T1, and may have an amplitude corresponding to the data signal Vdata. For example, a driving current having an amplitude corresponding to the data signal Vdata may be generated between the first node N1 and the second node N2 through the turned-on first transistor T1.

[0127] The eighth transistor T8 and the ninth transistor T9 may be turned on by a bias control signal BC of a bias control line BCL.

[0128] Accordingly, the potential of the first electrode of the first transistor T1 connected to the first node N1 may be reset to the bias voltage VBS through the turned-on eighth transistor T8 .

[0129] For example, the potential of the anode electrode of the light emitting element LE connected to the fifth node N5 may be initialized to the second initialization voltage VAINT by the turned-on ninth transistor T9.

[0130] The sixth transistor T6 may be turned on by the first emission control signal EC1 of the first emission control line ECL1 .

[0131] The seventh transistor T7 may be turned on by the second emission control signal EC2 of the second emission control line ECL2.

[0132] Since the first transistor T1 and the light emitting element LE are connected in series to each other between the first power line VDL transmitting the first power ELVDD and the line transmitting the second power ELVSS through the turned-on sixth transistor T6 and the turned-on seventh transistor T7, the drain-source current of the first transistor T1 can be supplied as a driving current of the light emitting element LE.

[0133] Accordingly, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0134] According to an embodiment, the third transistor T3 may include a plurality of sub-transistors connected in series. As an example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. For example, the potential of the gate electrode of the first transistor T1 may be prevented from changing due to leakage current caused by the turned-off third transistor T3.

[0135] According to the embodiment, Figure 5 As illustrated in FIG. 1 , the transistors T1 to T9 of each of the light-emitting pixel drivers EPD may be provided (or formed) as P-type MOSFETs. However, this is only an example, and at least some of the transistors T1 to T9 of each of the light-emitting pixel drivers EPD may also be provided (or formed) as N-type MOSFETs.

[0136] As described above, according to the embodiment, the light emitting pixel driver EPD may include a compensation circuit including a fifth transistor T5 to compensate for the potential of the gate electrode of the first transistor T1. For example, the potential of the gate electrode of the first transistor T1 may be compensated by the third power VREF through the turned-on fifth transistor T5.

[0137] Accordingly, compensation for the potential of the gate electrode of the first transistor T1 can be performed using a separate third power VREF instead of the first power ELVDD. As a result, since compensation for the potential of the gate electrode of the first transistor T1 is performed more stably, high-speed driving of the display device 100 can be more advantageous, and the image quality of the display device 100 can be improved.

[0138] According to an embodiment, in order to improve the uniformity of the driving characteristics of the first transistor T1 of all the light-emitting pixel drivers EPD, the third power VREF for compensating the potential of the gate electrode of the first transistor T1 may need to be supplied to the display area DA through a grid-shaped line including lines in the first direction DR1 and lines in the second direction DR2.

[0139] Figure 6 It is a graphic Figure 2 Schematic plan view of the substrate and circuit layer.

[0140] refer to Figure 6 , the display device 100 according to the embodiment may include a substrate 110 and a circuit layer 120 disposed on the substrate 110 .

[0141] The substrate 110 may include a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA.

[0142] The main area MA may include a display area DA disposed at a central portion and a non-display area NDA surrounding the display area DA.

[0143] The display area DA may include a light emitting area (eg, Figure 4 in EA).

[0144] The sub-area SBA may include a bending area BA deformed into a bending shape, a first sub-area SB1 disposed between one side of the bending area BA and the main area MA, and a second sub-area SB2 connected to the other side of the bending area BA.

[0145] In the case where the bending area BA is deformed into a bent shape, the second sub-area SB2 may be disposed under the substrate 110 and may overlap the main area MA.

[0146] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0147] According to an embodiment, the circuit layer 120 may include a circuit layer that is disposed in the non-display area NDA and transmits signals for driving the light emitting elements (eg, Figure 5 The first power of the LE in the Figure 5 ELVDD in) and a second power (e.g., Figure 5 The first power line VDSPL and the second power line VSSPL of the ELVSS in the light emitting region (eg, Figure 4 EA) of the light emitting element (e.g., Figure 5 LE in the first direction DR1 and the second direction DR2 are arranged parallel to each other. Figure 4 and Figure 5 ), extending in the first direction DR1 and connecting (eg, electrically connecting) the first power line VDSPL and the light-emitting pixel driver (eg, Figure 4 and Figure 5 The first power line VDL between the EPD in the first direction DR1 and the first power line VDL between the EPD in the first direction DR2 and the ... Figure 5 ELVDD in) and a second power (e.g., Figure 5 ELVSS) different third power (for example, Figure 5VREF in the ) is transmitted to the light-emitting pixel driver (for example, Figure 4 and Figure 5 The invention also provides a second power line VRFL of the EPD in the embodiment of the present invention and a mesh auxiliary line MASL extending in the second direction DR2.

[0148] The mesh auxiliary lines MASL may include a first mesh auxiliary line MASL1 connected (eg, electrically connected) to the first power line VDL and a second mesh auxiliary line MASL2 connected (eg, electrically connected) to the second power line VRFL.

[0149] According to an embodiment, the circuit layer 120 may further include a circuit extending in the second direction DR2 and transmitting the data signal (eg, Figure 5 Vdata in) is transmitted to the light-emitting pixel driver (for example, Figure 4 and Figure 5 The data line DL of the EPD in the device.

[0150] The data line DL may be adjacent to the mesh auxiliary line MASL.

[0151] According to an embodiment, the first power lines VDL and the second power lines VRFL may be arranged to alternate with each other in the second direction DR2.

[0152] For example, the first mesh auxiliary lines MASL1 and the second mesh auxiliary lines MASL2 may be arranged to alternate with each other in the first direction DR1.

[0153] According to an embodiment, since the first mesh auxiliary line MASL1 in the second direction DR2 among the mesh auxiliary lines MASL is connected (eg, electrically connected) to the first power line VDL in the first direction DR1, the first power (eg, Figure 5 The first power line VDL in the first direction DR1 and the first grid auxiliary line MASL1 in the second direction DR2 may be supplied to the entire display area DA. As a result, the first power (e.g., ELVDD in the first direction DR1) at a stable voltage level may be supplied to the entire display area DA through the grid-shaped lines including the first power line VDL in the first direction DR1 and the first grid auxiliary line MASL1 in the second direction DR2. Figure 5 ELVDD in) can be applied to a light-emitting pixel driver (e.g., Figure 4 and Figure 5 in EPD).

[0154] In addition, since the second mesh auxiliary line MASL2 in the second direction DR2 among the mesh auxiliary lines MASL is connected (eg, electrically connected) to the second power line VRFL in the first direction DR1, the first transistor (eg, Figure 5 The third electric power (for example, Figure 5The third power (e.g., VREF) in the first direction DR1 can also be supplied to the entire display area DA through the grid-shaped lines including the second power lines VRFL in the first direction DR1 and the second grid auxiliary lines MASL2 in the second direction DR2. As a result, in the entire display area DA, the third power (e.g., Figure 5 VREF in can be applied to the light-emitting pixel driver (e.g., Figure 4 and Figure 5 in EPD).

[0155] Therefore, due to the first power (eg, Figure 5 ELVDD in) and a second power (e.g., Figure 5 ELVSS) different third power (for example, Figure 5 VREF in the display area DA) can be applied to the light-emitting pixel drivers (eg, Figure 4 and Figure 5 The EPD in the display device 100 is therefore beneficial for improving the resolution of the display device 100.

[0156] According to an embodiment, the circuit layer 120 may further include a circuit that is disposed in the non-display area NDA and transmits a third power (eg, Figure 5 The third power line VRSPL of VREF in the circuit.

[0157] For example, the circuit layer 120 may further include a supply pad SPD disposed at an edge portion of the second sub-region SB2 .

[0158] Circuit Board( Figure 1 and Figure 3 300 ) may be bonded to the supply pad SPD and connected (eg, electrically connected) to the circuit layer 120 and the display driving circuit 200 .

[0159] The supply pad SPD may include a data supply pad DSPD connected (e.g., electrically connected) to the display driving circuit 200, a first power pad VDPD connected (e.g., electrically connected) to the first power line VDSPL, a second power pad VSPD connected (e.g., electrically connected) to the second power line VSSPL, and a third power pad VRPD connected (e.g., electrically connected) to the third power line VRSPL.

[0160] The first power line VDSPL may be disposed in parallel with a side facing the sub area SBA in an edge portion of the display area DA and extend to a first power pad VDPD of the sub area SBA.

[0161] The second power line VSSPL may be disposed in parallel with the remaining sides except for one side facing the sub area SBA in the edge portion of the display area DA and extend to the second power pad VSPD of the sub area SBA.

[0162] The third power line VRSPL may be disposed in parallel with the remaining sides except for one side facing the sub area SBA in the edge portion of the display area DA and extend to the third power pad VRPD of the sub area SBA.

[0163] The second power line VSSPL may be disposed between an edge portion of the substrate 110 and the third power line VRSPL. For example, the third power line VRSPL may be disposed between the second power line VSSPL and an edge portion of the display area DA. However, this is merely an example, and the arrangement and shape of each of the first power line VDSPL, the second power line VSSPL, and the third power line VRSPL may be changed as desired.

[0164] According to an embodiment, the circuit layer 120 may further include a data supply line DSPL disposed in the non-display area NDA, extending to the display driving circuit 200 of the sub-area SBA, and connected (eg, electrically connected) to the data line DL.

[0165] Figure 7 is a diagram illustrating Figure 6 Layout diagram of part C. Figure 8 It is a graphic Figure 7 Schematic plan view of portion D of FIG.

[0166] refer to Figure 7 and Figure 8 Since the display device 100 according to the embodiment is Figures 1 to 6 The display device 100 of the embodiment illustrated in the figure is basically the same, except that the light-emitting pixel driver EPD includes a first light-emitting pixel driver EPD1, a second light-emitting pixel driver EPD2, a third light-emitting pixel driver EPD3 and a fourth light-emitting pixel driver EPD4 that are adjacent to each other in the first direction DR1, the first grid auxiliary line MASL1 is arranged adjacent to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, and the second grid auxiliary line MASL2 is arranged adjacent to the boundary between the third light-emitting pixel driver EPD3 and the fourth light-emitting pixel driver EPD4, and therefore redundant description will be omitted below.

[0167] like Figure 7 and Figure 8 As illustrated in FIG. 1 , according to an embodiment, each of the light emitting pixel drivers EPD may overlap at least one of the first power lines VDL and at least one of the second power lines VRFL.

[0168] For example, the first to fourth light emitting pixel drivers EPD1 , EPD2 , EPD3 , and EPD4 adjacent to each other in the first direction DR1 may overlap the corresponding first power line VDL and the corresponding second power line VRFL.

[0169] like Figure 8 As illustrated in FIG. 1 , according to an embodiment, the first mesh auxiliary line MASL1 may be connected (eg, electrically connected) to the first power line VDL through the first mesh connection hole MCH1 .

[0170] For example, the second mesh auxiliary line MASL2 may be connected (eg, electrically connected) to the second power line VRFL through the second mesh connection hole MCH2.

[0171] According to an embodiment, the first mesh auxiliary line MASL1 may be adjacent to or may overlap a boundary between the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 .

[0172] Accordingly, the first grid connection hole MCH1 for electrical connection between the first grid auxiliary line MASL1 and the first power line VDL may be adjacent to or overlap the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2. For example, the first grid connection hole MCH1 may overlap the first light-emitting pixel driver EPD1 or the second light-emitting pixel driver EPD2.

[0173] The first mesh auxiliary line MASL1 may be adjacent to the data line DL connected (eg, electrically connected) to the first light emitting pixel driver EPD1 at one side in the first direction DR1.

[0174] At the other side in the first direction DR1 , the first mesh auxiliary line MASL1 may be adjacent to the data line DL connected (eg, electrically connected) to the second light emitting pixel driver EPD2 .

[0175] At the other side in the first direction DR1 , the data line DL connected (eg, electrically connected) to the second light emitting pixel driver EPD2 may face the data line DL connected (eg, electrically connected) to the third light emitting pixel driver EPD3 .

[0176] According to an embodiment, the second grid auxiliary line MASL2 may be adjacent to or overlap a boundary between the third pixel driver EPD3 and the fourth pixel driver EPD4. For example, the second grid connection hole MCH2 may overlap the third pixel driver EPD3 or the fourth pixel driver EPD4.

[0177] Accordingly, the second mesh connection hole MCH2 for electrical connection between the second mesh auxiliary line MASL2 and the second power line VRFL may be adjacent to or may overlap the boundary between the third light emitting pixel driver EPD3 and the fourth light emitting pixel driver EPD4 .

[0178] The second mesh auxiliary line MASL2 may be adjacent to the data line DL connected (eg, electrically connected) to the third light emitting pixel driver EPD3 at one side in the first direction DR1.

[0179] At the other side in the first direction DR1 , the second mesh auxiliary line MASL2 may be adjacent to the data line DL connected (eg, electrically connected) to the fourth light emitting pixel driver EPD4 .

[0180] As described above, according to Figure 7 and Figure 8 In the embodiment illustrated in FIG, a corresponding first grid auxiliary line MASL1 and a corresponding second grid auxiliary line MASL2 are disposed in each of four light-emitting pixel driver EPDs adjacent to each other in the first direction DR1. Therefore, in the case where the light-emitting pixel driver EPDs are arranged in a matrix having N columns (where N is the number of light-emitting pixel driver EPDs parallel to each other in the first direction DR1) and M rows (where M is the number of light-emitting pixel driver EPDs parallel to each other in the second direction DR2), the number of grid auxiliary lines MASL can be reduced to N / 2 instead of N. As a result, this can be beneficial to improving the resolution of the display device 100.

[0181] like Figure 4 As shown in the figure, among the light emitting areas EA, the first light emitting areas EA1 and the third light emitting areas EA3 can be arranged to alternate with each other in the first direction DR1, and the second light emitting areas EA2 can be arranged to be parallel to each other in the first direction DR1 and can be adjacent to the first light emitting areas EA and the third light emitting areas EA3 in the fourth direction DR4 or the fifth direction DR5.

[0182] Accordingly, each of the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 can be connected (e.g., electrically connected) to the light-emitting element LE of the first light-emitting area EA1 and one of the light-emitting elements LE of the third light-emitting area EA3, and each of the second light-emitting pixel driver EPD2 and the fourth light-emitting pixel driver EPD4 can be connected (e.g., electrically connected) to the light-emitting element LE of the second light-emitting area EA2.

[0183] according to Figure 7 and Figure 8In the embodiment illustrated in FIG. 1 , since the second grid auxiliary line MASL2 connected (e.g., electrically connected) to the second power line VRFL is disposed adjacent to the boundary between the third light-emitting pixel driver EPD3 and the fourth light-emitting pixel driver EPD4, the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 are relatively far from the second grid auxiliary line MASL2. As a result, the third power (e.g., Figure 5 The voltage level of VREF in the third light-emitting pixel driver EPD3 or the fourth light-emitting pixel driver EPD4 may be different from the third power (eg, Figure 5 As a result, since the brightness of the light emitting element LE connected (eg, electrically connected) to the second light emitting area EA2 of the second light emitting pixel driver EPD2 is reduced, an image quality problem such as spots may occur.

[0184] Accordingly, a display device 100 according to another embodiment is provided, in which the second mesh auxiliary line MASL2 connected (eg, electrically connected) to the second power line VRFL may be disposed adjacent to all the light emitting pixel drivers EPD.

[0185] Fig. 9 is a diagram illustrating a method according to another embodiment Figure 6 Layout diagram of part C. Fig.10 It is a graphic Fig. 9 Schematic plan view of portion D of FIG.

[0186] refer to Fig. 9 and Fig.10 Since the display device 100 according to the embodiment is Figures 1 to 6 The display device 100 of the embodiment shown in FIG. Figure 7 and Figure 8 The display device 100 of the embodiment illustrated in FIG is substantially the same, except that the light-emitting pixel driver EPD includes a first light-emitting pixel driver EPD1 and a second light-emitting pixel driver EPD2 that are adjacent to each other in a first direction DR1, a first grid auxiliary line MASL1 is disposed adjacent to a boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 and overlaps with the first light-emitting pixel driver EPD1, and a second grid auxiliary line MASL2 is disposed adjacent to a boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 and overlaps with the second light-emitting pixel driver EPD2, and therefore redundant description will be omitted below.

[0187] like Fig. 9 and Fig.10As illustrated in FIG. 1 , according to another embodiment, a corresponding first grid auxiliary line MASL1 and a corresponding second grid auxiliary line MASL2 among the grid auxiliary lines MASL may be disposed adjacent to a boundary between the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 .

[0188] The corresponding first grid auxiliary line MASL1 may overlap the first light emitting pixel driver EPD1. Accordingly, the first grid connection hole MCH1 for electrical connection between the first grid auxiliary line MASL1 and the first power line VDL may overlap the first light emitting pixel driver EPD1.

[0189] The corresponding second grid auxiliary line MASL2 may overlap with the second light emitting pixel driver EPD2. Accordingly, the second grid connection hole MCH2 for electrical connection between the second grid auxiliary line MASL2 and the second power line VRFL may overlap with the second light emitting pixel driver EPD2.

[0190] For example, the light emitting pixel driver EPD may further include third and fourth light emitting pixel drivers EPD3 and EPD4 arranged in parallel with the first and second light emitting pixel drivers EPD1 and EPD2 in the first direction DR1 and adjacent to each other.

[0191] Another first grid auxiliary line MASL1 and another second grid auxiliary line MASL2 among the grid auxiliary lines MASL may be disposed adjacent to a boundary between the third light emitting pixel driver EPD3 and the fourth light emitting pixel driver EPD4 .

[0192] Another first mesh auxiliary line MASL1 may overlap the third light emitting pixel driver EPD3 .

[0193] Another second mesh auxiliary line MASL2 may overlap the fourth light emitting pixel driver EPD4.

[0194] As described above, according to another embodiment, since all the light emitting pixel drivers EPD are disposed adjacent to each of the first and second mesh auxiliary lines MASL1 and MASL2 , the light emitting pixel drivers EPD may be relatively stably supplied with the first power ELVDD and the third power VREF.

[0195] For example, according to another embodiment, since each of the second light-emitting pixel driver EPD2 and the fourth light-emitting pixel driver EPD4 connected (e.g., electrically connected) to the light-emitting element LE of the second light-emitting area EA2 overlaps with the second grid auxiliary line MASL2 that transmits the third power VREF, each of the second light-emitting pixel driver EPD2 and the fourth light-emitting pixel driver EPD4 can be more stably supplied with the third power VREF for compensating for the potential of the gate electrode of the first transistor T1.

[0196] Considering that the light-emitting element LE of the second light-emitting area EA2 emits light with a brightness that varies relatively sensitively with respect to the amplitude of the driving current, when the third power VREF having a more stable voltage level is applied to the second light-emitting pixel driver EPD2 and the fourth light-emitting pixel driver EPD4 as in another embodiment, an improvement in the image quality of the display device 100 can be easily expected.

[0197] Fig.11 It is a graphic Fig.10 Schematic plan view of portion F of FIG. Fig.12 It is a graphic Fig.11 A schematic plan view of a semiconductor layer, a first gate conductive layer, and a second gate conductive layer in a schematic plan view of . Fig.13 It is a graphic Fig.11 A schematic plan view of a semiconductor layer, a first gate conductive layer, a second gate conductive layer and a third gate conductive layer in a schematic plan view of . Fig.14 It is a graphic Fig.11 A schematic plan view of a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a third gate conductive layer and a first source and drain conductive layer in a schematic plan view. Fig.15 is along Fig.11 Schematic cross-sectional view taken along line G-G'. Fig.16 is along Fig.11 Schematic cross-sectional view taken along line H-H'.

[0198] refer to Fig.15 and Fig.16 According to the embodiment, the circuit layer 120 of the display device 100 may include: a semiconductor layer (eg, SEL: Fig.12 , CH1, S1, D1, CH31, S31, D31, CH32, S32, D32, CH4, S4 and D4 in the embodiment of the present invention), a first gate insulating layer 122 covering the semiconductor layer, and a first gate conductive layer (e.g., GCDL1: Fig.12 and Fig.13, G1, GCL, G31, G32, G4, G5, G6 in the embodiment of the present invention), a second gate insulating layer 123 covering the first gate conductive layer, and a second gate conductive layer (e.g., GCDL2: Fig.12 and Fig.13 CAE in the embodiment, a third gate insulating layer 124 covering the second gate conductive layer, and a third gate conductive layer (eg, Fig.13 VDL in the middle), an interlayer insulating layer 125 covering the third gate conductive layer, and a first source-drain conductive layer (eg, SDCDL1: Fig.14 VRFL, ACE1, ACE2, ACE3, VDCE in the embodiment of the present invention), a first planarization layer 126 covering the first source-drain conductive layer, and a second source-drain conductive layer (for example, SDCDL2: Fig.11 DL, MASL) in the middle and a second planarization layer 127 covering the second source and drain conductive layer.

[0199] For example, according to an embodiment, the circuit layer 120 may further include a buffer layer 121 covering the substrate 110. In this case, the semiconductor layer (eg, SEL: Fig.12 CH1, S1, D1, CH31, S31, D31, CH32, S32, D32, CH4, S4 and D4) may be disposed on the buffer layer 121.

[0200] like Fig.12 , the first transistor T1 may include a channel CH1, a first electrode S1, a second electrode D1, and a gate electrode G1. The channel CH1, the first electrode S1, and the second electrode D1 of the first transistor T1 may be disposed on the semiconductor layer SEL. The first electrode S1 and the second electrode D1 of the first transistor T1 may be connected (e.g., electrically connected) to respective sides (e.g., opposite sides) of the channel CH1. The gate electrode G1 of the first transistor T1 may be formed as a first gate conductive layer GCDL1 and may overlap with the channel CH1 of the first transistor T1.

[0201] The third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32 connected in series.

[0202] The first sub-transistor T31 may include a channel CH31, a first electrode S31, a second electrode D31, and a gate electrode G31. The channel CH31, the first electrode S31, and the second electrode D31 of the first sub-transistor T31 may be disposed on the semiconductor layer SEL. The first electrode S31 and the second electrode D31 of the first sub-transistor T31 may be connected (e.g., electrically connected) to respective sides (e.g., opposite sides) of the channel CH31. The gate electrode G31 of the first sub-transistor T31 may be formed as a first gate conductive layer GCDL1 and may overlap with the channel CH31 of the first sub-transistor T31.

[0203] The second sub-transistor T32 may include a channel CH32, a first electrode S32, a second electrode D32, and a gate electrode G32. The channel CH32, the first electrode S32, and the second electrode D32 of the second sub-transistor T32 may be disposed on the semiconductor layer SEL. The first electrode S32 and the second electrode D32 of the second sub-transistor T32 may be connected (e.g., electrically connected) to each side (e.g., opposite sides) of the channel CH32. The gate electrode G32 of the second sub-transistor T32 may be formed as a first gate conductive layer GCDL1 and may overlap with the channel CH32 of the second sub-transistor T32.

[0204] The first electrode S31 of the first sub-transistor T31 may be connected (eg, electrically connected) to the second electrode D1 of the first transistor T1 .

[0205] The second electrode D31 of the first sub-transistor T31 may be connected (eg, electrically connected) to the first electrode S32 of the second sub-transistor T32 .

[0206] The gate electrode G31 of the first sub-transistor T31 and the gate electrode G32 of the second sub-transistor T32 may be formed as different portions of the gate control line GCL.

[0207] The gate control line GCL may be formed as a first gate conductive layer GCDL1 .

[0208] The fourth transistor T4 may include a channel CH4, a first electrode S4, a second electrode D4, and a gate electrode G4. The channel CH4, the first electrode S4, and the second electrode D4 of the fourth transistor T4 may be disposed on the semiconductor layer SEL. The first electrode S4 and the second electrode D4 of the fourth transistor T4 may be connected (e.g., electrically connected) to respective sides (e.g., opposite sides) of the channel CH4. The gate electrode G4 of the fourth transistor T4 may be formed as a first gate conductive layer GCDL1 and may overlap with the channel CH4 of the fourth transistor T4.

[0209] The second electrode D4 of the fourth transistor T4 may be connected (eg, electrically connected) to the second electrode D32 of the second sub-transistor T32 .

[0210] The fifth transistor T5 may include a channel CH5, a first electrode S5, a second electrode D5, and a gate electrode G5. The channel CH5, the first electrode S5, and the second electrode D5 of the fifth transistor T5 may be disposed on the semiconductor layer SEL. The first electrode S5 and the second electrode D5 of the fifth transistor T5 may be connected (e.g., electrically connected) to respective sides (e.g., opposite sides) of the channel CH5. The gate electrode G5 of the fifth transistor T5 may be formed as a first gate conductive layer GCDL1 and may overlap with the channel CH5 of the fifth transistor T5.

[0211] The gate electrode G5 of the fifth transistor T5 may be provided (or formed) as the other portion of the gate control line GCL.

[0212] The sixth transistor (eg, Figure 5 The gate electrode G6 of T6 in FIG. 1 may be formed as the first gate conductive layer GCDL1 .

[0213] For example, since the second transistor (eg, Figure 5 T2 in the figure), the sixth transistor T6, the seventh transistor (for example, Figure 5 T7), an eighth transistor (eg, Figure 5 T8 in ) and the ninth transistor (eg, Figure 5 T9 in the figure has a structure similar to that of the first transistor T1, the first sub-transistor T31, the second sub-transistor T32, the fourth transistor T4 and the fifth transistor T5 when they are provided (or formed) as N-type MOSFETs like the first transistor T1, the first sub-transistor T31, the second sub-transistor T32, the fourth transistor T4 and the fifth transistor T5, so redundant descriptions will be omitted below.

[0214] The capacitor electrode CAE may be formed as the second gate conductive layer GCDL2 .

[0215] The capacitor electrode CAE may overlap with the gate electrode G1 of the first transistor T1. As a result, the first pixel capacitor (eg, Figure 5 PC1 in FIG. 5 may be provided by an overlapping region between the gate electrode G1 of the first transistor T1 and the capacitor electrode CAE.

[0216] The semiconductor layer SEL, the first gate conductive layer GCDL1, and the second gate conductive layer GCDL2 of the first light emitting pixel driver EPD1 may be symmetrical with the semiconductor layer SEL, the first gate conductive layer GCDL1, and the second gate conductive layer GCDL2 of the second light emitting pixel driver EPD2 adjacent to the first light emitting pixel driver EPD1 in the first direction DR1.

[0217] refer to Fig.13, the first power line VDL may be formed as a third gate conductive layer GCDL3.

[0218] The first power line VDL may extend in the first direction DR1 and may overlap the capacitor electrode CAE. As a result, the second pixel capacitor (eg, Figure 5 PC2) in may be provided by an overlapping area between the capacitor electrode CAE and the first power line VDL.

[0219] refer to Fig.14 The second power line VRFL, the first auxiliary connection electrode ACE1, the second auxiliary connection electrode ACE2, the third auxiliary connection electrode ACE3, and the power connection electrode VDCE may be disposed on the first source-drain conductive layer SDCDL1.

[0220] The second power lines VRFL may extend in the first direction DR1.

[0221] The second power line VRFL may include a protruding portion overlapping a boundary between the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 .

[0222] like Fig.14 and Fig.16 As illustrated in FIG. 1 , a portion of the second power line VRFL may overlap the first electrode S5 of the fifth transistor T5 and the first connection hole CCH1 . Accordingly, the second power line VRFL may be connected (eg, electrically connected) to the first electrode S5 of the fifth transistor T5 through the first connection hole CCH1 .

[0223] like Fig.12 and Fig.14 As shown in FIG. 1 , the end of the first auxiliary connection electrode ACE1 may be connected to the second sub-transistor (eg, Fig.12 The second electrode (eg, Fig.12 D32 in) and a fourth transistor (eg, Fig.12 The second electrode (eg, Fig.12 D4) of the semiconductor layer (for example, Fig.12 The first auxiliary connection electrode ACE1 may overlap a portion of the SEL in the embodiment of the present invention, and the other end of the first auxiliary connection electrode ACE1 may overlap with the first transistor (eg, Fig.12 The gate electrode G1 of T1) overlaps.

[0224] like Fig.15 As illustrated in FIG. 1 , the first auxiliary connection electrode ACE1 may be connected (eg, electrically connected) to the gate electrode G1 of the first transistor T1 through the first auxiliary connection hole ACCH1 .

[0225] For example, the first auxiliary connection electrode ACE1 may be connected (eg, electrically connected) to the second sub transistor (eg, Fig.12 The second electrode (eg, Fig.12 D32 in) and a fourth transistor (eg, Fig.12 The second electrode (eg, Fig.12 D4 in ).

[0226] Accordingly, since the gate electrode G1 of the first transistor T1 is connected (eg, electrically connected) to the second sub-transistor (eg, Fig.12 The second electrode (eg, Fig.12 D32 in) and a fourth transistor (eg, Fig.12 The second electrode (eg, Fig.12 D4 in , so the third node ( Figure 5 N3 in ).

[0227] like Fig.15 and Fig.16 As illustrated in FIG. 1 , the second auxiliary connection electrode ACE2 may be connected (eg, electrically connected) to the capacitor electrode CAE through the third auxiliary connection hole ACCH3 , and may be connected (eg, electrically connected) to the second electrode D5 of the fifth transistor T5 through the fourth auxiliary connection hole ACCH4 .

[0228] For example, the extended portion of the second auxiliary connection electrode ACE2 may be connected (eg, electrically connected) to the second transistor (eg, Figure 5 The second electrode T2 in FIG.

[0229] Accordingly, the first pixel capacitor (eg, Figure 5 PC1 in), a second pixel capacitor (eg, Figure 5 PC2 in), the fifth transistor (eg, Figure 5 T5 in) and a second transistor (eg, Figure 5 The electrical connection between T2 in (eg, the fourth node (eg, Figure 5 N4)) in the figure can be provided by the second auxiliary connection electrode ACE2.

[0230] like Fig.14 As illustrated in FIG. 1 , the third auxiliary connection electrode ACE3 may be connected (eg, electrically connected) to the gate electrode G6 of the sixth transistor T6 of the first light emitting pixel driver EPD1 and the gate electrode G6 of the sixth transistor T6 of the second light emitting pixel driver EPD2 through the fifth auxiliary connection hole ACCH5 .

[0231] Accordingly, since the gate electrodes G6 of the sixth transistors T6 of the light emitting pixel drivers EPD adjacent in the first direction DR1 are connected (eg, electrically connected) to each other through the third auxiliary connection electrode ACE3 , the first emission control line ECL1 may be provided.

[0232] The power connection electrode VDCE may be provided in an island shape overlapping a boundary between the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 .

[0233] like Fig.11 As illustrated in FIG. 2 , the data lines DL and the mesh auxiliary lines MASL may extend in the second direction DR2 and may be disposed on the second source-drain conductive layer SDCDL2 .

[0234] The grid auxiliary lines MASL may include first and second grid auxiliary lines MASL1 and MASL2 disposed adjacent to a boundary between the first and second light emitting pixel drivers EPD1 and EPD2 adjacent to each other in the first direction DR1 .

[0235] The first and second mesh auxiliary lines MASL1 and MASL2 may include main line portions MLP1 and MLP2 extending in the second direction DR2 and sub-protrusion portions SPR1 and SPR2 protruding from the main line portions MLP1 and MLP2 , respectively.

[0236] According to an embodiment, the main line portion MLP1 of the first mesh auxiliary line MASL1 and the main line portion MLP2 of the second mesh auxiliary line MASL2 may be symmetrical to each other based on a boundary between the first light emitting pixel driver EPD1 and the second light emitting pixel driver EPD2 .

[0237] like Fig.11 As illustrated in FIG. 1 , the power connection electrode VDCE may overlap the first mesh connection hole MCH1 and the sub protrusion portion SPR1 of the first mesh auxiliary line MASL1 .

[0238] The first mesh auxiliary line MASL1 may be connected (eg, electrically connected) to the first power line VDL through the first mesh connection hole MCH1 and the power connection electrode VDCE.

[0239] For example, Fig.15 As illustrated in FIG. 1 , the power connection electrode VDCE may be connected (eg, electrically connected) to the first mesh auxiliary line MASL1 through the first mesh auxiliary connection hole MCH11 , and may be connected (eg, electrically connected) to the first power line VDL through the second mesh auxiliary connection hole MCH12 .

[0240] For example, the first mesh connection hole MCH1 for electrical connection between the first mesh auxiliary line MASL1 and the first power line VDL may include a first mesh auxiliary connection hole MCH11 and a second mesh auxiliary connection hole MCH12 .

[0241] The sub-protrusion portion SPR2 of the second mesh auxiliary line MASL2 may overlap the protrusion portion of the second power line VRFL and the second mesh connection hole MCH2 .

[0242] Accordingly, if Fig.16 As illustrated in FIG. 1 , the second mesh auxiliary line MASL2 may be connected (eg, electrically connected) to the second power line VRFL through a second mesh connection hole MCH2 .

[0243] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the claims.

Claims

1. A display device, comprising: substrate; A circuit layer is arranged on the substrate; as well as A component layer is arranged on the circuit layer, wherein The substrate includes a display area in which a light emitting area is arranged and a non-display area provided around the display area, The element layer includes a light emitting element disposed in the light emitting region, The circuit layer comprises: A first power line and a second power line are provided in the non-display area and transmit a first power and a second power for driving the light emitting element, respectively; a light-emitting pixel driver electrically connected to the light-emitting element and arranged parallel to each other in a first direction and a second direction; a first power line extending in the first direction and electrically connected between the first power line and the light-emitting pixel driver; a second power line extending in the first direction and transmitting a third power different from the first power and the second power to the light-emitting pixel driver; and The grid auxiliary lines extend in the second direction, and the grid auxiliary lines include a first grid auxiliary line electrically connected to the first power line and a second grid auxiliary line electrically connected to the second power line.

2. The display device according to claim 1, wherein: The circuit layer further includes a data line extending in the second direction and transmitting a data signal to the light-emitting pixel driver. The data line is adjacent to the grid auxiliary line, Each of the light emitting elements is electrically connected between each of the light emitting pixel drivers and a line that transmits the second power, Each of the light-emitting pixel drivers comprises: a first transistor electrically connected between the first node and the second node; a first pixel capacitor electrically connected between the third node and the fourth node; a second transistor electrically connected between a corresponding data line among the data lines and the fourth node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a first initialization voltage line transmitting a first initialization voltage and the third node; a fifth transistor electrically connected between a corresponding second power line among the second power lines and the fourth node; and a second pixel capacitor electrically connected between a corresponding first power line among the first power lines and the fourth node, The first node is electrically connected to a first electrode of the first transistor, The second node is electrically connected to the second electrode of the first transistor, and The third node is electrically connected to a gate electrode of the first transistor.

3. The display device according to claim 2, wherein: Each of the light-emitting pixel drivers further comprises: a sixth transistor electrically connected between the corresponding first power line and the first node; a seventh transistor electrically connected between the second node and the fifth node; an eighth transistor electrically connected between a bias voltage line transmitting a bias voltage and the first node; and a ninth transistor electrically connected between a second initialization voltage line transmitting a second initialization voltage and the fifth node, and The fifth node is electrically connected to each of the light emitting elements.

4. The display device according to claim 3, wherein: The second transistor is turned on by a scan write signal of a scan write line, The third transistor and the fifth transistor are turned on by a gate control signal of a gate control line, The fourth transistor is turned on by a scan initialization signal of a scan initialization line, The sixth transistor is turned on by a first emission control signal of the first emission control line, The seventh transistor is turned on by a second emission control signal of a second emission control line, and The eighth transistor and the ninth transistor are turned on by a bias control signal of a bias control line.

5. The display device according to claim 2, wherein: The first power lines and the second power lines are arranged to alternate with each other in the second direction, and Each of the light emitting pixel drivers overlaps the corresponding first power line and the corresponding second power line.

6. The display device according to claim 5, wherein: The grid auxiliary lines are disposed on one or more insulating layers covering the first power lines and one or more insulating layers covering the second power lines.

7. The display device according to claim 5, wherein: The circuit layer further includes a third power line disposed in the non-display area and transmitting the third power, and Each of the second power lines and the second grid auxiliary lines extends into the non-display area and is electrically connected to the third power lines.

8. The display device according to claim 7, wherein: The light-emitting pixel driver includes a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver adjacent to each other in the first direction, The first grid auxiliary line is arranged adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, The second grid auxiliary line is arranged adjacent to a boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver, The corresponding first power line and the corresponding second power line overlap with the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver, The corresponding first power line is electrically connected to the first grid auxiliary line through a first grid connection hole, The corresponding second power line is electrically connected to the second grid auxiliary line through a second grid connection hole, The first grid connection hole overlaps with the first light-emitting pixel driver or the second light-emitting pixel driver, and The second grid connection hole overlaps with the third light-emitting pixel driver or the fourth light-emitting pixel driver.

9. The display device according to claim 7, wherein: The light-emitting pixel driver includes a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the first direction, The first grid auxiliary line is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and overlaps with the first light-emitting pixel driver. The second grid auxiliary line is adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and overlaps with the second light-emitting pixel driver, The corresponding first power line and the corresponding second power line overlap with the first light-emitting pixel driver and the second light-emitting pixel driver, The corresponding first power line is electrically connected to the first grid auxiliary line through a first grid connection hole, The corresponding second power line is electrically connected to the second grid auxiliary line through a second grid connection hole, The first grid connection hole overlaps with the first light-emitting pixel driver, and The second grid connection hole overlaps with the second light-emitting pixel driver.

10. The display device according to claim 9, wherein: The light emitting area includes: A first light emitting region emitting light of a first color; a second light emitting region that emits light of a second color in a wavelength band lower than that of the first color; and a third light emitting region emitting light of a third color in a wavelength band lower than the wavelength band of the second color, The first light emitting areas and the third light emitting areas are arranged to alternate with each other in the first direction, The second light emitting regions are arranged parallel to each other in the first direction, The first light-emitting pixel driver is electrically connected to the light-emitting element of one of the first light-emitting area and the third light-emitting area, and The second light-emitting pixel driver is electrically connected to the light-emitting elements of the second light-emitting area.

11. The display device according to claim 9, wherein: The circuit layer comprises: A semiconductor layer is disposed on the substrate; a first gate insulating layer, covering the semiconductor layer; A first gate conductive layer, disposed on the first gate insulating layer; a second gate insulating layer, covering the first gate conductive layer; a second gate conductive layer, disposed on the second gate insulating layer; a third gate insulating layer, covering the second gate conductive layer; A third gate conductive layer is disposed on the third gate insulating layer; an interlayer insulating layer, covering the third gate conductive layer; A first source-drain conductive layer is disposed on the interlayer insulating layer; a first planarization layer, covering the first source-drain conductive layer; A second source-drain conductive layer, disposed on the first planarization layer; and a second planarization layer, covering the second source-drain conductive layer; The first electric power line is formed as the third gate conductive layer, The second power line is formed as the first source-drain conductive layer, and The grid auxiliary lines are formed as the second source-drain conductive layer.

12. The display device according to claim 11, wherein: The circuit layer further includes a capacitor electrode formed as the second gate conductive layer and electrically connected to the fourth node, The gate electrode of the first transistor is formed as the first gate conductive layer, The first pixel capacitor is formed between the capacitor electrode and the gate electrode of the first transistor, and The second pixel capacitor is formed between the capacitor electrode and the first power line.

13. The display device according to claim 9, wherein: Each of the first grid auxiliary lines and the second grid auxiliary lines includes a main line portion extending in the second direction and a secondary protruding portion protruding from the main line portion, The circuit layer further includes a power connection electrode overlapping the secondary protrusion of the first grid auxiliary line and the first grid connection hole, The power connection electrode is electrically connected to the first grid auxiliary line through a first grid auxiliary connection hole, and is electrically connected to the corresponding first power line through a second grid auxiliary connection hole, The first grid connection hole includes the first grid auxiliary connection hole and the second grid auxiliary connection hole, and The sub-protruding portion of the second grid auxiliary line overlaps a portion of the corresponding second power line and the second grid connection hole.

14. The display device according to claim 13, wherein: The main line portion of the first grid auxiliary line and the main line portion of the second grid auxiliary line are symmetrical to each other based on the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

15. A display device, comprising: substrate; A circuit layer is arranged on the substrate; as well as A component layer is arranged on the circuit layer, wherein The substrate includes a display area in which a light emitting area is arranged and a non-display area provided around the display area, The element layer includes a light emitting element disposed in the light emitting region, The circuit layer comprises: A first power line and a second power line are provided in the non-display area and transmit a first power and a second power for driving the light emitting element, respectively; a third power line disposed in the non-display area and transmitting a third power different from the first power and the second power; a light-emitting pixel driver electrically connected to the light-emitting element and arranged parallel to each other in a first direction and a second direction; a first power line extending in the first direction and electrically connected between the first power line and the light-emitting pixel driver; a second power line extending in the first direction and transmitting the third power to the light-emitting pixel driver; and Grid auxiliary lines, extending in the second direction, The grid auxiliary line includes a first grid auxiliary line electrically connected to the first power line and a second grid auxiliary line electrically connected to the second power line, The first grid auxiliary lines and the second grid auxiliary lines are arranged to alternate with each other in the first direction, The first power lines and the second power lines are arranged to alternate with each other in the second direction, Each of the light-emitting pixel drivers overlaps with a corresponding first power line and a corresponding second power line, and Each of the second power lines and the second grid auxiliary lines extends into the non-display area and is electrically connected to the third power lines.

16. The display device according to claim 15, wherein: The circuit layer further includes a data line extending in the second direction and transmitting a data signal to the light-emitting pixel driver. The data line is adjacent to the grid auxiliary line, Each of the light emitting elements is electrically connected between each of the light emitting pixel drivers and a line that transmits the second power, Each of the light-emitting pixel drivers comprises: a first transistor electrically connected between the first node and the second node; a first pixel capacitor electrically connected between the third node and the fourth node; a second transistor electrically connected between a corresponding data line among the data lines and the fourth node; a third transistor electrically connected between the second node and the third node; a fourth transistor electrically connected between a first initialization voltage line transmitting a first initialization voltage and the third node; a fifth transistor electrically connected between a corresponding second power line among the second power lines and the fourth node; and a second pixel capacitor electrically connected between a corresponding first power line among the first power lines and the fourth node, The first node is electrically connected to a first electrode of the first transistor, The second node is electrically connected to the second electrode of the first transistor, and The third node is electrically connected to a gate electrode of the first transistor.

17. The display device according to claim 16, wherein: The light-emitting pixel driver includes a first light-emitting pixel driver, a second light-emitting pixel driver, a third light-emitting pixel driver, and a fourth light-emitting pixel driver adjacent to each other in the first direction, Each of the first grid auxiliary lines is disposed adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, Each of the second grid auxiliary lines is disposed adjacent to a boundary between the third light-emitting pixel driver and the fourth light-emitting pixel driver, The corresponding first power line and the corresponding second power line overlap the first light emitting pixel driver, the second light emitting pixel driver, the third light emitting pixel driver, and the fourth light emitting pixel driver.

18. The display device according to claim 16, wherein: The light-emitting pixel driver includes a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the first direction, Each of the first grid auxiliary lines is adjacent to a boundary between the first light-emitting pixel driver and the second light-emitting pixel driver and overlaps with the first light-emitting pixel driver, Each of the second grid auxiliary lines is adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver and overlaps with the second light-emitting pixel driver, and The corresponding first power line and the corresponding second power line overlap with the first light emitting pixel driver and the second light emitting pixel driver.

19. The display device according to claim 18, wherein: The light emitting area includes: A first light emitting region emitting light of a first color; a second light emitting region that emits light of a second color in a wavelength band lower than that of the first color; and a third light emitting region emitting light of a third color in a wavelength band lower than the wavelength band of the second color, The first light emitting areas and the third light emitting areas are arranged to alternate with each other in the first direction, The second light emitting regions are arranged parallel to each other in the first direction, The first light-emitting pixel driver is electrically connected to the light-emitting element of one of the first light-emitting area and the third light-emitting area, and The second light-emitting pixel driver is electrically connected to the light-emitting elements of the second light-emitting area.

20. The display device according to claim 18, wherein: Each of the first grid auxiliary lines and the second grid auxiliary lines includes a main line portion extending in the second direction and a secondary protruding portion protruding from the main line portion, The circuit layer further includes a power connection electrode overlapping the sub-protrusion portion of the corresponding first grid auxiliary line and the first grid connection hole, The power connection electrode is electrically connected to the corresponding first grid auxiliary line through a first grid auxiliary connection hole, and is electrically connected to the corresponding first power line through a second grid auxiliary connection hole, The first grid connection hole includes the first grid auxiliary connection hole and the second grid auxiliary connection hole, The secondary protrusion of the corresponding second grid auxiliary line overlaps with a portion of the corresponding second power line and the second grid connection hole, and The main line portion of the corresponding first grid auxiliary line and the main line portion of the corresponding second grid auxiliary line are symmetrical to each other based on the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver.

Images