Light emitting device including LED die having portions in adjusting pixels and method of making the same

Abstract

A light emitting device includes: a back plate; a plurality of light emitting diode (LED) dies mounted on the backplane such that each of the LED dies includes a plurality of LEDs; and a pixel including an adjacent micro LED of the plurality of LEDs located in an adjacent LED die of the plurality of LED dies.

Description

Technical Field

[0001] The present invention relates to a light emitting device, and in particular to a light emitting device including a light emitting diode (LED) die having different portions located in different adjacent pixels and a method of manufacturing the same. Background Art

[0002] As the size of light emitting devices (e.g., displays) decreases, the size of micro-LEDs (e.g., LEDs having a size in the micron or sub-micron range) used in the light emitting devices may also decrease in order to maintain high resolution. As the size of micro-LEDs decreases, it may become more difficult to manufacture the micro-LEDs on both the wafer manufacturing and mass transfer sides of the process. Summary of the invention

[0003] According to aspects of the present disclosure, a light emitting device includes: a backplane; a plurality of light emitting diode (LED) dies mounted on the backplane such that each of the LED dies includes a plurality of LEDs; and pixels comprising adjacent micro-LEDs among the plurality of LEDs located in adjacent LED dies among the plurality of LED dies.

[0004] According to another aspect of the present disclosure, a method for forming a light-emitting device includes: setting a backplane; setting a plurality of light-emitting diode (LED) bare chips, each of the plurality of LED bare chips including a plurality of LEDs; and mounting the plurality of LED bare chips on the backplane so that adjacent LEDs among the plurality of LED bare chips in the plurality of LED bare chips constitute pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a plan view (eg, a top view showing an overview of a layout) of a light emitting device according to one or more embodiments.

[0006] Figure 1B According to one or more embodiments Figure 1A Top stereoscopic view of the left half of the light emitting device in FIG.

[0007] Figure 1C A light emitting device according to one or more embodiments is Figure 1A A vertical cross-sectional view along line II'.

[0008] Figure 1D is a bottom perspective view of an LED die according to one or more embodiments.

[0009] Figure 2A is a schematic diagram of a pixel that may include a portion of four adjacent LED dies in a light emitting device according to one or more embodiments.

[0010] Figure 2Bis a schematic diagram of a portion of a pixel array that may be included in a display module of a backplane according to one or more embodiments.

[0011] Figure 3A is a schematic diagram of a defect repair system for repairing a defective micro LED in a light emitting device according to one or more embodiments.

[0012] Figure 3B is a flow chart illustrating a method of repairing a defective micro LED according to one or more embodiments.

[0013] Figure 4 is a schematic diagram of a light emitting device having an alternative layout pattern for LED dies according to one or more embodiments.

[0014] Figure 5 is a vertical cross-sectional view of a back plate according to one or more embodiments.

[0015] Fig. 6A is a vertical cross-sectional view of an exemplary intermediate structure including an LED die base layer formed on a substrate according to one or more embodiments.

[0016] Figure 6B is a vertical cross-sectional view of an exemplary intermediate structure including various layers of micro-LEDs on an LED die base layer according to one or more embodiments.

[0017] Figure 6C is a vertical cross-sectional view of an exemplary intermediate structure including micro-LEDs on an LED die base layer according to one or more embodiments.

[0018] Fig.6D is another vertical cross-sectional view of an exemplary intermediate structure including micro-LEDs on an LED die base layer according to one or more embodiments.

[0019] Fig. 6E is a vertical cross-sectional view of an exemplary intermediate structure including an LED die mounted on a backplane and separated from a substrate according to one or more embodiments.

[0020] Figure 7 is a vertical cross-sectional view of an illustrative intermediate structure including an LED die mounted on a backplane after being separated from a substrate according to one or more embodiments.

[0021] Figure 8 is a flow chart illustrating a method of making a light emitting device according to one or more embodiments. DETAILED DESCRIPTION

[0022] As discussed above, embodiments of the present disclosure are directed to light emitting devices, and specifically to light emitting devices including LED dies having different portions located in different adjacent pixels and methods for manufacturing the same, and various aspects of which are discussed in detail herein. The drawings are not necessarily drawn to scale. Unless otherwise explicitly described or clearly indicated that there is no duplication of an element, multiple instances of an element may be duplicated in the case of a single instance of an element shown. Ordinals such as "first", "second" and "third" are used only to identify similar elements, and different ordinals may be used throughout the currently disclosed specification and claims. The same reference numerals represent the same elements or similar elements. Unless otherwise indicated, elements with the same reference numerals are assumed to have the same components. As used herein, a first element located "on" a second element may be located on the outside of a surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" located "on" the second element. As used herein, a "layer" means a continuous portion of at least one material including an area having a thickness. A layer may consist of a single material portion having a homogeneous component, or may include multiple material portions having different components.

[0023] As used herein, "conductive material" means a conductive material having a conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" means a material having an electrical conductivity of less than 1.0×10 -5 S / cm. As used herein, "semiconductor material" means a material having an electrical conductivity ranging from 1.0×10 -5 S / cm to 1.0×10 5 S / cm. As used herein, "metallic material" means a conductive material that includes at least one metal element. All measurements of conductivity are performed under standard conditions.

[0024] A light emitting device, such as a display device (e.g., a direct view display), may be formed by an ordered array of pixels. Each pixel may include a set of sub-pixels that emit light of a corresponding peak wavelength. For example, a pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel may include one or more light emitting diodes that emit light of a specific wavelength. Each pixel may be driven by a backplane circuit so that any combination of colors within a color gamut may be shown on the display for each pixel. A display (e.g., a display panel) may be formed by a process in which light emitting diode (LED) sub-pixels are soldered to or otherwise electrically attached to bonding pads on the surface of a backplane. The bonding pads may be electrically driven by the backplane circuit and other drive electronics.

[0025] In a typical red / green / blue (RGB) mass transfer technology, one micro-LED may be transferred per sub-pixel. Therefore, the size of the micro-LED size may shrink as the sub-pixel size decreases. Common mass transfer technologies (such as elastic stamp and electrostatic pickup) may have difficulty achieving high yield at micro-LED sizes below about 5 microns and sub-pixel pitches below about 10 microns.

[0026] One or more embodiments of the present disclosure may include a light emitting device (e.g., an RGB micro-LED display) and a method of manufacturing a light emitting device that can help alleviate problems of a typical light emitting device (e.g., a display). The light emitting device may include, for example, a plurality of LED dies (e.g., a micro-monolithic micro-LED) that may each include a plurality of micro-LEDs. As used herein, a micro-LED has a width and / or length of 20 microns or less, such as 5 microns or less (e.g., 500nm to 3 microns). The light emitting device may be referred to as a micro-monolithic micro-LED display (e.g., a micro-monolithic RGB micro-LED display). In at least one embodiment, the micro-monolithic micro-LED may each include four separate mesas that may be connected to separate backplane electrical connections and form four adjacent sub-pixels located in four separate adjacent pixels.

[0027] In general, larger micro-LEDs can be transferred more easily than smaller micro-LEDs. To address the difficulty of transferring small micro-LEDs (e.g., micro-LEDs as sizes below 20 microns (such as, 5 microns or less), one or more embodiments may divide the portion of the larger LED die (which can be easily transferred) that faces the backplane into smaller sub-units. The sub-units of the larger LED die may be located in multiple adjacent pixels, so that one LED die can be individually addressed by the backplane as multiple individual micro-LED sub-pixels. This may allow maintaining high pixels per inch (PPI) resolution while transferring larger LED dies with large wafer-level pitch to the backplane.

[0028] For example, in at least one embodiment, the transferred LED die size (e.g., length and width of the square die) and pitch can be 7 microns and 32 microns, respectively, to achieve a 3 micron sub-pixel size and a 16 micron pixel pitch. To achieve the same sub-pixel size and pixel pitch as a conventional layout, it would be necessary to transfer individual LEDs having a size and pitch of 3 microns and 16 microns, respectively. Thus, by utilizing this "micro-monolithic" integration and layout scheme, existing transfer technology nodes can be utilized and immediately access nodes that can double the resolution (e.g., a 7 micron node can be used for a 3 micron node).

[0029] Embodiments may include several advantages over typical light emitting devices and typical methods of forming light emitting devices. Specifically, embodiments may help completely eliminate back end of line (BEOL) processes. Embodiments may require only one transfer step for every four sub-pixels. Embodiments may provide a local cathode (e.g., substantially no voltage (IR) drop when a common cathode ring is used). In addition, by transferring multiple sub-pixels of different pixels together, embodiments may allow multiple uses of a test piece, and may also allow low PPI displays to successfully use micro-LEDs and still maintain high utilization of the donor LED wafer.

[0030] One or more embodiments of the present disclosure may also provide a mechanism for repairing defective micro-LEDs without physically repairing the light emitting device. Specifically, in the present disclosure, defective micro-LEDs may be "repaired" by using a software-based method or a hardware-based method.

[0031] A typical light emitting device (e.g., a high PPI display device) may not provide the ability to repair defective pixels without physically repairing the light emitting device. Specifically, in a typical light emitting device, it can be determined that a particular micro-LED is indeed defective (or not defective) only after a front-side electrode (e.g., a transparent electrode such as an indium tin oxide (ITO) electrode) for a negative (e.g., n-type side) cathode contact is put down. Even if it is possible to determine whether a micro-LED is defective by photoluminescence (PL) before the back-end of line (BEOL) process (and after transfer to the backplane), it will still be difficult to pull out the defective micro-LED and replace the defective micro-LED with a good micro-LED (such as by using a pick and place (PnP) machine and local heating and welding).

[0032] Embodiments of the present disclosure may provide an alternative that can be facilitated by the architecture of most silicon backplanes (e.g., 2×2 configurations). In at least one embodiment, every three RGB pixels may have an additional R, G, or B redundant micro-LED. If (e.g., at the end of manufacturing) a particular micro-LED is determined to be defective, the current (or voltage) originally intended for the defective micro-LED may be disconnected in software and redirected (e.g., rerouted) to the nearest micro-LED of the same color.

[0033] Thus, even if the original panel had, for example, up to 5000 parts per million (ppm) ignition defects, the method of one or more embodiments can provide virtually zero ppm ignition defect rate (e.g., perfect panel) without physical repair. Typical circuitry in the backplane (e.g., complementary metal oxide semiconductor (CMOS) circuitry) can allow signals to be altered on the fly to achieve this.

[0034] Figure 1Ais a plan view (eg, top view, layout overview) of a light emitting device 100 according to one or more embodiments. Figure 1B According to one or more embodiments Figure 1A 100 is a top perspective view of the underside of the light emitting device 100 in FIG. Figure 1A and Figure 1B Some elements of the light emitting device 100 are omitted. In one embodiment, the light emitting device 100 may include a direct view display.

[0035] like Figure 1A As shown in , the light emitting device 100 may include a backplane 110 including a backplane substrate 111 and a bonding pad 112 formed on the substrate 111. One or more pixel driving circuits (not shown) may be formed on the backplane substrate 111 and electrically connected to the bonding pad 112. The light emitting device 100 may also include a plurality of light emitting diode (LED) dies 10 (e.g., micro-monolithic micro-LEDs) mounted on the backplane 100. The plurality of LED dies 10 may include a plurality of micro-LEDs 12. The light emitting device 100 may also include pixels 130 including adjacent micro-LEDs 12 in adjacent LED dies 10. The pixels 130 may be driven by the pixel driving circuit on the backplane 110.

[0036] The backplane 110 may include an active matrix display backplane or a passive matrix display backplane. The backplane 110 may include a display module (not shown) for controlling the micro-LEDs 12 of the pixels 130. The display module may include, for example, a complementary metal oxide semiconductor (CMOS) circuit system. The display module may include, for example, a pixel array (e.g., a two-dimensional pixel circuit arrangement) including a pixel driving circuit. The display module may also include a data driver and a scan driver for activating the micro-LEDs 12 through the pixel driving circuit. In at least one embodiment, the display module may include a control circuit system including a logic element for filling the data driver and the scan driver with data for displaying an image and the brightness of the image to be displayed. The brightness of the micro-LEDs 12 may be controlled across the micro-LEDs 12 by using a pulse width modulation (PWM) scheme or by current modulation.

[0037] like Figure 1A As shown in FIG. 1 , the backplane 110 may have a rectangular shape in plan view. However, other shapes are within the contemplated scope of the disclosure. The backplane substrate 111 may include one or more layers of insulating material (e.g., dielectric material (such as a polymer material used in a printed circuit board)) and / or semiconductor material (e.g., silicon, germanium, silicon germanium, etc.). The bonding pads 112 may be arranged in a bonding pad array (e.g., a 16×8 array in FIG. 1 ). Figure 1AThe bonding pads 112 may be arranged on and / or in the backplane substrate 111 in the form of (shown in FIG. 1 ). The bonding pad array may include, for example, one or more rows of bonding pads 112 extending in the x-direction and one or more columns of bonding pads 112 extending in the y-direction. The bonding pads 112 may have a pitch of approximately 8 μm or less corresponding to the sub-pixel pitch of the backplane 110 (e.g., approximately 8 μm). The bonding pads 112 may have a rectangular shape in a plan view. However, other shapes are within the intended scope of the disclosure. The bonding pads 112 may include copper or another suitable metal (e.g., silver, chromium, nickel, tin, tungsten, titanium, gold, etc.), a copper alloy, or other suitable metal alloy. Other suitable metal materials are within the intended scope of the disclosure.

[0038] The LED die 10 may be mounted on the bonding pads 112 of the back plate 110 (e.g., bonded to the bonding pads 112 of the back plate 110). The LED die 10 may be mounted on the back plate 110 so as to lie substantially flat on the bonding pads 112. In at least one embodiment, the LED die 10 may be bonded to the surface of the bonding pads 112 by a solder material portion (e.g., a solder bump). The LED die 10 may include, for example, one or more semiconductor material layers. Specifically, the LED die 10 may include one or more layers of III-V compound semiconductor material layers.

[0039] like Figure 1A As shown in , the LED die 10 can be mounted on the backplane 110 in the form of an LED die array. The size and shape of the LED die array can be substantially the same as the size and shape of the bonding pad array. The LED die array may include, for example, one or more LED die rows extending in the x-direction and one or more LED die columns extending in the y-direction. The LED die rows may include a first LED die row 121, a second LED die row 122, a third LED die row 123, and a fourth LED die row 124.

[0040] The LED die 10 may include one or more micro-LEDs 12, which may also be referred to herein as "sub-pixels" or "sub-units." It should be noted that the micro-LEDs 12 may be on the underside of the LED die 10 and may not be visible from a top view of the light emitting device 100 (see FIG. Figure 1B ). Figure 1A The location of the micro-LEDs 12 on the underside of the LED die 10 is shown.

[0041] like Figure 1AAs shown in FIG. 1 , the LED dies 10 may each include four (4) micro-LEDs 12. However, other numbers of micro-LEDs 12 may be within the contemplated scope of the disclosure. The LED dies 10 may be mounted on a backplane 110 such that the micro-LEDs 12 are substantially located above bonding pads 112, respectively. In at least one embodiment, the micro-LEDs 12 may be bonded to the bonding pads 112 by soldering material portions. The micro-LEDs 12 may be electrically connected to the pixel driving circuitry through the bonding pads 112 to which the micro-LEDs 12 are respectively bonded.

[0042] The micro-LED 12 may include one or more layers of III-V compound semiconductor materials. The one or more layers of III-V compound semiconductor materials may include one or more light-emitting layers (eg, active layers for emitting light). Figure 1A , the color of light emitted by the light emitting layer of the micro-LED 12 may be indicated as "R" for red, "G" for green, or "B" for blue. A micro-LED 12 that emits light having a red color may be referred to as a red micro-LED 12R. A micro-LED 12 that emits light having a green color may be referred to as a green micro-LED 12G. A micro-LED 12 that emits light having a blue color may be referred to herein as a blue micro-LED 12B. Other colors of light or different radiation wavelengths (e.g., ultraviolet or infrared) may also be used.

[0043] In at least one embodiment, the micro-LEDs 12 on the LED die 10 can emit light of the same color (i.e., light having the same peak wavelength). An LED die 10 that includes only red micro-LEDs 12R may be referred to herein as a red LED die 10R. An LED die 10 that includes only green micro-LEDs 12G may be referred to herein as a green LED die 10G. An LED die 10 that includes only blue micro-LEDs 12B may be referred to herein as a blue LED die 10B. Figure 1A In the light emitting device 100 in FIG. 1 , the first LED die row 121 and the third LED die row 123 may include alternating red LED dies 10R and blue LED dies 10B. The second LED die row 122 and the fourth LED die row 124 may include alternating green LED dies 10G and red LED dies 10R. The red LED dies 10R in adjacent rows may be staggered in the x direction.

[0044] like Figure 1AAs further shown in , the light emitting device 100 may include one or more pixels 130 indicated by dashed lines. The pixel 130 may be driven by one or more of the pixel driving circuits in the backplane 110. The pixel 130 may include adjacent micro-LEDs 12 from adjacent LED dies 10. In at least one embodiment, the pixel 130 may include two red micro-LEDs 12R, a green micro-LED 12G, and a blue micro-LED 12B. In this case, the pixel 130 may be referred to as an RRGB pixel 130. Optionally, each pixel 130 may include two green micro-LEDs 12G or two blue micro-LEDs 12B. The pixels 130 may be arranged on the backplane 110 in the form of a pixel array. The pixel array may include, for example, one or more pixel rows extending in the x direction. The pixel row may include a first pixel row 131, a second pixel row 132, and a third pixel row 133. The pixel array may also include one or more columns of pixels 130 extending in the y direction.

[0045] In at least one embodiment, the pixels 130 in the first pixel row 131 may include adjacent micro-LEDs 12 from adjacent LED dies 10 in the first LED die row 121 and the second LED die row 122. Specifically, the pixels 130 in the first pixel row 131 may include red micro-LEDs 12R from the red LED die 10R in the first LED die row 121, blue micro-LEDs 12B from the blue LED die 10B in the first LED die row 121, green micro-LEDs 12G from the green LED die 10G in the second LED die row 122, and red micro-LEDs 12R from the red LED die 10R in the second LED die row 122.

[0046] The pixels 130 in the second pixel row 132 may include adjacent micro-LEDs 12 from adjacent LED dies 10 in the second LED die row 122 and the third LED die row 123. Specifically, the pixels 130 in the second pixel row 132 may include red micro-LEDs 12R from the red LED die 10R in the second LED die row 122, green micro-LEDs 12G from the green LED die 10G in the second LED die row 122, blue micro-LEDs 12B from the blue LED die 10B in the third LED die row 123, and red micro-LEDs 12R from the red LED die 10R in the third LED die row 123.

[0047] The pixels 130 in the third pixel row 133 may include adjacent micro LEDs 12 from adjacent LED dies 10 in the third LED die row 123 and the fourth LED die row 124. The pixels 130 in the third pixel row 133 may have a similar construction to the pixels 130 in the first pixel row 131. Specifically, the pixels 130 in the third pixel row 133 may include red micro LEDs 12R from the red LED die 10R in the third LED die row 123, blue micro LEDs 12B from the blue LED die 10B in the third LED die row 123, green micro LEDs 12G from the green LED die 10G in the fourth LED die row 124, and red micro LEDs 12R from the red LED die 10R in the fourth LED die row 124.

[0048] Thus, each LED die 10 includes a plurality of micro-LEDs 12 located in different adjacent pixels. For example, each LED die 10 may include four micro-LEDs 12 that emit the same color light (ie, emit radiation having the same peak wavelength) and are located in four different pixels 130.

[0049] In at least one embodiment, the size of the red LED die 10, the green LED die 10, and the blue LED die 10B can be about 7 μm or less, and the size of the micro-LEDs 12 on the LED die 10 can be about 3 μm or less. The pitch between the LED dies can be about 16 μm or less, and similarly the transfer pitch (P T )(For example, the pitch between green LED dies 10G; see Figure 1B ) may be about 32 μm or less. The size of the LED die 10 in the light emitting device 100 and the pitch between the LED die 10 (e.g., 16 μm or less) may provide a large diagonal distance between the blue micro-LEDs 12B and a large diagonal distance between the green micro-LEDs 12G (e.g., Figure 1A indicated by arrows in the figure).

[0050] The size and pitch of LED die 10 can also help alleviate problems associated with manufacturing typical light emitting devices that may require transferring small (e.g., 5 μm or less) devices. In at least one embodiment, the transfer device size (e.g., about 7 μm or less) and the transfer pitch P T(e.g., about 32 μm or less) can achieve a sub-pixel size of about 3 μm (e.g., the size of the micro-LED 12) and a pixel pitch of about 16 μm. In order to achieve the same sub-pixel size and pixel pitch as a typical layout, it would be necessary to transfer devices with sizes and pitches of 3 μm and 16 μm, respectively. Therefore, in essence, by utilizing the "micro-monolithic" integration and layout scheme of the embodiments of the present disclosure, existing transfer technology nodes (e.g., in the backplane 110) can be utilized and immediately accessed (e.g., the 7 μm node can be used for the next generation 3 μm node), so that the resolution of the light-emitting device 100 can be twice that of a typical light-emitting device.

[0051] It should be noted that several aspects of the embodiments may be easily varied or altered. Specifically, variations or changes in the number of micro-LEDs 12 on the LED die 10, the size and pitch of the LED die 10, the size and pitch of the micro-LEDs 12, the size and pitch of the pixels, the shape of the LED die array (e.g., a layout grid) (e.g., a square grid, a triangular grid, a hexagonal grid), the color positions of the LED die array, and aspects of the micro-LED wafer-level integration (metallization, mesa profile, LED shaping, etc.) may be within the intended scope of the disclosure. Specifically, it should be noted that by replacing the green LED die 10G with the green LED die 10G, the micro-LEDs 12 may be easily altered or altered. Figure 1A and replace the red LED bare chip 10R with the red LED bare chip 10R Figure 1A Green LED die 10G, Figure 1A The RRGB pixels 130 in the light emitting device 100 may alternatively be configured as GGRB pixels. In addition, each LED die 10 may include more or less than four sub-pixels 12. For example, each LED die 10 may include two, three, five, or six sub-pixels located in two, three, five, or six different pixels 130.

[0052] Figure 1C The light emitting device 100 according to one or more embodiments is Figure 1A Specifically, Figure 1C is a view along a column of an LED die array including red LED die 10R and blue LED die 10B.

[0053] like Figure 1CAs shown in , the LED die 10 (e.g., the red LED die 10R and the blue LED die 10B) can be flip-chip mounted to the corresponding bonding pads 112 of the backplane 110. Each micro-LED 12 can be mounted to a separate bonding pad 112 that can be driven individually by the backplane 110. A soldering material portion 90 can be formed between the micro-LED 12 and the bonding pad 112. The soldering material portion 90 may include, for example, a tin-silver-copper alloy including approximately 3-4% silver, 0.5-0.7% copper, and the balance (95%+) tin. A fourth metal (such as indium, antimony, bismuth, zinc, or manganese) may be added to the tin-silver-copper alloy.

[0054] In at least one embodiment, the p-type layer (not shown) of the micro-LED 12 can be electrically connected to the bonding pad 112. In other words, in one embodiment, each micro-LED p-side is bonded to the backplane 110 and has a common n-side with other micro-LEDs 12 in the same LED die 10 (for example, with three other micro-LEDs 12). Therefore, the bonding pad 112 can be used as an anode in the light-emitting device 100. The light-emitting device 100 may include one or more dielectric material layers 150 formed between the LED dies 10 so as to substantially surround the LED dies 10 (in the xy direction). The LED dies 10 may be substantially embedded in the dielectric material layer 150. The upper surface of the dielectric material layer 150 may be substantially coplanar with the upper surface of the LED die 10. The dielectric material may include, for example, a polymer material, silicon oxide, or aluminum oxide. However, other dielectric materials may be within the intended scope of the disclosure.

[0055] The light emitting device 100 may also include a continuous n-type (i.e., n-type side) contact layer 160 (e.g., a first conductive type contact layer) formed on the upper surface of the plurality of LED dies 10 and the upper surface of the dielectric material layer 150. The n-type contact layer 160 may be electrically connected to the n-type layer of the micro-LED 12 and may thus serve as a shared cathode for the plurality of LED dies 10 in the light emitting device 100. The n-type contact layer 160 may include an optically transparent material. In at least one embodiment, the n-type contact layer 160 may include indium tin oxide (ITO) or another transparent conductive metal oxide. As in Figure 1C As indicated by arrows extending in the z direction in FIG. 1 , light emitted by the micro LED 12 may be guided through the n-type contact layer 160 in the region of the pixel 130. Therefore, the upper surface of the n-type contact layer 160 may be used as a light emitting surface of the light emitting device 100.

[0056] The light emitting device 100 may further include a frame 170. The frame 170 may be formed around the periphery of the light emitting device 100 (e.g., the periphery of the back plate 110, the dielectric material layer 150, and the n-type contact layer 160). Specifically, the frame 170 may continuously surround the periphery of the light emitting device 100 (e.g., from the front side to the back side). The frame 170 may include one or more metal or plastic materials. However, other materials may be within the intended scope of the disclosure.

[0057] In operation, a voltage or current may be applied across one of the micro-LEDs 12 in the LED die 10 (e.g., a selected micro-LED 12), while other micro-LEDs 12 in the same LED die 10 (e.g., unselected micro-LEDs 12) may be electrically deactivated. This may be accomplished by applying a voltage or current to the bonding pads 112 bonded to the selected micro-LED 12 relative to the n-type contact layer 160, while not applying a voltage or current to the bonding pads 112 bonded to the unselected micro-LEDs 12 of the same LED die 10. This causes the selected micro-LED 12 (i.e., sub-pixel) in one pixel 130 to emit light, while the unselected micro-LEDs 12 of the same LED die 10 that are sub-pixels located in other pixels do not emit light.

[0058] Figure 1D FIG. 1 is a bottom perspective view of an LED die 10 according to one or more embodiments. Figure 1D As shown in FIG. 1 , the LED die 10 may include an LED die base layer 15 (e.g., a tape layer) and one or more micro-LEDs 12 formed on the LED die base layer 15. The LED die base layer 15 may have a trapezoidal prism shape. However, other shapes are within the contemplated scope of the disclosure. The LED die base layer 15 may have a first surface 15S. 1 and the first surface 15S 1 The second opposite surface 15S 2 . First surface 15S 1 This may include Figure 1D The light emitting surface indicated by the one-way arrow. First surface 15S 1 The area may be larger than the second surface 15S 2 On the first surface 15S 1 The LED die base layer 15 may have a width W in the x direction. 15 and the length L in the y direction 15 In at least one embodiment, the width W 15 Can be basically equal to the length L 15 Width W 15 and / or length L 15 It may be 20 μm or less (such as 7 to 10 μm).

[0059] The LED die base layer 15 may include one or more layers of n-type semiconductor material. In at least one embodiment, the n-type semiconductor layer may include a layer of n-type III-V compound semiconductor material. (Such as, n-type GaN). As indicated by the unidirectional arrows, light emitted by the micro-LEDs 12 may be directed through the LED die base layer 15. Thus, the first surface 15S of the LED die base layer 15 may be formed of a plurality of layers of n-type semiconductor material. 1 Can be used as the light emitting surface of the LED die 10 .

[0060] like Figure 1D As further shown in FIG. 1 , the micro LED 12 may be formed on the second surface 15S of the LED die base layer 15. 2 Specifically, the micro LED 12 may be formed as a second surface 15S 2 The micro-LEDs 12 (e.g., the mesas) may have a tapered shape substantially similar to the tapered shape of the LED die base layer 15. Specifically, the micro-LEDs 12 may also have a trapezoidal prism shape. However, other shapes are within the intended scope of the disclosure. 2 The micro LED 12 may have a width W in the x direction. 12 and the length L in the y direction 12 In at least one embodiment, the width W 12 Can be basically equal to the length L 12 Width W 12 and / or length L 12 It may be about 3 μm or less (such as 500 nm to 3 μm).

[0061] The micro-LED 12 may include, for example, a light-emitting layer (e.g., an active layer; not shown) and other layers on the light-emitting layer (not shown). The light-emitting layer may have a quantum well (QW) or a multiple quantum well (MQW) structure. In at least one embodiment, the light-emitting layer may include indium gallium nitride (InGaN) having a narrower band gap than GaN, which allows light emitted from the InGaN to pass through the n-type GaN base layer 115. The contact portion may include a p-type semiconductor material (e.g., a second conductive type semiconductor material). In at least one embodiment, the contact portion may include a p-type III-V compound semiconductor material layer (such as p-type GaN). Other layers may also include a first surface 15S for facing the LED die base layer 15. 1 A reflective layer (not shown) that reflects back the light from the light emitting layer. The reflective layer may include a metal such as aluminum, silver, etc.

[0062] Figure 2A is a schematic diagram of a pixel 130 that may include portions of four adjacent LED dies 10 in a light emitting device 100 according to one or more embodiments. Figure 2A As shown in FIG. 1 , the four adjacent LED dies 10 may include a first red LED die 10R-1, a blue LED die 10B, a green LED die 10G, and a second red LED die 10R-2. The first red LED die 10R-1 includes a blue LED die 10B, a green LED die 10G, and a second red LED die 10R-2. 11 , R 12 , R 13 and R 14 The four red micro LEDs 12R, the blue LED die 10B include what may be referred to as B 1 , B 2 , B 3 and B 4 The four blue micro LEDs 12B, the green LED die 10G includes what may be referred to as G 1 , G 2 , G 3 and G 4 The four green micro LEDs 12G, the second red LED die 10R-2 includes what may be referred to as R 21 , R 22 , R 23 and R 24 The pixel 130 may be formed by four adjacent micro-LEDs 12R in adjacent LED dies 10. Specifically, the pixel 130 may be formed by four adjacent micro-LEDs 12R in adjacent LED dies 10. 14 , Blue Micro LED B 3 , Green Micro LED G 2 and red micro LED R 21 form.

[0063] Figure 2B 1 is a schematic diagram of a portion of a pixel array 20 that may be included in a display module of a backplane 110 according to one or more embodiments. Figure 2B As shown in , the pixel array 20 may include an active matrix pixel array. However, the pixel array 20 may alternatively include a passive matrix pixel array. The pixel array 20 may include data lines 251 (251a, 251b) and selection lines 252 (252a, 252b). The pixel driving circuit 200 may be located at the intersection of the data lines 251 and the selection lines 252. The pixel driving circuit 200 may include micro LEDs 12, respectively. Figure 2B As shown in the figure, for red micro LED 12R (R 14 ) can be connected to the data line 251a and the selection line 252a. 2 ) can be connected to the data line 251a and the selection line 252b. 3) can be connected to the data line 251b and the selection line 252a. 21 ) can be connected to the data line 251b and the selection line 252b. Therefore, the pixel driving circuit 200 can be connected to the data line 251b and the selection line 252b at least partially. Figure 2B The four pixel driving circuits 200 are used to control Figure 2A Operation of pixel 130 in .

[0064] like Figure 2B As shown in , the pixel driving circuit 200 (e.g., pixel circuit) may have a 2-transistor, 1-capacitor (2T1C) configuration located on the backplane 110. However, other configurations of the pixel driving circuit 200 may be within the intended scope of the disclosure. The pixel driving circuit 200 may include a first transistor 201 (e.g., a switching transistor), a second transistor 202 (e.g., a driving transistor), and a capacitor 203 (e.g., a storage capacitor). The first transistor 201 and the second transistor 202 may include thin film transistors (TFTs).

[0065] The first transistor 201 (e.g., a first TFT) may be connected to a data line 251 in the pixel array 20 of the backplane 110. The control gate of the first transistor 201 may be connected to a selection line 252 in the pixel array 20. The second transistor 202 (e.g., a second TFT) may be connected between a power supply Vdd and the micro LED 12. The control gate of the second transistor 202 may be connected to the data line 251 through the first transistor 201. The capacitor 203 may be connected between the power supply Vdd and the control gate of the second transistor 202. Therefore, when a selection signal is sent on the selection line 252, the first transistor 201 (e.g., a switching TFT) may be used as a transfer gate for transferring data on the data line 251 to the storage capacitor 203 and turning on the second transistor 202 (e.g., a driving TFT). When the second transistor 202 is turned on, the micro LED 12 may be activated and emit light from its light emitting layer.

[0066] Figure 3A is a schematic diagram of a defect repair system 300 for repairing defective micro-LEDs 12 in a light emitting device 100 according to one or more embodiments. The defect repair system 300 can be used to implement a software-based method to repair defective micro-LEDs 12. However, a hardware-based method can alternatively be used to repair defective micro-LEDs 12. At least a portion of the defect repair system 300 can be connected to or included in the backplane 110. The light emitting device 100 can be designed to substantially eliminate defective micro-LEDs 12. That is, the light emitting device 100 can provide a zero lit parts per million (PPM) defect rate without physical repair.

[0067] The software-based approach can be facilitated by the architecture of most silicon backplanes (e.g., a 2×2 construction). Typically, if a micro-LED 12 is determined to be defective, software can be used to cut off the current to the defective micro-LED 12. Thereafter, the current can be routed to a micro-LED 12 of the same color that is close to (e.g., closest to) the defective micro-LED 12. In at least one embodiment, the current can be routed to a redundant micro-LED in a pixel 130 having a defective micro-LED 12. In this way, one or more embodiments can provide a zero ppm lighting defect rate (e.g., a perfect panel) even if the original light-emitting device 100 has up to 5000 ppm lighting. In at least one embodiment, the current can be routed to a redundant micro-LED outside the pixel 130 having a defective micro-LED 12.

[0068] In at least one embodiment, the defect repair system 300 may be included as part of a control system for the light emitting device 100. The defect repair system 300 may include, for example, a defective micro LED detector 310, a processing device 320, and a memory device 330. The defective micro LED detector 310 may be connected to the pixel array 20 included in the display module 340 of the light emitting device 100. The defective micro LED detector 310 may detect defective micro LEDs 12 in the pixel array 20. The defective micro LED detector 310 may include, for example, a sensing circuit that senses a voltage or current on a power line that supplies power (Vdd) to the micro LEDs 12. If the defective micro LED detector 310 senses a voltage or current on the power line that is different from expected, the defective micro LED detector 310 may send a defect notification signal Sd to the processing device 320. The defect notification signal Sd may include an identification and / or location of the defective micro LED 12 in the pixel array 20.

[0069] The memory device 330 may include, for example, a read-only memory (ROM) and / or a random access memory (RAM). The memory device 330 may be physically located in a location remote from the processing device 320. The memory device 330 may store a defect repair program including instructions for repairing defective micro LEDs in the pixel array 20. The processing device 320 may include a central processing unit (CPU), a microcontroller, a microprocessor, etc. Upon receiving the defect notification signal Sd, the processing device 320 may access the memory device 330 and execute instructions in the defect repair program stored in the memory device 330. The defect repair program may include, for example, a lookup table indicating redundant micro LEDs 12 and / or adjacent micro LEDs 12 associated with the defective micro LED 12.

[0070] The display module 340 may include a data line 251 (see FIG. 25) for driving the data in the pixel array 20. Figure 2B ) data driver 351. The display module 340 may further include a selection line 252 (see FIG. 25) for driving a selection signal in the pixel array 20. Figure 2B ) of the scan driver 352. After executing the instruction, the processing device 320 can control the data driver 351 to reroute the data on the data line 251 from the defective micro LED 12 to the redundant micro LED 12. The processing device 320 can also control the scan driver 351 to reroute the selection signal on the selection line 252 from the defective micro LED 12 to the redundant micro LED 12.

[0071] So, for example, referring to Figure 2B The pixel 130 in the embodiment of the present invention can activate the red micro LED 12R (R) by sending data on the data line 251a and sending a selection signal on the selection line 252a. 14 ). Red Micro LED 12R(R 21 ) (e.g., a redundant red micro LED 12 in pixel 130) can be activated by sending data on data line 251b and sending a selection signal on selection line 252b. If defective micro LED detector 310 detects that red micro LED 12R (R 14 ) is defective, the defective micro LED detector 310 may notify the processing device 320. The processing device 320 may execute the instructions of the defect repair program stored in the memory device 330. Thereafter, the processing device 320 may operate according to the executed instructions to control the data driver 351 and the scan driver 352 to activate the redundant red micro LED 12R (R 21 ) instead of the red micro LED 12R(R 14 That is, under the control of the processing device 320, instead of the data driver 351 sending data on the data line 251a and the scan driver 352 sending the selection signal on the selection line 252a, the data driver 351 may send data on the data line 251b and the scan driver 352 may send the selection signal on the selection line 252b.

[0072] The processing device 320 may also store the repair data in the memory device 330 so that the redundant red micro LED 12R (R 21 ) can permanently replace the red micro LED 12R (R 14 ). Therefore, the data driver 351 and the scan driver 352 may continue to activate the redundant red micro LEDs 12R (R 21 ) replaces the red micro LED12R (R14 ).

[0073] Figure 3B is a flow chart illustrating a method of repairing a defective micro-LED 12 according to one or more embodiments. The method can be performed, for example, using a defect repair system 300. Step 310 includes detecting a defective micro-LED 12 in a pixel array. Step 320 includes identifying a redundant micro-LED 12 associated with the defective micro-LED 12. Step 330 includes activating the redundant micro-LED 12 to replace the defective micro-LED 12.

[0074] Figure 4 is a schematic diagram of a light emitting device 100 having an alternative layout pattern for an LED die 10 according to one or more embodiments. Figure 4 In the optional layout pattern of , because each of the LED dies 10 may include at least one red micro LED 12R, at least one green micro LED 12G, and at least one blue micro LED 12B, the LED dies 10 may be collectively referred to as "RGB LED dies 10". The RGB LED dies 10 may also include a redundant micro LED 12. Specifically, some of the RGB LED dies 10 may include a redundant red micro LED 12R, and thus may be referred to as RRGB LED dies 10. Some of the RGB LED dies 10 may include a redundant green micro LED 12G, and thus may be referred to as RGGB LED dies 10. Some of the RGB LED dies 10 may include a redundant blue micro LED 12B, and thus may be referred to as RGBB LED dies 10.

[0075] exist Figure 4 In an optional layout pattern of FIG. 1 , the light emitting device 100 may include a first LED die column 30a including RRGB LED dies 10, a second LED die column 30b including RGGB LED dies 10, and a third LED die column 30c including RGBB LED dies 10. The pattern of the first LED die column 30a, the second LED die column 30b, and the third LED die column 30c may be repeated once to form a 12×12 array of LED dies 10. The LED dies 10 may also constitute pixels 130 in the light emitting device 100. Therefore, the light emitting device 100 may include at least a 12×12 array of pixels 130 (e.g., 144 pixels).

[0076] Thus, in an alternative layout pattern, every third RGB LED die 10 (e.g., RGB pixel 130) may have additional R, G, and B redundant micro-LEDs 12. That is, the pixels 130 in the first LED die column 30a may include redundant red micro-LEDs 12R, the pixels 130 in the second LED die column 30b may include redundant green micro-LEDs 12G, and the pixels 130 in the third LED die column 30c may include redundant blue micro-LEDs 12B.

[0077] The optional layout pattern can be used with the defect repair system 300 (see Figure 3A ) is implemented to efficiently and effectively repair defective micro LEDs 12 in the light emitting device 100. For example, if it is determined that the red micro LED 12R1 in the LED die column 30a is defective, the defect repair system 300 may cause the redundant red micro LED 12R2 in the same pixel 130 to be activated instead of the defective red micro LED 12R1. However, the LED die 10 (e.g., pixel 130) in the LED die column 30b does not include a redundant red micro LED 12R. Therefore, if it is determined that the red micro LED 12R3 in the LED die column 30b is defective, the defect repair system 300 may identify a redundant red micro LED 12R outside the LED die column 30b. For example, the defect repair system 300 may identify the red micro LED 12R2 or the red micro LED 12R4 as a redundant red micro LED 12R.

[0078] Figure 5 1 is a vertical cross-sectional view of a backplane 110 according to one or more embodiments. The backplane 110 may include a backplane lower substrate 610. The backplane lower substrate 610 may include, for example, an insulating material (e.g., a dielectric material) and / or a semiconductor material (e.g., silicon, germanium, silicon germanium, etc.). A control circuit system for controlling the operation of the light emitting device 100 may be formed on the backplane lower substrate 610. Such a control circuit system may include, for example, a display module 340 (e.g., see Figure 3A ), and specifically includes a pixel array 20 of a display module 340. Figure 5 As shown in FIG. 1 , the second transistor 202 (eg, driving transistor; second TFT) of the pixel driving circuit 200 may be formed on the backplane lower substrate 610. The second transistor 202 may be formed on the backplane lower substrate 610 in a 16×8 array configuration to accommodate the 16×8 array configuration of the bonding pad 112 later (eg, see FIG. 1 ). Figure 1A It should be noted that there may be more than 16×8 bonding pads in the display device.

[0079] The second transistor 202 may include a gate electrode 620, a gate dielectric 630, a channel region 642, a source region 646, and a drain region 644. Figure 5 644 (or source region 646)).

[0080] The interconnection-level dielectric layer 675 may be formed over the encapsulation dielectric layer 665. The backplane lower substrate 610, the encapsulation dielectric layer 665, and the interconnection-level dielectric layer 675 may together constitute the backplane substrate 111. Figure 5 As shown in FIG. 1 , bonding pads 112 (eg, second level metal interconnect structures) may be formed on interconnect level dielectric layer 675 of backplane substrate 111. Bonding pads 112 may be connected to first level metal interconnect structures 660 through openings in interconnect level dielectric layer 675.

[0081] FIG. 6A to FIG. 6E A method of forming an LED die 10 (eg, a micro-monolithic micro-LED) according to one or more embodiments is shown. Specifically, FIG. 6A to FIG. 6E The method shown in can be used to form Figure 1A In other words, FIG. 6A to FIG. 6E The LED die 10 in FIG. 1 may include a red LED die 10R, a green LED die 10G, or a blue LED die 10B.

[0082] Fig. 6A 1 is a vertical cross-sectional view of an exemplary intermediate structure including an LED die base layer 15 formed on a substrate 22 according to one or more embodiments. The substrate 22 may be referred to as a growth substrate. The substrate 22 may include a single crystal growth substrate material (such as Al2O3 using a basal or r-plane growth surface). 2 O 3(sapphire), diamond, Si in both wurtzite (α) and sphalerite (β) forms, Ge in both wurtzite (α) and sphalerite (β) forms, GaN in both wurtzite (α) and sphalerite (β) forms, AlN in both wurtzite (α) and sphalerite (β) forms, SiC in both wurtzite (α) and sphalerite (β) forms, InN, GaP, GaAsP, GaAs, InP, ZnO, ZnS, and ZnSe). For example, substrate 22 may include sapphire (i.e., single crystal aluminum oxide) with a suitable surface orientation. Substrate 22 may include a patterned sapphire substrate (PSS) having a patterned (e.g., rough) growth surface. Bumps, pits, and / or angled cuts may or may not be provided on the top surface of substrate 22 to facilitate epitaxial growth of upper layers on substrate 22, and / or facilitate separation from the upper layers of substrate 22 in a subsequent separation process.

[0083] The LED die base layer 15 may include one or more layers of semiconductor material grown on the substrate 22. The semiconductor material may include, for example, a III-V compound semiconductor material. Specifically, the semiconductor material may include a III-nitride compound semiconductor material (such as n-type GaN). The LED die base layer 15 may be formed by any suitable method (such as metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metal organic molecular beam epitaxy (MOMBE), and atomic layer deposition (ALD)).

[0084] Figure 6B is a vertical cross-sectional view of an exemplary intermediate structure including various layers of a micro-LED 12 on an LED die base layer 15 according to one or more embodiments. The single crystal buffer semiconductor layer 24 may be formed on the LED die base layer 15 by a suitable method including, for example, MOVPE, MBE, HVPE, LPE, MOMBE, and ALD. The single crystal compound semiconductor material 24 may include, for example, a III-V compound semiconductor material, and in particular, a III-nitride compound semiconductor material. In at least one embodiment, the single crystal buffer semiconductor layer 24 may include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride, and indium gallium nitride, as well as other III-V materials such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb).

[0085] An n-doped compound semiconductor base layer 26 may be formed on the single crystal buffer semiconductor layer 24. The n-doped compound semiconductor base layer 26 may be formed as a continuous material layer having a uniform thickness over the entire top surface of the single crystal buffer semiconductor layer 24. The n-doped compound semiconductor base layer 26 may be lattice matched to the single crystal compound semiconductor material of the top of the single crystal buffer semiconductor layer 24. The n-doped compound semiconductor base layer 26 may or may not include the same compound semiconductor material as the top of the single crystal buffer semiconductor layer 24. In at least one embodiment, the n-doped compound semiconductor base layer 26 may include an n-doped direct bandgap compound semiconductor material. In at least one embodiment, the n-doped compound semiconductor base layer 26 may include n-doped gallium nitride (GaN), indium gallium nitride (InGaN), or other III-V compound semiconductor materials (such as gallium phosphide or its ternary or quaternary compounds). The n-doped compound semiconductor base layer 26 may be formed by any suitable method including, for example, MOVPE, MBE, HVPE, LPE, MOMBE, and ALD.

[0086] The n-doped compound semiconductor region 32 may be grown on the n-doped compound semiconductor base layer 26. An optional patterned growth mask layer (not shown) may be formed on the n-doped compound semiconductor base layer 26, in which case the n-doped compound semiconductor region 32 may be grown through the openings in the patterned growth mask layer. The n-doped compound semiconductor region 32 may be grown, for example, by a selective compound semiconductor deposition process that may include a selective epitaxy process. If there is an optional patterned growth mask layer, the shape and size of the n-doped compound semiconductor region 32 may be determined based on the shape and size of the openings through the patterned growth mask layer and by the process conditions of the selective compound semiconductor deposition process. The n-doped compound semiconductor region 32 may be formed with various crystal facets located within corresponding crystal planes. The n-doped compound semiconductor region 32 may include micro-disks, nano-disks, nano-wire cores, micro-wire cores, nano-pyramids, micro-pyramids, nano-frustums, micro-frustums, combinations thereof, or other nano-scale structures or micro-scale structures. Alternatively, the n-doped compound semiconductor region 32 may include a continuous planar semiconductor layer.

[0087] The active region 34 may be formed on the n-doped compound semiconductor region 32 (e.g., by a selective epitaxial process). The active region 34 may include a light active compound semiconductor layer stack configured to emit light. The active region 34 may include one or more layers (e.g., active layers) of semiconductor materials that emit light when a suitable electrical bias is applied. The active region 34 may include one or more layers of III-V compound semiconductor materials (such as gallium nitride, indium gallium nitride wells, aluminum gallium nitride, etc.). The active region 34 may include any other suitable semiconductor layer (e.g., such as gallium phosphide or its ternary or quaternary compound) or stack of layers as long as it can be grown on the n-doped compound semiconductor region 32 for light emitting diode applications. The active region 34 may include a quantum well (QW) or multiple quantum well (MQW) structure that emits light when an electrical bias is applied across it. For example, the active region 34 may include (one or more) indium gallium nitride wells located between gallium nitride or aluminum gallium nitride barrier layers.

[0088] A p-doped semiconductor material layer 36 may be formed on the active region 34 (e.g., on the top surface of the planar surface and, if present, on the faceted outer surface of the active region 34) (e.g., by selective deposition (such as, selective epitaxy)). The p-doped semiconductor material layer 36 may include a doped semiconductor material having a second conductivity type, which is opposite to the first conductivity type. The p-doped semiconductor material layer 36 may include a compound semiconductor material. The compound semiconductor material of the p-doped semiconductor material layer 36 may be any suitable semiconductor material (such as, a p-type Group III nitride compound semiconductor material (e.g., gallium nitride and / or aluminum gallium nitride)). In one embodiment, the n-doped compound semiconductor region 32 may include n-doped GaN or InGaN, and the p-doped semiconductor material layer 36 may include p-doped AlGaN and / or GaN. The n-doped compound semiconductor region 32 and / or the p-doped semiconductor material layer 36 may include other semiconductor materials (such as, for example, gallium phosphide or a ternary or quaternary compound thereof).

[0089] An anode contact layer 50 may be formed on the p-doped semiconductor material layer 36. The anode contact layer 50 may include one or more layers (e.g., a layer stack) including one or more of a nickel layer, a platinum layer, a silver layer, and / or a transparent conductive oxide layer. The layers may be formed by conformal or non-conformal deposition. The transparent conductive oxide layer may include a layer selected from doped zinc oxide, indium tin oxide, cadmium tin oxide (Cd 2 SnO 4 ), zinc stannate (Zn 2 SnO 4 ) and doped titanium dioxide (TiO 2) selected material. In one or more embodiments, the anode contact layer 50 may include a layer stack including an adhesive metal layer (e.g., a platinum layer, a nickel layer, etc.) and a silver layer. The anode contact layer 50 may be formed, for example, by physical vapor deposition.

[0090] Figure 6C is a vertical cross-sectional view of an exemplary intermediate structure including a micro-LED 12 on an LED die base layer 15 according to one or more embodiments. The micro-LED 12 may be formed by forming a photoresist layer on an anode contact layer 50 and patterning the photoresist layer to cover each discrete area corresponding to the area of ​​the micro-LED 12. The photoresist layer may include a two-dimensional array of discrete portions that are laterally spaced apart from each other. For example, two sets of linear grooves extending along orthogonal horizontal directions may be provided in the patterned portion of the photoresist layer.

[0091] An anisotropic etching process that may include multiple etching steps may be performed to etch through the unmasked portions of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n-doped compound semiconductor base layer 26 and / or the single-crystalline buffer semiconductor layer 24. Multiple etching steps may be used to etch through various material portions. Each of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n-doped compound semiconductor base layer 26 and / or the single-crystalline buffer semiconductor layer 24 may be divided into a plurality of discrete portions, and the plurality of discrete portions are located under a corresponding one of the patterned portions of the photoresist layer. Therefore, the stack of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the n-doped compound semiconductor base layer 26 and / or the single-crystalline buffer semiconductor layer 24 may be patterned by a combination of an imprinting process and an anisotropic etching process.

[0092] Each continuous group of the anode contact layer 50, the p-doped semiconductor material layer 36, the active region 34, the n-doped compound semiconductor region 32, and optionally the remaining portion of the n-doped compound semiconductor base layer 26 and / or the single-crystalline buffer semiconductor layer 24 may constitute a component of a corresponding micro-LED 12. Since the selectivity of the anisotropic etching process for etching the materials of the n-doped compound semiconductor base layer 26 and the single-crystalline buffer semiconductor layer 24 is less than infinite, the sidewalls of the n-doped compound semiconductor base layer 26 and the single-crystalline buffer semiconductor layer 24 of each light emitting diode 10 may be formed with a finite taper angle. The taper angle may be in the range of from 1 degree to 15 degrees (e.g., from 2 degrees to 10 degrees and / or from 3 degrees to 6 degrees), but smaller and larger taper angles may also be employed.

[0093] The LED die base layer 15 may also be separated into multiple sections, each section including a group of four (4) adjacent micro-LEDs 12 (see, for example, Figure 1D ). The LED die base layer 15 may be separated, for example, simultaneously with the formation of the micro-LEDs 12. That is, the LED die base layer 15 may be separated by the same photolithography process used to form the micro-LEDs 12. Alternatively, the LED die base layer 15 may be separated by a photolithography process similar to the photolithography process used to form the micro-LEDs 12 before or after the formation of the micro-LEDs 12.

[0094] Fig.6D 1 is another vertical cross-sectional view of an exemplary intermediate structure including a micro-LED 12 on an LED die base layer 15 according to one or more embodiments. If the anode contact layer 50 is not reflective, an optional reflective metal layer 70 can be formed on the anode contact layer 50. In some configurations, the reflective metal layer 70 can be formed as a planar structure that completely covers the top surface of the underlying anode contact layer 50. In such a configuration, the entire reflective material layer 70 is farther from the n-doped compound semiconductor base layer 26 than the farthest surface of the n-doped compound semiconductor region 32 is from the n-doped compound semiconductor base layer 26. In such an embodiment, the reflective material layer 70 can have a smaller area than the anode contact layer 50.

[0095] Optionally, the reflective metal layer 70 may be formed with a lateral extension portion and a sidewall portion, the lateral extension portion being further from the n-doped compound semiconductor base layer 26 than the farthest surface of the p-doped semiconductor material layer 36 (which contacts the anode contact layer 50) is from the n-doped compound semiconductor base layer 26, the sidewall portion being adjacent to the periphery of the lateral extension portion, extending downward from the periphery of the lateral extension portion, and laterally surrounding the n-doped compound semiconductor region 32, the n-doped compound semiconductor base layer 26, and the single-crystalline buffer semiconductor layer 24. In general, the reflective material layer 70 may be patterned to provide a suitable lateral extent for each micro-LED 12. A combination of photolithographic patterning and an etching process (such as an anisotropic etching process or an isotropic etching process) may be employed.

[0096] A bonding pad 80 including an under-bump metallurgy (UBM) layer stack may be formed on each reflective material layer 70 (or on each anode contact layer 50 if a reflective material layer 70 is not used). The UBM layer stack may include any metal layer stack known in the art that can be used as a bonding pad structure on which a solder material can be attached. A solder material portion 90 may be formed on the bonding pad 80 by a suitable process such as electroplating.

[0097] Fig. 6E2 is a vertical cross-sectional view of an exemplary intermediate structure including an LED die 10 separated from a substrate 22 according to one or more embodiments. The LED die 10 is placed in contact with the back plate 110 so that the solder material portion 90 on the micro LED 12 may face the back plate 110 and contact the bonding pad 112. Specifically, the four (4) solder material portions 90 on the four (4) micro LEDs 12 of the LED die 10 may contact the four (4) bonding pads 112, respectively. Thereafter, the solder material portions 90 may be reflowed so that the micro LEDs 12 of the LED die 10 are respectively bonded to the bonding pads 112 through the solder material portions 90. The reflow may be performed by heating the solder material portions 90 by irradiating an infrared laser beam onto the solder material portions 90 through the LED die 10. The reflow may be optionally performed by annealing the light emitting device 10 in a furnace or similar heating device above the melting temperature of the solder material portions 90.

[0098] A laser lift-off process is performed to separate each bonded LED die 10 from the substrate 22. In the laser lift-off process, ultraviolet laser radiation 600 may be irradiated through the substrate 22 to the interface between the LED die 10 and the substrate 22. The laser radiation 600 may heat a portion of the LED die base 15 (e.g., GaN layer) at the interface between the LED die 10 and the substrate 22, releasing the LED die 10 from the substrate 22. The laser lift-off process may be performed before or after the LED die 10 is bonded to the backplane 110. If the laser lift-off process is performed before the LED die 10 is bonded to the backplane 110, the LED die 10 may be clamped to the backplane by any clamping device.

[0099] Figure 7 is a vertical cross-sectional view of an exemplary intermediate structure including LED die 10 mounted on backplane 110 after removal of substrate 22 according to one or more embodiments. The method of transferring LED die 10 from substrate 22 to backplane 110 can be similar to Figure 4 The optional layout pattern of the RGB LED die 10 and Figure 1A The single-color LED bare chips 10 in both are basically the same.

[0100] Refer again Figure 1C After the LED die 10 is mounted on the back plate 110, a dielectric material layer 150 may be formed in the gap between the back plate 110 and the LED die 10. The dielectric material layer 150 may be formed so that the LED die 10 is substantially embedded in the dielectric material layer 150. The dielectric material layer 150 may be formed, for example, by a suitable deposition process such as spin coating.

[0101] Thereafter, an n-type contact layer 160 (eg, a shared cathode) may be formed on the substantially coplanar surface 15S of the LED die base layer 15. 1and the dielectric material layer 150. The n-type contact layer 160 may be formed by a suitable process including, for example, MOVPE, MBE, HVPE, LPE, MOMBE, and ALD. Thereafter, a frame 170 (e.g., a metal frame) may be formed around the periphery of the light emitting device 100 to complete the manufacture of the light emitting device 100.

[0102] Figure 8 8 is a flow chart illustrating a method of making a light emitting device 100 according to one or more embodiments. Step 810 includes providing a backplane including a pixel driving circuit. Step 820 includes forming a plurality of light emitting diode (LED) dies 10 including a plurality of micro-LEDs 12. Step 830 includes mounting the plurality of LED dies 10 on the backplane 110 such that adjacent micro-LEDs 12 in the plurality of micro-LEDs in adjacent LED dies 10 in the plurality of LED dies constitute pixels 130 to be driven by the pixel driving circuit.

[0103] In one embodiment, the light emitting device 100 comprises a display device including a plurality of pixels 130. The pixel driving circuit is configured to drive the pixels to form an image in the display device.

[0104] Refer again FIG. 2A to FIG. 3B Another aspect of the present disclosure is directed to a computer program product, which may include, for example, a computer-readable storage medium (hereinafter, "storage medium"), which may store computer-readable program instructions (hereinafter, "computer program" or "instructions") for performing the features and functions of the defective micro-LED detector 310, the processing device 320, the memory device 330, or the display module 340. The computer-readable storage medium may store thereon instructions for causing the processing device 320 (e.g., a computer, an instruction execution device, a computing device, a computer processor, a central processing unit (CPU), a microprocessor, etc.) to perform the features or functions of the present disclosure. That is, at least one embodiment may include a programmable storage medium that tangibly embodies a program of machine-readable instructions that can be executed by a digital processing device to perform a method of repairing a defective micro-LED, the method including detecting a defective micro-LED in a pixel array, identifying a redundant micro-LED associated with the defective micro-LED, and activating the redundant micro-LED to replace the defective micro-LED.

[0105] Computer readable storage media may be tangible devices that can hold and store instructions executed by processing device 320. Computer readable storage media may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing.

[0106] A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves having instructions recorded thereon), and any suitable combination of the foregoing.

[0107] As used herein, computer-readable storage media should not be interpreted as being merely "transient signals," (such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses transmitted through fiber-optic cables), or electrical signals sent through wires). Processing device 320 can access instructions on the computer-readable storage medium. Alternatively, processing device 320 can access (e.g., download) instructions from an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network).

[0108] The network may include, for example, copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. For example, the processing device 320 may include a network adapter card or a network interface that receives instructions from the network and forwards the instructions to a computer-readable storage medium within the processing device that stores the instructions.

[0109] Instructions for performing the features and functions of the present disclosure may include, for example, assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in one or more programming languages ​​(or a combination of programming languages), including object-oriented programming languages ​​(such as, Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as, "C" programming language or similar programming languages).

[0110] The instructions may execute entirely on processing device 320 (e.g., a user's computer), partially on processing device 320, as a stand-alone software package, partially on processing device 320 and partially on a remote computer, or entirely on a remote computer or server. For example, the instructions may execute on a remote computer connected to a processing device (e.g., a user's computer) through a network, such as a local area network (LAN) or a wide area network (WAN), or may execute on an external computer connected to processing device 320 over the Internet using an Internet service provider.

[0111] The processing device 320 may include, for example, an electronic circuit system including, for example, a programmable logic circuit system, a field programmable gate array (FPGA), or a programmable logic array (PLA) that can execute instructions by utilizing state information of the instructions to personalize the electronic circuit system in order to perform the features or functions of the present disclosure.

[0112] It should be noted that the above reference FIG. 2A to FIG. 3B The features and functions of the embodiments of the present disclosure described may be implemented by the processing device 320 executing instructions. That is, each block of the flowchart illustrations and / or block diagrams and combinations of blocks in the flowchart illustrations and / or block diagrams may be implemented by the processing device 320 executing instructions.

[0113] The instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device for producing a machine, such that the instructions executed via the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more flowcharts and / or block diagram blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium, which may direct the computer, programmable data processing device, and / or other device to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture, which comprises instructions for implementing aspects of the functions / actions specified in one or more flowcharts and / or block diagram blocks.

[0114] That is, the instructions may be executed by the processing device 320 to cause a series of operating steps to be performed by the processing device 320 to produce a computer-implemented process, such that the executed instructions implement the above description of FIG. 2A to FIG. 3B One or more flowcharts and / or block diagrams describe the features / functions / actions. FIG. 2A to FIG. 3B The flowcharts and block diagrams in the 320 illustrate not only the method, system, apparatus or device, but also the architecture, functionality and operation of the processing device 320 that executes the instructions. In this regard, each block in the flowchart or block diagram may represent a module, segment or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s).

[0115] In some alternative implementations, the features or functions in the blocks may not occur in the order mentioned in the drawings. For example, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block of the block diagrams and / or flow charts and combinations of blocks illustrated by the block diagrams and / or flow charts may be implemented by a dedicated hardware-based system that performs the specified functions or actions or executes a combination of dedicated hardware and computer instructions.

[0116] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but rather to be accorded the widest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A light emitting device, comprising: Back panel; A plurality of light emitting diode (LED) dies mounted on the backplane, wherein each of the plurality of LED dies comprises a plurality of LEDs; as well as A pixel includes adjacent micro-LEDs among the plurality of LEDs located in adjacent LED dies among the plurality of LED dies.

2. The light emitting device according to claim 1, wherein: The plurality of LEDs include: a plurality of micro LEDs having at least one of a length and a width of less than 20 micrometers, the plurality of micro LEDs serving as sub-pixels of a pixel.

3. The light emitting device according to claim 2, wherein: The adjacent micro-LEDs include four adjacent micro-LEDs of a pixel, and the adjacent LED dies include four adjacent LED dies; and The four adjacent micro-LEDs include micro-LEDs respectively located at adjacent corners of the four adjacent LED dies.

4. The light emitting device according to claim 3, wherein: The four adjacent micro LEDs include two red micro LEDs, a green micro LED, and a blue micro LED.

5. The light emitting device according to claim 3, wherein: The four adjacent micro LEDs include two green micro LEDs, a red micro LED, and a blue micro LED.

6. The light emitting device according to claim 2, wherein: Each of the plurality of LED dies comprises a first conductivity type semiconductor layer; A common transparent cathode electrode is electrically connected to the first conductivity type semiconductor layer of the plurality of LED dies; The plurality of micro LEDs include a plurality of mesas formed on a first conductive type semiconductor layer; and Each of the plurality of mesas includes a second conductive type semiconductor layer and a light emitting active region between the first conductive type semiconductor layer and the second conductive type semiconductor layer.

7. The light emitting device according to claim 6, wherein: The back plate includes a plurality of bonding pads, and the plurality of micro LEDs and the plurality of LED dies are bonded to the plurality of bonding pads.

8. The light emitting device according to claim 7, wherein: The plurality of LED bare chips include: a plurality of red LED dies, including a plurality of red micro-LEDs; a plurality of green LED dies including a plurality of green micro-LEDs; and A plurality of blue LED dies including a plurality of blue micro-LEDs.

9. The light emitting device according to claim 8, wherein: The plurality of LED dies are bonded to the plurality of bonding pads in an array, the array comprising: a first row including the plurality of red LED dies alternating with the plurality of blue LED dies; and The second row includes the plurality of green LED dies alternating with the plurality of red LED dies.

10. The light emitting device according to claim 9, wherein: Adjacent micro-LEDs in a pixel include: a red micro-LED in the plurality of red LED dies in the first row; a blue micro-LED in the plurality of blue LED dies in the first row; a green micro-LED in the plurality of green LED dies in the second row; and Red micro-LEDs, among the plurality of red LED dies in the second row.

11. The light emitting device according to claim 9, wherein: Adjacent micro-LEDs in a pixel include: a green micro-LED in the plurality of green LED dies in the second row; a red micro-LED in the plurality of red LED dies in the second row; a red micro-LED in the plurality of red LED dies in the third row; and Blue micro-LEDs, among the plurality of blue LED dies in the third row.

12. The light emitting device according to claim 7, wherein: The light emitting device comprises a display device including a plurality of pixels; and The backplane also includes a pixel driving circuit configured to drive the plurality of pixels to form an image.

13. The light emitting device according to claim 2, wherein: The back panel also includes: a defective micro LED detector to detect a defective micro LED among the plurality of micro LEDs; and The processing device redirects the signal for activating the defective micro LED to a redundant micro LED having the same color as the defective micro LED based on the signal from the defective micro LED detector.

14. The light emitting device according to claim 13, wherein: The redundant micro LEDs are included in the same pixel as the defective micro LEDs.

15. A method of forming a light emitting device, comprising: Set up the back panel; Provide a plurality of light emitting diode (LED) bare chips, each of the plurality of LED bare chips comprising a plurality of LEDs; as well as The plurality of LED dies are mounted on a backplane such that adjacent LEDs in the plurality of LEDs in adjacent LED dies in the plurality of LED dies constitute a pixel.

16. The method according to claim 15, wherein: The plurality of LEDs include: a plurality of micro LEDs having at least one of a length and a width of less than 20 micrometers, the plurality of micro LEDs serving as sub-pixels of a pixel.

17. The method according to claim 16, wherein: The step of mounting the plurality of LED dies includes mounting the plurality of LED dies such that the adjacent LED dies include four adjacent LED dies, and the adjacent micro-LEDs include four adjacent micro-LEDs respectively located at adjacent corners of the four adjacent LED dies.

18. The method according to claim 16, wherein: The step of providing the plurality of LED bare chips comprises: providing a plurality of red LED dies including a plurality of red micro-LEDs; providing a plurality of green LED dies including a plurality of green micro-LEDs; and A plurality of blue LED dies including a plurality of blue micro-LEDs are provided.

19. The method of claim 16, wherein: Each of the plurality of LED dies comprises a first conductivity type semiconductor layer; The plurality of micro LEDs include a plurality of mesas formed on a first conductive type semiconductor layer; and Each of the plurality of mesas includes a second conductive type semiconductor layer and a light emitting active region between the first conductive type semiconductor layer and the second conductive type semiconductor layer.

20. The method according to claim 19, further comprising: bonding the plurality of micro LEDs and the plurality of LED dies to a corresponding plurality of bonding pads located on the backplane; as well as A common transparent cathode electrode is formed on the first conductivity type semiconductor layer of the plurality of LED dies.

Images