Communication system and method based on zipper code framework

Abstract

The disclosed systems and methods for transmitting and receiving include: (i) receiving a plurality of data bits; (ii) generating FEC-based encoded data bits according to a zipper code frame comprising a component non-binary code, the zipper code frame comprising a buffer area having a virtual buffer area and a real buffer area; (iii) storing a codeword associated with the FEC-based coded bits in a row of the real buffer; (iv) mapping a given codeword in a given row of the real buffer to a different row of the virtual buffer; (v) receiving the analog signal transmitted by the transmitter; (vi) processing the received analog signal according to a zipper code framework containing a component non-binary code, and generating a received forward error correction (FEC)-based coded bit, and generating a code frame containing a component non-binary code according to the received code frame, the code frame containing a component non-binary code, the code frame containing a component non-binary code, the component non-binary code containing a component non-binary code, and the component non-binary code containing a component non-binary code. And (vii) decoding the received FEC-based encoded bits according to a non-binary decoding technique, and generating information bits.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application No. 17 / 973,574, filed on October 26, 2022, and entitled “Zipper Code Framework-Based Communication Systems and Methods.” Technical Field

[0003] The present invention relates generally to digital communications and, more particularly, to a communication system and method based on a zip code framework. Background Art

[0004] Fiber-optic communication systems have been widely deployed recently, from data center interconnects to cellular network backhaul to transcontinental submarine systems. In modern high-throughput optical communication systems, forward error correction (FEC) is a key technology to protect data from channel noise and inherent system impairments. However, FEC technology usually consumes a lot of power and may account for an acceptable portion of the total power consumption of the transceiver chip (e.g., more than 30%). Due to the complexity limitations at high data throughput, FEC schemes that perform hard decision decoding are of great significance for fiber-optic communication systems.

[0005] Typically, the zipper code-based framework has been used to describe spatially coupled product-like codes, such as staircase codes and braided block codes. Traditionally, zipper codes are constructed using algebraic Bose–Chaudhuri–Hocquenghem (BCH) component codes and decoded by iteratively decoding each component binary code.

[0006] The problem with the conventional framework is that when higher order modulation is used (common in modern high throughput systems), multi-level coding or bit interleaved coded modulation schemes are employed. When conventional zip codes are used with higher order modulation and concatenated coding schemes, better performance can usually be achieved by employing ultra-low overhead (OH) zip codes (whose overhead is about 1.5% to 2.5%). However, the decoding memory required at such low OH is too large for zip codes, making the implementation complicated. In addition, as a stand-alone scheme, conventional zip code schemes using binary BCH component codes have an inherent performance loss due to the suboptimality of treating symbols as uncorrelated bits.

[0007] Therefore, developing an efficient communication system framework based on zip codes has attracted attention. Summary of the invention

[0008] Typically, a zipper-based framework has been used to describe spatially coupled product-like codes, such as staircase codes and weaving block codes. The problem with the conventional framework is that when high-order modulation is used (common in modern high-throughput systems), multi-level coding or bit-interleaved coded modulation schemes are employed.

[0009] To this end, the developers of the present technology have designed a communication system and method based on a zip code framework, which relies on component non-binary codes. The zip code framework designed in the present technology may ignore the interdependence between symbols. This zip code framework can further reduce the error flattening problem that may occur with the increase of the coupling factor in the quasi-diagonal interleaver mapping. In addition, since Reed-Solomon (RS) component codes are used in various non-limiting embodiments, the resulting zip code framework can have a higher tolerance to burst errors.

[0010] According to a first broad aspect of the present invention, a transmitter is provided, comprising: an FEC-based encoder for: receiving a plurality of data bits; generating FEC-based encoded data bits according to a zip code framework comprising component non-binary codes, wherein: the zip code framework comprises a buffer having a virtual buffer and a real buffer; the FEC-based encoder stores codewords associated with the FEC-based encoded bits in rows of the real buffer; and mapping a given codeword in a given row of the real buffer to a different row of the virtual buffer.

[0011] According to any embodiment of the present invention, the non-binary code is a Reed-Solomon code.

[0012] According to any embodiment of the present invention, the FEC-based encoder is also used to: map the given codeword in the given row of the real buffer to different rows of the virtual buffer in a quasi-diagonal interleaving manner; select at least a first group of bits from the given codeword stored in the given row of the real buffer, and copy the first group of bits to the first row of the virtual buffer, so that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; select at least a second group of bits from the given codeword stored in the given row of the real buffer, and copy the second group of bits to a second row of the virtual buffer adjacent to the first row, so that the second group of bits is diagonal to the first group of bits.

[0013] According to any embodiment of the present invention, the length of the first group of bits is equal to the length of the second group of bits.

[0014] According to any embodiment of the present invention, the first group of bits belongs to the same non-binary code symbol.

[0015] According to any embodiment of the present invention, the second group of bits belongs to the same non-binary code symbol.

[0016] According to any embodiment of the present invention, the transmitter further comprises: a transmitter processor configured to: process the FEC-based encoded data bits and generate an analog signal; and transmit the analog signal to a communication channel.

[0017] According to a second broad aspect of the present invention, a receiver is provided, comprising: a receiver processor, configured to: receive an analog signal sent by a transmitter; process the received analog signal according to a zipper code framework comprising component non-binary codes, and generate received FEC-based coded bits; and an FEC-based decoder, configured to decode the received FEC-based coded bits according to a non-binary decoding technique, and generate information bits.

[0018] According to any embodiment of the present invention, the non-binary code is a Reed-Solomon code.

[0019] According to any embodiment of the present invention, the FEC-based decoder is further configured to store a codeword associated with the received FEC-based encoded bits in a row of a real buffer associated with the zip code frame.

[0020] According to any embodiment of the present invention, the FEC-based decoder is also used to: select at least a first group of bits from a given codeword stored in a given row of the real buffer, and copy the first group of bits to a first row of a virtual buffer associated with the zipper code frame, so that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; select at least a second group of bits from the given codeword stored in the given row of the real buffer, and copy the second group of bits to a second row of the virtual buffer adjacent to the first row, so that the second group of bits is diagonal to the first group of bits.

[0021] According to any embodiment of the present invention, the FEC-based decoder is further configured to: select the first group of bits and the second group of bits according to an interleaver mapping.

[0022] According to any embodiment of the present invention, the receiver further comprises: a demapper, configured to calculate an absolute value of a log-likelihood ratio (LLR) based on the received FEC-based coded bits.

[0023] According to any embodiment of the present invention, the FEC-based decoder is further used to: determine the erasure bits in the received FEC-based coded bits based on the absolute value of the LLR less than a predefined threshold; determine the reliable bits in the received FEC-based coded bits based on the absolute value of the LLR greater than the predefined threshold; decode the given codeword associated with the received FEC-based coded bits by one or more of the following: mark the symbols with erasure bits in the given codeword associated with the received FEC-based coded bits as erased symbols, and decode the given codeword using error-and-erasure; decode the given codeword based on the absolute value of the LLR associated with the FEC-based coded bits; flip the erasure bits, and decode the given codeword using the flipped erasure bits and the reliable bits.

[0024] According to any embodiment of the present invention, the FEC-based decoder is also used to: determine whether more than one valid codeword corresponding to the given codeword is decoded; if more than one valid codeword is decoded, select the codeword with the least number of reliable bits flipped, and remove the erasure markers used for the remaining decoding iterations.

[0025] According to any embodiment of the present invention, the FEC-based decoder is further configured to: determine whether only one valid codeword corresponding to the given codeword is decoded; and remove erasure markers for remaining decoding iterations if only one valid codeword is decoded.

[0026] According to any embodiment of the present invention, the FEC-based decoder is further configured to: determine whether a valid codeword corresponding to the given codeword is not decoded; and if the valid codeword is not decoded, not perform a decoding operation on the given codeword.

[0027] According to a third broad aspect of the present invention, there is provided a transmission method, comprising: receiving a plurality of data bits; generating FEC-based coded data bits according to a zip code framework comprising component non-binary codes, wherein the zip code framework comprises a buffer having a virtual buffer and a real buffer; storing codewords associated with the FEC-based coded bits in rows of the real buffer; and mapping a given codeword in a given row of the real buffer to a different row of the virtual buffer.

[0028] According to any embodiment of the present invention, the sending method also includes: mapping the given codeword in the given row of the real buffer to different rows of the virtual buffer in a quasi-diagonal interleaving manner; selecting at least a first group of bits from the given codeword stored in the given row of the real buffer, and copying the first group of bits to the first row of the virtual buffer, so that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; selecting at least a second group of bits from the given codeword stored in the given row of the real buffer, and copying the second group of bits to a second row of the virtual buffer adjacent to the first row, so that the second group of bits is diagonal to the first group of bits.

[0029] According to any embodiment of the present invention, the sending method further comprises: processing the FEC-based encoded data bits and generating an analog signal; and sending the analog signal to a communication channel.

[0030] According to a fourth broad aspect of the present invention, a receiving method is provided, comprising: receiving an analog signal sent by a transmitter; processing the received analog signal according to a zipper code framework containing component non-binary codes, and generating received FEC-based coded bits; decoding the received FEC-based coded bits according to a non-binary decoding technique, and generating information bits.

[0031] According to any embodiment of the present invention, the receiving method further comprises: storing a codeword associated with the received FEC-based coded bits in a row of a real buffer associated with the zip code frame.

[0032] According to any embodiment of the present invention, the receiving method also includes: selecting at least a first group of bits from a given codeword stored in a given row of the real buffer, and copying the first group of bits to a first row of a virtual buffer associated with the zipper code frame, so that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; selecting at least a second group of bits from the given codeword stored in the given row of the real buffer, and copying the second group of bits to a second row of the virtual buffer adjacent to the first row, so that the second group of bits is diagonal to the first group of bits.

[0033] According to any embodiment of the present invention, the receiving method further comprises: selecting the first group of bits and the second group of bits according to an interleaver mapping.

[0034] According to any embodiment of the present invention, the receiving method further comprises: calculating an absolute value of LLR according to the received FEC-based coded bits.

[0035] According to any embodiment of the present invention, the receiving method further includes: determining the erasure bits in the received FEC-based coded bits based on the absolute value of the LLR less than a predefined threshold; determining the reliable bits in the received FEC-based coded bits based on the absolute value of the LLR greater than the predefined threshold; decoding the given codeword associated with the received FEC-based coded bits by one or more of the following: marking the symbols with erasure bits in the given codeword associated with the received FEC-based coded bits as erased symbols, and decoding the given codeword using errors and erasures; decoding the given codeword based on the absolute value of the LLR associated with the FEC-based coded bits; flipping the erasure bits, and decoding the given codeword using the flipped erasure bits and the reliable bits.

[0036] According to any embodiment of the present invention, the receiving method also includes: determining whether more than one valid codeword corresponding to the given codeword is decoded; if more than one valid codeword is decoded, selecting the codeword with the least number of reliable bits flipped, and removing the erasure markers used for the remaining decoding iterations.

[0037] According to any embodiment of the present invention, the receiving method further comprises: determining whether only one valid codeword corresponding to the given codeword is decoded; and removing the erasure marker for the remaining decoding iterations if only one valid codeword is decoded.

[0038] According to any embodiment of the present invention, the receiving method further comprises: determining whether a valid codeword corresponding to the given codeword has not been decoded; and if the valid codeword has not been decoded, not performing a decoding operation on the given codeword. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other features and advantages of the present invention will become apparent through the following detailed description in conjunction with the accompanying drawings, in which:

[0040] Figure 1 shows a high-level functional block diagram of a communication system 100 using forward error correction techniques according to various non-limiting embodiments of the present invention;

[0041] Figure 2 shows representative examples of zip code frames according to various non-limiting embodiments of the present invention;

[0042] Figure 3 shows mapping of a given codeword in a given row of a real buffer to a different row of a virtual buffer;

[0043] Figure 4The benefits of error and erasure based decoding using a zip code framework are illustrated according to various non-limiting embodiments of the present invention;

[0044] Figure 5 A flow chart illustrating a process implemented on a transmitter according to various non-limiting embodiments of the present invention;

[0045] Figure 6 A flow chart illustrating a process implemented on a receiver according to various non-limiting embodiments of the present invention.

[0046] It should be understood that in all drawings and corresponding descriptions, like features are identified by like reference numerals. In addition, it should also be understood that the drawings and the following descriptions are for illustration purposes only, and such disclosure does not limit the scope of the claims. DETAILED DESCRIPTION

[0047] The present invention aims to address at least some of the shortcomings of the current technology. Specifically, the present invention describes a communication system and method based on a zip code framework.

[0048] Unless otherwise defined or illustrated by the context, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

[0049] In the context of this specification, unless otherwise expressly provided, the words "first", "second", "third", etc. are used as adjectives and are used only to distinguish nouns that modify each other, rather than to describe any specific relationship between these nouns. Thus, for example, it should be understood that the use of the terms "first processor" and "third processor" is not intended to imply any particular order, type, chronological order, hierarchy or ranking (for example) between processors / processors, nor is their use (by itself) intended to imply that there must be any "second processor" in any given case. In addition, as discussed in other contexts herein, reference to a "first" element and a "second" element does not exclude that the two elements are the same actual real-world element. Thus, for example, in some cases, the "first" processor and the "second" processor may be the same software and / or hardware; in other cases, they may be different software and / or hardware.

[0050] It should be understood that when an element is described as being "connected" or "coupled" to another element, it may be directly or indirectly connected or coupled to the other element, and there may be intermediate elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other words used to describe the relationship between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0051] In the context of this specification, when an element is referred to as being “associated with” another element, in some embodiments, the two elements may be directly or indirectly linked, related, connected, coupled, the second element employs the first element, etc., without limiting the scope of the present invention.

[0052] The terms used herein are only used to describe specific representative embodiments and are not used to limit the present technology. The singular forms "a / a" and "the" used herein also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" used in this specification is used to illustrate the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0053] The implementation of the present technology has at least one of the above-mentioned objectives and / or aspects, but does not necessarily have all of these objectives and / or aspects. It should be understood that some aspects of the present technology are generated in an attempt to achieve the above-mentioned objectives, and these aspects may not meet the objectives and / or may meet other objectives not specifically described herein.

[0054] The examples and conditional language described in this article are mainly to help readers understand the principles of the present technology, rather than to limit its scope to these specific examples and conditions. It is understood that those skilled in the art can design various devices that, although not explicitly described or shown in this article, embody the principles of the present technology and are included in the spirit and scope of the present technology.

[0055] In addition, for ease of understanding, the following description may describe a relatively simplified implementation of the present technology. Those skilled in the art may understand that various implementations of the present technology may have greater complexity.

[0056] In some cases, useful examples of modifications to the present technology may also be listed. This is only for ease of understanding, not for defining the scope of the present technology or clarifying the limits of the present technology. These modifications are not an exhaustive list, and those skilled in the art may make other modifications while still remaining within the scope of the present technology. In addition, if no modification examples are listed, it should not be interpreted that modifications cannot be made and / or that the content described is the only way to implement the element of the present technology.

[0057] In addition, all statements herein describing the principles, aspects, and implementations of the present technology and specific examples thereof are intended to cover their structural and functional equivalents, whether they are currently known or developed in the future. Thus, for example, it will be understood by those skilled in the art that any block diagram herein is a conceptual view of an illustrative circuit that embodies the principles of the present technology. Similarly, it will be understood that any flow chart, flow chart, state transition diagram, pseudo code, etc. represent various processes that can be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such computer or processor is explicitly shown.

[0058] The functions of the various elements shown in the figure, including any functional blocks marked as "processor" or "processing unit", can be provided by using dedicated hardware and hardware capable of executing software related to appropriate software. When the processor provides functions, these functions can be provided by a single dedicated processor, a single shared processor, or multiple separate processors, some of which can be shared. In some embodiments of the present technology, the processor can be a general-purpose processor, such as a central processing unit (CPU), or a processor dedicated to a specific purpose, such as a graphics processing unit (GPU). In addition, the explicit use of the term "processor" or "controller" should not be interpreted as specifically referring to hardware capable of executing software, and may also implicitly include but are not limited to digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read-only memory (ROM), random access memory (RAM) and non-volatile memory for storing software. Other traditional and / or custom hardware may also be included.

[0059] In the context of the present invention, the expression "data" includes data of any nature or kind that can be stored in a database. Thus, data includes, but is not limited to, audiovisual works (images, films, recordings, presentations, etc.), data (location data, numerical data, etc.), texts (opinions, comments, questions, messages, etc.), documents, spreadsheets, etc.

[0060] Software modules or modules or units represented as software may be represented herein as flow chart elements or any combination of other elements indicating execution process steps and / or text descriptions. Such modules may be executed by hardware shown explicitly or implicitly.

[0061] With these basic principles, the present invention aims to address at least some of the shortcomings of the prior art. Specifically, the present invention describes a communication system and method based on a zip code framework.

[0062] Figure 1 1 shows a high-level functional block diagram of a communication system 100 using FEC technology according to various non-limiting embodiments of the present invention. As shown, the communication system 100 may include a transmitter 102 and a receiver 118. The transmitter 102 may include an FEC encoder 106, a mapper and pulse shaper 110, a pre-equalizer 112, and a modulator 114. The receiver 118 may include a demodulator 122, a post-equalizer 124, a demapper 126, and an FEC decoder 130. It should be noted that the communication system 100 may include other components, however, in Figure 1 These components are omitted in the diagram. The communication system 100 may be an optical communication system, a wired communication system, or a wireless communication system. The use of the term "transmitter" or "receiver" may refer to any type of transmitter or receiver that uses FEC.

[0063] In certain non-limiting embodiments, at the transmitter 102, the FEC encoder 106 may receive a digital data signal including a plurality of data bits 104 (i.e., information bits) and generate FEC-based coded bits. The FEC encoder 106 may generate the FEC-based coded bits based on a zip code framework including component non-binary codes, wherein the zip code framework includes a buffer having a virtual buffer and a real buffer (details of which will be discussed later in the present invention).

[0064] It should be noted that the total number of FEC-based coded bits Lc may generally be greater than the total number of data bits Li. The number (Lc-Li) / Li may be referred to as the overhead (OH) of the FEC encoder 106, and the number r=Li / Lc may also be referred to as the code rate of the FEC encoder 106.

[0065] The FEC encoder 106 may rearrange the FEC-based coded bits to generate rearranged FEC-based coded bits. The FEC encoder 106 may shuffle the FEC-based coded bits in a predefined manner.

[0066] In certain non-limiting embodiments, the encoding method performed by FEC encoder 106 may be based on a zip code framework. Figure 2200 according to various non-limiting embodiments of the present invention. The zip code framework 200 may include a real buffer 202 and a virtual buffer 204. The real buffer 202 and the virtual buffer 204 may include a plurality of rows. A codeword associated with FEC-based coded bits may be stored on each row. The total length of the real buffer 202 and the virtual buffer 204 may be represented as n c In addition, the codeword associated with the FEC-based coded bits may include redundant bits r added to the information bits 104. c . Redundant bits r c Can assist FEC decoder 130 (such as Figure 1 In a non-limiting example, the redundant bits r c The parity of the information bit 104 may be indicated.

[0067] In certain non-limiting embodiments, the component codes associated with the zip code framework 200 may be non-binary codes. An example of such a non-binary code may include a RS code.

[0068] refer to Figure 1 The FEC encoder 106 may encode the plurality of data bits 104 according to the RS code and generate FEC-based coded bits. The FEC encoder 106 may store the codeword associated with the FEC-based coded bits in a row of the real buffer 202.

[0069] In certain non-limiting embodiments, FEC encoder 106 may access real buffer 202 and virtual buffer 204. FEC encoder 106 may be operable to map a given codeword in real buffer 202 (e.g., codeword 301 located in row 308) to a different row of virtual buffer 204 (e.g., rows 310, 312, and 314).

[0070] Figure 3 2. The mapping 300 of a given codeword in a given row of the real buffer 202 to a different row of the virtual buffer 204 is shown. As shown, in this example, the codeword 301 associated with the FEC-based coded bits (including the redundant bits r c) may be stored in row 308 of real buffer 202. FEC encoder 106 may perform interleaving in a quasi-diagonal manner and may select a first group of bits 302 from codewords 301 stored in row 308 of real buffer 202 and copy the first group of bits 302 to row 310 of virtual buffer 204. Row 308 and row 310 may be diagonally adjacent to each other. FEC encoder 106 may select a second group of bits 304 from codewords 301 stored in row 308 and copy the second group of bits 304 to row 312 of virtual buffer 204. Row 312 may be adjacent to row 310. In addition, the first group of bits 302 copied to virtual buffer 204 may be diagonally aligned with the second group of bits 304 copied to virtual buffer 204.

[0071] In a similar manner, the FEC encoder 106 may select a third group of bits 306 from the codeword 301 stored in row 308 and copy the third group of bits 306 to row 314 of the virtual buffer 204. Row 314 may be adjacent to row 312. In addition, the first group of bits 302, the second group of bits 304, and the third group of bits 306 copied to the virtual buffer 204 may be diagonal to each other. It should be noted that the codewords in each given row (e.g., 308, 310, 312, and 314) may be referred to as component non-binary codewords.

[0072] In certain non-limiting embodiments, the first group of bits 302, the second group of bits 304, and the third group of bits 306 may have the same length. In addition, each group of bits in the first group of bits 302, the second group of bits 304, and the third group of bits 306 may belong to a corresponding non-binary code symbol. For example, the first group of bits 302 may belong to the first symbol in the codeword 301, the second group of bits 304 may belong to the second symbol in the codeword 301, and the third group of bits 306 may belong to the third symbol in the codeword 301.

[0073] In general, FEC encoder 106 may allow up to c bits in codeword 301 to be grouped and copied diagonally from row 308 of real buffer 202 to rows 310, 312, and 314. In this way, the duration of interleaving may be reduced by a factor of c. In other words, without grouping the bits, the number of rows required in virtual buffer 204 may increase significantly.

[0074] The mapping performed by the FEC encoder 106 is an important component of the zip code framework 200, which directly affects the code performance and memory requirements at the FEC decoder 130. For example (see Figure 3 ), for n c= 12 and a coupling factor of c = 2 for the zip code frame, the interleaving period of the quasi-diagonal interleaver mapping is 3. Therefore, the memory requirement at the FEC decoder 130 is significantly reduced compared to the interleaving period of the diagonal interleaver without any grouping of bits.

[0075] It should be noted that, since RS code is used as a component code in the zip code framework 200 and bits belonging to the same RS code symbol are grouped, the zip code framework 200 may ignore the interdependence between symbols. Such a zip code framework 200 can further reduce the error floor problem that may occur with the increase of the coupling factor c in the quasi-diagonal interleaver mapping. In addition, since RS component codes are used, the obtained zip code framework 200 can have a higher tolerance to burst errors.

[0076] The FEC encoder 106 may provide the FEC-based coded bits to the mapper and pulse shaper 110. The mapper and pulse shaper 110 may apply a suitable mapping technique to convert the FEC-based coded bits into discrete constellation points according to a suitable constellation label design. The mapper and pulse shaper 110 may convert the constellation points into digital pulses according to any suitable predefined pulse shaping function to generate a digital electrical signal.

[0077] The mapper and pulse shaper 110 may provide the digital electrical signal to the pre-equalizer 112. In certain non-limiting embodiments, the pre-equalizer 112 may optionally be used on the transmitter side to compensate for a portion of the channel distortion, thereby generating an equalized digital electrical signal from the digital electrical signal. The equalized digital electrical signal may be modulated into an analog optical signal by the modulator 114. In certain non-limiting embodiments, the mapper and pulse shaper 110, the pre-equalizer 112, and the modulator 114 may be referred to as a transmitter processor.

[0078] The transmitter 102 may transmit an optical signal via an optical channel 116 (e.g., a fiber channel). In certain non-limiting embodiments, an interleaver mapping may be predefined in the transmitter 102 and the receiver 118. The interleaver mapping may assist the receiver 118 in filling a receiver virtual buffer in a manner similar to filling the virtual buffer 204.

[0079] The analog optical signal 120 may be received by the receiver 118 from the optical channel 116. The demodulator 122 may demodulate the received analog optical signal 120 into a received digital signal. The post-equalizer 124 may equalize the received digital signal and may generate an equalized digital signal. The post-equalization process may compensate for channel distortion. In certain non-limiting embodiments, the demodulator 112 and the post-equalizer 124 may be referred to as a receiver processor.

[0080] The demapper 126 may convert the equalized digital signal back into a bit sequence that represents the FEC-based coded bits in the transmitter 102. The bit sequence may have errors introduced from the optical channel 116. In some examples, the bit sequence may be referred to as received FEC-based coded bits.

[0081] In certain non-limiting embodiments, the FEC decoder 130 may be configured to store codewords associated with received FEC-based coded bits in rows of a receiver real buffer associated with the zip code frame. It should be noted that the receiver real buffer may be implemented similarly to the real buffer 202 associated with the transmitter 102.

[0082] In certain non-limiting embodiments, the FEC decoder 130 may be configured to select at least a first set of bits from a given codeword stored in a given row of a receiver real buffer. The FEC decoder 130 may copy the first set of bits in a first row of a receiver virtual buffer associated with the zip code frame. The receiver real buffer may be implemented similarly to the virtual buffer 204 associated with the transmitter 102. It should be noted that the first row of the receiver virtual buffer may be diagonally adjacent to a given row of the receiver real buffer.

[0083] In certain non-limiting embodiments, FEC decoder 130 may be configured to select at least a second set of bits from a given codeword stored in a given row of a receiver real buffer. FEC decoder 130 may copy a second set of bits in a second row of a receiver virtual buffer. The second row may be adjacent to the first row such that the second set of bits is diagonal to the first set of bits.

[0084] In certain non-limiting embodiments, FEC decoder 130 may select the first group of bits and the second group of bits based on an interleaver mapping.

[0085] The FEC decoder 130 may perform decoding of the codewords in the receiver real buffer and the bit groups copied to the receiver virtual buffer according to a non-binary decoding technique and generate information bits 132 showing the information bits 104 .

[0086] In certain non-limiting embodiments, the decoding technique can be based on iterative window decoding. Meanwhile, the zip code can also realize the flexible selection of the decoding window size W. The window size W can be the number of rows that the FEC decoder 130 can process in a given iteration. In each iteration, the FEC decoder 130 can use a component decoder to decode the row. In the case where the FEC decoder 130 corrects (or less often incorrectly corrects) any bit, the FEC decoder 130 can also update the copy of the changed bit of the bit in the receiver virtual buffer accordingly. In certain non-limiting embodiments, decoding can continue until the maximum predefined number of iterations of the block is reached. Then, the FEC decoder 130 can output the oldest bit block in the decoding window and introduce the newly received bit block into the FEC decoder 130.

[0087] To further improve the performance of the zip code framework 200 with RS component codes, in various non-limiting embodiments, the FEC decoder 130 can rely on error and erasure decoding of the component codes. To this end, the demapper 126 can calculate the log-likelihood ratio (LLR) based on the received FEC-based coded bits. For a given bit, the LLR can be calculated by the following equation:

[0088]

[0089] Demapper 126 may provide FEC decoder 130 with LLR values ​​associated with the received FEC-based coded bits.

[0090] The FEC decoder 130 can be used to determine the erasure bits and reliable bits in the received FEC-based coded bits. In order to make a selection, the FEC decoder 130 can rely on the LLR values ​​of the received FEC-based coded bits. A threshold value n of the LLR value can be predefined. Based on the threshold value n, the FEC decoder 130 can determine the erasure bits and reliable bits in the received FEC-based coded bits. In certain non-limiting embodiments, if the absolute value of the LLR of a given bit is greater than the threshold value n, the corresponding bit can be considered to be highly reliable. On the other hand, if the absolute value of the LLR of a given bit is less than the threshold value n, the corresponding bit can be considered to be an erasure bit. In certain non-limiting embodiments, the threshold value n can be determined by simulation during the design of the communication system 100.

[0091] In certain non-limiting embodiments, FEC encoder 130 may mark symbols with erasure bits in codewords associated with received FEC-based coded bits as erased symbols. FEC decoder 130 may perform error and erasure decoding based on erased symbols.

[0092] In certain non-limiting embodiments, FEC decoder 130 may perform decoding based on all LLR values ​​of bits associated with a given codeword. In this embodiment, FEC decoder 130 may rely on erasure bits and reliable bits for decoding. In this embodiment, FEC decoder 130 may perform error-only decoding.

[0093] In certain non-limiting embodiments, the FEC decoder 130 may flip the erasure bit. For example, if the erasure bit is "0", the FEC decoder 130 may flip the value of the erasure bit to "1". In this embodiment, the FEC decoder 130 may perform error-only decoding using the reliable bits and the flipped bits.

[0094] Based on the above decoding techniques, FEC decoder 130 can determine whether more than one valid codeword corresponding to a given codeword is decoded. In the event that more than one valid codeword is decoded, FEC decoder 130 can select the codeword with the fewest reliable bits flipped and remove the erasure markers for the remaining decoding iterations.

[0095] In certain non-limiting embodiments, FEC decoder 130 may determine whether only one valid codeword corresponding to a given codeword is decoded. In the event that only one valid codeword is decoded, FEC decoder 130 may remove the erasure marker for the remaining decoding iterations.

[0096] In certain non-limiting embodiments, FEC decoder 130 may determine whether a valid codeword corresponding to a given codeword is not decoded. In the event that a valid codeword is not decoded, FEC decoder 130 may not perform a decoding operation on the given codeword.

[0097] Figure 4 The benefits of error and erasure based decoding using the zip code framework 200 according to various non-limiting embodiments of the present invention are shown. Under a fixed signal-to-noise ratio, by varying the threshold η, it is observed that various non-limiting embodiments of the present invention can reduce the output BER by up to four orders of magnitude. This in turn means that the waterfall curve of the zip-RS code will start earlier.

[0098] Therefore, by means of the zip code framework 200 with RS component codes and quasi-interleaver mapping, decoding memory and latency at ultra-low OH can be reduced. In addition, a steep waterfall performance curve with a reduced error floor can be achieved, which may be suitable for burst error correction. Error and erasure based decoding of RS component codes further improves the performance of zip codes.

[0099] Figure 5A flow chart of a process 500 implemented at a transmitter 102 according to various non-limiting embodiments of the present invention is shown. As shown, the process 500 begins at step 502, where the transmitter 102 receives a plurality of data bits. As previously described, at the transmitter 102, the FEC encoder 106 may receive a digital data signal including a plurality of data bits 104 (i.e., information bits).

[0100] The process proceeds to step 504, where the transmitter 102 generates FEC-based coded data bits according to a zip code framework including component non-binary codes, wherein the zip code framework includes a buffer having a virtual buffer and a real buffer. As described above, the FEC encoder 106 included in the transmitter 102 generates FEC-based coded data bits according to the zip code framework 200. The zip code framework 200 may include component non-binary codes such as RS codes. In addition, the zip code framework 200 may include a real buffer 202 and a virtual buffer 204.

[0101] Process 500 proceeds to step 506, where transmitter 506 stores the codeword associated with the FEC-based coded bits in the rows of the real buffer. As described above, FEC encoder 106 stores the codeword associated with the FEC-based coded bits in the rows of the real buffer 202.

[0102] Finally, at step 508, the transmitter 506 maps a given codeword in a given row of the real buffer to a different row of the virtual buffer. As previously described, the FEC encoder 106 maps a given codeword in the real buffer 202 (e.g., codeword 301 located in row 308) to different rows of the virtual buffer 204 (e.g., rows 310, 312, and 314).

[0103] Figure 6 A flow chart of a process 600 implemented on a receiver 118 according to various non-limiting embodiments of the present invention is shown. As shown, the process begins at step 602, where the receiver 118 receives an analog signal transmitted by a transmitter 602. As previously described, the analog optical signal 120 may be received by the receiver 118 from the optical channel 116.

[0104] The process 600 proceeds to step 604, where the receiver 118 processes the received analog signal according to the zip code framework including the component non-binary code and generates the received FEC-based coded bits. As previously described, the demodulator 122 can demodulate the received analog optical signal 120 into a received digital signal. The post-equalizer 124 can equalize the received digital signal and can generate an equalized digital signal. The demapper 126 can convert the equalized digital signal back into a bit sequence, which displays the FEC-based coded bits in the transmitter 102. The FEC-based coded bits are generated according to the zip code framework 200, which includes the component non-binary code such as the RS code.

[0105] Finally, at step 606, the receiver 606 decodes the received FEC-based coded bits according to a non-binary decoding technique and generates information bits. As described above, the FEC decoder 130 can perform decoding of the codewords in the receiver real buffer and the bit groups copied to the receiver virtual buffer according to a non-binary decoding technique and generate information bits 132 showing information bits 104.

[0106] It should be understood that the operation and functionality of the communication system 100, the constituent components and associated processes may be implemented by any one or more of hardware-based, software-based and firmware-based elements. Such operational alternatives do not limit the scope of the present invention in any way.

[0107] It should also be understood that although the embodiments presented herein have been described with reference to specific features and structures, it is apparent that various modifications and combinations may be made without departing from these disclosures. Therefore, the specification and drawings are only to be regarded as illustrations of the implementations or embodiments discussed and their principles as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention.

Claims

1. A transmitter, characterized in that: include: Forward Error Correction (FEC) based encoder for: receiving a plurality of data bits; Generate FEC-based coded data bits according to a zip code framework containing component non-binary codes, where: The zip code framework includes a buffer having a virtual buffer and a real buffer; The FEC-based encoder stores codewords associated with the FEC-based coded bits in rows of the real buffer; A given codeword in a given row of the real buffer is mapped to a different row of the virtual buffer.

2. The transmitter according to claim 1, characterized in that The non-binary code is a Reed-Solomon code.

3. The transmitter according to claim 1 or 2, characterized in that: The FEC-based encoder is also used to: Mapping the given codeword in the given row of the real buffer to different rows of the virtual buffer in a quasi-diagonal interleaving manner; selecting at least a first group of bits from the given codeword stored in the given row of the real buffer and copying the first group of bits to a first row of the virtual buffer such that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; At least a second group of bits is selected from the given codeword stored in the given row of the real buffer and the second group of bits is copied to a second row of the virtual buffer adjacent to the first row such that the second group of bits is diagonal to the first group of bits.

4. The transmitter according to claim 3, characterized in that The length of the first group of bits is equal to the length of the second group of bits.

5. The transmitter according to claim 3 or 4, characterized in that The first group of bits belongs to the same non-binary code symbol.

6. The transmitter according to claim 3 or 4, characterized in that The second group of bits belongs to the same non-binary code symbol.

7. The transmitter according to any one of claims 1 to 6, characterized in that Also includes: Transmitter processor for: Processing the FEC-based encoded data bits and generating an analog signal; The analog signal is transmitted to a communication channel.

8. A receiver, characterized in that: include: Receiver processor for: Receive analog signals sent by the transmitter; processing the received analog signal according to a zip code framework including component non-binary codes and generating received FEC-based coded bits; The FEC-based decoder is used to decode the received FEC-based coded bits according to a non-binary decoding technique and generate information bits.

9. The receiver according to claim 8, characterized in that The non-binary code is a Reed-Solomon code.

10. The receiver according to claim 8 or 9, characterized in that The FEC-based decoder is further configured to store a codeword associated with the received FEC-based encoded bits in a row of a real buffer associated with the zip code frame.

11. The receiver according to claim 10, characterized in that The FEC-based decoder is also used to: selecting at least a first set of bits from a given codeword stored in a given row of the real buffer and copying the first set of bits to a first row of a virtual buffer associated with the zip code frame such that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; At least a second group of bits is selected from the given codeword stored in the given row of the real buffer and the second group of bits is copied to a second row of the virtual buffer adjacent to the first row such that the second group of bits is diagonal to the first group of bits.

12. The receiver according to claim 11, characterized in that The FEC-based decoder is further configured to select the first group of bits and the second group of bits according to an interleaver mapping.

13. The receiver according to any one of claims 8 to 12, characterized in that Also includes: A demapper is used to calculate an absolute value of a log-likelihood ratio (LLR) according to the received FEC-based coded bits.

14. The receiver according to claim 13, characterized in that The FEC-based decoder is also used to: determining erasure bits in the received FEC-based coded bits based on an absolute value of the LLR that is less than a predefined threshold; determining reliable bits among the received FEC-based coded bits based on absolute values ​​of the LLRs that are greater than the predefined threshold; Decoding a given codeword associated with the received FEC-based coded bits by one or more of: marking symbols with erasure bits in the given codeword associated with the received FEC-based coded bits as erased symbols and decoding the given codeword using errors and erasures; decoding the given codeword based on absolute values ​​of the LLRs associated with the FEC-based coded bits; The erasure bits are flipped, and the given codeword is decoded using the flipped erasure bits and the reliable bits.

15. The receiver according to claim 14, characterized in that The FEC-based decoder is also used to: determining whether more than one valid codeword corresponding to the given codeword is decoded; In case more than one valid codeword is decoded, the codeword with the fewest number of flipped reliable bits is selected and the erasure markers are removed for the remaining decoding iterations.

16. The receiver according to claim 14 or 15, characterized in that The FEC-based decoder is also used to: determining whether only one valid codeword corresponding to the given codeword is decoded; In case only one valid codeword is decoded, the erasure markers are removed for the remaining decoding iterations.

17. The receiver according to any one of claims 14 to 16, characterized in that The FEC-based decoder is also used to: determining whether a valid codeword corresponding to the given codeword has not been decoded; In case a valid codeword is not decoded, no decoding operation is performed on the given codeword.

18. A sending method, characterized in that: include: receiving a plurality of data bits; generating FEC-based encoded data bits according to a zip code framework including component non-binary codes, wherein the zip code framework includes a buffer having a virtual buffer and a real buffer; storing a codeword associated with the FEC-based coded bits in a row of the real buffer; A given codeword in a given row of the real buffer is mapped to a different row of the virtual buffer.

19. The method according to claim 18, characterized in that The non-binary code is a Reed-Solomon code.

20. The method according to claim 18 or 19, characterized in that Also includes: Mapping the given codeword in the given row of the real buffer to different rows of the virtual buffer in a quasi-diagonal interleaving manner; selecting at least a first group of bits from the given codeword stored in the given row of the real buffer and copying the first group of bits to a first row of the virtual buffer such that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; At least a second group of bits is selected from the given codeword stored in the given row of the real buffer and the second group of bits is copied to a second row of the virtual buffer adjacent to the first row such that the second group of bits is diagonal to the first group of bits.

21. The method according to claim 20, characterized in that The length of the first group of bits is equal to the length of the second group of bits.

22. The method according to claim 20 or 21, characterized in that The first group of bits belongs to the same non-binary code symbol.

23. The method according to any one of claims 20 or 21, characterized in that The second group of bits belongs to the same non-binary code symbol.

24. The method according to any one of claims 18 to 23, characterized in that Also includes: Processing the FEC-based encoded data bits and generating an analog signal; The analog signal is transmitted to a communication channel.

25. A receiving method, characterized in that: include: Receive analog signals sent by the transmitter; processing the received analog signal according to a zip code framework including component non-binary codes and generating received FEC-based coded bits; The received FEC-based coded bits are decoded according to a non-binary decoding technique and information bits are generated.

26. The method according to claim 25, characterized in that The non-binary code is a Reed-Solomon code.

27. The method according to claim 25 or 26, characterized in that Also includes: A codeword associated with the received FEC-based coded bits is stored in a row of a real buffer associated with the zip code frame.

28. The method according to claim 27, characterized in that Also includes: selecting at least a first set of bits from a given codeword stored in a given row of the real buffer and copying the first set of bits to a first row of a virtual buffer associated with the zip code frame such that the first row of the virtual buffer is diagonally adjacent to the given row of the real buffer; At least a second group of bits is selected from the given codeword stored in the given row of the real buffer and the second group of bits is copied to a second row of the virtual buffer adjacent to the first row such that the second group of bits is diagonal to the first group of bits.

29. The method according to claim 28, characterized in that Also includes: The first group of bits and the second group of bits are selected according to an interleaver mapping.

30. The method according to any one of claims 25 to 29, characterized in that Also includes: The absolute value of the LLR is calculated according to the received FEC-based coded bits.

31. The method according to claim 30, characterized in that Also includes: determining erasure bits in the received FEC-based coded bits based on an absolute value of the LLR that is less than a predefined threshold; determining reliable bits among the received FEC-based coded bits based on absolute values ​​of the LLRs that are greater than the predefined threshold; Decoding a given codeword associated with the received FEC-based coded bits by one or more of: marking symbols with erasure bits in the given codeword associated with the received FEC-based coded bits as erased symbols and decoding the given codeword using errors and erasures; decoding the given codeword based on absolute values ​​of the LLRs associated with the FEC-based coded bits; The erasure bits are flipped, and the given codeword is decoded using the flipped erasure bits and the reliable bits.

32. The method according to claim 31, characterized in that Also includes: determining whether more than one valid codeword corresponding to the given codeword is decoded; In case more than one valid codeword is decoded, the codeword with the fewest number of flipped reliable bits is selected and the erasure markers are removed for the remaining decoding iterations.

33. The method according to claim 31 or 32, characterized in that Also includes: determining whether only one valid codeword corresponding to the given codeword is decoded; In case only one valid codeword is decoded, the erasure markers are removed for the remaining decoding iterations.

34. The method according to any one of claims 31 to 33, characterized in that Also includes: determining whether a valid codeword corresponding to the given codeword has not been decoded; In case a valid codeword is not decoded, no decoding operation is performed on the given codeword.

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