Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method. A semiconductor device includes: a bit line formed to extend in a first direction; a word line formed to extend in a second direction perpendicular to the first direction; and at least one thyristor formed to contact the bit line and extending in a third direction perpendicular to each of the first direction and the second direction. The thyristor includes a first region, a second region disposed below the first region, a third region disposed below the second region, and a fourth region disposed below the third region and connected to a bit line. The word line surrounds the third region.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0161547, filed on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The technology and embodiments of the present disclosure generally relate to semiconductor devices, and more particularly, to semiconductor devices including vertical memory cells and methods of manufacturing the same. Background art

[0004] As the miniaturization and higher integration of semiconductor devices have emerged as major challenges, various technical problems have been encountered.

[0005] For example, as the unit cell area of semiconductor devices decreases, it is difficult to ensure sufficient capacitance. Therefore, by vertically organizing the memory cells included in semiconductor devices, the operating characteristics of semiconductor devices can be improved. Summary of the invention

[0006] According to an embodiment of the present disclosure, a semiconductor device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, and at least one thyristor contacting the bit line and extending in a third direction perpendicular to each of the first direction and the second direction. The thyristor includes a first region, a second region disposed below the first region, a third region disposed below the second region, and a fourth region disposed below the third region and connected to the bit line.

[0007] In some embodiments, the first region and the third region may be regions containing impurities of a first conductivity type, the second region and the fourth region may be regions containing impurities of a second conductivity type, and the word line surrounds at least a portion of the third region.

[0008] In some embodiments, the word line may include, for example, polysilicon.

[0009] In some embodiments, the semiconductor device may further include a gate insulating layer disposed between the word line and the third region.

[0010] In some embodiments, the gate insulating layer may include silicon oxide.

[0011] In some embodiments, the first region may be disposed above the second region included in the first thyristor and the second thyristor.

[0012] In some embodiments, the semiconductor device may further include a plurality of thyristors arranged in a zigzag pattern with respect to the second direction and spaced apart from each other by a preset distance.

[0013] In some embodiments, a plurality of thyristors may be arranged in two rows, and word lines may be formed to surround at least a portion of each of the plurality of thyristors.

[0014] In some embodiments, the word lines may further include metal silicide.

[0015] In some embodiments, the fourth region may further include metal silicide.

[0016] According to an embodiment of the present disclosure, a semiconductor device may include: a memory cell array; and a peripheral circuit region disposed below the memory cell array. The memory cell array includes bit lines formed in a first direction, word lines formed to extend in a second direction perpendicular to the first direction, and at least one thyristor contacting the bit lines and extending in a third direction perpendicular to each of the first direction and the second direction. The peripheral circuit region may include a control circuit configured to provide control signals to the memory cell array and a connection structure connected to the bit lines.

[0017] In some other embodiments, a thyristor may include a first region extending in a first direction, a second region disposed below the first region, a third region disposed below the second region, and a fourth region disposed below the third region and connected to the bit line.

[0018] In some other embodiments, the first region and the third region include impurities of a first conductivity type, and the second region and the fourth region include impurities of a second conductivity type.

[0019] In some other embodiments, the word lines may be formed to surround the third region.

[0020] In some other embodiments, the semiconductor device may further include a gate insulating layer disposed between the word line and the third region.

[0021] In some other embodiments, the word line includes polysilicon and the gate insulating layer includes silicon oxide.

[0022] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a conductive material layer over an upper substrate layer; forming a pre-word line and at least one first opening by etching the conductive material layer; forming a gate insulating layer by oxidizing a portion of the pre-word line exposed via the first opening; forming a second region, a third region, and a fourth region in the first opening by an epitaxial process; forming a word line surrounding the third region by forming at least one second opening in the pre-word line; forming a bit line connected to the fourth region; and forming the first region by back-grinding the upper substrate layer and doping impurities into the back-ground ground upper substrate layer.

[0023] In some other embodiments, the method for manufacturing a semiconductor device may further include: forming a metal silicide layer within the word line; and forming a metal silicide layer within the fourth region.

[0024] In some other embodiments, the method for manufacturing a semiconductor device may further include: forming a first bonding layer over the bit line; forming a peripheral circuit region including a lower substrate layer and a second bonding layer; and connecting the first bonding layer and the second bonding layer to each other.

[0025] According to another embodiment of the present disclosure, a semiconductor device may include: at least two bit lines spaced apart from each other and extending parallel to each other in a first horizontal direction; at least two thyristors each extending vertically and connected at its first end to one of the at least two bit lines; a word line extending in a second direction perpendicular to the first horizontal direction and surrounding a part of the sidewall surfaces of the at least two thyristors, wherein the at least two thyristors are aligned in a diagonal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] When considered in conjunction with the accompanying drawings, the above and other features and advantageous aspects of the present disclosure will become readily apparent from the following detailed description.

[0027] Figure 1 is a plan view showing a memory cell array according to some embodiments of the present disclosure.

[0028] Figure 2 is a cross-sectional view showing a memory cell array taken along a first cutting line according to some embodiments of the present disclosure Figure 1 thereof.

[0029] Figure 3 is a cross-sectional view showing a memory cell array taken along a second cutting line according to some embodiments of the present disclosure Figure 1 thereof.

[0030] Figure 4 is a cross-sectional view showing a memory cell array taken along a third cutting line according to some embodiments of the present disclosure Figure 1 thereof.

[0031] Figure 5 is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure.

[0032] Figure 6 is a perspective view showing the configuration of a unit memory cell according to some embodiments of the present disclosure.

[0033] Figures 7 to 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] The present disclosure provides embodiments and examples of semiconductor devices including vertical memory cells, as well as methods for manufacturing such semiconductor devices, which can be used in configurations to substantially solve one or more technical or engineering problems and alleviate limitations or drawbacks encountered in some other semiconductor device designs. Some embodiments of the present disclosure relate to vertical memory devices with higher integration levels and methods for manufacturing the same. In view of the above problems, according to some embodiments of the present disclosure, a semiconductor device may include a thyristor instead of a capacitor. The semiconductor device can implement a highly integrated memory device including a vertical thyristor and can simplify its manufacturing process.

[0035] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings. However, the present disclosure should not be construed as limited to the embodiments described herein.

[0036] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to specific embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized.

[0037] In the following description, detailed descriptions of related known configurations or functions included herein will be omitted to avoid obscuring the subject matter.

[0038] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. It should also be understood that the terms "comprising," "including," "having," and / or "containing," when used in this specification, specify the presence of the stated components, steps, operations, and / or elements, but do not preclude the presence or addition of one or more other components, steps, operations, and / or elements thereof. The term "and / or" can include combinations of multiple items or any one of the multiple items.

[0039] The drawings may not necessarily be drawn to scale. In some examples, the scale of at least some structures in the drawings may be enlarged to clearly show the features of the embodiments. When a multi-layer structure having two or more layers is disclosed in the drawings or the detailed description, the relative positional relationship or layout order of the layers only reflects specific embodiments, and the scope or spirit of the present disclosure is not limited thereto. It should be noted that the relative positional relationship or layout order of these layers can also be changed as needed.

[0040] Various embodiments of the present disclosure relate to vertical memory devices with higher integration levels and methods for manufacturing the same.

[0041] It should be understood that the above general description and the following detailed description of the present disclosure are both illustrative and descriptive, and are intended to provide a further description of the claimed embodiments.

[0042] Hereinafter, a semiconductor device and a method of manufacturing the same according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 is a plan view showing a memory cell array (MCA) according to some embodiments of the present disclosure.

[0044] Referring to Figure 1 , the semiconductor device may include a memory cell array (MCA).

[0045] The semiconductor device may be implemented as a thyristor-based random access memory (RAM) that includes one or more thyristors instead of one or more capacitors to minimize volatility and power consumption, and to increase circuit integration.

[0046] The thyristor included in the semiconductor device may be a thyristor based on a PNPN thyristor, and the thyristor may be implemented as a vertical thyristor structure. Thus, the thyristor can minimize the area of the memory cell.

[0047] The memory cell array (MCA) may be an area located above a peripheral circuit area (not shown) included in the semiconductor device, and may include a plurality of thyristors (VT).

[0048] Each unit memory cell included in the memory cell array (MCA) may include a single thyristor (VT).

[0049] The thyristor (VT) may have a PNPN structure that includes silicon materials with P-type impurities and silicon materials with N-type impurities stacked on top of each other repeatedly.

[0050] The unit memory cell may store data using the high resistance characteristic and the low resistance characteristic of the thyristor (VT).

[0051] Bit lines BL extending in a first direction (i.e., the D1 direction) may be disposed below each thyristor (VT). Each bit line (BL) may be connected to a plurality of thyristors (VT) arranged in the same direction (e.g., the "D1" direction or the "row" direction).

[0052] In addition, word lines (WL) may be arranged to surround at least a part of the side surface of the thyristor (VT).

[0053] The thyristors (VTs) included in the memory cell array (MCA) can be arranged in a zigzag pattern with respect to a second direction (i.e., the D2 direction).

[0054] The thyristors (VTs) can be spaced apart from each other by a preset distance. Each word line (WL) can be arranged to surround the side surfaces of a plurality of thyristors (VTs) arranged in two rows.

[0055] Two thyristors (VTs) surrounded by one word line (WL) and adjacent to each other can be arranged in a diagonal direction.

[0056] Since two adjacent thyristors are arranged diagonally in the memory cell array (MCA), the integration degree of the memory cell array (MCA) is improved.

[0057] In addition, since two adjacent thyristors (VTs) are arranged in a diagonal direction, each thyristor (VT) can perform read operations and write operations individually.

[0058] The word line (WL) can include, for example, polysilicon. In some embodiments, the word line (WL) can also include a metal silicide such as nickel silicide.

[0059] The gate insulating layer can be formed between the word line (WL) and the thyristor (VT), and the word line (WL) can also be referred to as a gate.

[0060] The word line (WL) can be connected to the control circuit via a first contact portion (C1). For example, the control circuit can supply a control voltage to the word line (WL). More specifically, the control circuit can include a word line driver. The word line driver can be disposed in a peripheral circuit region (not shown) located below the memory cell array (MCA).

[0061] The first contact portion (C1) can be a conductive through-silicon via (TSV) structure. For example, the first contact portion (C1) can be a through hole containing a metal material.

[0062] The bit line (BL) can be connected to one side of the thyristor (VT), and can be a layer containing a conductive material. In some embodiments, the bit line (BL) can include multiple layers, and each layer can include tungsten, tungsten nitride, tungsten silicide, etc.

[0063] The bit line (BL) can be electrically connected to the P-type impurity layer included in the thyristor (VT). The bit line (BL) and the thyristor (VT) can be connected to each other via a bit line contact portion (not shown) containing a conductive material.

[0064] The second contact portion (C2) can be a conductive TSV structure. For example, the second contact portion (C2) can be a through hole containing a metal material.

[0065] The bit line (BL) can be connected to the control circuit via the second contact portion (C2). For example, the control circuit can include a sense amplifier. The sense amplifier can be disposed in a peripheral circuit region (not shown) located below the memory cell array (MCA).

[0066] Figure 2 is a cross-sectional view of a memory cell array (MCA) taken along a first cut line A-A' Figure 1 in accordance with some embodiments of the present disclosure.

[0067] Figure 3 is a cross-sectional view of a memory cell array (MCA) taken along a second cut line B-B' Figure 1 in accordance with some embodiments of the present disclosure.

[0068] Figure 4 is a cross-sectional view of a memory cell array (MCA) taken along a third cut line C-C' Figure 1 in accordance with some embodiments of the present disclosure.

[0069] The positional relationship among the thyristor 50, the word line 130, and the bit line 170 included in the memory cell array (MCA) will be described below with reference to Figures 2 to 4 the cross-sectional views.

[0070] Figure 2 The cross-sectional view of Figure 2 is a cross-sectional view of the memory cell array (MCA) taken along a cut line A-A' passing through the center of the bit line 170 extending in the first direction (i.e., the D1 direction).

[0071] Figure 3 The cross-sectional view of Figure 3 is a cross-sectional view of the memory cell array (MCA) taken along a cut line B-B' passing through the center of the thyristor 50 and extending in the second direction (i.e., the D2 direction).

[0072] Figure 4 The cross-sectional view of

[0073] is a cross-sectional view of the memory cell array (MCA) taken along a cut line C-C' diagonally extending in the first direction (i.e., the D1 direction) and the second direction (i.e., the D2 direction). The cut line C-C' passes through the centers of a plurality of thyristors 50.

[0074] Each of the first region 110 and the third region 150 may be a silicon region doped with impurities of a first conductivity type. Each of the second region 140 and the fourth region 160 may be a silicon region doped with impurities of a second conductivity type. The impurities of the first conductivity type may be P-type impurities, and the impurities of the second conductivity type may be N-type impurities.

[0075] In some embodiments, the concentration of impurities in the first region 110 may be higher than the concentration of impurities in the third region 150.

[0076] In addition, the concentration of impurities in the second region 140 may be equal to the concentration of impurities in the fourth region 160.

[0077] The first region 110 may be formed by back-grinding a silicon substrate (i.e., the upper substrate layer) and then performing ion implantation on the resulting silicon substrate.

[0078] The second region 140, the third region 150, and the fourth region 160 may be regions grown by forming openings via an etching process and then performing an epitaxial process in the formed openings.

[0079] Two adjacent thyristors 50 may share a word line 130.

[0080] The word line 130 may be arranged to at least partially surround the sidewall of the third region 150 included in the thyristor 50. In some embodiments, the third region 150 may be a storage layer of the thyristor 50.

[0081] The length of the word line 130 in the third direction (D3 direction) may be shorter than the length of the third region 150 in the third direction (D3 direction).

[0082] The word line 130 may include, for example, polysilicon. In some embodiments, the word line 130 may include a metal silicide such as nickel silicide (NiSi). In some embodiments, the word line 130 may include both polysilicon and metal silicide. In some embodiments, certain portions of the word line may include polysilicon while other portions may include metal silicide. Employing metal silicide for the word line 130 can significantly improve the resistance characteristics of the word line.

[0083] The gate insulating layer 132 may be formed between the thyristor 50 and the word line 130. The thyristor 50 and the word line 130 may be electrically isolated from each other through the gate insulating layer 132.

[0084] For example, the gate insulating layer 132 may be formed by oxidizing polysilicon. More specifically, the gate insulating layer 132 may be formed by selectively oxidizing the polysilicon located within the openings formed via a lithography process.

[0085] The fourth region 160 of the thyristor 50 may be in contact with the bit line contact portion 172. The fourth region 160 may include a metal silicide in a region formed to be in contact with the bit line contact portion 172. Since the fourth region 160 includes the metal silicide, the contact resistance between the bit line contact portion 172 and the fourth region 160 can be reduced.

[0086] The bit line contact portion 172 may be connected to the bit line 170. The bit line contact portion 172 may be a vertical via contact portion including a conductive material and extending in a vertical direction (i.e., the D3 direction).

[0087] The memory cell array (MCA) may further include a plurality of layers for electrically insulating the thyristor 50 and the bit line 170.

[0088] For example, the memory cell array (MCA) may include a first isolation layer 100 that is disposed not only between the bit line contact portions 172 but also between the thyristors 50.

[0089] The first isolation layer 100 may include an insulating material such as silicon oxide and may be formed by a deposition and chemical mechanical planarization (CMP) process of silicon oxide.

[0090] The second isolation layer 120 may be a region disposed between the second regions 140 included in the thyristor 50 and may include an insulating material such as silicon oxide. The second isolation layer 120 may be formed by depositing silicon oxide and an etching process.

[0091] The cover layer 162 may be a layer for insulating the fourth region 160 of the thyristor 50 and may include an insulating material such as silicon oxide. The cover layer 162 may be formed by a deposition and etching process of silicon oxide.

[0092] Figure 5 is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure.

[0093] Figure 5 A detailed cross-sectional view of a semiconductor device including a memory cell array (MCA) and a peripheral circuit region (PRP) is shown.

[0094] Figure 5 The cross-sectional view of is a cross-sectional view including Figure 4 the memory cell array (MCA) shown.

[0095] More specifically, Figure 5 the cross-sectional view of is Figure 4 a cross-sectional view in which the cross-section is extended to the entire semiconductor device.

[0096] Redundant descriptions in the content described with reference to Figures 1 to 4 previously will be omitted here.

[0097] Referring to Figure 5 , a peripheral circuit region (PRP) can be provided under a memory cell array (MCA).

[0098] The memory cell array (MCA) and the peripheral circuit region (PRP) can be connected to each other by wafer bonding.

[0099] The memory cell array (MCA) can include a plurality of thyristors 50.

[0100] A first region 110 included in the thyristor 50 can be connected to a first upper interconnect layer 114 through one or more upper interconnect contacts 112.

[0101] The first region 110 can generally be included in the plurality of thyristors 50 included in the memory cell array (MCA).

[0102] The first region 110 can be provided above a second region 140 included in any one of the thyristors 50 included in the memory cell array (MCA).

[0103] Each of the plurality of upper interconnect contacts 112 can be a vertical via contact formed in a first isolation layer 100. The upper interconnect contact 112 can include a conductive material and can extend in a vertical direction.

[0104] The first upper interconnect layer 114 can include a conductive material. The first upper interconnect layer 114 can be connected to the first region 110 and can be used as a source line.

[0105] A metal line 180 located on the same layer as the bit line 170 in the vertical direction can be a region connected to a second upper interconnect layer 184 via a vertical via 182. The metal line 180, the vertical via 182, and the second upper interconnect layer 184 can include a conductive material and can electrically connect elements (e.g., thyristors 50) included in the memory cell array (MCA) to elements (e.g., control circuit 214) of the memory cell array. The metal line 180 and the bit line 170 can be formed by an interconnect process (also referred to as a wiring process).

[0106] A first bonding layer 190 located under the bit line 170 and the metal line 180 can include a first bonding pad 192 and a second bonding pad 194.

[0107] The first bonding layer 190 can contain an insulating material such as silicon oxide and can contain the same material as the second bonding layer 220.

[0108] Each of the first bonding pad 192 and the second bonding pad 194 may include a conductive material. For example, each of the first bonding pad 192 and the second bonding pad 194 may be implemented as a bonding metal pad including a metal material.

[0109] The peripheral circuit region (PRP) may include a lower substrate layer 200, a third isolation layer 210, and a second bonding layer 220.

[0110] The lower substrate layer 200 may be a semiconductor substrate layer including a silicon substrate. In some embodiments, the lower substrate layer 200 may include materials suitable for semiconductor processing.

[0111] For example, the lower substrate layer 200 may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0112] In addition, the lower substrate layer 200 may further include other semiconductor materials such as germanium. The lower substrate layer 200 may include a III / V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide.

[0113] The third isolation layer 210 may include a first connection structure 212, a control circuit 214, and a second connection structure 216, and may be a layer including an insulating material such as silicon oxide.

[0114] The first connection structure 212, the control circuit 214, and the second connection structure 216 located within the third isolation layer 210 may be electrically isolated from each other by the insulating material constituting the remainder of the third isolation layer 210.

[0115] The first connection structure 212 may include at least one metal interconnect, and may include a multi-layer metal interconnect including a plurality of vias and a plurality of metal interconnects.

[0116] The first connection structure 212 may be connected to a third bonding pad 222 included in the second bonding layer 220, and may be electrically connected to components (such as bit line 170, etc.) included in the memory cell array (MCA) via the third bonding pad 222.

[0117] The control circuit 214 may include at least one transistor. The transistor may be a planar channel transistor. In addition to the planar channel transistor, the transistor structures included in the control circuit 214 may further include, for example, recessed channel transistors, buried gate transistors, or fin field effect transistors (FinFETs).

[0118] The control circuit 214 may determine whether to provide a control signal to the bit line 170, the word line 130, or the first upper interconnect 114 (i.e., the source line) included in the memory cell array (MCA).

[0119] The second connection structure 216 may include at least one metal interconnect, and may include a multi-layer metal interconnect including a plurality of vias and a plurality of metal interconnects. The second connection structure 216 may be connected to the fourth bonding pad 224, and may be connected to the metal wire 180 and the vertical via 182 via the fourth bonding pad 224.

[0120] The second bonding layer 220 is disposed on the third isolation layer 210. The second bonding layer 220 may cover the third isolation layer 210 and may be in contact with the third isolation layer 210. The second bonding layer 220 may include a third bonding pad 222 and a fourth bonding pad 224. The third bonding pad 222 and the fourth bonding pad 224 may be spaced apart from each other.

[0121] The second bonding layer 220 may be a layer including an insulating material such as silicon oxide. The second bonding layer 220 may include the same material as the first bonding layer 190.

[0122] The third bonding pad 222 and the fourth bonding pad 224 may include a conductive material. For example, each of the third bonding pad 222 and the fourth bonding pad 224 may be a bonding metal pad including a metal material.

[0123] Figure 5 An embodiment is shown in which the peripheral circuit region (PRP) is disposed below the memory cell array (MCA). However, in some embodiments, the semiconductor device may have a per-cell peripheral (POC) structure in which the peripheral circuit region (PRP) is located above the memory cell array (MCA).

[0124] Figure 6 is a perspective view showing the configuration of a unit memory cell according to some embodiments of the present disclosure.

[0125] The following will refer to Figure 6 describe Figure 5 the detailed structure of the partial region 1 of the memory cell array (MCA) shown.

[0126] Figure 5 The partial region 1 of the memory cell array (MCA) shown (see Figure 5 ) may be a region including two adjacent thyristors 50.

[0127] As Figure 6 shown, the positional relationship between the thyristor 50, the word line 130, the bit line 170, and the first upper interconnect layer 114 (i.e., the source line) is shown in detail.

[0128] Refer to Figure 6, the bit line 170 and the first upper interconnect layer 114 may extend in a first direction (i.e., the D1 direction). The word line 130 may extend in a second direction (i.e., the D2 direction) perpendicular to the first direction (i.e., the D1 direction). In addition, the word line 130 may be formed to surround the sidewall of the thyristor 50.

[0129] The word line 130 and the thyristor 50 may be spaced apart from each other by the thickness of the gate insulating layer 132.

[0130] The thyristor 50 may be connected to the bit line 170 via a bit line contact portion and may be connected to the first upper interconnect layer 114 via an upper interconnect contact portion, but is not limited thereto. However, for ease of description, Figure 6 the bit line contact portion and the upper interconnect layer are omitted in

[0131] The first upper interconnect layer 114 may be commonly connected to a plurality of thyristors 50. The first upper interconnect layer 114 may serve as a source line for the plurality of thyristors 50.

[0132] The bit line 170 may be connected to each of the plurality of thyristors 50. Since the bit line 170 is connected to each thyristor 50, the thyristor 50 may operate as an individual memory element.

[0133] Since the semiconductor device according to some embodiments of the present disclosure includes a thyristor 50 instead of a capacitor, the semiconductor device does not need to be refreshed and may have a structure in which each memory cell includes one transistor.

[0134] Figures 7 to 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0135] Referring to Figure 7 , an insulating material layer 12L, a conductive material layer 13L, and a first protective layer P1 may be stacked on top of the upper substrate layer 11S.

[0136] The upper substrate layer 11S is made of a material suitable for semiconductor processing. For example, the upper substrate layer 11S may include a silicon substrate. The upper substrate layer 11S may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof.

[0137] The upper substrate layer 11S may also include other semiconductor materials such as germanium. The upper substrate layer 11S may include a III / V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide. The upper substrate layer 11S may be a substrate obtained by removing at least a part of the upper substrate layer 11S by subsequent back grinding and then performing additional impurity doping.

[0138] An insulating material layer 12L containing an insulating material such as silicon oxide can be formed on the upper substrate layer 11S. The insulating material layer 12L can electrically isolate the upper substrate layer 11S and the conductive material layer 13L from each other.

[0139] The conductive material layer 13L can be formed on the insulating material layer 12L.

[0140] The height of the conductive material layer 13L can be lower than the height of the third region 15 formed later.

[0141] The conductive material layer 13L can include, for example, polysilicon. In some embodiments, the conductive material layer 13L can include a metal, a metal nitride, a metal silicide, or a combination thereof.

[0142] Hereinafter, the following description will be based on the conductive material layer 13L containing polysilicon.

[0143] The first protective layer P1 can be formed on the conductive material layer 13L. The first protective layer P1 can include silicon nitride.

[0144] Refer to Figure 8 , a first mask layer M1 can be formed on the first protective layer P1, and a plurality of first openings 2 can be formed using the first mask film M1.

[0145] When forming the first opening 2, the second isolation layer 12 can be disposed on the upper substrate layer 11S, and the pre-word line 13P can be disposed on the second isolation layer 12. The second protective layer P2 can be disposed on the pre-word line 13P.

[0146] Refer to Figure 9 , the gate insulating layer 13I can be formed by oxidizing the pre-word line 13P exposed through the first opening 2.

[0147] As Figure 9 shown, the first mask layer M1 can be removed.

[0148] The gate insulating layer 13I can be formed by oxidizing the sidewalls of the pre-word line 13P containing polysilicon.

[0149] Since the upper part of the pre-word line 13P overlaps with the second protective layer P2, the part of this region corresponding to the sidewalls of the pre-word line 13P can be selectively oxidized. In addition, a part of the upper substrate layer 11S exposed by the first opening 2 can be oxidized.

[0150] Refer to Figure 10 , the second region 14, the third region 15, and the fourth region 16 can be formed in the first opening 2 by an epitaxial process.

[0151] In some embodiments, before forming the second region 14, the third region 15, and the fourth region 16, a partial region of the oxidized upper liner layer 11S may be removed.

[0152] The second region 14 may be an N-type impurity region. In addition, the third region 15 may be a P-type impurity region, and the fourth region 16 may be an N-type impurity region.

[0153] The upper region of the fourth region 16 may contain an N-type impurity with a higher concentration than the lower region of the fourth region 16. An impurity implantation process and an annealing (heat treatment) process may be performed to change the concentration of the upper region of the fourth region 16.

[0154] A semiconductor device according to some embodiments of the present disclosure may be formed by performing an epitaxial process on the second region 14, the third region 15, and the fourth region 16, such that the impurity concentrations of the second region 14, the third region 15, and the fourth region 16 can be easily controlled.

[0155] The impurity concentrations of the second region 14, the third region 15, and the fourth region 16 are controlled such that the operating characteristics of the memory cell, such as leakage current or operating voltage, can be improved.

[0156] Referring to Figure 11 , the second protective layer P2 may be selectively removed such that a pre-cover layer 16D can be formed over the fourth region 16.

[0157] The second protective layer P2 may be selectively removed by using the etching selectivity to silicon nitride.

[0158] The pre-cover layer 16D may include an insulating material such as silicon oxide. The pre-cover layer 16D may allow the fourth region 16 and the pre-word line 13P to overlap each other.

[0159] Referring to Figure 12 , a second mask layer M2 may be formed over the pre-cover layer 16D, and the pre-cover layer 16D and the pre-word line 13P may be selectively removed.

[0160] In the Figure 12 process, adjacent pre-word lines 13P may be separated from each other to form word lines 13.

[0161] Since at least one second opening 3 is formed by using the second mask layer M2, adjacent pre-word lines 13P and the pre-cover layer 16D may be separated from each other. In the Figure 12 process, at least a part of the second isolation layer 12 may be removed.

[0162] Referring to Figure 13, the second mask layer M2 can be removed, and the pre-covering layer 16D can be etched to form the covering layer 16I. In addition, the first isolation layer 10 can be formed on the covering layer 16I, the word line 13, and the fourth region 16.

[0163] The first isolation layer 10 can be a region containing silicon oxide. The first isolation layer 10 can be formed by silicon oxide deposition and CMP (chemical mechanical planarization) processing.

[0164] In some embodiments, before forming the first isolation layer 10, metal silicide can be formed in some regions of the word line 13 and some regions of the fourth region 16.

[0165] Since the metal silicide is formed as described above, the contact resistance between the bit line contact portion and the fourth region 16 can be reduced.

[0166] Refer to Figure 14 , a plurality of bit line contact portions 17C connected to the fourth region 16 and bit lines 17 connected to the bit line contact portions 17C can be formed.

[0167] Each bit line contact portion 17C can be a vertical through hole containing a conductive material.

[0168] The bit line 17 can include multiple layers, and each layer can include metal, metal nitride, or metal silicide.

[0169] As Figure 15 shown, a first bonding layer 19 can be formed on the bit line 17.

[0170] The first bonding layer 19 can include at least one first bonding pad 19C.

[0171] The first bonding layer 19 can include an insulating material, and each first bonding pad 19C can include a metal material.

[0172] As Figure 16 shown, the upper substrate layer 11S can be back-grinded (or back-grinding processed).

[0173] The back-grinded upper substrate layer 11S can be additionally doped with P-type impurities, and the region additionally doped with P-type impurities can be called the first region 11.

[0174] The first region 11 can be formed by back-grinding, P-type impurity doping, and annealing.

[0175] In addition, the memory cell array (MCA) and the peripheral circuit region (PRP) can be connected via the first bonding layer 19 and the first bonding pad 19C.

[0176] As described above, the peripheral circuit region (PRP) may include a lower liner layer 20, a third isolation layer 21, and a second bonding layer 22.

[0177] The lower liner layer 20 may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0178] The third isolation layer 21 may include a first connection structure 21C and a control circuit 21T. The first connection structure 21C may include a multi-layer metal interconnect. In addition, the control circuit 21T may include at least one transistor.

[0179] The second bonding layer 22 may include insulating materials spaced apart from each other and third bonding pads 22C. The third bonding pads 22C may include a metal material.

[0180] The memory cell array (MCA) and the peripheral circuit region (PRP) may be connected via the second bonding layer 22 and the third bonding pads 22C.

[0181] More specifically, the first bonding layer 19 and the second bonding layer 22 may be connected to each other, and the first bonding pads 19C and the third bonding pads 22C may be connected to each other.

[0182] Referring Figure 17 , an upper interconnect contact 11C and a first upper interconnect layer 11M may be formed over the first region 11.

[0183] The upper interconnect contact 11C may be a vertical via contact formed in the first isolation layer 10, and the first upper interconnect layer 11M may be a metal interconnect including a conductive material.

[0184] It is obvious from the above description that a semiconductor device according to some embodiments of the present disclosure may include a thyristor instead of a capacitor.

[0185] A semiconductor device according to some embodiments of the present disclosure may implement a highly integrated memory device including a vertical thyristor, and may simplify its manufacturing process.

[0186] Embodiments of the present disclosure may provide various effects that can be directly or indirectly recognized.

[0187] Those skilled in the art will understand that embodiments of the present disclosure may be implemented in other specific manners than those described herein. In addition, claims not explicitly set forth in the appended claims may be presented as combinations of embodiments, or may be included as new claims through subsequent amendments after the filing of the application.

[0188] Although multiple exemplary embodiments have been described, it should be understood that modifications and / or enhancements to the disclosed embodiments and other embodiments can be designed based on what is described and / or shown in the present disclosure. Additionally, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A bit line extending along a first direction; a word line extending in a second direction perpendicular to the first direction; as well as at least one thyristor contacting the bit line and extending in a third direction, the third direction being perpendicular to each of the first direction and the second direction, Wherein, the thyristor comprises: First region; A second area, arranged below the first area; A third region is disposed below the second region; and The fourth region is disposed under the third region and connected to the bit line.

2. The semiconductor device according to claim 1, wherein: The first region and the third region are regions containing impurities of a first conductivity type; The second region and the fourth region are regions containing impurities of the second conductivity type; and The word line surrounds at least a portion of the third region.

3. The semiconductor device according to claim 1, wherein: The word line includes polysilicon.

4. The semiconductor device according to claim 1, further comprising: A gate insulating layer is disposed between the word line and the third region.

5. The semiconductor device according to claim 4, wherein: The gate insulating layer includes silicon oxide.

6. The semiconductor device according to claim 1, wherein: The first region is disposed on second regions included in the first thyristor and the second thyristor.

7. The semiconductor device according to claim 1, further comprising: A plurality of thyristors are arranged in a zigzag pattern with respect to the second direction and are spaced apart from each other by a predetermined distance.

8. The semiconductor device according to claim 7, wherein: The plurality of thyristors are arranged in two rows; and The word line is formed to surround at least a portion of each of the plurality of thyristors.

9. The semiconductor device according to claim 1, wherein: The word line also includes metal silicide.

10. The semiconductor device according to claim 1, wherein: The fourth region also includes metal silicide.

11. A semiconductor device comprising: A memory cell array; as well as A peripheral circuit region is arranged below the memory cell array, Wherein, the storage cell array comprises: A bit line extending along a first direction; a word line extending in a second direction perpendicular to the first direction; and at least one thyristor contacting the bit line and extending in a third direction, the third direction being perpendicular to each of the first direction and the second direction, Wherein, the peripheral circuit area includes: a control circuit that provides a control signal to the memory cell array; and A connection structure is connected to the bit line.

12. The semiconductor device according to claim 11, wherein the thyristor comprises: a first region extending along the first direction; a second region disposed below the first region; a third region disposed below the second region; as well as A fourth region is disposed under the third region and connected to the bit line.

13. The semiconductor device according to claim 12, wherein: The first region and the third region include impurities of a first conductivity type; and The second region and the fourth region include impurities of a second conductivity type.

14. The semiconductor device according to claim 12, wherein: The word line is formed to surround the third region.

15. The semiconductor device according to claim 14, further comprising: A gate insulating layer is disposed between the word line and the third region.

16. The semiconductor device according to claim 15, wherein: The word line comprises polysilicon; and The gate insulating layer includes silicon oxide.

17. A method for manufacturing a semiconductor device, the method comprising: forming a conductive material layer over the upper substrate layer; forming a pre-word line and at least one first opening by etching the conductive material layer; forming a gate insulating layer by oxidizing a portion of the pre-word line exposed through the first opening; forming a second region, a third region and a fourth region in the first opening by an epitaxial process; forming a word line surrounding the third region by forming at least one second opening in the pre-word line; forming a bit line connected to the fourth region; as well as The first region is formed by back-grinding the upper substrate layer and performing impurity doping on the back-grinded upper substrate layer.

18. The method according to claim 17, further comprising: forming a metal silicide layer in the word line; as well as The metal silicide layer is formed in the fourth region.

19. The method according to claim 17, further comprising: forming a first bonding layer over the bit line; forming a peripheral circuit region including a lower substrate layer and a second bonding layer; as well as The first bonding layer and the second bonding layer are connected to each other.

20. A semiconductor device comprising: at least two bit lines spaced apart from each other and extending parallel to each other along a first horizontal direction; at least two thyristors, each thyristor extending vertically and connected at a first end thereof to one of the at least two bit lines; a word line extending in a second direction perpendicular to the first horizontal direction and surrounding a portion of a sidewall surface of the at least two thyristors; The at least two thyristors are aligned in a diagonal direction.

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